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ASoC: max98090: Use params_width() rather than memory format
[deliverable/linux.git] / sound / soc / codecs / max98095.c
CommitLineData
82a5a936
PH		 1/*
2 * max98095.c -- MAX98095 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
82a5a936
PH		 18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
22#include <sound/initval.h>
23#include <sound/tlv.h>
24#include <linux/slab.h>
25#include <asm/div64.h>
26#include <sound/max98095.h>
9dd90c5d 27#include <sound/jack.h>
82a5a936
PH		 28#include "max98095.h"
29
30enum max98095_type {
31 MAX98095,
32};
33
34struct max98095_cdata {
35 unsigned int rate;
36 unsigned int fmt;
dad31ec1
PH		 37 int eq_sel;
38 int bq_sel;
82a5a936
PH		 39};
40
41struct max98095_priv {
14acbbbb 42 struct regmap *regmap;
82a5a936 43 enum max98095_type devtype;
82a5a936
PH		 44 struct max98095_pdata *pdata;
45 unsigned int sysclk;
46 struct max98095_cdata dai[3];
dad31ec1
PH		 47 const char **eq_texts;
48 const char **bq_texts;
49 struct soc_enum eq_enum;
50 struct soc_enum bq_enum;
51 int eq_textcnt;
52 int bq_textcnt;
82a5a936
PH		 53 u8 lin_state;
54 unsigned int mic1pre;
55 unsigned int mic2pre;
9dd90c5d
RK		 56 struct snd_soc_jack *headphone_jack;
57 struct snd_soc_jack *mic_jack;
82a5a936
PH		 58};
59
14acbbbb
MB		 60static const struct reg_default max98095_reg_def[] = {
61 { 0xf, 0x00 }, /* 0F */
62 { 0x10, 0x00 }, /* 10 */
63 { 0x11, 0x00 }, /* 11 */
64 { 0x12, 0x00 }, /* 12 */
65 { 0x13, 0x00 }, /* 13 */
66 { 0x14, 0x00 }, /* 14 */
67 { 0x15, 0x00 }, /* 15 */
68 { 0x16, 0x00 }, /* 16 */
69 { 0x17, 0x00 }, /* 17 */
70 { 0x18, 0x00 }, /* 18 */
71 { 0x19, 0x00 }, /* 19 */
72 { 0x1a, 0x00 }, /* 1A */
73 { 0x1b, 0x00 }, /* 1B */
74 { 0x1c, 0x00 }, /* 1C */
75 { 0x1d, 0x00 }, /* 1D */
76 { 0x1e, 0x00 }, /* 1E */
77 { 0x1f, 0x00 }, /* 1F */
78 { 0x20, 0x00 }, /* 20 */
79 { 0x21, 0x00 }, /* 21 */
80 { 0x22, 0x00 }, /* 22 */
81 { 0x23, 0x00 }, /* 23 */
82 { 0x24, 0x00 }, /* 24 */
83 { 0x25, 0x00 }, /* 25 */
84 { 0x26, 0x00 }, /* 26 */
85 { 0x27, 0x00 }, /* 27 */
86 { 0x28, 0x00 }, /* 28 */
87 { 0x29, 0x00 }, /* 29 */
88 { 0x2a, 0x00 }, /* 2A */
89 { 0x2b, 0x00 }, /* 2B */
90 { 0x2c, 0x00 }, /* 2C */
91 { 0x2d, 0x00 }, /* 2D */
92 { 0x2e, 0x00 }, /* 2E */
93 { 0x2f, 0x00 }, /* 2F */
94 { 0x30, 0x00 }, /* 30 */
95 { 0x31, 0x00 }, /* 31 */
96 { 0x32, 0x00 }, /* 32 */
97 { 0x33, 0x00 }, /* 33 */
98 { 0x34, 0x00 }, /* 34 */
99 { 0x35, 0x00 }, /* 35 */
100 { 0x36, 0x00 }, /* 36 */
101 { 0x37, 0x00 }, /* 37 */
102 { 0x38, 0x00 }, /* 38 */
103 { 0x39, 0x00 }, /* 39 */
104 { 0x3a, 0x00 }, /* 3A */
105 { 0x3b, 0x00 }, /* 3B */
106 { 0x3c, 0x00 }, /* 3C */
107 { 0x3d, 0x00 }, /* 3D */
108 { 0x3e, 0x00 }, /* 3E */
109 { 0x3f, 0x00 }, /* 3F */
110 { 0x40, 0x00 }, /* 40 */
111 { 0x41, 0x00 }, /* 41 */
112 { 0x42, 0x00 }, /* 42 */
113 { 0x43, 0x00 }, /* 43 */
114 { 0x44, 0x00 }, /* 44 */
115 { 0x45, 0x00 }, /* 45 */
116 { 0x46, 0x00 }, /* 46 */
117 { 0x47, 0x00 }, /* 47 */
118 { 0x48, 0x00 }, /* 48 */
119 { 0x49, 0x00 }, /* 49 */
120 { 0x4a, 0x00 }, /* 4A */
121 { 0x4b, 0x00 }, /* 4B */
122 { 0x4c, 0x00 }, /* 4C */
123 { 0x4d, 0x00 }, /* 4D */
124 { 0x4e, 0x00 }, /* 4E */
125 { 0x4f, 0x00 }, /* 4F */
126 { 0x50, 0x00 }, /* 50 */
127 { 0x51, 0x00 }, /* 51 */
128 { 0x52, 0x00 }, /* 52 */
129 { 0x53, 0x00 }, /* 53 */
130 { 0x54, 0x00 }, /* 54 */
131 { 0x55, 0x00 }, /* 55 */
132 { 0x56, 0x00 }, /* 56 */
133 { 0x57, 0x00 }, /* 57 */
134 { 0x58, 0x00 }, /* 58 */
135 { 0x59, 0x00 }, /* 59 */
136 { 0x5a, 0x00 }, /* 5A */
137 { 0x5b, 0x00 }, /* 5B */
138 { 0x5c, 0x00 }, /* 5C */
139 { 0x5d, 0x00 }, /* 5D */
140 { 0x5e, 0x00 }, /* 5E */
141 { 0x5f, 0x00 }, /* 5F */
142 { 0x60, 0x00 }, /* 60 */
143 { 0x61, 0x00 }, /* 61 */
144 { 0x62, 0x00 }, /* 62 */
145 { 0x63, 0x00 }, /* 63 */
146 { 0x64, 0x00 }, /* 64 */
147 { 0x65, 0x00 }, /* 65 */
148 { 0x66, 0x00 }, /* 66 */
149 { 0x67, 0x00 }, /* 67 */
150 { 0x68, 0x00 }, /* 68 */
151 { 0x69, 0x00 }, /* 69 */
152 { 0x6a, 0x00 }, /* 6A */
153 { 0x6b, 0x00 }, /* 6B */
154 { 0x6c, 0x00 }, /* 6C */
155 { 0x6d, 0x00 }, /* 6D */
156 { 0x6e, 0x00 }, /* 6E */
157 { 0x6f, 0x00 }, /* 6F */
158 { 0x70, 0x00 }, /* 70 */
159 { 0x71, 0x00 }, /* 71 */
160 { 0x72, 0x00 }, /* 72 */
161 { 0x73, 0x00 }, /* 73 */
162 { 0x74, 0x00 }, /* 74 */
163 { 0x75, 0x00 }, /* 75 */
164 { 0x76, 0x00 }, /* 76 */
165 { 0x77, 0x00 }, /* 77 */
166 { 0x78, 0x00 }, /* 78 */
167 { 0x79, 0x00 }, /* 79 */
168 { 0x7a, 0x00 }, /* 7A */
169 { 0x7b, 0x00 }, /* 7B */
170 { 0x7c, 0x00 }, /* 7C */
171 { 0x7d, 0x00 }, /* 7D */
172 { 0x7e, 0x00 }, /* 7E */
173 { 0x7f, 0x00 }, /* 7F */
174 { 0x80, 0x00 }, /* 80 */
175 { 0x81, 0x00 }, /* 81 */
176 { 0x82, 0x00 }, /* 82 */
177 { 0x83, 0x00 }, /* 83 */
178 { 0x84, 0x00 }, /* 84 */
179 { 0x85, 0x00 }, /* 85 */
180 { 0x86, 0x00 }, /* 86 */
181 { 0x87, 0x00 }, /* 87 */
182 { 0x88, 0x00 }, /* 88 */
183 { 0x89, 0x00 }, /* 89 */
184 { 0x8a, 0x00 }, /* 8A */
185 { 0x8b, 0x00 }, /* 8B */
186 { 0x8c, 0x00 }, /* 8C */
187 { 0x8d, 0x00 }, /* 8D */
188 { 0x8e, 0x00 }, /* 8E */
189 { 0x8f, 0x00 }, /* 8F */
190 { 0x90, 0x00 }, /* 90 */
191 { 0x91, 0x00 }, /* 91 */
192 { 0x92, 0x30 }, /* 92 */
193 { 0x93, 0xF0 }, /* 93 */
194 { 0x94, 0x00 }, /* 94 */
195 { 0x95, 0x00 }, /* 95 */
196 { 0x96, 0x3F }, /* 96 */
197 { 0x97, 0x00 }, /* 97 */
198 { 0xff, 0x00 }, /* FF */
82a5a936
PH		 199};
200
201static struct {
202 int readable;
203 int writable;
204} max98095_access[M98095_REG_CNT] = {
205 { 0x00, 0x00 }, /* 00 */
206 { 0xFF, 0x00 }, /* 01 */
207 { 0xFF, 0x00 }, /* 02 */
208 { 0xFF, 0x00 }, /* 03 */
209 { 0xFF, 0x00 }, /* 04 */
210 { 0xFF, 0x00 }, /* 05 */
211 { 0xFF, 0x00 }, /* 06 */
212 { 0xFF, 0x00 }, /* 07 */
213 { 0xFF, 0x00 }, /* 08 */
214 { 0xFF, 0x00 }, /* 09 */
215 { 0xFF, 0x00 }, /* 0A */
216 { 0xFF, 0x00 }, /* 0B */
217 { 0xFF, 0x00 }, /* 0C */
218 { 0xFF, 0x00 }, /* 0D */
219 { 0xFF, 0x00 }, /* 0E */
220 { 0xFF, 0x9F }, /* 0F */
221 { 0xFF, 0xFF }, /* 10 */
222 { 0xFF, 0xFF }, /* 11 */
223 { 0xFF, 0xFF }, /* 12 */
224 { 0xFF, 0xFF }, /* 13 */
225 { 0xFF, 0xFF }, /* 14 */
226 { 0xFF, 0xFF }, /* 15 */
227 { 0xFF, 0xFF }, /* 16 */
228 { 0xFF, 0xFF }, /* 17 */
229 { 0xFF, 0xFF }, /* 18 */
230 { 0xFF, 0xFF }, /* 19 */
231 { 0xFF, 0xFF }, /* 1A */
232 { 0xFF, 0xFF }, /* 1B */
233 { 0xFF, 0xFF }, /* 1C */
234 { 0xFF, 0xFF }, /* 1D */
235 { 0xFF, 0x77 }, /* 1E */
236 { 0xFF, 0x77 }, /* 1F */
237 { 0xFF, 0x77 }, /* 20 */
238 { 0xFF, 0x77 }, /* 21 */
239 { 0xFF, 0x77 }, /* 22 */
240 { 0xFF, 0x77 }, /* 23 */
241 { 0xFF, 0xFF }, /* 24 */
242 { 0xFF, 0x7F }, /* 25 */
243 { 0xFF, 0x31 }, /* 26 */
244 { 0xFF, 0xFF }, /* 27 */
245 { 0xFF, 0xFF }, /* 28 */
246 { 0xFF, 0xFF }, /* 29 */
247 { 0xFF, 0xF7 }, /* 2A */
248 { 0xFF, 0x2F }, /* 2B */
249 { 0xFF, 0xEF }, /* 2C */
250 { 0xFF, 0xFF }, /* 2D */
251 { 0xFF, 0xFF }, /* 2E */
252 { 0xFF, 0xFF }, /* 2F */
253 { 0xFF, 0xFF }, /* 30 */
254 { 0xFF, 0xFF }, /* 31 */
255 { 0xFF, 0xFF }, /* 32 */
256 { 0xFF, 0xFF }, /* 33 */
257 { 0xFF, 0xF7 }, /* 34 */
258 { 0xFF, 0x2F }, /* 35 */
259 { 0xFF, 0xCF }, /* 36 */
260 { 0xFF, 0xFF }, /* 37 */
261 { 0xFF, 0xFF }, /* 38 */
262 { 0xFF, 0xFF }, /* 39 */
263 { 0xFF, 0xFF }, /* 3A */
264 { 0xFF, 0xFF }, /* 3B */
265 { 0xFF, 0xFF }, /* 3C */
266 { 0xFF, 0xFF }, /* 3D */
267 { 0xFF, 0xF7 }, /* 3E */
268 { 0xFF, 0x2F }, /* 3F */
269 { 0xFF, 0xCF }, /* 40 */
270 { 0xFF, 0xFF }, /* 41 */
271 { 0xFF, 0x77 }, /* 42 */
272 { 0xFF, 0xFF }, /* 43 */
273 { 0xFF, 0xFF }, /* 44 */
274 { 0xFF, 0xFF }, /* 45 */
275 { 0xFF, 0xFF }, /* 46 */
276 { 0xFF, 0xFF }, /* 47 */
277 { 0xFF, 0xFF }, /* 48 */
278 { 0xFF, 0x0F }, /* 49 */
279 { 0xFF, 0xFF }, /* 4A */
280 { 0xFF, 0xFF }, /* 4B */
281 { 0xFF, 0x3F }, /* 4C */
282 { 0xFF, 0x3F }, /* 4D */
283 { 0xFF, 0x3F }, /* 4E */
284 { 0xFF, 0xFF }, /* 4F */
285 { 0xFF, 0x7F }, /* 50 */
286 { 0xFF, 0x7F }, /* 51 */
287 { 0xFF, 0x0F }, /* 52 */
288 { 0xFF, 0x3F }, /* 53 */
289 { 0xFF, 0x3F }, /* 54 */
290 { 0xFF, 0x3F }, /* 55 */
291 { 0xFF, 0xFF }, /* 56 */
292 { 0xFF, 0xFF }, /* 57 */
293 { 0xFF, 0xBF }, /* 58 */
294 { 0xFF, 0x1F }, /* 59 */
295 { 0xFF, 0xBF }, /* 5A */
296 { 0xFF, 0x1F }, /* 5B */
297 { 0xFF, 0xBF }, /* 5C */
298 { 0xFF, 0x3F }, /* 5D */
299 { 0xFF, 0x3F }, /* 5E */
300 { 0xFF, 0x7F }, /* 5F */
301 { 0xFF, 0x7F }, /* 60 */
302 { 0xFF, 0x47 }, /* 61 */
303 { 0xFF, 0x9F }, /* 62 */
304 { 0xFF, 0x9F }, /* 63 */
305 { 0xFF, 0x9F }, /* 64 */
306 { 0xFF, 0x9F }, /* 65 */
307 { 0xFF, 0x9F }, /* 66 */
308 { 0xFF, 0xBF }, /* 67 */
309 { 0xFF, 0xBF }, /* 68 */
310 { 0xFF, 0xFF }, /* 69 */
311 { 0xFF, 0xFF }, /* 6A */
312 { 0xFF, 0x7F }, /* 6B */
313 { 0xFF, 0xF7 }, /* 6C */
314 { 0xFF, 0xFF }, /* 6D */
315 { 0xFF, 0xFF }, /* 6E */
316 { 0xFF, 0x1F }, /* 6F */
317 { 0xFF, 0xF7 }, /* 70 */
318 { 0xFF, 0xFF }, /* 71 */
319 { 0xFF, 0xFF }, /* 72 */
320 { 0xFF, 0x1F }, /* 73 */
321 { 0xFF, 0xF7 }, /* 74 */
322 { 0xFF, 0xFF }, /* 75 */
323 { 0xFF, 0xFF }, /* 76 */
324 { 0xFF, 0x1F }, /* 77 */
325 { 0xFF, 0xF7 }, /* 78 */
326 { 0xFF, 0xFF }, /* 79 */
327 { 0xFF, 0xFF }, /* 7A */
328 { 0xFF, 0x1F }, /* 7B */
329 { 0xFF, 0xF7 }, /* 7C */
330 { 0xFF, 0xFF }, /* 7D */
331 { 0xFF, 0xFF }, /* 7E */
332 { 0xFF, 0x1F }, /* 7F */
333 { 0xFF, 0xF7 }, /* 80 */
334 { 0xFF, 0xFF }, /* 81 */
335 { 0xFF, 0xFF }, /* 82 */
336 { 0xFF, 0x1F }, /* 83 */
337 { 0xFF, 0x7F }, /* 84 */
338 { 0xFF, 0x0F }, /* 85 */
339 { 0xFF, 0xD8 }, /* 86 */
340 { 0xFF, 0xFF }, /* 87 */
341 { 0xFF, 0xEF }, /* 88 */
342 { 0xFF, 0xFE }, /* 89 */
343 { 0xFF, 0xFE }, /* 8A */
344 { 0xFF, 0xFF }, /* 8B */
345 { 0xFF, 0xFF }, /* 8C */
346 { 0xFF, 0x3F }, /* 8D */
347 { 0xFF, 0xFF }, /* 8E */
348 { 0xFF, 0x3F }, /* 8F */
349 { 0xFF, 0x8F }, /* 90 */
350 { 0xFF, 0xFF }, /* 91 */
351 { 0xFF, 0x3F }, /* 92 */
352 { 0xFF, 0xFF }, /* 93 */
353 { 0xFF, 0xFF }, /* 94 */
354 { 0xFF, 0x0F }, /* 95 */
355 { 0xFF, 0x3F }, /* 96 */
356 { 0xFF, 0x8C }, /* 97 */
357 { 0x00, 0x00 }, /* 98 */
358 { 0x00, 0x00 }, /* 99 */
359 { 0x00, 0x00 }, /* 9A */
360 { 0x00, 0x00 }, /* 9B */
361 { 0x00, 0x00 }, /* 9C */
362 { 0x00, 0x00 }, /* 9D */
363 { 0x00, 0x00 }, /* 9E */
364 { 0x00, 0x00 }, /* 9F */
365 { 0x00, 0x00 }, /* A0 */
366 { 0x00, 0x00 }, /* A1 */
367 { 0x00, 0x00 }, /* A2 */
368 { 0x00, 0x00 }, /* A3 */
369 { 0x00, 0x00 }, /* A4 */
370 { 0x00, 0x00 }, /* A5 */
371 { 0x00, 0x00 }, /* A6 */
372 { 0x00, 0x00 }, /* A7 */
373 { 0x00, 0x00 }, /* A8 */
374 { 0x00, 0x00 }, /* A9 */
375 { 0x00, 0x00 }, /* AA */
376 { 0x00, 0x00 }, /* AB */
377 { 0x00, 0x00 }, /* AC */
378 { 0x00, 0x00 }, /* AD */
379 { 0x00, 0x00 }, /* AE */
380 { 0x00, 0x00 }, /* AF */
381 { 0x00, 0x00 }, /* B0 */
382 { 0x00, 0x00 }, /* B1 */
383 { 0x00, 0x00 }, /* B2 */
384 { 0x00, 0x00 }, /* B3 */
385 { 0x00, 0x00 }, /* B4 */
386 { 0x00, 0x00 }, /* B5 */
387 { 0x00, 0x00 }, /* B6 */
388 { 0x00, 0x00 }, /* B7 */
389 { 0x00, 0x00 }, /* B8 */
390 { 0x00, 0x00 }, /* B9 */
391 { 0x00, 0x00 }, /* BA */
392 { 0x00, 0x00 }, /* BB */
393 { 0x00, 0x00 }, /* BC */
394 { 0x00, 0x00 }, /* BD */
395 { 0x00, 0x00 }, /* BE */
396 { 0x00, 0x00 }, /* BF */
397 { 0x00, 0x00 }, /* C0 */
398 { 0x00, 0x00 }, /* C1 */
399 { 0x00, 0x00 }, /* C2 */
400 { 0x00, 0x00 }, /* C3 */
401 { 0x00, 0x00 }, /* C4 */
402 { 0x00, 0x00 }, /* C5 */
403 { 0x00, 0x00 }, /* C6 */
404 { 0x00, 0x00 }, /* C7 */
405 { 0x00, 0x00 }, /* C8 */
406 { 0x00, 0x00 }, /* C9 */
407 { 0x00, 0x00 }, /* CA */
408 { 0x00, 0x00 }, /* CB */
409 { 0x00, 0x00 }, /* CC */
410 { 0x00, 0x00 }, /* CD */
411 { 0x00, 0x00 }, /* CE */
412 { 0x00, 0x00 }, /* CF */
413 { 0x00, 0x00 }, /* D0 */
414 { 0x00, 0x00 }, /* D1 */
415 { 0x00, 0x00 }, /* D2 */
416 { 0x00, 0x00 }, /* D3 */
417 { 0x00, 0x00 }, /* D4 */
418 { 0x00, 0x00 }, /* D5 */
419 { 0x00, 0x00 }, /* D6 */
420 { 0x00, 0x00 }, /* D7 */
421 { 0x00, 0x00 }, /* D8 */
422 { 0x00, 0x00 }, /* D9 */
423 { 0x00, 0x00 }, /* DA */
424 { 0x00, 0x00 }, /* DB */
425 { 0x00, 0x00 }, /* DC */
426 { 0x00, 0x00 }, /* DD */
427 { 0x00, 0x00 }, /* DE */
428 { 0x00, 0x00 }, /* DF */
429 { 0x00, 0x00 }, /* E0 */
430 { 0x00, 0x00 }, /* E1 */
431 { 0x00, 0x00 }, /* E2 */
432 { 0x00, 0x00 }, /* E3 */
433 { 0x00, 0x00 }, /* E4 */
434 { 0x00, 0x00 }, /* E5 */
435 { 0x00, 0x00 }, /* E6 */
436 { 0x00, 0x00 }, /* E7 */
437 { 0x00, 0x00 }, /* E8 */
438 { 0x00, 0x00 }, /* E9 */
439 { 0x00, 0x00 }, /* EA */
440 { 0x00, 0x00 }, /* EB */
441 { 0x00, 0x00 }, /* EC */
442 { 0x00, 0x00 }, /* ED */
443 { 0x00, 0x00 }, /* EE */
444 { 0x00, 0x00 }, /* EF */
445 { 0x00, 0x00 }, /* F0 */
446 { 0x00, 0x00 }, /* F1 */
447 { 0x00, 0x00 }, /* F2 */
448 { 0x00, 0x00 }, /* F3 */
449 { 0x00, 0x00 }, /* F4 */
450 { 0x00, 0x00 }, /* F5 */
451 { 0x00, 0x00 }, /* F6 */
452 { 0x00, 0x00 }, /* F7 */
453 { 0x00, 0x00 }, /* F8 */
454 { 0x00, 0x00 }, /* F9 */
455 { 0x00, 0x00 }, /* FA */
456 { 0x00, 0x00 }, /* FB */
457 { 0x00, 0x00 }, /* FC */
458 { 0x00, 0x00 }, /* FD */
459 { 0x00, 0x00 }, /* FE */
460 { 0xFF, 0x00 }, /* FF */
461};
462
14acbbbb 463static bool max98095_readable(struct device *dev, unsigned int reg)
82a5a936
PH		 464{
465 if (reg >= M98095_REG_CNT)
466 return 0;
467 return max98095_access[reg].readable != 0;
468}
469
14acbbbb 470static bool max98095_volatile(struct device *dev, unsigned int reg)
82a5a936
PH		 471{
472 if (reg > M98095_REG_MAX_CACHED)
473 return 1;
474
475 switch (reg) {
476 case M98095_000_HOST_DATA:
477 case M98095_001_HOST_INT_STS:
478 case M98095_002_HOST_RSP_STS:
479 case M98095_003_HOST_CMD_STS:
480 case M98095_004_CODEC_STS:
481 case M98095_005_DAI1_ALC_STS:
482 case M98095_006_DAI2_ALC_STS:
483 case M98095_007_JACK_AUTO_STS:
484 case M98095_008_JACK_MANUAL_STS:
485 case M98095_009_JACK_VBAT_STS:
486 case M98095_00A_ACC_ADC_STS:
487 case M98095_00B_MIC_NG_AGC_STS:
488 case M98095_00C_SPK_L_VOLT_STS:
489 case M98095_00D_SPK_R_VOLT_STS:
490 case M98095_00E_TEMP_SENSOR_STS:
491 return 1;
492 }
493
494 return 0;
495}
496
14acbbbb
MB		 497static const struct regmap_config max98095_regmap = {
498 .reg_bits = 8,
499 .val_bits = 8,
dad31ec1 500
14acbbbb
MB		 501 .reg_defaults = max98095_reg_def,
502 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
503 .max_register = M98095_0FF_REV_ID,
504 .cache_type = REGCACHE_RBTREE,
0d8d2938 505
14acbbbb
MB		 506 .readable_reg = max98095_readable,
507 .volatile_reg = max98095_volatile,
508};
dad31ec1
PH		 509
510/*
511 * Load equalizer DSP coefficient configurations registers
512 */
513static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
514 unsigned int band, u16 *coefs)
515{
516 unsigned int eq_reg;
517 unsigned int i;
518
a922cd71
TI		 519 if (WARN_ON(band > 4) ||
520 WARN_ON(dai > 1))
521 return;
dad31ec1
PH		 522
523 /* Load the base register address */
524 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
525
526 /* Add the band address offset, note adjustment for word address */
527 eq_reg += band * (M98095_COEFS_PER_BAND << 1);
528
529 /* Step through the registers and coefs */
530 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
d36126ac
MB		 531 snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
532 snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
dad31ec1
PH		 533 }
534}
535
536/*
537 * Load biquad filter coefficient configurations registers
538 */
539static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
540 unsigned int band, u16 *coefs)
541{
542 unsigned int bq_reg;
543 unsigned int i;
544
a922cd71
TI		 545 if (WARN_ON(band > 1) ||
546 WARN_ON(dai > 1))
547 return;
dad31ec1
PH		 548
549 /* Load the base register address */
550 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
551
552 /* Add the band address offset, note adjustment for word address */
553 bq_reg += band * (M98095_COEFS_PER_BAND << 1);
554
555 /* Step through the registers and coefs */
556 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
d36126ac
MB		 557 snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
558 snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
dad31ec1
PH		 559 }
560}
561
82a5a936
PH		 562static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
563static const struct soc_enum max98095_dai1_filter_mode_enum[] = {
564 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode),
565};
566static const struct soc_enum max98095_dai2_filter_mode_enum[] = {
567 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode),
568};
569
570static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
571
572static const struct soc_enum max98095_extmic_enum =
573 SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text);
574
575static const struct snd_kcontrol_new max98095_extmic_mux =
576 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
577
578static const char * const max98095_linein_text[] = { "INA", "INB" };
579
580static const struct soc_enum max98095_linein_enum =
581 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text);
582
583static const struct snd_kcontrol_new max98095_linein_mux =
584 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
585
586static const char * const max98095_line_mode_text[] = {
587 "Stereo", "Differential"};
588
589static const struct soc_enum max98095_linein_mode_enum =
590 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text);
591
592static const struct soc_enum max98095_lineout_mode_enum =
593 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text);
594
595static const char * const max98095_dai_fltr[] = {
596 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
597 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
598static const struct soc_enum max98095_dai1_dac_filter_enum[] = {
599 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr),
600};
601static const struct soc_enum max98095_dai2_dac_filter_enum[] = {
602 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr),
603};
604static const struct soc_enum max98095_dai3_dac_filter_enum[] = {
605 SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr),
606};
607
608static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
609 struct snd_ctl_elem_value *ucontrol)
610{
611 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
612 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
613 unsigned int sel = ucontrol->value.integer.value[0];
614
615 max98095->mic1pre = sel;
616 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
617 (1+sel)<<M98095_MICPRE_SHIFT);
618
619 return 0;
620}
621
622static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
623 struct snd_ctl_elem_value *ucontrol)
624{
625 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
626 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
627
628 ucontrol->value.integer.value[0] = max98095->mic1pre;
629 return 0;
630}
631
632static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
633 struct snd_ctl_elem_value *ucontrol)
634{
635 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
636 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
637 unsigned int sel = ucontrol->value.integer.value[0];
638
639 max98095->mic2pre = sel;
640 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
641 (1+sel)<<M98095_MICPRE_SHIFT);
642
643 return 0;
644}
645
646static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
647 struct snd_ctl_elem_value *ucontrol)
648{
649 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
650 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
651
652 ucontrol->value.integer.value[0] = max98095->mic2pre;
653 return 0;
654}
655
656static const unsigned int max98095_micboost_tlv[] = {
657 TLV_DB_RANGE_HEAD(2),
658 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
659 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
660};
661
662static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
663static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
664static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
665
666static const unsigned int max98095_hp_tlv[] = {
667 TLV_DB_RANGE_HEAD(5),
668 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
669 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
670 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
671 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
672 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
673};
674
675static const unsigned int max98095_spk_tlv[] = {
676 TLV_DB_RANGE_HEAD(4),
677 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
678 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
679 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
680 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0),
681};
682
683static const unsigned int max98095_rcv_lout_tlv[] = {
684 TLV_DB_RANGE_HEAD(5),
685 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
686 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
687 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
688 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
689 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
690};
691
692static const unsigned int max98095_lin_tlv[] = {
693 TLV_DB_RANGE_HEAD(3),
694 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
695 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
696 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
697};
698
699static const struct snd_kcontrol_new max98095_snd_controls[] = {
700
701 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
702 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
703
704 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
705 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
706
707 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
708 0, 31, 0, max98095_rcv_lout_tlv),
709
710 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
711 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
712
713 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
714 M98095_065_LVL_HP_R, 7, 1, 1),
715
716 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
717 M98095_068_LVL_SPK_R, 7, 1, 1),
718
719 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
720
721 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
722 M98095_063_LVL_LINEOUT2, 7, 1, 1),
723
724 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
725 max98095_mic_tlv),
726
727 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
728 max98095_mic_tlv),
729
730 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
731 M98095_05F_LVL_MIC1, 5, 2, 0,
732 max98095_mic1pre_get, max98095_mic1pre_set,
733 max98095_micboost_tlv),
734 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
735 M98095_060_LVL_MIC2, 5, 2, 0,
736 max98095_mic2pre_get, max98095_mic2pre_set,
737 max98095_micboost_tlv),
738
739 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
740 max98095_lin_tlv),
741
742 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
743 max98095_adc_tlv),
744 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
745 max98095_adc_tlv),
746
747 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
748 max98095_adcboost_tlv),
749 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
750 max98095_adcboost_tlv),
751
dad31ec1
PH		 752 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
753 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
754
755 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
756 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
757
82a5a936
PH		 758 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
759 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
760 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
761 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
762 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
763
764 SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
765 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
766};
767
768/* Left speaker mixer switch */
769static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
770 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
771 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
772 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
773 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
774 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
775 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
776 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
777 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
778};
779
780/* Right speaker mixer switch */
781static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
782 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
783 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
784 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
785 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
786 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
787 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
788 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
789 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
790};
791
792/* Left headphone mixer switch */
793static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
794 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
795 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
796 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
797 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
798 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
799 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
800};
801
802/* Right headphone mixer switch */
803static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
804 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
805 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
806 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
807 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
808 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
809 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
810};
811
812/* Receiver earpiece mixer switch */
813static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
814 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
815 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
816 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
817 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
818 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
819 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
820};
821
822/* Left lineout mixer switch */
823static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
824 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
825 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
826 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
827 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
828 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
829 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
830};
831
832/* Right lineout mixer switch */
833static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
834 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
835 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
836 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
837 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
838 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
839 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
840};
841
842/* Left ADC mixer switch */
843static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
844 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
845 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
846 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
847 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
848};
849
850/* Right ADC mixer switch */
851static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
852 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
853 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
854 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
855 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
856};
857
858static int max98095_mic_event(struct snd_soc_dapm_widget *w,
859 struct snd_kcontrol *kcontrol, int event)
860{
861 struct snd_soc_codec *codec = w->codec;
862 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
863
864 switch (event) {
865 case SND_SOC_DAPM_POST_PMU:
866 if (w->reg == M98095_05F_LVL_MIC1) {
867 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
868 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
869 } else {
870 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
871 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
872 }
873 break;
874 case SND_SOC_DAPM_POST_PMD:
875 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0);
876 break;
877 default:
878 return -EINVAL;
879 }
880
881 return 0;
882}
883
884/*
885 * The line inputs are stereo inputs with the left and right
886 * channels sharing a common PGA power control signal.
887 */
888static int max98095_line_pga(struct snd_soc_dapm_widget *w,
889 int event, u8 channel)
890{
891 struct snd_soc_codec *codec = w->codec;
892 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
893 u8 *state;
894
a922cd71
TI		 895 if (WARN_ON(!(channel == 1 || channel == 2)))
896 return -EINVAL;
82a5a936
PH		 897
898 state = &max98095->lin_state;
899
900 switch (event) {
901 case SND_SOC_DAPM_POST_PMU:
902 *state |= channel;
903 snd_soc_update_bits(codec, w->reg,
904 (1 << w->shift), (1 << w->shift));
905 break;
906 case SND_SOC_DAPM_POST_PMD:
907 *state &= ~channel;
908 if (*state == 0) {
909 snd_soc_update_bits(codec, w->reg,
910 (1 << w->shift), 0);
911 }
912 break;
913 default:
914 return -EINVAL;
915 }
916
917 return 0;
918}
919
920static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
921 struct snd_kcontrol *k, int event)
922{
923 return max98095_line_pga(w, event, 1);
924}
925
926static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
927 struct snd_kcontrol *k, int event)
928{
929 return max98095_line_pga(w, event, 2);
930}
931
932/*
933 * The stereo line out mixer outputs to two stereo line outs.
934 * The 2nd pair has a separate set of enables.
935 */
936static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
937 struct snd_kcontrol *kcontrol, int event)
938{
939 struct snd_soc_codec *codec = w->codec;
940
941 switch (event) {
942 case SND_SOC_DAPM_POST_PMU:
943 snd_soc_update_bits(codec, w->reg,
944 (1 << (w->shift+2)), (1 << (w->shift+2)));
945 break;
946 case SND_SOC_DAPM_POST_PMD:
947 snd_soc_update_bits(codec, w->reg,
948 (1 << (w->shift+2)), 0);
949 break;
950 default:
951 return -EINVAL;
952 }
953
954 return 0;
955}
956
957static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
958
959 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
960 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
961
962 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
963 M98095_091_PWR_EN_OUT, 0, 0),
964 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
965 M98095_091_PWR_EN_OUT, 1, 0),
966 SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
967 M98095_091_PWR_EN_OUT, 2, 0),
968 SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
969 M98095_091_PWR_EN_OUT, 2, 0),
970
971 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
972 6, 0, NULL, 0),
973 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
974 7, 0, NULL, 0),
975
976 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
977 4, 0, NULL, 0),
978 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
979 5, 0, NULL, 0),
980
981 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
982 3, 0, NULL, 0),
983
984 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
985 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
986 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
987 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
988
989 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
990 &max98095_extmic_mux),
991
992 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
993 &max98095_linein_mux),
994
995 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
996 &max98095_left_hp_mixer_controls[0],
997 ARRAY_SIZE(max98095_left_hp_mixer_controls)),
998
999 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1000 &max98095_right_hp_mixer_controls[0],
1001 ARRAY_SIZE(max98095_right_hp_mixer_controls)),
1002
1003 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1004 &max98095_left_speaker_mixer_controls[0],
1005 ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
1006
1007 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1008 &max98095_right_speaker_mixer_controls[0],
1009 ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
1010
1011 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
1012 &max98095_mono_rcv_mixer_controls[0],
1013 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
1014
1015 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
1016 &max98095_left_lineout_mixer_controls[0],
1017 ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
1018
1019 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
1020 &max98095_right_lineout_mixer_controls[0],
1021 ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
1022
1023 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1024 &max98095_left_ADC_mixer_controls[0],
1025 ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
1026
1027 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1028 &max98095_right_ADC_mixer_controls[0],
1029 ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
1030
1031 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
1032 5, 0, NULL, 0, max98095_mic_event,
1033 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1034
1035 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
1036 5, 0, NULL, 0, max98095_mic_event,
1037 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1038
1039 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
1040 7, 0, NULL, 0, max98095_pga_in1_event,
1041 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1042
1043 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
1044 7, 0, NULL, 0, max98095_pga_in2_event,
1045 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1046
1047 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
1048 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
1049
1050 SND_SOC_DAPM_OUTPUT("HPL"),
1051 SND_SOC_DAPM_OUTPUT("HPR"),
1052 SND_SOC_DAPM_OUTPUT("SPKL"),
1053 SND_SOC_DAPM_OUTPUT("SPKR"),
1054 SND_SOC_DAPM_OUTPUT("RCV"),
1055 SND_SOC_DAPM_OUTPUT("OUT1"),
1056 SND_SOC_DAPM_OUTPUT("OUT2"),
1057 SND_SOC_DAPM_OUTPUT("OUT3"),
1058 SND_SOC_DAPM_OUTPUT("OUT4"),
1059
1060 SND_SOC_DAPM_INPUT("MIC1"),
1061 SND_SOC_DAPM_INPUT("MIC2"),
1062 SND_SOC_DAPM_INPUT("INA1"),
1063 SND_SOC_DAPM_INPUT("INA2"),
1064 SND_SOC_DAPM_INPUT("INB1"),
1065 SND_SOC_DAPM_INPUT("INB2"),
1066};
1067
1068static const struct snd_soc_dapm_route max98095_audio_map[] = {
1069 /* Left headphone output mixer */
1070 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1071 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1072 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1073 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1074 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
1075 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
1076
1077 /* Right headphone output mixer */
1078 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1079 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1080 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1081 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1082 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
1083 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
1084
1085 /* Left speaker output mixer */
1086 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1087 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1088 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1089 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1090 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1091 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1092 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
1093 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
1094
1095 /* Right speaker output mixer */
1096 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1097 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1098 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1099 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1100 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1101 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1102 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
1103 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
1104
1105 /* Earpiece/Receiver output mixer */
1106 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
1107 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
1108 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1109 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1110 {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
1111 {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
1112
1113 /* Left Lineout output mixer */
1114 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1115 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1116 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1117 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1118 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
1119 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
1120
1121 /* Right lineout output mixer */
1122 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1123 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1124 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1125 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1126 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
1127 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
1128
1129 {"HP Left Out", NULL, "Left Headphone Mixer"},
1130 {"HP Right Out", NULL, "Right Headphone Mixer"},
1131 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1132 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1133 {"RCV Mono Out", NULL, "Receiver Mixer"},
1134 {"LINE Left Out", NULL, "Left Lineout Mixer"},
1135 {"LINE Right Out", NULL, "Right Lineout Mixer"},
1136
1137 {"HPL", NULL, "HP Left Out"},
1138 {"HPR", NULL, "HP Right Out"},
1139 {"SPKL", NULL, "SPK Left Out"},
1140 {"SPKR", NULL, "SPK Right Out"},
1141 {"RCV", NULL, "RCV Mono Out"},
1142 {"OUT1", NULL, "LINE Left Out"},
1143 {"OUT2", NULL, "LINE Right Out"},
1144 {"OUT3", NULL, "LINE Left Out"},
1145 {"OUT4", NULL, "LINE Right Out"},
1146
1147 /* Left ADC input mixer */
1148 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1149 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1150 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
1151 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
1152
1153 /* Right ADC input mixer */
1154 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1155 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1156 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
1157 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
1158
1159 /* Inputs */
1160 {"ADCL", NULL, "Left ADC Mixer"},
1161 {"ADCR", NULL, "Right ADC Mixer"},
1162
1163 {"IN1 Input", NULL, "INA1"},
1164 {"IN2 Input", NULL, "INA2"},
1165
1166 {"MIC1 Input", NULL, "MIC1"},
1167 {"MIC2 Input", NULL, "MIC2"},
1168};
1169
82a5a936
PH		 1170/* codec mclk clock divider coefficients */
1171static const struct {
1172 u32 rate;
1173 u8 sr;
1174} rate_table[] = {
1175 {8000, 0x01},
1176 {11025, 0x02},
1177 {16000, 0x03},
1178 {22050, 0x04},
1179 {24000, 0x05},
1180 {32000, 0x06},
1181 {44100, 0x07},
1182 {48000, 0x08},
1183 {88200, 0x09},
1184 {96000, 0x0A},
1185};
1186
1187static int rate_value(int rate, u8 *value)
1188{
1189 int i;
1190
1191 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1192 if (rate_table[i].rate >= rate) {
1193 *value = rate_table[i].sr;
1194 return 0;
1195 }
1196 }
1197 *value = rate_table[0].sr;
1198 return -EINVAL;
1199}
1200
1201static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
1202 struct snd_pcm_hw_params *params,
1203 struct snd_soc_dai *dai)
1204{
1205 struct snd_soc_codec *codec = dai->codec;
1206 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1207 struct max98095_cdata *cdata;
1208 unsigned long long ni;
1209 unsigned int rate;
1210 u8 regval;
1211
1212 cdata = &max98095->dai[0];
1213
1214 rate = params_rate(params);
1215
1216 switch (params_format(params)) {
1217 case SNDRV_PCM_FORMAT_S16_LE:
1218 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1219 M98095_DAI_WS, 0);
1220 break;
1221 case SNDRV_PCM_FORMAT_S24_LE:
1222 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1223 M98095_DAI_WS, M98095_DAI_WS);
1224 break;
1225 default:
1226 return -EINVAL;
1227 }
1228
1229 if (rate_value(rate, &regval))
1230 return -EINVAL;
1231
1232 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE,
1233 M98095_CLKMODE_MASK, regval);
1234 cdata->rate = rate;
1235
1236 /* Configure NI when operating as master */
1237 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
1238 if (max98095->sysclk == 0) {
1239 dev_err(codec->dev, "Invalid system clock frequency\n");
1240 return -EINVAL;
1241 }
1242 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1243 * (unsigned long long int)rate;
1244 do_div(ni, (unsigned long long int)max98095->sysclk);
1245 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1246 (ni >> 8) & 0x7F);
1247 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1248 ni & 0xFF);
1249 }
1250
1251 /* Update sample rate mode */
1252 if (rate < 50000)
1253 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1254 M98095_DAI_DHF, 0);
1255 else
1256 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1257 M98095_DAI_DHF, M98095_DAI_DHF);
1258
1259 return 0;
1260}
1261
1262static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1263 struct snd_pcm_hw_params *params,
1264 struct snd_soc_dai *dai)
1265{
1266 struct snd_soc_codec *codec = dai->codec;
1267 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1268 struct max98095_cdata *cdata;
1269 unsigned long long ni;
1270 unsigned int rate;
1271 u8 regval;
1272
1273 cdata = &max98095->dai[1];
1274
1275 rate = params_rate(params);
1276
1277 switch (params_format(params)) {
1278 case SNDRV_PCM_FORMAT_S16_LE:
1279 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1280 M98095_DAI_WS, 0);
1281 break;
1282 case SNDRV_PCM_FORMAT_S24_LE:
1283 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1284 M98095_DAI_WS, M98095_DAI_WS);
1285 break;
1286 default:
1287 return -EINVAL;
1288 }
1289
1290 if (rate_value(rate, &regval))
1291 return -EINVAL;
1292
1293 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE,
1294 M98095_CLKMODE_MASK, regval);
1295 cdata->rate = rate;
1296
1297 /* Configure NI when operating as master */
1298 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1299 if (max98095->sysclk == 0) {
1300 dev_err(codec->dev, "Invalid system clock frequency\n");
1301 return -EINVAL;
1302 }
1303 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1304 * (unsigned long long int)rate;
1305 do_div(ni, (unsigned long long int)max98095->sysclk);
1306 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1307 (ni >> 8) & 0x7F);
1308 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1309 ni & 0xFF);
1310 }
1311
1312 /* Update sample rate mode */
1313 if (rate < 50000)
1314 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1315 M98095_DAI_DHF, 0);
1316 else
1317 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1318 M98095_DAI_DHF, M98095_DAI_DHF);
1319
1320 return 0;
1321}
1322
1323static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1324 struct snd_pcm_hw_params *params,
1325 struct snd_soc_dai *dai)
1326{
1327 struct snd_soc_codec *codec = dai->codec;
1328 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1329 struct max98095_cdata *cdata;
1330 unsigned long long ni;
1331 unsigned int rate;
1332 u8 regval;
1333
1334 cdata = &max98095->dai[2];
1335
1336 rate = params_rate(params);
1337
1338 switch (params_format(params)) {
1339 case SNDRV_PCM_FORMAT_S16_LE:
1340 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1341 M98095_DAI_WS, 0);
1342 break;
1343 case SNDRV_PCM_FORMAT_S24_LE:
1344 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1345 M98095_DAI_WS, M98095_DAI_WS);
1346 break;
1347 default:
1348 return -EINVAL;
1349 }
1350
1351 if (rate_value(rate, &regval))
1352 return -EINVAL;
1353
1354 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE,
1355 M98095_CLKMODE_MASK, regval);
1356 cdata->rate = rate;
1357
1358 /* Configure NI when operating as master */
1359 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1360 if (max98095->sysclk == 0) {
1361 dev_err(codec->dev, "Invalid system clock frequency\n");
1362 return -EINVAL;
1363 }
1364 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1365 * (unsigned long long int)rate;
1366 do_div(ni, (unsigned long long int)max98095->sysclk);
1367 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1368 (ni >> 8) & 0x7F);
1369 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1370 ni & 0xFF);
1371 }
1372
1373 /* Update sample rate mode */
1374 if (rate < 50000)
1375 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1376 M98095_DAI_DHF, 0);
1377 else
1378 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1379 M98095_DAI_DHF, M98095_DAI_DHF);
1380
1381 return 0;
1382}
1383
1384static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1385 int clk_id, unsigned int freq, int dir)
1386{
1387 struct snd_soc_codec *codec = dai->codec;
1388 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1389
1390 /* Requested clock frequency is already setup */
1391 if (freq == max98095->sysclk)
1392 return 0;
1393
82a5a936
PH		 1394 /* Setup clocks for slave mode, and using the PLL
1395 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1396 * 0x02 (when master clk is 20MHz to 40MHz)..
1397 * 0x03 (when master clk is 40MHz to 60MHz)..
1398 */
1399 if ((freq >= 10000000) && (freq < 20000000)) {
1400 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10);
1401 } else if ((freq >= 20000000) && (freq < 40000000)) {
1402 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20);
1403 } else if ((freq >= 40000000) && (freq < 60000000)) {
1404 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30);
1405 } else {
1406 dev_err(codec->dev, "Invalid master clock frequency\n");
1407 return -EINVAL;
1408 }
1409
1410 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1411
1412 max98095->sysclk = freq;
1413 return 0;
1414}
1415
1416static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1417 unsigned int fmt)
1418{
1419 struct snd_soc_codec *codec = codec_dai->codec;
1420 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1421 struct max98095_cdata *cdata;
1422 u8 regval = 0;
1423
1424 cdata = &max98095->dai[0];
1425
1426 if (fmt != cdata->fmt) {
1427 cdata->fmt = fmt;
1428
1429 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1430 case SND_SOC_DAIFMT_CBS_CFS:
1431 /* Slave mode PLL */
1432 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1433 0x80);
1434 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1435 0x00);
1436 break;
1437 case SND_SOC_DAIFMT_CBM_CFM:
1438 /* Set to master mode */
1439 regval |= M98095_DAI_MAS;
1440 break;
1441 case SND_SOC_DAIFMT_CBS_CFM:
1442 case SND_SOC_DAIFMT_CBM_CFS:
1443 default:
1444 dev_err(codec->dev, "Clock mode unsupported");
1445 return -EINVAL;
1446 }
1447
1448 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1449 case SND_SOC_DAIFMT_I2S:
1450 regval |= M98095_DAI_DLY;
1451 break;
1452 case SND_SOC_DAIFMT_LEFT_J:
1453 break;
1454 default:
1455 return -EINVAL;
1456 }
1457
1458 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1459 case SND_SOC_DAIFMT_NB_NF:
1460 break;
1461 case SND_SOC_DAIFMT_NB_IF:
1462 regval |= M98095_DAI_WCI;
1463 break;
1464 case SND_SOC_DAIFMT_IB_NF:
1465 regval |= M98095_DAI_BCI;
1466 break;
1467 case SND_SOC_DAIFMT_IB_IF:
1468 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1469 break;
1470 default:
1471 return -EINVAL;
1472 }
1473
1474 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1475 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1476 M98095_DAI_WCI, regval);
1477
1478 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1479 }
1480
1481 return 0;
1482}
1483
1484static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1485 unsigned int fmt)
1486{
1487 struct snd_soc_codec *codec = codec_dai->codec;
1488 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1489 struct max98095_cdata *cdata;
1490 u8 regval = 0;
1491
1492 cdata = &max98095->dai[1];
1493
1494 if (fmt != cdata->fmt) {
1495 cdata->fmt = fmt;
1496
1497 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1498 case SND_SOC_DAIFMT_CBS_CFS:
1499 /* Slave mode PLL */
1500 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1501 0x80);
1502 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1503 0x00);
1504 break;
1505 case SND_SOC_DAIFMT_CBM_CFM:
1506 /* Set to master mode */
1507 regval |= M98095_DAI_MAS;
1508 break;
1509 case SND_SOC_DAIFMT_CBS_CFM:
1510 case SND_SOC_DAIFMT_CBM_CFS:
1511 default:
1512 dev_err(codec->dev, "Clock mode unsupported");
1513 return -EINVAL;
1514 }
1515
1516 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1517 case SND_SOC_DAIFMT_I2S:
1518 regval |= M98095_DAI_DLY;
1519 break;
1520 case SND_SOC_DAIFMT_LEFT_J:
1521 break;
1522 default:
1523 return -EINVAL;
1524 }
1525
1526 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1527 case SND_SOC_DAIFMT_NB_NF:
1528 break;
1529 case SND_SOC_DAIFMT_NB_IF:
1530 regval |= M98095_DAI_WCI;
1531 break;
1532 case SND_SOC_DAIFMT_IB_NF:
1533 regval |= M98095_DAI_BCI;
1534 break;
1535 case SND_SOC_DAIFMT_IB_IF:
1536 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1537 break;
1538 default:
1539 return -EINVAL;
1540 }
1541
1542 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1543 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1544 M98095_DAI_WCI, regval);
1545
1546 snd_soc_write(codec, M98095_035_DAI2_CLOCK,
1547 M98095_DAI_BSEL64);
1548 }
1549
1550 return 0;
1551}
1552
1553static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1554 unsigned int fmt)
1555{
1556 struct snd_soc_codec *codec = codec_dai->codec;
1557 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1558 struct max98095_cdata *cdata;
1559 u8 regval = 0;
1560
1561 cdata = &max98095->dai[2];
1562
1563 if (fmt != cdata->fmt) {
1564 cdata->fmt = fmt;
1565
1566 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1567 case SND_SOC_DAIFMT_CBS_CFS:
1568 /* Slave mode PLL */
1569 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1570 0x80);
1571 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1572 0x00);
1573 break;
1574 case SND_SOC_DAIFMT_CBM_CFM:
1575 /* Set to master mode */
1576 regval |= M98095_DAI_MAS;
1577 break;
1578 case SND_SOC_DAIFMT_CBS_CFM:
1579 case SND_SOC_DAIFMT_CBM_CFS:
1580 default:
1581 dev_err(codec->dev, "Clock mode unsupported");
1582 return -EINVAL;
1583 }
1584
1585 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1586 case SND_SOC_DAIFMT_I2S:
1587 regval |= M98095_DAI_DLY;
1588 break;
1589 case SND_SOC_DAIFMT_LEFT_J:
1590 break;
1591 default:
1592 return -EINVAL;
1593 }
1594
1595 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1596 case SND_SOC_DAIFMT_NB_NF:
1597 break;
1598 case SND_SOC_DAIFMT_NB_IF:
1599 regval |= M98095_DAI_WCI;
1600 break;
1601 case SND_SOC_DAIFMT_IB_NF:
1602 regval |= M98095_DAI_BCI;
1603 break;
1604 case SND_SOC_DAIFMT_IB_IF:
1605 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1606 break;
1607 default:
1608 return -EINVAL;
1609 }
1610
1611 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1612 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1613 M98095_DAI_WCI, regval);
1614
1615 snd_soc_write(codec, M98095_03F_DAI3_CLOCK,
1616 M98095_DAI_BSEL64);
1617 }
1618
1619 return 0;
1620}
1621
1622static int max98095_set_bias_level(struct snd_soc_codec *codec,
1623 enum snd_soc_bias_level level)
1624{
14acbbbb 1625 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
82a5a936
PH		 1626 int ret;
1627
1628 switch (level) {
1629 case SND_SOC_BIAS_ON:
1630 break;
1631
1632 case SND_SOC_BIAS_PREPARE:
1633 break;
1634
1635 case SND_SOC_BIAS_STANDBY:
1636 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
14acbbbb 1637 ret = regcache_sync(max98095->regmap);
82a5a936
PH		 1638
1639 if (ret != 0) {
1640 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1641 return ret;
1642 }
1643 }
1644
1645 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1646 M98095_MBEN, M98095_MBEN);
1647 break;
1648
1649 case SND_SOC_BIAS_OFF:
1650 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1651 M98095_MBEN, 0);
14acbbbb 1652 regcache_mark_dirty(max98095->regmap);
82a5a936
PH		 1653 break;
1654 }
1655 codec->dapm.bias_level = level;
1656 return 0;
1657}
1658
1659#define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1660#define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1661
85e7652d 1662static const struct snd_soc_dai_ops max98095_dai1_ops = {
82a5a936
PH		 1663 .set_sysclk = max98095_dai_set_sysclk,
1664 .set_fmt = max98095_dai1_set_fmt,
1665 .hw_params = max98095_dai1_hw_params,
1666};
1667
85e7652d 1668static const struct snd_soc_dai_ops max98095_dai2_ops = {
82a5a936
PH		 1669 .set_sysclk = max98095_dai_set_sysclk,
1670 .set_fmt = max98095_dai2_set_fmt,
1671 .hw_params = max98095_dai2_hw_params,
1672};
1673
85e7652d 1674static const struct snd_soc_dai_ops max98095_dai3_ops = {
82a5a936
PH		 1675 .set_sysclk = max98095_dai_set_sysclk,
1676 .set_fmt = max98095_dai3_set_fmt,
1677 .hw_params = max98095_dai3_hw_params,
1678};
1679
1680static struct snd_soc_dai_driver max98095_dai[] = {
1681{
1682 .name = "HiFi",
1683 .playback = {
1684 .stream_name = "HiFi Playback",
1685 .channels_min = 1,
1686 .channels_max = 2,
1687 .rates = MAX98095_RATES,
1688 .formats = MAX98095_FORMATS,
1689 },
1690 .capture = {
1691 .stream_name = "HiFi Capture",
1692 .channels_min = 1,
1693 .channels_max = 2,
1694 .rates = MAX98095_RATES,
1695 .formats = MAX98095_FORMATS,
1696 },
1697 .ops = &max98095_dai1_ops,
1698},
1699{
1700 .name = "Aux",
1701 .playback = {
1702 .stream_name = "Aux Playback",
1703 .channels_min = 1,
1704 .channels_max = 1,
1705 .rates = MAX98095_RATES,
1706 .formats = MAX98095_FORMATS,
1707 },
1708 .ops = &max98095_dai2_ops,
1709},
1710{
1711 .name = "Voice",
1712 .playback = {
1713 .stream_name = "Voice Playback",
1714 .channels_min = 1,
1715 .channels_max = 1,
1716 .rates = MAX98095_RATES,
1717 .formats = MAX98095_FORMATS,
1718 },
1719 .ops = &max98095_dai3_ops,
1720}
1721
1722};
1723
dad31ec1
PH		 1724static int max98095_get_eq_channel(const char *name)
1725{
1726 if (strcmp(name, "EQ1 Mode") == 0)
1727 return 0;
1728 if (strcmp(name, "EQ2 Mode") == 0)
1729 return 1;
1730 return -EINVAL;
1731}
1732
1733static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1734 struct snd_ctl_elem_value *ucontrol)
1735{
1736 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1737 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1738 struct max98095_pdata *pdata = max98095->pdata;
1739 int channel = max98095_get_eq_channel(kcontrol->id.name);
1740 struct max98095_cdata *cdata;
f8d7b13e 1741 unsigned int sel = ucontrol->value.integer.value[0];
dad31ec1
PH		 1742 struct max98095_eq_cfg *coef_set;
1743 int fs, best, best_val, i;
1744 int regmask, regsave;
1745
a922cd71
TI		 1746 if (WARN_ON(channel > 1))
1747 return -EINVAL;
dad31ec1 1748
53949425
TH		 1749 if (!pdata || !max98095->eq_textcnt)
1750 return 0;
dad31ec1
PH		 1751
1752 if (sel >= pdata->eq_cfgcnt)
1753 return -EINVAL;
1754
53949425 1755 cdata = &max98095->dai[channel];
dad31ec1 1756 cdata->eq_sel = sel;
dad31ec1
PH		 1757 fs = cdata->rate;
1758
1759 /* Find the selected configuration with nearest sample rate */
1760 best = 0;
1761 best_val = INT_MAX;
1762 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1763 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1764 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1765 best = i;
1766 best_val = abs(pdata->eq_cfg[i].rate - fs);
1767 }
1768 }
1769
1770 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1771 pdata->eq_cfg[best].name,
1772 pdata->eq_cfg[best].rate, fs);
1773
1774 coef_set = &pdata->eq_cfg[best];
1775
1776 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1777
1778 /* Disable filter while configuring, and save current on/off state */
1779 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1780 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1781
1782 mutex_lock(&codec->mutex);
1783 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1784 m98095_eq_band(codec, channel, 0, coef_set->band1);
1785 m98095_eq_band(codec, channel, 1, coef_set->band2);
1786 m98095_eq_band(codec, channel, 2, coef_set->band3);
1787 m98095_eq_band(codec, channel, 3, coef_set->band4);
1788 m98095_eq_band(codec, channel, 4, coef_set->band5);
1789 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
1790 mutex_unlock(&codec->mutex);
1791
1792 /* Restore the original on/off state */
1793 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1794 return 0;
1795}
1796
1797static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1798 struct snd_ctl_elem_value *ucontrol)
1799{
1800 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1801 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1802 int channel = max98095_get_eq_channel(kcontrol->id.name);
1803 struct max98095_cdata *cdata;
1804
1805 cdata = &max98095->dai[channel];
1806 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1807
1808 return 0;
1809}
1810
1811static void max98095_handle_eq_pdata(struct snd_soc_codec *codec)
1812{
1813 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1814 struct max98095_pdata *pdata = max98095->pdata;
1815 struct max98095_eq_cfg *cfg;
1816 unsigned int cfgcnt;
1817 int i, j;
1818 const char **t;
1819 int ret;
1820
1821 struct snd_kcontrol_new controls[] = {
1822 SOC_ENUM_EXT("EQ1 Mode",
1823 max98095->eq_enum,
1824 max98095_get_eq_enum,
1825 max98095_put_eq_enum),
1826 SOC_ENUM_EXT("EQ2 Mode",
1827 max98095->eq_enum,
1828 max98095_get_eq_enum,
1829 max98095_put_eq_enum),
1830 };
1831
1832 cfg = pdata->eq_cfg;
1833 cfgcnt = pdata->eq_cfgcnt;
1834
1835 /* Setup an array of texts for the equalizer enum.
1836 * This is based on Mark Brown's equalizer driver code.
1837 */
1838 max98095->eq_textcnt = 0;
1839 max98095->eq_texts = NULL;
1840 for (i = 0; i < cfgcnt; i++) {
1841 for (j = 0; j < max98095->eq_textcnt; j++) {
1842 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1843 break;
1844 }
1845
1846 if (j != max98095->eq_textcnt)
1847 continue;
1848
1849 /* Expand the array */
1850 t = krealloc(max98095->eq_texts,
1851 sizeof(char *) * (max98095->eq_textcnt + 1),
1852 GFP_KERNEL);
1853 if (t == NULL)
1854 continue;
1855
1856 /* Store the new entry */
1857 t[max98095->eq_textcnt] = cfg[i].name;
1858 max98095->eq_textcnt++;
1859 max98095->eq_texts = t;
1860 }
1861
1862 /* Now point the soc_enum to .texts array items */
1863 max98095->eq_enum.texts = max98095->eq_texts;
1864 max98095->eq_enum.max = max98095->eq_textcnt;
1865
022658be 1866 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
dad31ec1
PH		 1867 if (ret != 0)
1868 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1869}
1870
c855a1a7
RM		 1871static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1872
1873static int max98095_get_bq_channel(struct snd_soc_codec *codec,
1874 const char *name)
dad31ec1 1875{
c855a1a7
RM		 1876 int i;
1877
1878 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++)
1879 if (strcmp(name, bq_mode_name[i]) == 0)
1880 return i;
1881
1882 /* Shouldn't happen */
1883 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name);
dad31ec1
PH		 1884 return -EINVAL;
1885}
1886
1887static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1888 struct snd_ctl_elem_value *ucontrol)
1889{
1890 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1891 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1892 struct max98095_pdata *pdata = max98095->pdata;
c855a1a7 1893 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
dad31ec1 1894 struct max98095_cdata *cdata;
f8d7b13e 1895 unsigned int sel = ucontrol->value.integer.value[0];
dad31ec1
PH		 1896 struct max98095_biquad_cfg *coef_set;
1897 int fs, best, best_val, i;
1898 int regmask, regsave;
1899
c855a1a7
RM		 1900 if (channel < 0)
1901 return channel;
dad31ec1 1902
53949425
TH		 1903 if (!pdata || !max98095->bq_textcnt)
1904 return 0;
dad31ec1
PH		 1905
1906 if (sel >= pdata->bq_cfgcnt)
1907 return -EINVAL;
1908
53949425 1909 cdata = &max98095->dai[channel];
dad31ec1 1910 cdata->bq_sel = sel;
dad31ec1
PH		 1911 fs = cdata->rate;
1912
1913 /* Find the selected configuration with nearest sample rate */
1914 best = 0;
1915 best_val = INT_MAX;
1916 for (i = 0; i < pdata->bq_cfgcnt; i++) {
1917 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
1918 abs(pdata->bq_cfg[i].rate - fs) < best_val) {
1919 best = i;
1920 best_val = abs(pdata->bq_cfg[i].rate - fs);
1921 }
1922 }
1923
1924 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1925 pdata->bq_cfg[best].name,
1926 pdata->bq_cfg[best].rate, fs);
1927
1928 coef_set = &pdata->bq_cfg[best];
1929
1930 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
1931
1932 /* Disable filter while configuring, and save current on/off state */
1933 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1934 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1935
1936 mutex_lock(&codec->mutex);
1937 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1938 m98095_biquad_band(codec, channel, 0, coef_set->band1);
1939 m98095_biquad_band(codec, channel, 1, coef_set->band2);
1940 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
1941 mutex_unlock(&codec->mutex);
1942
1943 /* Restore the original on/off state */
1944 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1945 return 0;
1946}
1947
1948static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1949 struct snd_ctl_elem_value *ucontrol)
1950{
1951 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1952 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
c855a1a7 1953 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
dad31ec1
PH		 1954 struct max98095_cdata *cdata;
1955
c855a1a7
RM		 1956 if (channel < 0)
1957 return channel;
1958
dad31ec1
PH		 1959 cdata = &max98095->dai[channel];
1960 ucontrol->value.enumerated.item[0] = cdata->bq_sel;
1961
1962 return 0;
1963}
1964
1965static void max98095_handle_bq_pdata(struct snd_soc_codec *codec)
1966{
1967 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1968 struct max98095_pdata *pdata = max98095->pdata;
1969 struct max98095_biquad_cfg *cfg;
1970 unsigned int cfgcnt;
1971 int i, j;
1972 const char **t;
1973 int ret;
1974
1975 struct snd_kcontrol_new controls[] = {
c855a1a7 1976 SOC_ENUM_EXT((char *)bq_mode_name[0],
dad31ec1
PH		 1977 max98095->bq_enum,
1978 max98095_get_bq_enum,
1979 max98095_put_bq_enum),
c855a1a7 1980 SOC_ENUM_EXT((char *)bq_mode_name[1],
dad31ec1
PH		 1981 max98095->bq_enum,
1982 max98095_get_bq_enum,
1983 max98095_put_bq_enum),
1984 };
c855a1a7 1985 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
dad31ec1
PH		 1986
1987 cfg = pdata->bq_cfg;
1988 cfgcnt = pdata->bq_cfgcnt;
1989
1990 /* Setup an array of texts for the biquad enum.
1991 * This is based on Mark Brown's equalizer driver code.
1992 */
1993 max98095->bq_textcnt = 0;
1994 max98095->bq_texts = NULL;
1995 for (i = 0; i < cfgcnt; i++) {
1996 for (j = 0; j < max98095->bq_textcnt; j++) {
1997 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
1998 break;
1999 }
2000
2001 if (j != max98095->bq_textcnt)
2002 continue;
2003
2004 /* Expand the array */
2005 t = krealloc(max98095->bq_texts,
2006 sizeof(char *) * (max98095->bq_textcnt + 1),
2007 GFP_KERNEL);
2008 if (t == NULL)
2009 continue;
2010
2011 /* Store the new entry */
2012 t[max98095->bq_textcnt] = cfg[i].name;
2013 max98095->bq_textcnt++;
2014 max98095->bq_texts = t;
2015 }
2016
2017 /* Now point the soc_enum to .texts array items */
2018 max98095->bq_enum.texts = max98095->bq_texts;
2019 max98095->bq_enum.max = max98095->bq_textcnt;
2020
022658be 2021 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
dad31ec1
PH		 2022 if (ret != 0)
2023 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret);
2024}
2025
82a5a936
PH		 2026static void max98095_handle_pdata(struct snd_soc_codec *codec)
2027{
2028 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2029 struct max98095_pdata *pdata = max98095->pdata;
2030 u8 regval = 0;
2031
2032 if (!pdata) {
2033 dev_dbg(codec->dev, "No platform data\n");
2034 return;
2035 }
2036
2037 /* Configure mic for analog/digital mic mode */
2038 if (pdata->digmic_left_mode)
2039 regval |= M98095_DIGMIC_L;
2040
2041 if (pdata->digmic_right_mode)
2042 regval |= M98095_DIGMIC_R;
2043
2044 snd_soc_write(codec, M98095_087_CFG_MIC, regval);
dad31ec1
PH		 2045
2046 /* Configure equalizers */
2047 if (pdata->eq_cfgcnt)
2048 max98095_handle_eq_pdata(codec);
2049
2050 /* Configure bi-quad filters */
2051 if (pdata->bq_cfgcnt)
2052 max98095_handle_bq_pdata(codec);
82a5a936
PH		 2053}
2054
9dd90c5d
RK		 2055static irqreturn_t max98095_report_jack(int irq, void *data)
2056{
2057 struct snd_soc_codec *codec = data;
2058 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2059 unsigned int value;
2060 int hp_report = 0;
2061 int mic_report = 0;
2062
2063 /* Read the Jack Status Register */
2064 value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS);
2065
2066 /* If ddone is not set, then detection isn't finished yet */
2067 if ((value & M98095_DDONE) == 0)
2068 return IRQ_NONE;
2069
2070 /* if hp, check its bit, and if set, clear it */
2071 if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
2072 max98095->headphone_jack)
2073 hp_report |= SND_JACK_HEADPHONE;
2074
2075 /* if mic, check its bit, and if set, clear it */
2076 if ((value & M98095_MIC_IN) && max98095->mic_jack)
2077 mic_report |= SND_JACK_MICROPHONE;
2078
2079 if (max98095->headphone_jack == max98095->mic_jack) {
2080 snd_soc_jack_report(max98095->headphone_jack,
2081 hp_report | mic_report,
2082 SND_JACK_HEADSET);
2083 } else {
2084 if (max98095->headphone_jack)
2085 snd_soc_jack_report(max98095->headphone_jack,
2086 hp_report, SND_JACK_HEADPHONE);
2087 if (max98095->mic_jack)
2088 snd_soc_jack_report(max98095->mic_jack,
2089 mic_report, SND_JACK_MICROPHONE);
2090 }
2091
2092 return IRQ_HANDLED;
2093}
2094
a265367c 2095static int max98095_jack_detect_enable(struct snd_soc_codec *codec)
9dd90c5d
RK		 2096{
2097 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2098 int ret = 0;
2099 int detect_enable = M98095_JDEN;
2100 unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
2101
2102 if (max98095->pdata->jack_detect_pin5en)
2103 detect_enable |= M98095_PIN5EN;
2104
0841b04a
MB		 2105 if (max98095->pdata->jack_detect_delay)
2106 slew = max98095->pdata->jack_detect_delay;
9dd90c5d
RK		 2107
2108 ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew);
2109 if (ret < 0) {
2110 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2111 return ret;
2112 }
2113
2114 /* configure auto detection to be enabled */
2115 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable);
2116 if (ret < 0) {
2117 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2118 return ret;
2119 }
2120
2121 return ret;
2122}
2123
a265367c 2124static int max98095_jack_detect_disable(struct snd_soc_codec *codec)
9dd90c5d
RK		 2125{
2126 int ret = 0;
2127
2128 /* configure auto detection to be disabled */
2129 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0);
2130 if (ret < 0) {
2131 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2132 return ret;
2133 }
2134
2135 return ret;
2136}
2137
2138int max98095_jack_detect(struct snd_soc_codec *codec,
2139 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
2140{
2141 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2142 struct i2c_client *client = to_i2c_client(codec->dev);
2143 int ret = 0;
2144
2145 max98095->headphone_jack = hp_jack;
2146 max98095->mic_jack = mic_jack;
2147
2148 /* only progress if we have at least 1 jack pointer */
2149 if (!hp_jack && !mic_jack)
2150 return -EINVAL;
2151
2152 max98095_jack_detect_enable(codec);
2153
2154 /* enable interrupts for headphone jack detection */
2155 ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN,
2156 M98095_IDDONE, M98095_IDDONE);
2157 if (ret < 0) {
2158 dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret);
2159 return ret;
2160 }
2161
2162 max98095_report_jack(client->irq, codec);
2163 return 0;
2164}
a265367c 2165EXPORT_SYMBOL_GPL(max98095_jack_detect);
9dd90c5d 2166
82a5a936 2167#ifdef CONFIG_PM
84b315ee 2168static int max98095_suspend(struct snd_soc_codec *codec)
82a5a936 2169{
9dd90c5d
RK		 2170 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2171
2172 if (max98095->headphone_jack || max98095->mic_jack)
2173 max98095_jack_detect_disable(codec);
2174
82a5a936
PH		 2175 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2176
2177 return 0;
2178}
2179
2180static int max98095_resume(struct snd_soc_codec *codec)
2181{
9dd90c5d
RK		 2182 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2183 struct i2c_client *client = to_i2c_client(codec->dev);
2184
82a5a936
PH		 2185 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2186
9dd90c5d
RK		 2187 if (max98095->headphone_jack || max98095->mic_jack) {
2188 max98095_jack_detect_enable(codec);
2189 max98095_report_jack(client->irq, codec);
2190 }
2191
82a5a936
PH		 2192 return 0;
2193}
2194#else
2195#define max98095_suspend NULL
2196#define max98095_resume NULL
2197#endif
2198
2199static int max98095_reset(struct snd_soc_codec *codec)
2200{
2201 int i, ret;
2202
2203 /* Gracefully reset the DSP core and the codec hardware
2204 * in a proper sequence */
2205 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0);
2206 if (ret < 0) {
2207 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
2208 return ret;
2209 }
2210
2211 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0);
2212 if (ret < 0) {
2213 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
2214 return ret;
2215 }
2216
2217 /* Reset to hardware default for registers, as there is not
2218 * a soft reset hardware control register */
2219 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
14acbbbb 2220 ret = snd_soc_write(codec, i, snd_soc_read(codec, i));
82a5a936
PH		 2221 if (ret < 0) {
2222 dev_err(codec->dev, "Failed to reset: %d\n", ret);
2223 return ret;
2224 }
2225 }
2226
2227 return ret;
2228}
2229
2230static int max98095_probe(struct snd_soc_codec *codec)
2231{
2232 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2233 struct max98095_cdata *cdata;
9dd90c5d 2234 struct i2c_client *client;
82a5a936
PH		 2235 int ret = 0;
2236
14acbbbb 2237 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
82a5a936
PH		 2238 if (ret != 0) {
2239 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2240 return ret;
2241 }
2242
2243 /* reset the codec, the DSP core, and disable all interrupts */
2244 max98095_reset(codec);
2245
9dd90c5d
RK		 2246 client = to_i2c_client(codec->dev);
2247
82a5a936
PH		 2248 /* initialize private data */
2249
2250 max98095->sysclk = (unsigned)-1;
dad31ec1
PH		 2251 max98095->eq_textcnt = 0;
2252 max98095->bq_textcnt = 0;
82a5a936
PH		 2253
2254 cdata = &max98095->dai[0];
2255 cdata->rate = (unsigned)-1;
2256 cdata->fmt = (unsigned)-1;
dad31ec1
PH		 2257 cdata->eq_sel = 0;
2258 cdata->bq_sel = 0;
82a5a936
PH		 2259
2260 cdata = &max98095->dai[1];
2261 cdata->rate = (unsigned)-1;
2262 cdata->fmt = (unsigned)-1;
dad31ec1
PH		 2263 cdata->eq_sel = 0;
2264 cdata->bq_sel = 0;
82a5a936
PH		 2265
2266 cdata = &max98095->dai[2];
2267 cdata->rate = (unsigned)-1;
2268 cdata->fmt = (unsigned)-1;
dad31ec1
PH		 2269 cdata->eq_sel = 0;
2270 cdata->bq_sel = 0;
82a5a936
PH		 2271
2272 max98095->lin_state = 0;
2273 max98095->mic1pre = 0;
2274 max98095->mic2pre = 0;
2275
9dd90c5d
RK		 2276 if (client->irq) {
2277 /* register an audio interrupt */
2278 ret = request_threaded_irq(client->irq, NULL,
2279 max98095_report_jack,
2280 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2281 "max98095", codec);
2282 if (ret) {
2283 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret);
2284 goto err_access;
2285 }
2286 }
2287
82a5a936
PH		 2288 ret = snd_soc_read(codec, M98095_0FF_REV_ID);
2289 if (ret < 0) {
bab3b59d 2290 dev_err(codec->dev, "Failure reading hardware revision: %d\n",
82a5a936 2291 ret);
9dd90c5d 2292 goto err_irq;
82a5a936 2293 }
bab3b59d 2294 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
82a5a936
PH		 2295
2296 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV);
2297
2298 /* initialize registers cache to hardware default */
2299 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2300
2301 snd_soc_write(codec, M98095_048_MIX_DAC_LR,
2302 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2303
2304 snd_soc_write(codec, M98095_049_MIX_DAC_M,
2305 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2306
2307 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2308 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2309 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL);
2310
2311 snd_soc_write(codec, M98095_02C_DAI1_IOCFG,
2312 M98095_S1NORMAL|M98095_SDATA);
2313
2314 snd_soc_write(codec, M98095_036_DAI2_IOCFG,
2315 M98095_S2NORMAL|M98095_SDATA);
2316
2317 snd_soc_write(codec, M98095_040_DAI3_IOCFG,
2318 M98095_S3NORMAL|M98095_SDATA);
2319
2320 max98095_handle_pdata(codec);
2321
2322 /* take the codec out of the shut down */
2323 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
2324 M98095_SHDNRUN);
2325
9dd90c5d
RK		 2326 return 0;
2327
2328err_irq:
2329 if (client->irq)
2330 free_irq(client->irq, codec);
82a5a936
PH		 2331err_access:
2332 return ret;
2333}
2334
2335static int max98095_remove(struct snd_soc_codec *codec)
2336{
9dd90c5d
RK		 2337 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2338 struct i2c_client *client = to_i2c_client(codec->dev);
2339
82a5a936
PH		 2340 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2341
9dd90c5d
RK		 2342 if (max98095->headphone_jack || max98095->mic_jack)
2343 max98095_jack_detect_disable(codec);
2344
2345 if (client->irq)
2346 free_irq(client->irq, codec);
2347
82a5a936
PH		 2348 return 0;
2349}
2350
2351static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
2352 .probe = max98095_probe,
2353 .remove = max98095_remove,
2354 .suspend = max98095_suspend,
2355 .resume = max98095_resume,
2356 .set_bias_level = max98095_set_bias_level,
c6b3283f
MB		 2357 .controls = max98095_snd_controls,
2358 .num_controls = ARRAY_SIZE(max98095_snd_controls),
82a5a936
PH		 2359 .dapm_widgets = max98095_dapm_widgets,
2360 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
2361 .dapm_routes = max98095_audio_map,
2362 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
2363};
2364
2365static int max98095_i2c_probe(struct i2c_client *i2c,
2366 const struct i2c_device_id *id)
2367{
2368 struct max98095_priv *max98095;
2369 int ret;
2370
b1b54882
AL		 2371 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2372 GFP_KERNEL);
82a5a936
PH		 2373 if (max98095 == NULL)
2374 return -ENOMEM;
2375
14acbbbb
MB		 2376 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2377 if (IS_ERR(max98095->regmap)) {
2378 ret = PTR_ERR(max98095->regmap);
2379 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2380 return ret;
2381 }
2382
82a5a936
PH		 2383 max98095->devtype = id->driver_data;
2384 i2c_set_clientdata(i2c, max98095);
82a5a936
PH		 2385 max98095->pdata = i2c->dev.platform_data;
2386
bab3b59d
TH		 2387 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095,
2388 max98095_dai, ARRAY_SIZE(max98095_dai));
82a5a936
PH		 2389 return ret;
2390}
2391
7a79e94e 2392static int max98095_i2c_remove(struct i2c_client *client)
82a5a936
PH		 2393{
2394 snd_soc_unregister_codec(&client->dev);
82a5a936
PH		 2395 return 0;
2396}
2397
2398static const struct i2c_device_id max98095_i2c_id[] = {
2399 { "max98095", MAX98095 },
2400 { }
2401};
2402MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2403
2404static struct i2c_driver max98095_i2c_driver = {
2405 .driver = {
2406 .name = "max98095",
2407 .owner = THIS_MODULE,
2408 },
2409 .probe = max98095_i2c_probe,
7a79e94e 2410 .remove = max98095_i2c_remove,
82a5a936
PH		 2411 .id_table = max98095_i2c_id,
2412};
2413
a8af02cf 2414module_i2c_driver(max98095_i2c_driver);
82a5a936
PH		 2415
2416MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2417MODULE_AUTHOR("Peter Hsiang");
2418MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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