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ASoC: max98095: Add an explicit of_match_table
[deliverable/linux.git] / sound / soc / codecs / max98095.c
CommitLineData
82a5a936
PH		 1/*
2 * max98095.c -- MAX98095 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
82a5a936
PH		 18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
22#include <sound/initval.h>
23#include <sound/tlv.h>
24#include <linux/slab.h>
25#include <asm/div64.h>
26#include <sound/max98095.h>
9dd90c5d 27#include <sound/jack.h>
82a5a936
PH		 28#include "max98095.h"
29
30enum max98095_type {
31 MAX98095,
32};
33
34struct max98095_cdata {
35 unsigned int rate;
36 unsigned int fmt;
dad31ec1
PH		 37 int eq_sel;
38 int bq_sel;
82a5a936
PH		 39};
40
41struct max98095_priv {
14acbbbb 42 struct regmap *regmap;
82a5a936 43 enum max98095_type devtype;
82a5a936
PH		 44 struct max98095_pdata *pdata;
45 unsigned int sysclk;
46 struct max98095_cdata dai[3];
dad31ec1
PH		 47 const char **eq_texts;
48 const char **bq_texts;
49 struct soc_enum eq_enum;
50 struct soc_enum bq_enum;
51 int eq_textcnt;
52 int bq_textcnt;
82a5a936
PH		 53 u8 lin_state;
54 unsigned int mic1pre;
55 unsigned int mic2pre;
9dd90c5d
RK		 56 struct snd_soc_jack *headphone_jack;
57 struct snd_soc_jack *mic_jack;
82a5a936
PH		 58};
59
14acbbbb
MB		 60static const struct reg_default max98095_reg_def[] = {
61 { 0xf, 0x00 }, /* 0F */
62 { 0x10, 0x00 }, /* 10 */
63 { 0x11, 0x00 }, /* 11 */
64 { 0x12, 0x00 }, /* 12 */
65 { 0x13, 0x00 }, /* 13 */
66 { 0x14, 0x00 }, /* 14 */
67 { 0x15, 0x00 }, /* 15 */
68 { 0x16, 0x00 }, /* 16 */
69 { 0x17, 0x00 }, /* 17 */
70 { 0x18, 0x00 }, /* 18 */
71 { 0x19, 0x00 }, /* 19 */
72 { 0x1a, 0x00 }, /* 1A */
73 { 0x1b, 0x00 }, /* 1B */
74 { 0x1c, 0x00 }, /* 1C */
75 { 0x1d, 0x00 }, /* 1D */
76 { 0x1e, 0x00 }, /* 1E */
77 { 0x1f, 0x00 }, /* 1F */
78 { 0x20, 0x00 }, /* 20 */
79 { 0x21, 0x00 }, /* 21 */
80 { 0x22, 0x00 }, /* 22 */
81 { 0x23, 0x00 }, /* 23 */
82 { 0x24, 0x00 }, /* 24 */
83 { 0x25, 0x00 }, /* 25 */
84 { 0x26, 0x00 }, /* 26 */
85 { 0x27, 0x00 }, /* 27 */
86 { 0x28, 0x00 }, /* 28 */
87 { 0x29, 0x00 }, /* 29 */
88 { 0x2a, 0x00 }, /* 2A */
89 { 0x2b, 0x00 }, /* 2B */
90 { 0x2c, 0x00 }, /* 2C */
91 { 0x2d, 0x00 }, /* 2D */
92 { 0x2e, 0x00 }, /* 2E */
93 { 0x2f, 0x00 }, /* 2F */
94 { 0x30, 0x00 }, /* 30 */
95 { 0x31, 0x00 }, /* 31 */
96 { 0x32, 0x00 }, /* 32 */
97 { 0x33, 0x00 }, /* 33 */
98 { 0x34, 0x00 }, /* 34 */
99 { 0x35, 0x00 }, /* 35 */
100 { 0x36, 0x00 }, /* 36 */
101 { 0x37, 0x00 }, /* 37 */
102 { 0x38, 0x00 }, /* 38 */
103 { 0x39, 0x00 }, /* 39 */
104 { 0x3a, 0x00 }, /* 3A */
105 { 0x3b, 0x00 }, /* 3B */
106 { 0x3c, 0x00 }, /* 3C */
107 { 0x3d, 0x00 }, /* 3D */
108 { 0x3e, 0x00 }, /* 3E */
109 { 0x3f, 0x00 }, /* 3F */
110 { 0x40, 0x00 }, /* 40 */
111 { 0x41, 0x00 }, /* 41 */
112 { 0x42, 0x00 }, /* 42 */
113 { 0x43, 0x00 }, /* 43 */
114 { 0x44, 0x00 }, /* 44 */
115 { 0x45, 0x00 }, /* 45 */
116 { 0x46, 0x00 }, /* 46 */
117 { 0x47, 0x00 }, /* 47 */
118 { 0x48, 0x00 }, /* 48 */
119 { 0x49, 0x00 }, /* 49 */
120 { 0x4a, 0x00 }, /* 4A */
121 { 0x4b, 0x00 }, /* 4B */
122 { 0x4c, 0x00 }, /* 4C */
123 { 0x4d, 0x00 }, /* 4D */
124 { 0x4e, 0x00 }, /* 4E */
125 { 0x4f, 0x00 }, /* 4F */
126 { 0x50, 0x00 }, /* 50 */
127 { 0x51, 0x00 }, /* 51 */
128 { 0x52, 0x00 }, /* 52 */
129 { 0x53, 0x00 }, /* 53 */
130 { 0x54, 0x00 }, /* 54 */
131 { 0x55, 0x00 }, /* 55 */
132 { 0x56, 0x00 }, /* 56 */
133 { 0x57, 0x00 }, /* 57 */
134 { 0x58, 0x00 }, /* 58 */
135 { 0x59, 0x00 }, /* 59 */
136 { 0x5a, 0x00 }, /* 5A */
137 { 0x5b, 0x00 }, /* 5B */
138 { 0x5c, 0x00 }, /* 5C */
139 { 0x5d, 0x00 }, /* 5D */
140 { 0x5e, 0x00 }, /* 5E */
141 { 0x5f, 0x00 }, /* 5F */
142 { 0x60, 0x00 }, /* 60 */
143 { 0x61, 0x00 }, /* 61 */
144 { 0x62, 0x00 }, /* 62 */
145 { 0x63, 0x00 }, /* 63 */
146 { 0x64, 0x00 }, /* 64 */
147 { 0x65, 0x00 }, /* 65 */
148 { 0x66, 0x00 }, /* 66 */
149 { 0x67, 0x00 }, /* 67 */
150 { 0x68, 0x00 }, /* 68 */
151 { 0x69, 0x00 }, /* 69 */
152 { 0x6a, 0x00 }, /* 6A */
153 { 0x6b, 0x00 }, /* 6B */
154 { 0x6c, 0x00 }, /* 6C */
155 { 0x6d, 0x00 }, /* 6D */
156 { 0x6e, 0x00 }, /* 6E */
157 { 0x6f, 0x00 }, /* 6F */
158 { 0x70, 0x00 }, /* 70 */
159 { 0x71, 0x00 }, /* 71 */
160 { 0x72, 0x00 }, /* 72 */
161 { 0x73, 0x00 }, /* 73 */
162 { 0x74, 0x00 }, /* 74 */
163 { 0x75, 0x00 }, /* 75 */
164 { 0x76, 0x00 }, /* 76 */
165 { 0x77, 0x00 }, /* 77 */
166 { 0x78, 0x00 }, /* 78 */
167 { 0x79, 0x00 }, /* 79 */
168 { 0x7a, 0x00 }, /* 7A */
169 { 0x7b, 0x00 }, /* 7B */
170 { 0x7c, 0x00 }, /* 7C */
171 { 0x7d, 0x00 }, /* 7D */
172 { 0x7e, 0x00 }, /* 7E */
173 { 0x7f, 0x00 }, /* 7F */
174 { 0x80, 0x00 }, /* 80 */
175 { 0x81, 0x00 }, /* 81 */
176 { 0x82, 0x00 }, /* 82 */
177 { 0x83, 0x00 }, /* 83 */
178 { 0x84, 0x00 }, /* 84 */
179 { 0x85, 0x00 }, /* 85 */
180 { 0x86, 0x00 }, /* 86 */
181 { 0x87, 0x00 }, /* 87 */
182 { 0x88, 0x00 }, /* 88 */
183 { 0x89, 0x00 }, /* 89 */
184 { 0x8a, 0x00 }, /* 8A */
185 { 0x8b, 0x00 }, /* 8B */
186 { 0x8c, 0x00 }, /* 8C */
187 { 0x8d, 0x00 }, /* 8D */
188 { 0x8e, 0x00 }, /* 8E */
189 { 0x8f, 0x00 }, /* 8F */
190 { 0x90, 0x00 }, /* 90 */
191 { 0x91, 0x00 }, /* 91 */
192 { 0x92, 0x30 }, /* 92 */
193 { 0x93, 0xF0 }, /* 93 */
194 { 0x94, 0x00 }, /* 94 */
195 { 0x95, 0x00 }, /* 95 */
196 { 0x96, 0x3F }, /* 96 */
197 { 0x97, 0x00 }, /* 97 */
198 { 0xff, 0x00 }, /* FF */
82a5a936
PH		 199};
200
201static struct {
202 int readable;
203 int writable;
204} max98095_access[M98095_REG_CNT] = {
205 { 0x00, 0x00 }, /* 00 */
206 { 0xFF, 0x00 }, /* 01 */
207 { 0xFF, 0x00 }, /* 02 */
208 { 0xFF, 0x00 }, /* 03 */
209 { 0xFF, 0x00 }, /* 04 */
210 { 0xFF, 0x00 }, /* 05 */
211 { 0xFF, 0x00 }, /* 06 */
212 { 0xFF, 0x00 }, /* 07 */
213 { 0xFF, 0x00 }, /* 08 */
214 { 0xFF, 0x00 }, /* 09 */
215 { 0xFF, 0x00 }, /* 0A */
216 { 0xFF, 0x00 }, /* 0B */
217 { 0xFF, 0x00 }, /* 0C */
218 { 0xFF, 0x00 }, /* 0D */
219 { 0xFF, 0x00 }, /* 0E */
220 { 0xFF, 0x9F }, /* 0F */
221 { 0xFF, 0xFF }, /* 10 */
222 { 0xFF, 0xFF }, /* 11 */
223 { 0xFF, 0xFF }, /* 12 */
224 { 0xFF, 0xFF }, /* 13 */
225 { 0xFF, 0xFF }, /* 14 */
226 { 0xFF, 0xFF }, /* 15 */
227 { 0xFF, 0xFF }, /* 16 */
228 { 0xFF, 0xFF }, /* 17 */
229 { 0xFF, 0xFF }, /* 18 */
230 { 0xFF, 0xFF }, /* 19 */
231 { 0xFF, 0xFF }, /* 1A */
232 { 0xFF, 0xFF }, /* 1B */
233 { 0xFF, 0xFF }, /* 1C */
234 { 0xFF, 0xFF }, /* 1D */
235 { 0xFF, 0x77 }, /* 1E */
236 { 0xFF, 0x77 }, /* 1F */
237 { 0xFF, 0x77 }, /* 20 */
238 { 0xFF, 0x77 }, /* 21 */
239 { 0xFF, 0x77 }, /* 22 */
240 { 0xFF, 0x77 }, /* 23 */
241 { 0xFF, 0xFF }, /* 24 */
242 { 0xFF, 0x7F }, /* 25 */
243 { 0xFF, 0x31 }, /* 26 */
244 { 0xFF, 0xFF }, /* 27 */
245 { 0xFF, 0xFF }, /* 28 */
246 { 0xFF, 0xFF }, /* 29 */
247 { 0xFF, 0xF7 }, /* 2A */
248 { 0xFF, 0x2F }, /* 2B */
249 { 0xFF, 0xEF }, /* 2C */
250 { 0xFF, 0xFF }, /* 2D */
251 { 0xFF, 0xFF }, /* 2E */
252 { 0xFF, 0xFF }, /* 2F */
253 { 0xFF, 0xFF }, /* 30 */
254 { 0xFF, 0xFF }, /* 31 */
255 { 0xFF, 0xFF }, /* 32 */
256 { 0xFF, 0xFF }, /* 33 */
257 { 0xFF, 0xF7 }, /* 34 */
258 { 0xFF, 0x2F }, /* 35 */
259 { 0xFF, 0xCF }, /* 36 */
260 { 0xFF, 0xFF }, /* 37 */
261 { 0xFF, 0xFF }, /* 38 */
262 { 0xFF, 0xFF }, /* 39 */
263 { 0xFF, 0xFF }, /* 3A */
264 { 0xFF, 0xFF }, /* 3B */
265 { 0xFF, 0xFF }, /* 3C */
266 { 0xFF, 0xFF }, /* 3D */
267 { 0xFF, 0xF7 }, /* 3E */
268 { 0xFF, 0x2F }, /* 3F */
269 { 0xFF, 0xCF }, /* 40 */
270 { 0xFF, 0xFF }, /* 41 */
271 { 0xFF, 0x77 }, /* 42 */
272 { 0xFF, 0xFF }, /* 43 */
273 { 0xFF, 0xFF }, /* 44 */
274 { 0xFF, 0xFF }, /* 45 */
275 { 0xFF, 0xFF }, /* 46 */
276 { 0xFF, 0xFF }, /* 47 */
277 { 0xFF, 0xFF }, /* 48 */
278 { 0xFF, 0x0F }, /* 49 */
279 { 0xFF, 0xFF }, /* 4A */
280 { 0xFF, 0xFF }, /* 4B */
281 { 0xFF, 0x3F }, /* 4C */
282 { 0xFF, 0x3F }, /* 4D */
283 { 0xFF, 0x3F }, /* 4E */
284 { 0xFF, 0xFF }, /* 4F */
285 { 0xFF, 0x7F }, /* 50 */
286 { 0xFF, 0x7F }, /* 51 */
287 { 0xFF, 0x0F }, /* 52 */
288 { 0xFF, 0x3F }, /* 53 */
289 { 0xFF, 0x3F }, /* 54 */
290 { 0xFF, 0x3F }, /* 55 */
291 { 0xFF, 0xFF }, /* 56 */
292 { 0xFF, 0xFF }, /* 57 */
293 { 0xFF, 0xBF }, /* 58 */
294 { 0xFF, 0x1F }, /* 59 */
295 { 0xFF, 0xBF }, /* 5A */
296 { 0xFF, 0x1F }, /* 5B */
297 { 0xFF, 0xBF }, /* 5C */
298 { 0xFF, 0x3F }, /* 5D */
299 { 0xFF, 0x3F }, /* 5E */
300 { 0xFF, 0x7F }, /* 5F */
301 { 0xFF, 0x7F }, /* 60 */
302 { 0xFF, 0x47 }, /* 61 */
303 { 0xFF, 0x9F }, /* 62 */
304 { 0xFF, 0x9F }, /* 63 */
305 { 0xFF, 0x9F }, /* 64 */
306 { 0xFF, 0x9F }, /* 65 */
307 { 0xFF, 0x9F }, /* 66 */
308 { 0xFF, 0xBF }, /* 67 */
309 { 0xFF, 0xBF }, /* 68 */
310 { 0xFF, 0xFF }, /* 69 */
311 { 0xFF, 0xFF }, /* 6A */
312 { 0xFF, 0x7F }, /* 6B */
313 { 0xFF, 0xF7 }, /* 6C */
314 { 0xFF, 0xFF }, /* 6D */
315 { 0xFF, 0xFF }, /* 6E */
316 { 0xFF, 0x1F }, /* 6F */
317 { 0xFF, 0xF7 }, /* 70 */
318 { 0xFF, 0xFF }, /* 71 */
319 { 0xFF, 0xFF }, /* 72 */
320 { 0xFF, 0x1F }, /* 73 */
321 { 0xFF, 0xF7 }, /* 74 */
322 { 0xFF, 0xFF }, /* 75 */
323 { 0xFF, 0xFF }, /* 76 */
324 { 0xFF, 0x1F }, /* 77 */
325 { 0xFF, 0xF7 }, /* 78 */
326 { 0xFF, 0xFF }, /* 79 */
327 { 0xFF, 0xFF }, /* 7A */
328 { 0xFF, 0x1F }, /* 7B */
329 { 0xFF, 0xF7 }, /* 7C */
330 { 0xFF, 0xFF }, /* 7D */
331 { 0xFF, 0xFF }, /* 7E */
332 { 0xFF, 0x1F }, /* 7F */
333 { 0xFF, 0xF7 }, /* 80 */
334 { 0xFF, 0xFF }, /* 81 */
335 { 0xFF, 0xFF }, /* 82 */
336 { 0xFF, 0x1F }, /* 83 */
337 { 0xFF, 0x7F }, /* 84 */
338 { 0xFF, 0x0F }, /* 85 */
339 { 0xFF, 0xD8 }, /* 86 */
340 { 0xFF, 0xFF }, /* 87 */
341 { 0xFF, 0xEF }, /* 88 */
342 { 0xFF, 0xFE }, /* 89 */
343 { 0xFF, 0xFE }, /* 8A */
344 { 0xFF, 0xFF }, /* 8B */
345 { 0xFF, 0xFF }, /* 8C */
346 { 0xFF, 0x3F }, /* 8D */
347 { 0xFF, 0xFF }, /* 8E */
348 { 0xFF, 0x3F }, /* 8F */
349 { 0xFF, 0x8F }, /* 90 */
350 { 0xFF, 0xFF }, /* 91 */
351 { 0xFF, 0x3F }, /* 92 */
352 { 0xFF, 0xFF }, /* 93 */
353 { 0xFF, 0xFF }, /* 94 */
354 { 0xFF, 0x0F }, /* 95 */
355 { 0xFF, 0x3F }, /* 96 */
356 { 0xFF, 0x8C }, /* 97 */
357 { 0x00, 0x00 }, /* 98 */
358 { 0x00, 0x00 }, /* 99 */
359 { 0x00, 0x00 }, /* 9A */
360 { 0x00, 0x00 }, /* 9B */
361 { 0x00, 0x00 }, /* 9C */
362 { 0x00, 0x00 }, /* 9D */
363 { 0x00, 0x00 }, /* 9E */
364 { 0x00, 0x00 }, /* 9F */
365 { 0x00, 0x00 }, /* A0 */
366 { 0x00, 0x00 }, /* A1 */
367 { 0x00, 0x00 }, /* A2 */
368 { 0x00, 0x00 }, /* A3 */
369 { 0x00, 0x00 }, /* A4 */
370 { 0x00, 0x00 }, /* A5 */
371 { 0x00, 0x00 }, /* A6 */
372 { 0x00, 0x00 }, /* A7 */
373 { 0x00, 0x00 }, /* A8 */
374 { 0x00, 0x00 }, /* A9 */
375 { 0x00, 0x00 }, /* AA */
376 { 0x00, 0x00 }, /* AB */
377 { 0x00, 0x00 }, /* AC */
378 { 0x00, 0x00 }, /* AD */
379 { 0x00, 0x00 }, /* AE */
380 { 0x00, 0x00 }, /* AF */
381 { 0x00, 0x00 }, /* B0 */
382 { 0x00, 0x00 }, /* B1 */
383 { 0x00, 0x00 }, /* B2 */
384 { 0x00, 0x00 }, /* B3 */
385 { 0x00, 0x00 }, /* B4 */
386 { 0x00, 0x00 }, /* B5 */
387 { 0x00, 0x00 }, /* B6 */
388 { 0x00, 0x00 }, /* B7 */
389 { 0x00, 0x00 }, /* B8 */
390 { 0x00, 0x00 }, /* B9 */
391 { 0x00, 0x00 }, /* BA */
392 { 0x00, 0x00 }, /* BB */
393 { 0x00, 0x00 }, /* BC */
394 { 0x00, 0x00 }, /* BD */
395 { 0x00, 0x00 }, /* BE */
396 { 0x00, 0x00 }, /* BF */
397 { 0x00, 0x00 }, /* C0 */
398 { 0x00, 0x00 }, /* C1 */
399 { 0x00, 0x00 }, /* C2 */
400 { 0x00, 0x00 }, /* C3 */
401 { 0x00, 0x00 }, /* C4 */
402 { 0x00, 0x00 }, /* C5 */
403 { 0x00, 0x00 }, /* C6 */
404 { 0x00, 0x00 }, /* C7 */
405 { 0x00, 0x00 }, /* C8 */
406 { 0x00, 0x00 }, /* C9 */
407 { 0x00, 0x00 }, /* CA */
408 { 0x00, 0x00 }, /* CB */
409 { 0x00, 0x00 }, /* CC */
410 { 0x00, 0x00 }, /* CD */
411 { 0x00, 0x00 }, /* CE */
412 { 0x00, 0x00 }, /* CF */
413 { 0x00, 0x00 }, /* D0 */
414 { 0x00, 0x00 }, /* D1 */
415 { 0x00, 0x00 }, /* D2 */
416 { 0x00, 0x00 }, /* D3 */
417 { 0x00, 0x00 }, /* D4 */
418 { 0x00, 0x00 }, /* D5 */
419 { 0x00, 0x00 }, /* D6 */
420 { 0x00, 0x00 }, /* D7 */
421 { 0x00, 0x00 }, /* D8 */
422 { 0x00, 0x00 }, /* D9 */
423 { 0x00, 0x00 }, /* DA */
424 { 0x00, 0x00 }, /* DB */
425 { 0x00, 0x00 }, /* DC */
426 { 0x00, 0x00 }, /* DD */
427 { 0x00, 0x00 }, /* DE */
428 { 0x00, 0x00 }, /* DF */
429 { 0x00, 0x00 }, /* E0 */
430 { 0x00, 0x00 }, /* E1 */
431 { 0x00, 0x00 }, /* E2 */
432 { 0x00, 0x00 }, /* E3 */
433 { 0x00, 0x00 }, /* E4 */
434 { 0x00, 0x00 }, /* E5 */
435 { 0x00, 0x00 }, /* E6 */
436 { 0x00, 0x00 }, /* E7 */
437 { 0x00, 0x00 }, /* E8 */
438 { 0x00, 0x00 }, /* E9 */
439 { 0x00, 0x00 }, /* EA */
440 { 0x00, 0x00 }, /* EB */
441 { 0x00, 0x00 }, /* EC */
442 { 0x00, 0x00 }, /* ED */
443 { 0x00, 0x00 }, /* EE */
444 { 0x00, 0x00 }, /* EF */
445 { 0x00, 0x00 }, /* F0 */
446 { 0x00, 0x00 }, /* F1 */
447 { 0x00, 0x00 }, /* F2 */
448 { 0x00, 0x00 }, /* F3 */
449 { 0x00, 0x00 }, /* F4 */
450 { 0x00, 0x00 }, /* F5 */
451 { 0x00, 0x00 }, /* F6 */
452 { 0x00, 0x00 }, /* F7 */
453 { 0x00, 0x00 }, /* F8 */
454 { 0x00, 0x00 }, /* F9 */
455 { 0x00, 0x00 }, /* FA */
456 { 0x00, 0x00 }, /* FB */
457 { 0x00, 0x00 }, /* FC */
458 { 0x00, 0x00 }, /* FD */
459 { 0x00, 0x00 }, /* FE */
460 { 0xFF, 0x00 }, /* FF */
461};
462
14acbbbb 463static bool max98095_readable(struct device *dev, unsigned int reg)
82a5a936
PH		 464{
465 if (reg >= M98095_REG_CNT)
466 return 0;
467 return max98095_access[reg].readable != 0;
468}
469
14acbbbb 470static bool max98095_volatile(struct device *dev, unsigned int reg)
82a5a936
PH		 471{
472 if (reg > M98095_REG_MAX_CACHED)
473 return 1;
474
475 switch (reg) {
476 case M98095_000_HOST_DATA:
477 case M98095_001_HOST_INT_STS:
478 case M98095_002_HOST_RSP_STS:
479 case M98095_003_HOST_CMD_STS:
480 case M98095_004_CODEC_STS:
481 case M98095_005_DAI1_ALC_STS:
482 case M98095_006_DAI2_ALC_STS:
483 case M98095_007_JACK_AUTO_STS:
484 case M98095_008_JACK_MANUAL_STS:
485 case M98095_009_JACK_VBAT_STS:
486 case M98095_00A_ACC_ADC_STS:
487 case M98095_00B_MIC_NG_AGC_STS:
488 case M98095_00C_SPK_L_VOLT_STS:
489 case M98095_00D_SPK_R_VOLT_STS:
490 case M98095_00E_TEMP_SENSOR_STS:
491 return 1;
492 }
493
494 return 0;
495}
496
14acbbbb
MB		 497static const struct regmap_config max98095_regmap = {
498 .reg_bits = 8,
499 .val_bits = 8,
dad31ec1 500
14acbbbb
MB		 501 .reg_defaults = max98095_reg_def,
502 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
503 .max_register = M98095_0FF_REV_ID,
504 .cache_type = REGCACHE_RBTREE,
0d8d2938 505
14acbbbb
MB		 506 .readable_reg = max98095_readable,
507 .volatile_reg = max98095_volatile,
508};
dad31ec1
PH		 509
510/*
511 * Load equalizer DSP coefficient configurations registers
512 */
513static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
514 unsigned int band, u16 *coefs)
515{
516 unsigned int eq_reg;
517 unsigned int i;
518
a922cd71
TI		 519 if (WARN_ON(band > 4) ||
520 WARN_ON(dai > 1))
521 return;
dad31ec1
PH		 522
523 /* Load the base register address */
524 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
525
526 /* Add the band address offset, note adjustment for word address */
527 eq_reg += band * (M98095_COEFS_PER_BAND << 1);
528
529 /* Step through the registers and coefs */
530 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
d36126ac
MB		 531 snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
532 snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
dad31ec1
PH		 533 }
534}
535
536/*
537 * Load biquad filter coefficient configurations registers
538 */
539static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
540 unsigned int band, u16 *coefs)
541{
542 unsigned int bq_reg;
543 unsigned int i;
544
a922cd71
TI		 545 if (WARN_ON(band > 1) ||
546 WARN_ON(dai > 1))
547 return;
dad31ec1
PH		 548
549 /* Load the base register address */
550 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
551
552 /* Add the band address offset, note adjustment for word address */
553 bq_reg += band * (M98095_COEFS_PER_BAND << 1);
554
555 /* Step through the registers and coefs */
556 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
d36126ac
MB		 557 snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
558 snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
dad31ec1
PH		 559 }
560}
561
82a5a936 562static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
af1f0a50
TI		 563static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
564 M98095_02E_DAI1_FILTERS, 7,
565 max98095_fltr_mode);
566static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
567 M98095_038_DAI2_FILTERS, 7,
568 max98095_fltr_mode);
82a5a936
PH		 569
570static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
571
af1f0a50
TI		 572static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
573 M98095_087_CFG_MIC, 0,
574 max98095_extmic_text);
82a5a936
PH		 575
576static const struct snd_kcontrol_new max98095_extmic_mux =
577 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
578
579static const char * const max98095_linein_text[] = { "INA", "INB" };
580
af1f0a50
TI		 581static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
582 M98095_086_CFG_LINE, 6,
583 max98095_linein_text);
82a5a936
PH		 584
585static const struct snd_kcontrol_new max98095_linein_mux =
586 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
587
588static const char * const max98095_line_mode_text[] = {
589 "Stereo", "Differential"};
590
af1f0a50
TI		 591static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
592 M98095_086_CFG_LINE, 7,
593 max98095_line_mode_text);
82a5a936 594
af1f0a50
TI		 595static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
596 M98095_086_CFG_LINE, 4,
597 max98095_line_mode_text);
82a5a936
PH		 598
599static const char * const max98095_dai_fltr[] = {
600 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
601 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
af1f0a50
TI		 602static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
603 M98095_02E_DAI1_FILTERS, 0,
604 max98095_dai_fltr);
605static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
606 M98095_038_DAI2_FILTERS, 0,
607 max98095_dai_fltr);
608static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
609 M98095_042_DAI3_FILTERS, 0,
610 max98095_dai_fltr);
82a5a936
PH		 611
612static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
613 struct snd_ctl_elem_value *ucontrol)
614{
615 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
616 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
617 unsigned int sel = ucontrol->value.integer.value[0];
618
619 max98095->mic1pre = sel;
620 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
621 (1+sel)<<M98095_MICPRE_SHIFT);
622
623 return 0;
624}
625
626static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
627 struct snd_ctl_elem_value *ucontrol)
628{
629 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
630 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
631
632 ucontrol->value.integer.value[0] = max98095->mic1pre;
633 return 0;
634}
635
636static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
637 struct snd_ctl_elem_value *ucontrol)
638{
639 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
640 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
641 unsigned int sel = ucontrol->value.integer.value[0];
642
643 max98095->mic2pre = sel;
644 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
645 (1+sel)<<M98095_MICPRE_SHIFT);
646
647 return 0;
648}
649
650static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
651 struct snd_ctl_elem_value *ucontrol)
652{
653 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
654 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
655
656 ucontrol->value.integer.value[0] = max98095->mic2pre;
657 return 0;
658}
659
660static const unsigned int max98095_micboost_tlv[] = {
661 TLV_DB_RANGE_HEAD(2),
662 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
663 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
664};
665
666static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
667static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
668static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
669
670static const unsigned int max98095_hp_tlv[] = {
671 TLV_DB_RANGE_HEAD(5),
672 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
673 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
674 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
675 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
676 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
677};
678
679static const unsigned int max98095_spk_tlv[] = {
680 TLV_DB_RANGE_HEAD(4),
681 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
682 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
683 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
684 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0),
685};
686
687static const unsigned int max98095_rcv_lout_tlv[] = {
688 TLV_DB_RANGE_HEAD(5),
689 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
690 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
691 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
692 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
693 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
694};
695
696static const unsigned int max98095_lin_tlv[] = {
697 TLV_DB_RANGE_HEAD(3),
698 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
699 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
700 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
701};
702
703static const struct snd_kcontrol_new max98095_snd_controls[] = {
704
705 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
706 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
707
708 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
709 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
710
711 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
712 0, 31, 0, max98095_rcv_lout_tlv),
713
714 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
715 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
716
717 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
718 M98095_065_LVL_HP_R, 7, 1, 1),
719
720 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
721 M98095_068_LVL_SPK_R, 7, 1, 1),
722
723 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
724
725 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
726 M98095_063_LVL_LINEOUT2, 7, 1, 1),
727
728 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
729 max98095_mic_tlv),
730
731 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
732 max98095_mic_tlv),
733
734 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
735 M98095_05F_LVL_MIC1, 5, 2, 0,
736 max98095_mic1pre_get, max98095_mic1pre_set,
737 max98095_micboost_tlv),
738 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
739 M98095_060_LVL_MIC2, 5, 2, 0,
740 max98095_mic2pre_get, max98095_mic2pre_set,
741 max98095_micboost_tlv),
742
743 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
744 max98095_lin_tlv),
745
746 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
747 max98095_adc_tlv),
748 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
749 max98095_adc_tlv),
750
751 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
752 max98095_adcboost_tlv),
753 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
754 max98095_adcboost_tlv),
755
dad31ec1
PH		 756 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
757 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
758
759 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
760 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
761
82a5a936
PH		 762 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
763 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
764 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
765 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
766 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
767
768 SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
769 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
770};
771
772/* Left speaker mixer switch */
773static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
774 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
775 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
776 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
777 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
778 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
779 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
780 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
781 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
782};
783
784/* Right speaker mixer switch */
785static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
786 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
787 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
788 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
789 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
790 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
791 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
792 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
793 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
794};
795
796/* Left headphone mixer switch */
797static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
798 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
799 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
800 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
801 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
802 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
803 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
804};
805
806/* Right headphone mixer switch */
807static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
808 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
809 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
810 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
811 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
812 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
813 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
814};
815
816/* Receiver earpiece mixer switch */
817static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
818 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
819 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
820 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
821 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
822 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
823 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
824};
825
826/* Left lineout mixer switch */
827static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
828 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
829 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
830 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
831 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
832 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
833 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
834};
835
836/* Right lineout mixer switch */
837static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
838 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
839 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
840 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
841 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
842 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
843 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
844};
845
846/* Left ADC mixer switch */
847static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
848 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
849 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
850 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
851 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
852};
853
854/* Right ADC mixer switch */
855static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
856 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
857 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
858 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
859 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
860};
861
862static int max98095_mic_event(struct snd_soc_dapm_widget *w,
863 struct snd_kcontrol *kcontrol, int event)
864{
865 struct snd_soc_codec *codec = w->codec;
866 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
867
868 switch (event) {
869 case SND_SOC_DAPM_POST_PMU:
870 if (w->reg == M98095_05F_LVL_MIC1) {
871 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
872 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
873 } else {
874 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
875 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
876 }
877 break;
878 case SND_SOC_DAPM_POST_PMD:
879 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0);
880 break;
881 default:
882 return -EINVAL;
883 }
884
885 return 0;
886}
887
888/*
889 * The line inputs are stereo inputs with the left and right
890 * channels sharing a common PGA power control signal.
891 */
892static int max98095_line_pga(struct snd_soc_dapm_widget *w,
893 int event, u8 channel)
894{
895 struct snd_soc_codec *codec = w->codec;
896 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
897 u8 *state;
898
a922cd71
TI		 899 if (WARN_ON(!(channel == 1 || channel == 2)))
900 return -EINVAL;
82a5a936
PH		 901
902 state = &max98095->lin_state;
903
904 switch (event) {
905 case SND_SOC_DAPM_POST_PMU:
906 *state |= channel;
907 snd_soc_update_bits(codec, w->reg,
908 (1 << w->shift), (1 << w->shift));
909 break;
910 case SND_SOC_DAPM_POST_PMD:
911 *state &= ~channel;
912 if (*state == 0) {
913 snd_soc_update_bits(codec, w->reg,
914 (1 << w->shift), 0);
915 }
916 break;
917 default:
918 return -EINVAL;
919 }
920
921 return 0;
922}
923
924static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
925 struct snd_kcontrol *k, int event)
926{
927 return max98095_line_pga(w, event, 1);
928}
929
930static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
931 struct snd_kcontrol *k, int event)
932{
933 return max98095_line_pga(w, event, 2);
934}
935
936/*
937 * The stereo line out mixer outputs to two stereo line outs.
938 * The 2nd pair has a separate set of enables.
939 */
940static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
941 struct snd_kcontrol *kcontrol, int event)
942{
943 struct snd_soc_codec *codec = w->codec;
944
945 switch (event) {
946 case SND_SOC_DAPM_POST_PMU:
947 snd_soc_update_bits(codec, w->reg,
948 (1 << (w->shift+2)), (1 << (w->shift+2)));
949 break;
950 case SND_SOC_DAPM_POST_PMD:
951 snd_soc_update_bits(codec, w->reg,
952 (1 << (w->shift+2)), 0);
953 break;
954 default:
955 return -EINVAL;
956 }
957
958 return 0;
959}
960
961static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
962
963 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
964 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
965
966 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
967 M98095_091_PWR_EN_OUT, 0, 0),
968 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
969 M98095_091_PWR_EN_OUT, 1, 0),
970 SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
971 M98095_091_PWR_EN_OUT, 2, 0),
972 SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
973 M98095_091_PWR_EN_OUT, 2, 0),
974
975 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
976 6, 0, NULL, 0),
977 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
978 7, 0, NULL, 0),
979
980 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
981 4, 0, NULL, 0),
982 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
983 5, 0, NULL, 0),
984
985 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
986 3, 0, NULL, 0),
987
988 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
989 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
990 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
991 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
992
993 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
994 &max98095_extmic_mux),
995
996 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
997 &max98095_linein_mux),
998
999 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1000 &max98095_left_hp_mixer_controls[0],
1001 ARRAY_SIZE(max98095_left_hp_mixer_controls)),
1002
1003 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1004 &max98095_right_hp_mixer_controls[0],
1005 ARRAY_SIZE(max98095_right_hp_mixer_controls)),
1006
1007 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1008 &max98095_left_speaker_mixer_controls[0],
1009 ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
1010
1011 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1012 &max98095_right_speaker_mixer_controls[0],
1013 ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
1014
1015 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
1016 &max98095_mono_rcv_mixer_controls[0],
1017 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
1018
1019 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
1020 &max98095_left_lineout_mixer_controls[0],
1021 ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
1022
1023 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
1024 &max98095_right_lineout_mixer_controls[0],
1025 ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
1026
1027 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1028 &max98095_left_ADC_mixer_controls[0],
1029 ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
1030
1031 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1032 &max98095_right_ADC_mixer_controls[0],
1033 ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
1034
1035 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
1036 5, 0, NULL, 0, max98095_mic_event,
1037 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1038
1039 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
1040 5, 0, NULL, 0, max98095_mic_event,
1041 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1042
1043 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
1044 7, 0, NULL, 0, max98095_pga_in1_event,
1045 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1046
1047 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
1048 7, 0, NULL, 0, max98095_pga_in2_event,
1049 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1050
1051 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
1052 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
1053
1054 SND_SOC_DAPM_OUTPUT("HPL"),
1055 SND_SOC_DAPM_OUTPUT("HPR"),
1056 SND_SOC_DAPM_OUTPUT("SPKL"),
1057 SND_SOC_DAPM_OUTPUT("SPKR"),
1058 SND_SOC_DAPM_OUTPUT("RCV"),
1059 SND_SOC_DAPM_OUTPUT("OUT1"),
1060 SND_SOC_DAPM_OUTPUT("OUT2"),
1061 SND_SOC_DAPM_OUTPUT("OUT3"),
1062 SND_SOC_DAPM_OUTPUT("OUT4"),
1063
1064 SND_SOC_DAPM_INPUT("MIC1"),
1065 SND_SOC_DAPM_INPUT("MIC2"),
1066 SND_SOC_DAPM_INPUT("INA1"),
1067 SND_SOC_DAPM_INPUT("INA2"),
1068 SND_SOC_DAPM_INPUT("INB1"),
1069 SND_SOC_DAPM_INPUT("INB2"),
1070};
1071
1072static const struct snd_soc_dapm_route max98095_audio_map[] = {
1073 /* Left headphone output mixer */
1074 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1075 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1076 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1077 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1078 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
1079 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
1080
1081 /* Right headphone output mixer */
1082 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
1083 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
1084 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1085 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1086 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
1087 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
1088
1089 /* Left speaker output mixer */
1090 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1091 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1092 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1093 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1094 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1095 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1096 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
1097 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
1098
1099 /* Right speaker output mixer */
1100 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
1101 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
1102 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
1103 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
1104 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1105 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1106 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
1107 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
1108
1109 /* Earpiece/Receiver output mixer */
1110 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
1111 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
1112 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1113 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1114 {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
1115 {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
1116
1117 /* Left Lineout output mixer */
1118 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1119 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1120 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1121 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1122 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
1123 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
1124
1125 /* Right lineout output mixer */
1126 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
1127 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
1128 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
1129 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
1130 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
1131 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
1132
1133 {"HP Left Out", NULL, "Left Headphone Mixer"},
1134 {"HP Right Out", NULL, "Right Headphone Mixer"},
1135 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1136 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1137 {"RCV Mono Out", NULL, "Receiver Mixer"},
1138 {"LINE Left Out", NULL, "Left Lineout Mixer"},
1139 {"LINE Right Out", NULL, "Right Lineout Mixer"},
1140
1141 {"HPL", NULL, "HP Left Out"},
1142 {"HPR", NULL, "HP Right Out"},
1143 {"SPKL", NULL, "SPK Left Out"},
1144 {"SPKR", NULL, "SPK Right Out"},
1145 {"RCV", NULL, "RCV Mono Out"},
1146 {"OUT1", NULL, "LINE Left Out"},
1147 {"OUT2", NULL, "LINE Right Out"},
1148 {"OUT3", NULL, "LINE Left Out"},
1149 {"OUT4", NULL, "LINE Right Out"},
1150
1151 /* Left ADC input mixer */
1152 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1153 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1154 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
1155 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
1156
1157 /* Right ADC input mixer */
1158 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1159 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1160 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
1161 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
1162
1163 /* Inputs */
1164 {"ADCL", NULL, "Left ADC Mixer"},
1165 {"ADCR", NULL, "Right ADC Mixer"},
1166
1167 {"IN1 Input", NULL, "INA1"},
1168 {"IN2 Input", NULL, "INA2"},
1169
1170 {"MIC1 Input", NULL, "MIC1"},
1171 {"MIC2 Input", NULL, "MIC2"},
1172};
1173
82a5a936
PH		 1174/* codec mclk clock divider coefficients */
1175static const struct {
1176 u32 rate;
1177 u8 sr;
1178} rate_table[] = {
1179 {8000, 0x01},
1180 {11025, 0x02},
1181 {16000, 0x03},
1182 {22050, 0x04},
1183 {24000, 0x05},
1184 {32000, 0x06},
1185 {44100, 0x07},
1186 {48000, 0x08},
1187 {88200, 0x09},
1188 {96000, 0x0A},
1189};
1190
1191static int rate_value(int rate, u8 *value)
1192{
1193 int i;
1194
1195 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1196 if (rate_table[i].rate >= rate) {
1197 *value = rate_table[i].sr;
1198 return 0;
1199 }
1200 }
1201 *value = rate_table[0].sr;
1202 return -EINVAL;
1203}
1204
1205static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
1206 struct snd_pcm_hw_params *params,
1207 struct snd_soc_dai *dai)
1208{
1209 struct snd_soc_codec *codec = dai->codec;
1210 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1211 struct max98095_cdata *cdata;
1212 unsigned long long ni;
1213 unsigned int rate;
1214 u8 regval;
1215
1216 cdata = &max98095->dai[0];
1217
1218 rate = params_rate(params);
1219
580ce08d
MB		 1220 switch (params_width(params)) {
1221 case 16:
82a5a936
PH		 1222 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1223 M98095_DAI_WS, 0);
1224 break;
580ce08d 1225 case 24:
82a5a936
PH		 1226 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1227 M98095_DAI_WS, M98095_DAI_WS);
1228 break;
1229 default:
1230 return -EINVAL;
1231 }
1232
1233 if (rate_value(rate, &regval))
1234 return -EINVAL;
1235
1236 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE,
1237 M98095_CLKMODE_MASK, regval);
1238 cdata->rate = rate;
1239
1240 /* Configure NI when operating as master */
1241 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
1242 if (max98095->sysclk == 0) {
1243 dev_err(codec->dev, "Invalid system clock frequency\n");
1244 return -EINVAL;
1245 }
1246 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1247 * (unsigned long long int)rate;
1248 do_div(ni, (unsigned long long int)max98095->sysclk);
1249 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1250 (ni >> 8) & 0x7F);
1251 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1252 ni & 0xFF);
1253 }
1254
1255 /* Update sample rate mode */
1256 if (rate < 50000)
1257 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1258 M98095_DAI_DHF, 0);
1259 else
1260 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1261 M98095_DAI_DHF, M98095_DAI_DHF);
1262
1263 return 0;
1264}
1265
1266static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1267 struct snd_pcm_hw_params *params,
1268 struct snd_soc_dai *dai)
1269{
1270 struct snd_soc_codec *codec = dai->codec;
1271 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1272 struct max98095_cdata *cdata;
1273 unsigned long long ni;
1274 unsigned int rate;
1275 u8 regval;
1276
1277 cdata = &max98095->dai[1];
1278
1279 rate = params_rate(params);
1280
1281 switch (params_format(params)) {
1282 case SNDRV_PCM_FORMAT_S16_LE:
1283 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1284 M98095_DAI_WS, 0);
1285 break;
1286 case SNDRV_PCM_FORMAT_S24_LE:
1287 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1288 M98095_DAI_WS, M98095_DAI_WS);
1289 break;
1290 default:
1291 return -EINVAL;
1292 }
1293
1294 if (rate_value(rate, &regval))
1295 return -EINVAL;
1296
1297 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE,
1298 M98095_CLKMODE_MASK, regval);
1299 cdata->rate = rate;
1300
1301 /* Configure NI when operating as master */
1302 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1303 if (max98095->sysclk == 0) {
1304 dev_err(codec->dev, "Invalid system clock frequency\n");
1305 return -EINVAL;
1306 }
1307 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1308 * (unsigned long long int)rate;
1309 do_div(ni, (unsigned long long int)max98095->sysclk);
1310 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1311 (ni >> 8) & 0x7F);
1312 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1313 ni & 0xFF);
1314 }
1315
1316 /* Update sample rate mode */
1317 if (rate < 50000)
1318 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1319 M98095_DAI_DHF, 0);
1320 else
1321 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1322 M98095_DAI_DHF, M98095_DAI_DHF);
1323
1324 return 0;
1325}
1326
1327static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1328 struct snd_pcm_hw_params *params,
1329 struct snd_soc_dai *dai)
1330{
1331 struct snd_soc_codec *codec = dai->codec;
1332 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1333 struct max98095_cdata *cdata;
1334 unsigned long long ni;
1335 unsigned int rate;
1336 u8 regval;
1337
1338 cdata = &max98095->dai[2];
1339
1340 rate = params_rate(params);
1341
1342 switch (params_format(params)) {
1343 case SNDRV_PCM_FORMAT_S16_LE:
1344 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1345 M98095_DAI_WS, 0);
1346 break;
1347 case SNDRV_PCM_FORMAT_S24_LE:
1348 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1349 M98095_DAI_WS, M98095_DAI_WS);
1350 break;
1351 default:
1352 return -EINVAL;
1353 }
1354
1355 if (rate_value(rate, &regval))
1356 return -EINVAL;
1357
1358 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE,
1359 M98095_CLKMODE_MASK, regval);
1360 cdata->rate = rate;
1361
1362 /* Configure NI when operating as master */
1363 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1364 if (max98095->sysclk == 0) {
1365 dev_err(codec->dev, "Invalid system clock frequency\n");
1366 return -EINVAL;
1367 }
1368 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1369 * (unsigned long long int)rate;
1370 do_div(ni, (unsigned long long int)max98095->sysclk);
1371 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1372 (ni >> 8) & 0x7F);
1373 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1374 ni & 0xFF);
1375 }
1376
1377 /* Update sample rate mode */
1378 if (rate < 50000)
1379 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1380 M98095_DAI_DHF, 0);
1381 else
1382 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1383 M98095_DAI_DHF, M98095_DAI_DHF);
1384
1385 return 0;
1386}
1387
1388static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1389 int clk_id, unsigned int freq, int dir)
1390{
1391 struct snd_soc_codec *codec = dai->codec;
1392 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1393
1394 /* Requested clock frequency is already setup */
1395 if (freq == max98095->sysclk)
1396 return 0;
1397
82a5a936
PH		 1398 /* Setup clocks for slave mode, and using the PLL
1399 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1400 * 0x02 (when master clk is 20MHz to 40MHz)..
1401 * 0x03 (when master clk is 40MHz to 60MHz)..
1402 */
1403 if ((freq >= 10000000) && (freq < 20000000)) {
1404 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10);
1405 } else if ((freq >= 20000000) && (freq < 40000000)) {
1406 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20);
1407 } else if ((freq >= 40000000) && (freq < 60000000)) {
1408 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30);
1409 } else {
1410 dev_err(codec->dev, "Invalid master clock frequency\n");
1411 return -EINVAL;
1412 }
1413
1414 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1415
1416 max98095->sysclk = freq;
1417 return 0;
1418}
1419
1420static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1421 unsigned int fmt)
1422{
1423 struct snd_soc_codec *codec = codec_dai->codec;
1424 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1425 struct max98095_cdata *cdata;
1426 u8 regval = 0;
1427
1428 cdata = &max98095->dai[0];
1429
1430 if (fmt != cdata->fmt) {
1431 cdata->fmt = fmt;
1432
1433 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1434 case SND_SOC_DAIFMT_CBS_CFS:
1435 /* Slave mode PLL */
1436 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1437 0x80);
1438 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1439 0x00);
1440 break;
1441 case SND_SOC_DAIFMT_CBM_CFM:
1442 /* Set to master mode */
1443 regval |= M98095_DAI_MAS;
1444 break;
1445 case SND_SOC_DAIFMT_CBS_CFM:
1446 case SND_SOC_DAIFMT_CBM_CFS:
1447 default:
1448 dev_err(codec->dev, "Clock mode unsupported");
1449 return -EINVAL;
1450 }
1451
1452 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1453 case SND_SOC_DAIFMT_I2S:
1454 regval |= M98095_DAI_DLY;
1455 break;
1456 case SND_SOC_DAIFMT_LEFT_J:
1457 break;
1458 default:
1459 return -EINVAL;
1460 }
1461
1462 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1463 case SND_SOC_DAIFMT_NB_NF:
1464 break;
1465 case SND_SOC_DAIFMT_NB_IF:
1466 regval |= M98095_DAI_WCI;
1467 break;
1468 case SND_SOC_DAIFMT_IB_NF:
1469 regval |= M98095_DAI_BCI;
1470 break;
1471 case SND_SOC_DAIFMT_IB_IF:
1472 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1473 break;
1474 default:
1475 return -EINVAL;
1476 }
1477
1478 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1479 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1480 M98095_DAI_WCI, regval);
1481
1482 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1483 }
1484
1485 return 0;
1486}
1487
1488static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1489 unsigned int fmt)
1490{
1491 struct snd_soc_codec *codec = codec_dai->codec;
1492 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1493 struct max98095_cdata *cdata;
1494 u8 regval = 0;
1495
1496 cdata = &max98095->dai[1];
1497
1498 if (fmt != cdata->fmt) {
1499 cdata->fmt = fmt;
1500
1501 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1502 case SND_SOC_DAIFMT_CBS_CFS:
1503 /* Slave mode PLL */
1504 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1505 0x80);
1506 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1507 0x00);
1508 break;
1509 case SND_SOC_DAIFMT_CBM_CFM:
1510 /* Set to master mode */
1511 regval |= M98095_DAI_MAS;
1512 break;
1513 case SND_SOC_DAIFMT_CBS_CFM:
1514 case SND_SOC_DAIFMT_CBM_CFS:
1515 default:
1516 dev_err(codec->dev, "Clock mode unsupported");
1517 return -EINVAL;
1518 }
1519
1520 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1521 case SND_SOC_DAIFMT_I2S:
1522 regval |= M98095_DAI_DLY;
1523 break;
1524 case SND_SOC_DAIFMT_LEFT_J:
1525 break;
1526 default:
1527 return -EINVAL;
1528 }
1529
1530 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1531 case SND_SOC_DAIFMT_NB_NF:
1532 break;
1533 case SND_SOC_DAIFMT_NB_IF:
1534 regval |= M98095_DAI_WCI;
1535 break;
1536 case SND_SOC_DAIFMT_IB_NF:
1537 regval |= M98095_DAI_BCI;
1538 break;
1539 case SND_SOC_DAIFMT_IB_IF:
1540 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1541 break;
1542 default:
1543 return -EINVAL;
1544 }
1545
1546 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1547 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1548 M98095_DAI_WCI, regval);
1549
1550 snd_soc_write(codec, M98095_035_DAI2_CLOCK,
1551 M98095_DAI_BSEL64);
1552 }
1553
1554 return 0;
1555}
1556
1557static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1558 unsigned int fmt)
1559{
1560 struct snd_soc_codec *codec = codec_dai->codec;
1561 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1562 struct max98095_cdata *cdata;
1563 u8 regval = 0;
1564
1565 cdata = &max98095->dai[2];
1566
1567 if (fmt != cdata->fmt) {
1568 cdata->fmt = fmt;
1569
1570 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1571 case SND_SOC_DAIFMT_CBS_CFS:
1572 /* Slave mode PLL */
1573 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1574 0x80);
1575 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1576 0x00);
1577 break;
1578 case SND_SOC_DAIFMT_CBM_CFM:
1579 /* Set to master mode */
1580 regval |= M98095_DAI_MAS;
1581 break;
1582 case SND_SOC_DAIFMT_CBS_CFM:
1583 case SND_SOC_DAIFMT_CBM_CFS:
1584 default:
1585 dev_err(codec->dev, "Clock mode unsupported");
1586 return -EINVAL;
1587 }
1588
1589 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1590 case SND_SOC_DAIFMT_I2S:
1591 regval |= M98095_DAI_DLY;
1592 break;
1593 case SND_SOC_DAIFMT_LEFT_J:
1594 break;
1595 default:
1596 return -EINVAL;
1597 }
1598
1599 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1600 case SND_SOC_DAIFMT_NB_NF:
1601 break;
1602 case SND_SOC_DAIFMT_NB_IF:
1603 regval |= M98095_DAI_WCI;
1604 break;
1605 case SND_SOC_DAIFMT_IB_NF:
1606 regval |= M98095_DAI_BCI;
1607 break;
1608 case SND_SOC_DAIFMT_IB_IF:
1609 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1610 break;
1611 default:
1612 return -EINVAL;
1613 }
1614
1615 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1616 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1617 M98095_DAI_WCI, regval);
1618
1619 snd_soc_write(codec, M98095_03F_DAI3_CLOCK,
1620 M98095_DAI_BSEL64);
1621 }
1622
1623 return 0;
1624}
1625
1626static int max98095_set_bias_level(struct snd_soc_codec *codec,
1627 enum snd_soc_bias_level level)
1628{
14acbbbb 1629 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
82a5a936
PH		 1630 int ret;
1631
1632 switch (level) {
1633 case SND_SOC_BIAS_ON:
1634 break;
1635
1636 case SND_SOC_BIAS_PREPARE:
1637 break;
1638
1639 case SND_SOC_BIAS_STANDBY:
1640 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
14acbbbb 1641 ret = regcache_sync(max98095->regmap);
82a5a936
PH		 1642
1643 if (ret != 0) {
1644 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1645 return ret;
1646 }
1647 }
1648
1649 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1650 M98095_MBEN, M98095_MBEN);
1651 break;
1652
1653 case SND_SOC_BIAS_OFF:
1654 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1655 M98095_MBEN, 0);
14acbbbb 1656 regcache_mark_dirty(max98095->regmap);
82a5a936
PH		 1657 break;
1658 }
1659 codec->dapm.bias_level = level;
1660 return 0;
1661}
1662
1663#define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1664#define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1665
85e7652d 1666static const struct snd_soc_dai_ops max98095_dai1_ops = {
82a5a936
PH		 1667 .set_sysclk = max98095_dai_set_sysclk,
1668 .set_fmt = max98095_dai1_set_fmt,
1669 .hw_params = max98095_dai1_hw_params,
1670};
1671
85e7652d 1672static const struct snd_soc_dai_ops max98095_dai2_ops = {
82a5a936
PH		 1673 .set_sysclk = max98095_dai_set_sysclk,
1674 .set_fmt = max98095_dai2_set_fmt,
1675 .hw_params = max98095_dai2_hw_params,
1676};
1677
85e7652d 1678static const struct snd_soc_dai_ops max98095_dai3_ops = {
82a5a936
PH		 1679 .set_sysclk = max98095_dai_set_sysclk,
1680 .set_fmt = max98095_dai3_set_fmt,
1681 .hw_params = max98095_dai3_hw_params,
1682};
1683
1684static struct snd_soc_dai_driver max98095_dai[] = {
1685{
1686 .name = "HiFi",
1687 .playback = {
1688 .stream_name = "HiFi Playback",
1689 .channels_min = 1,
1690 .channels_max = 2,
1691 .rates = MAX98095_RATES,
1692 .formats = MAX98095_FORMATS,
1693 },
1694 .capture = {
1695 .stream_name = "HiFi Capture",
1696 .channels_min = 1,
1697 .channels_max = 2,
1698 .rates = MAX98095_RATES,
1699 .formats = MAX98095_FORMATS,
1700 },
1701 .ops = &max98095_dai1_ops,
1702},
1703{
1704 .name = "Aux",
1705 .playback = {
1706 .stream_name = "Aux Playback",
1707 .channels_min = 1,
1708 .channels_max = 1,
1709 .rates = MAX98095_RATES,
1710 .formats = MAX98095_FORMATS,
1711 },
1712 .ops = &max98095_dai2_ops,
1713},
1714{
1715 .name = "Voice",
1716 .playback = {
1717 .stream_name = "Voice Playback",
1718 .channels_min = 1,
1719 .channels_max = 1,
1720 .rates = MAX98095_RATES,
1721 .formats = MAX98095_FORMATS,
1722 },
1723 .ops = &max98095_dai3_ops,
1724}
1725
1726};
1727
dad31ec1
PH		 1728static int max98095_get_eq_channel(const char *name)
1729{
1730 if (strcmp(name, "EQ1 Mode") == 0)
1731 return 0;
1732 if (strcmp(name, "EQ2 Mode") == 0)
1733 return 1;
1734 return -EINVAL;
1735}
1736
1737static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1738 struct snd_ctl_elem_value *ucontrol)
1739{
1740 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1741 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1742 struct max98095_pdata *pdata = max98095->pdata;
1743 int channel = max98095_get_eq_channel(kcontrol->id.name);
1744 struct max98095_cdata *cdata;
f8d7b13e 1745 unsigned int sel = ucontrol->value.integer.value[0];
dad31ec1
PH		 1746 struct max98095_eq_cfg *coef_set;
1747 int fs, best, best_val, i;
1748 int regmask, regsave;
1749
a922cd71
TI		 1750 if (WARN_ON(channel > 1))
1751 return -EINVAL;
dad31ec1 1752
53949425
TH		 1753 if (!pdata || !max98095->eq_textcnt)
1754 return 0;
dad31ec1
PH		 1755
1756 if (sel >= pdata->eq_cfgcnt)
1757 return -EINVAL;
1758
53949425 1759 cdata = &max98095->dai[channel];
dad31ec1 1760 cdata->eq_sel = sel;
dad31ec1
PH		 1761 fs = cdata->rate;
1762
1763 /* Find the selected configuration with nearest sample rate */
1764 best = 0;
1765 best_val = INT_MAX;
1766 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1767 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1768 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1769 best = i;
1770 best_val = abs(pdata->eq_cfg[i].rate - fs);
1771 }
1772 }
1773
1774 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1775 pdata->eq_cfg[best].name,
1776 pdata->eq_cfg[best].rate, fs);
1777
1778 coef_set = &pdata->eq_cfg[best];
1779
1780 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1781
1782 /* Disable filter while configuring, and save current on/off state */
1783 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1784 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1785
1786 mutex_lock(&codec->mutex);
1787 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1788 m98095_eq_band(codec, channel, 0, coef_set->band1);
1789 m98095_eq_band(codec, channel, 1, coef_set->band2);
1790 m98095_eq_band(codec, channel, 2, coef_set->band3);
1791 m98095_eq_band(codec, channel, 3, coef_set->band4);
1792 m98095_eq_band(codec, channel, 4, coef_set->band5);
1793 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
1794 mutex_unlock(&codec->mutex);
1795
1796 /* Restore the original on/off state */
1797 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1798 return 0;
1799}
1800
1801static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1802 struct snd_ctl_elem_value *ucontrol)
1803{
1804 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1805 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1806 int channel = max98095_get_eq_channel(kcontrol->id.name);
1807 struct max98095_cdata *cdata;
1808
1809 cdata = &max98095->dai[channel];
1810 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1811
1812 return 0;
1813}
1814
1815static void max98095_handle_eq_pdata(struct snd_soc_codec *codec)
1816{
1817 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1818 struct max98095_pdata *pdata = max98095->pdata;
1819 struct max98095_eq_cfg *cfg;
1820 unsigned int cfgcnt;
1821 int i, j;
1822 const char **t;
1823 int ret;
1824
1825 struct snd_kcontrol_new controls[] = {
1826 SOC_ENUM_EXT("EQ1 Mode",
1827 max98095->eq_enum,
1828 max98095_get_eq_enum,
1829 max98095_put_eq_enum),
1830 SOC_ENUM_EXT("EQ2 Mode",
1831 max98095->eq_enum,
1832 max98095_get_eq_enum,
1833 max98095_put_eq_enum),
1834 };
1835
1836 cfg = pdata->eq_cfg;
1837 cfgcnt = pdata->eq_cfgcnt;
1838
1839 /* Setup an array of texts for the equalizer enum.
1840 * This is based on Mark Brown's equalizer driver code.
1841 */
1842 max98095->eq_textcnt = 0;
1843 max98095->eq_texts = NULL;
1844 for (i = 0; i < cfgcnt; i++) {
1845 for (j = 0; j < max98095->eq_textcnt; j++) {
1846 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1847 break;
1848 }
1849
1850 if (j != max98095->eq_textcnt)
1851 continue;
1852
1853 /* Expand the array */
1854 t = krealloc(max98095->eq_texts,
1855 sizeof(char *) * (max98095->eq_textcnt + 1),
1856 GFP_KERNEL);
1857 if (t == NULL)
1858 continue;
1859
1860 /* Store the new entry */
1861 t[max98095->eq_textcnt] = cfg[i].name;
1862 max98095->eq_textcnt++;
1863 max98095->eq_texts = t;
1864 }
1865
1866 /* Now point the soc_enum to .texts array items */
1867 max98095->eq_enum.texts = max98095->eq_texts;
9a8d38db 1868 max98095->eq_enum.items = max98095->eq_textcnt;
dad31ec1 1869
022658be 1870 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
dad31ec1
PH		 1871 if (ret != 0)
1872 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1873}
1874
c855a1a7
RM		 1875static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1876
1877static int max98095_get_bq_channel(struct snd_soc_codec *codec,
1878 const char *name)
dad31ec1 1879{
c855a1a7
RM		 1880 int i;
1881
1882 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++)
1883 if (strcmp(name, bq_mode_name[i]) == 0)
1884 return i;
1885
1886 /* Shouldn't happen */
1887 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name);
dad31ec1
PH		 1888 return -EINVAL;
1889}
1890
1891static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1892 struct snd_ctl_elem_value *ucontrol)
1893{
1894 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1895 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1896 struct max98095_pdata *pdata = max98095->pdata;
c855a1a7 1897 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
dad31ec1 1898 struct max98095_cdata *cdata;
f8d7b13e 1899 unsigned int sel = ucontrol->value.integer.value[0];
dad31ec1
PH		 1900 struct max98095_biquad_cfg *coef_set;
1901 int fs, best, best_val, i;
1902 int regmask, regsave;
1903
c855a1a7
RM		 1904 if (channel < 0)
1905 return channel;
dad31ec1 1906
53949425
TH		 1907 if (!pdata || !max98095->bq_textcnt)
1908 return 0;
dad31ec1
PH		 1909
1910 if (sel >= pdata->bq_cfgcnt)
1911 return -EINVAL;
1912
53949425 1913 cdata = &max98095->dai[channel];
dad31ec1 1914 cdata->bq_sel = sel;
dad31ec1
PH		 1915 fs = cdata->rate;
1916
1917 /* Find the selected configuration with nearest sample rate */
1918 best = 0;
1919 best_val = INT_MAX;
1920 for (i = 0; i < pdata->bq_cfgcnt; i++) {
1921 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
1922 abs(pdata->bq_cfg[i].rate - fs) < best_val) {
1923 best = i;
1924 best_val = abs(pdata->bq_cfg[i].rate - fs);
1925 }
1926 }
1927
1928 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1929 pdata->bq_cfg[best].name,
1930 pdata->bq_cfg[best].rate, fs);
1931
1932 coef_set = &pdata->bq_cfg[best];
1933
1934 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
1935
1936 /* Disable filter while configuring, and save current on/off state */
1937 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1938 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1939
1940 mutex_lock(&codec->mutex);
1941 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1942 m98095_biquad_band(codec, channel, 0, coef_set->band1);
1943 m98095_biquad_band(codec, channel, 1, coef_set->band2);
1944 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
1945 mutex_unlock(&codec->mutex);
1946
1947 /* Restore the original on/off state */
1948 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1949 return 0;
1950}
1951
1952static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1953 struct snd_ctl_elem_value *ucontrol)
1954{
1955 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1956 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
c855a1a7 1957 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
dad31ec1
PH		 1958 struct max98095_cdata *cdata;
1959
c855a1a7
RM		 1960 if (channel < 0)
1961 return channel;
1962
dad31ec1
PH		 1963 cdata = &max98095->dai[channel];
1964 ucontrol->value.enumerated.item[0] = cdata->bq_sel;
1965
1966 return 0;
1967}
1968
1969static void max98095_handle_bq_pdata(struct snd_soc_codec *codec)
1970{
1971 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1972 struct max98095_pdata *pdata = max98095->pdata;
1973 struct max98095_biquad_cfg *cfg;
1974 unsigned int cfgcnt;
1975 int i, j;
1976 const char **t;
1977 int ret;
1978
1979 struct snd_kcontrol_new controls[] = {
c855a1a7 1980 SOC_ENUM_EXT((char *)bq_mode_name[0],
dad31ec1
PH		 1981 max98095->bq_enum,
1982 max98095_get_bq_enum,
1983 max98095_put_bq_enum),
c855a1a7 1984 SOC_ENUM_EXT((char *)bq_mode_name[1],
dad31ec1
PH		 1985 max98095->bq_enum,
1986 max98095_get_bq_enum,
1987 max98095_put_bq_enum),
1988 };
c855a1a7 1989 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
dad31ec1
PH		 1990
1991 cfg = pdata->bq_cfg;
1992 cfgcnt = pdata->bq_cfgcnt;
1993
1994 /* Setup an array of texts for the biquad enum.
1995 * This is based on Mark Brown's equalizer driver code.
1996 */
1997 max98095->bq_textcnt = 0;
1998 max98095->bq_texts = NULL;
1999 for (i = 0; i < cfgcnt; i++) {
2000 for (j = 0; j < max98095->bq_textcnt; j++) {
2001 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
2002 break;
2003 }
2004
2005 if (j != max98095->bq_textcnt)
2006 continue;
2007
2008 /* Expand the array */
2009 t = krealloc(max98095->bq_texts,
2010 sizeof(char *) * (max98095->bq_textcnt + 1),
2011 GFP_KERNEL);
2012 if (t == NULL)
2013 continue;
2014
2015 /* Store the new entry */
2016 t[max98095->bq_textcnt] = cfg[i].name;
2017 max98095->bq_textcnt++;
2018 max98095->bq_texts = t;
2019 }
2020
2021 /* Now point the soc_enum to .texts array items */
2022 max98095->bq_enum.texts = max98095->bq_texts;
9a8d38db 2023 max98095->bq_enum.items = max98095->bq_textcnt;
dad31ec1 2024
022658be 2025 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
dad31ec1
PH		 2026 if (ret != 0)
2027 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret);
2028}
2029
82a5a936
PH		 2030static void max98095_handle_pdata(struct snd_soc_codec *codec)
2031{
2032 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2033 struct max98095_pdata *pdata = max98095->pdata;
2034 u8 regval = 0;
2035
2036 if (!pdata) {
2037 dev_dbg(codec->dev, "No platform data\n");
2038 return;
2039 }
2040
2041 /* Configure mic for analog/digital mic mode */
2042 if (pdata->digmic_left_mode)
2043 regval |= M98095_DIGMIC_L;
2044
2045 if (pdata->digmic_right_mode)
2046 regval |= M98095_DIGMIC_R;
2047
2048 snd_soc_write(codec, M98095_087_CFG_MIC, regval);
dad31ec1
PH		 2049
2050 /* Configure equalizers */
2051 if (pdata->eq_cfgcnt)
2052 max98095_handle_eq_pdata(codec);
2053
2054 /* Configure bi-quad filters */
2055 if (pdata->bq_cfgcnt)
2056 max98095_handle_bq_pdata(codec);
82a5a936
PH		 2057}
2058
9dd90c5d
RK		 2059static irqreturn_t max98095_report_jack(int irq, void *data)
2060{
2061 struct snd_soc_codec *codec = data;
2062 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2063 unsigned int value;
2064 int hp_report = 0;
2065 int mic_report = 0;
2066
2067 /* Read the Jack Status Register */
2068 value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS);
2069
2070 /* If ddone is not set, then detection isn't finished yet */
2071 if ((value & M98095_DDONE) == 0)
2072 return IRQ_NONE;
2073
2074 /* if hp, check its bit, and if set, clear it */
2075 if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
2076 max98095->headphone_jack)
2077 hp_report |= SND_JACK_HEADPHONE;
2078
2079 /* if mic, check its bit, and if set, clear it */
2080 if ((value & M98095_MIC_IN) && max98095->mic_jack)
2081 mic_report |= SND_JACK_MICROPHONE;
2082
2083 if (max98095->headphone_jack == max98095->mic_jack) {
2084 snd_soc_jack_report(max98095->headphone_jack,
2085 hp_report | mic_report,
2086 SND_JACK_HEADSET);
2087 } else {
2088 if (max98095->headphone_jack)
2089 snd_soc_jack_report(max98095->headphone_jack,
2090 hp_report, SND_JACK_HEADPHONE);
2091 if (max98095->mic_jack)
2092 snd_soc_jack_report(max98095->mic_jack,
2093 mic_report, SND_JACK_MICROPHONE);
2094 }
2095
2096 return IRQ_HANDLED;
2097}
2098
a265367c 2099static int max98095_jack_detect_enable(struct snd_soc_codec *codec)
9dd90c5d
RK		 2100{
2101 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2102 int ret = 0;
2103 int detect_enable = M98095_JDEN;
2104 unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
2105
2106 if (max98095->pdata->jack_detect_pin5en)
2107 detect_enable |= M98095_PIN5EN;
2108
0841b04a
MB		 2109 if (max98095->pdata->jack_detect_delay)
2110 slew = max98095->pdata->jack_detect_delay;
9dd90c5d
RK		 2111
2112 ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew);
2113 if (ret < 0) {
2114 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2115 return ret;
2116 }
2117
2118 /* configure auto detection to be enabled */
2119 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable);
2120 if (ret < 0) {
2121 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2122 return ret;
2123 }
2124
2125 return ret;
2126}
2127
a265367c 2128static int max98095_jack_detect_disable(struct snd_soc_codec *codec)
9dd90c5d
RK		 2129{
2130 int ret = 0;
2131
2132 /* configure auto detection to be disabled */
2133 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0);
2134 if (ret < 0) {
2135 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2136 return ret;
2137 }
2138
2139 return ret;
2140}
2141
2142int max98095_jack_detect(struct snd_soc_codec *codec,
2143 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
2144{
2145 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2146 struct i2c_client *client = to_i2c_client(codec->dev);
2147 int ret = 0;
2148
2149 max98095->headphone_jack = hp_jack;
2150 max98095->mic_jack = mic_jack;
2151
2152 /* only progress if we have at least 1 jack pointer */
2153 if (!hp_jack && !mic_jack)
2154 return -EINVAL;
2155
2156 max98095_jack_detect_enable(codec);
2157
2158 /* enable interrupts for headphone jack detection */
2159 ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN,
2160 M98095_IDDONE, M98095_IDDONE);
2161 if (ret < 0) {
2162 dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret);
2163 return ret;
2164 }
2165
2166 max98095_report_jack(client->irq, codec);
2167 return 0;
2168}
a265367c 2169EXPORT_SYMBOL_GPL(max98095_jack_detect);
9dd90c5d 2170
82a5a936 2171#ifdef CONFIG_PM
84b315ee 2172static int max98095_suspend(struct snd_soc_codec *codec)
82a5a936 2173{
9dd90c5d
RK		 2174 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2175
2176 if (max98095->headphone_jack || max98095->mic_jack)
2177 max98095_jack_detect_disable(codec);
2178
82a5a936
PH		 2179 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2180
2181 return 0;
2182}
2183
2184static int max98095_resume(struct snd_soc_codec *codec)
2185{
9dd90c5d
RK		 2186 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2187 struct i2c_client *client = to_i2c_client(codec->dev);
2188
82a5a936
PH		 2189 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2190
9dd90c5d
RK		 2191 if (max98095->headphone_jack || max98095->mic_jack) {
2192 max98095_jack_detect_enable(codec);
2193 max98095_report_jack(client->irq, codec);
2194 }
2195
82a5a936
PH		 2196 return 0;
2197}
2198#else
2199#define max98095_suspend NULL
2200#define max98095_resume NULL
2201#endif
2202
2203static int max98095_reset(struct snd_soc_codec *codec)
2204{
2205 int i, ret;
2206
2207 /* Gracefully reset the DSP core and the codec hardware
2208 * in a proper sequence */
2209 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0);
2210 if (ret < 0) {
2211 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
2212 return ret;
2213 }
2214
2215 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0);
2216 if (ret < 0) {
2217 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
2218 return ret;
2219 }
2220
2221 /* Reset to hardware default for registers, as there is not
2222 * a soft reset hardware control register */
2223 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
14acbbbb 2224 ret = snd_soc_write(codec, i, snd_soc_read(codec, i));
82a5a936
PH		 2225 if (ret < 0) {
2226 dev_err(codec->dev, "Failed to reset: %d\n", ret);
2227 return ret;
2228 }
2229 }
2230
2231 return ret;
2232}
2233
2234static int max98095_probe(struct snd_soc_codec *codec)
2235{
2236 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2237 struct max98095_cdata *cdata;
9dd90c5d 2238 struct i2c_client *client;
82a5a936
PH		 2239 int ret = 0;
2240
82a5a936
PH		 2241 /* reset the codec, the DSP core, and disable all interrupts */
2242 max98095_reset(codec);
2243
9dd90c5d
RK		 2244 client = to_i2c_client(codec->dev);
2245
82a5a936
PH		 2246 /* initialize private data */
2247
2248 max98095->sysclk = (unsigned)-1;
dad31ec1
PH		 2249 max98095->eq_textcnt = 0;
2250 max98095->bq_textcnt = 0;
82a5a936
PH		 2251
2252 cdata = &max98095->dai[0];
2253 cdata->rate = (unsigned)-1;
2254 cdata->fmt = (unsigned)-1;
dad31ec1
PH		 2255 cdata->eq_sel = 0;
2256 cdata->bq_sel = 0;
82a5a936
PH		 2257
2258 cdata = &max98095->dai[1];
2259 cdata->rate = (unsigned)-1;
2260 cdata->fmt = (unsigned)-1;
dad31ec1
PH		 2261 cdata->eq_sel = 0;
2262 cdata->bq_sel = 0;
82a5a936
PH		 2263
2264 cdata = &max98095->dai[2];
2265 cdata->rate = (unsigned)-1;
2266 cdata->fmt = (unsigned)-1;
dad31ec1
PH		 2267 cdata->eq_sel = 0;
2268 cdata->bq_sel = 0;
82a5a936
PH		 2269
2270 max98095->lin_state = 0;
2271 max98095->mic1pre = 0;
2272 max98095->mic2pre = 0;
2273
9dd90c5d
RK		 2274 if (client->irq) {
2275 /* register an audio interrupt */
2276 ret = request_threaded_irq(client->irq, NULL,
2277 max98095_report_jack,
2278 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2279 "max98095", codec);
2280 if (ret) {
2281 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret);
2282 goto err_access;
2283 }
2284 }
2285
82a5a936
PH		 2286 ret = snd_soc_read(codec, M98095_0FF_REV_ID);
2287 if (ret < 0) {
bab3b59d 2288 dev_err(codec->dev, "Failure reading hardware revision: %d\n",
82a5a936 2289 ret);
9dd90c5d 2290 goto err_irq;
82a5a936 2291 }
bab3b59d 2292 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
82a5a936
PH		 2293
2294 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV);
2295
2296 /* initialize registers cache to hardware default */
2297 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2298
2299 snd_soc_write(codec, M98095_048_MIX_DAC_LR,
2300 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2301
2302 snd_soc_write(codec, M98095_049_MIX_DAC_M,
2303 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2304
2305 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2306 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2307 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL);
2308
2309 snd_soc_write(codec, M98095_02C_DAI1_IOCFG,
2310 M98095_S1NORMAL|M98095_SDATA);
2311
2312 snd_soc_write(codec, M98095_036_DAI2_IOCFG,
2313 M98095_S2NORMAL|M98095_SDATA);
2314
2315 snd_soc_write(codec, M98095_040_DAI3_IOCFG,
2316 M98095_S3NORMAL|M98095_SDATA);
2317
2318 max98095_handle_pdata(codec);
2319
2320 /* take the codec out of the shut down */
2321 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
2322 M98095_SHDNRUN);
2323
9dd90c5d
RK		 2324 return 0;
2325
2326err_irq:
2327 if (client->irq)
2328 free_irq(client->irq, codec);
82a5a936
PH		 2329err_access:
2330 return ret;
2331}
2332
2333static int max98095_remove(struct snd_soc_codec *codec)
2334{
9dd90c5d
RK		 2335 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2336 struct i2c_client *client = to_i2c_client(codec->dev);
2337
82a5a936
PH		 2338 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2339
9dd90c5d
RK		 2340 if (max98095->headphone_jack || max98095->mic_jack)
2341 max98095_jack_detect_disable(codec);
2342
2343 if (client->irq)
2344 free_irq(client->irq, codec);
2345
82a5a936
PH		 2346 return 0;
2347}
2348
2349static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
2350 .probe = max98095_probe,
2351 .remove = max98095_remove,
2352 .suspend = max98095_suspend,
2353 .resume = max98095_resume,
2354 .set_bias_level = max98095_set_bias_level,
c6b3283f
MB		 2355 .controls = max98095_snd_controls,
2356 .num_controls = ARRAY_SIZE(max98095_snd_controls),
82a5a936
PH		 2357 .dapm_widgets = max98095_dapm_widgets,
2358 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
2359 .dapm_routes = max98095_audio_map,
2360 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
2361};
2362
2363static int max98095_i2c_probe(struct i2c_client *i2c,
2364 const struct i2c_device_id *id)
2365{
2366 struct max98095_priv *max98095;
2367 int ret;
2368
b1b54882
AL		 2369 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2370 GFP_KERNEL);
82a5a936
PH		 2371 if (max98095 == NULL)
2372 return -ENOMEM;
2373
14acbbbb
MB		 2374 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2375 if (IS_ERR(max98095->regmap)) {
2376 ret = PTR_ERR(max98095->regmap);
2377 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2378 return ret;
2379 }
2380
82a5a936
PH		 2381 max98095->devtype = id->driver_data;
2382 i2c_set_clientdata(i2c, max98095);
82a5a936
PH		 2383 max98095->pdata = i2c->dev.platform_data;
2384
bab3b59d
TH		 2385 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095,
2386 max98095_dai, ARRAY_SIZE(max98095_dai));
82a5a936
PH		 2387 return ret;
2388}
2389
7a79e94e 2390static int max98095_i2c_remove(struct i2c_client *client)
82a5a936
PH		 2391{
2392 snd_soc_unregister_codec(&client->dev);
82a5a936
PH		 2393 return 0;
2394}
2395
2396static const struct i2c_device_id max98095_i2c_id[] = {
2397 { "max98095", MAX98095 },
2398 { }
2399};
2400MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2401
c4839c87
TB		 2402static const struct of_device_id max98095_of_match[] = {
2403 { .compatible = "maxim,max98095", },
2404 { }
2405};
2406MODULE_DEVICE_TABLE(of, max98095_of_match);
2407
82a5a936
PH		 2408static struct i2c_driver max98095_i2c_driver = {
2409 .driver = {
2410 .name = "max98095",
2411 .owner = THIS_MODULE,
c4839c87 2412 .of_match_table = of_match_ptr(max98095_of_match),
82a5a936
PH		 2413 },
2414 .probe = max98095_i2c_probe,
7a79e94e 2415 .remove = max98095_i2c_remove,
82a5a936
PH		 2416 .id_table = max98095_i2c_id,
2417};
2418
a8af02cf 2419module_i2c_driver(max98095_i2c_driver);
82a5a936
PH		 2420
2421MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2422MODULE_AUTHOR("Peter Hsiang");
2423MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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