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1ff27651 AK |
1 | /* |
2 | * max98925.h -- MAX98925 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2013-2015 Maxim Integrated Products | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifndef _MAX98925_H | |
12 | #define _MAX98925_H | |
13 | ||
14 | #define MAX98925_VERSION 0x51 | |
15 | #define MAX98925_VERSION1 0x80 | |
16 | #define MAX98925_VBAT_DATA 0x00 | |
17 | #define MAX98925_VBST_DATA 0x01 | |
18 | #define MAX98925_LIVE_STATUS0 0x02 | |
19 | #define MAX98925_LIVE_STATUS1 0x03 | |
20 | #define MAX98925_LIVE_STATUS2 0x04 | |
21 | #define MAX98925_STATE0 0x05 | |
22 | #define MAX98925_STATE1 0x06 | |
23 | #define MAX98925_STATE2 0x07 | |
24 | #define MAX98925_FLAG0 0x08 | |
25 | #define MAX98925_FLAG1 0x09 | |
26 | #define MAX98925_FLAG2 0x0A | |
27 | #define MAX98925_IRQ_ENABLE0 0x0B | |
28 | #define MAX98925_IRQ_ENABLE1 0x0C | |
29 | #define MAX98925_IRQ_ENABLE2 0x0D | |
30 | #define MAX98925_IRQ_CLEAR0 0x0E | |
31 | #define MAX98925_IRQ_CLEAR1 0x0F | |
32 | #define MAX98925_IRQ_CLEAR2 0x10 | |
33 | #define MAX98925_MAP0 0x11 | |
34 | #define MAX98925_MAP1 0x12 | |
35 | #define MAX98925_MAP2 0x13 | |
36 | #define MAX98925_MAP3 0x14 | |
37 | #define MAX98925_MAP4 0x15 | |
38 | #define MAX98925_MAP5 0x16 | |
39 | #define MAX98925_MAP6 0x17 | |
40 | #define MAX98925_MAP7 0x18 | |
41 | #define MAX98925_MAP8 0x19 | |
42 | #define MAX98925_DAI_CLK_MODE1 0x1A | |
43 | #define MAX98925_DAI_CLK_MODE2 0x1B | |
44 | #define MAX98925_DAI_CLK_DIV_M_MSBS 0x1C | |
45 | #define MAX98925_DAI_CLK_DIV_M_LSBS 0x1D | |
46 | #define MAX98925_DAI_CLK_DIV_N_MSBS 0x1E | |
47 | #define MAX98925_DAI_CLK_DIV_N_LSBS 0x1F | |
48 | #define MAX98925_FORMAT 0x20 | |
49 | #define MAX98925_TDM_SLOT_SELECT 0x21 | |
50 | #define MAX98925_DOUT_CFG_VMON 0x22 | |
51 | #define MAX98925_DOUT_CFG_IMON 0x23 | |
52 | #define MAX98925_DOUT_CFG_VBAT 0x24 | |
53 | #define MAX98925_DOUT_CFG_VBST 0x25 | |
54 | #define MAX98925_DOUT_CFG_FLAG 0x26 | |
55 | #define MAX98925_DOUT_HIZ_CFG1 0x27 | |
56 | #define MAX98925_DOUT_HIZ_CFG2 0x28 | |
57 | #define MAX98925_DOUT_HIZ_CFG3 0x29 | |
58 | #define MAX98925_DOUT_HIZ_CFG4 0x2A | |
59 | #define MAX98925_DOUT_DRV_STRENGTH 0x2B | |
60 | #define MAX98925_FILTERS 0x2C | |
61 | #define MAX98925_GAIN 0x2D | |
62 | #define MAX98925_GAIN_RAMPING 0x2E | |
63 | #define MAX98925_SPK_AMP 0x2F | |
64 | #define MAX98925_THRESHOLD 0x30 | |
65 | #define MAX98925_ALC_ATTACK 0x31 | |
66 | #define MAX98925_ALC_ATTEN_RLS 0x32 | |
67 | #define MAX98925_ALC_HOLD_RLS 0x33 | |
68 | #define MAX98925_ALC_CONFIGURATION 0x34 | |
69 | #define MAX98925_BOOST_CONVERTER 0x35 | |
70 | #define MAX98925_BLOCK_ENABLE 0x36 | |
71 | #define MAX98925_CONFIGURATION 0x37 | |
72 | #define MAX98925_GLOBAL_ENABLE 0x38 | |
73 | #define MAX98925_BOOST_LIMITER 0x3A | |
74 | #define MAX98925_REV_VERSION 0xFF | |
75 | ||
76 | #define MAX98925_REG_CNT (MAX98925_R03A_BOOST_LIMITER+1) | |
77 | ||
78 | /* MAX98925 Register Bit Fields */ | |
79 | ||
80 | /* MAX98925_R002_LIVE_STATUS0 */ | |
81 | #define M98925_THERMWARN_STATUS_MASK (1<<3) | |
82 | #define M98925_THERMWARN_STATUS_SHIFT 3 | |
83 | #define M98925_THERMWARN_STATUS_WIDTH 1 | |
84 | #define M98925_THERMSHDN_STATUS_MASK (1<<1) | |
85 | #define M98925_THERMSHDN_STATUS_SHIFT 1 | |
86 | #define M98925_THERMSHDN_STATUS_WIDTH 1 | |
87 | ||
88 | /* MAX98925_R003_LIVE_STATUS1 */ | |
89 | #define M98925_SPKCURNT_STATUS_MASK (1<<5) | |
90 | #define M98925_SPKCURNT_STATUS_SHIFT 5 | |
91 | #define M98925_SPKCURNT_STATUS_WIDTH 1 | |
92 | #define M98925_WATCHFAIL_STATUS_MASK (1<<4) | |
93 | #define M98925_WATCHFAIL_STATUS_SHIFT 4 | |
94 | #define M98925_WATCHFAIL_STATUS_WIDTH 1 | |
95 | #define M98925_ALCINFH_STATUS_MASK (1<<3) | |
96 | #define M98925_ALCINFH_STATUS_SHIFT 3 | |
97 | #define M98925_ALCINFH_STATUS_WIDTH 1 | |
98 | #define M98925_ALCACT_STATUS_MASK (1<<2) | |
99 | #define M98925_ALCACT_STATUS_SHIFT 2 | |
100 | #define M98925_ALCACT_STATUS_WIDTH 1 | |
101 | #define M98925_ALCMUT_STATUS_MASK (1<<1) | |
102 | #define M98925_ALCMUT_STATUS_SHIFT 1 | |
103 | #define M98925_ALCMUT_STATUS_WIDTH 1 | |
104 | #define M98925_ACLP_STATUS_MASK (1<<0) | |
105 | #define M98925_ACLP_STATUS_SHIFT 0 | |
106 | #define M98925_ACLP_STATUS_WIDTH 1 | |
107 | ||
108 | /* MAX98925_R004_LIVE_STATUS2 */ | |
109 | #define M98925_SLOTOVRN_STATUS_MASK (1<<6) | |
110 | #define M98925_SLOTOVRN_STATUS_SHIFT 6 | |
111 | #define M98925_SLOTOVRN_STATUS_WIDTH 1 | |
112 | #define M98925_INVALSLOT_STATUS_MASK (1<<5) | |
113 | #define M98925_INVALSLOT_STATUS_SHIFT 5 | |
114 | #define M98925_INVALSLOT_STATUS_WIDTH 1 | |
115 | #define M98925_SLOTCNFLT_STATUS_MASK (1<<4) | |
116 | #define M98925_SLOTCNFLT_STATUS_SHIFT 4 | |
117 | #define M98925_SLOTCNFLT_STATUS_WIDTH 1 | |
118 | #define M98925_VBSTOVFL_STATUS_MASK (1<<3) | |
119 | #define M98925_VBSTOVFL_STATUS_SHIFT 3 | |
120 | #define M98925_VBSTOVFL_STATUS_WIDTH 1 | |
121 | #define M98925_VBATOVFL_STATUS_MASK (1<<2) | |
122 | #define M98925_VBATOVFL_STATUS_SHIFT 2 | |
123 | #define M98925_VBATOVFL_STATUS_WIDTH 1 | |
124 | #define M98925_IMONOVFL_STATUS_MASK (1<<1) | |
125 | #define M98925_IMONOVFL_STATUS_SHIFT 1 | |
126 | #define M98925_IMONOVFL_STATUS_WIDTH 1 | |
127 | #define M98925_VMONOVFL_STATUS_MASK (1<<0) | |
128 | #define M98925_VMONOVFL_STATUS_SHIFT 0 | |
129 | #define M98925_VMONOVFL_STATUS_WIDTH 1 | |
130 | ||
131 | /* MAX98925_R005_STATE0 */ | |
132 | #define M98925_THERMWARN_END_STATE_MASK (1<<3) | |
133 | #define M98925_THERMWARN_END_STATE_SHIFT 3 | |
134 | #define M98925_THERMWARN_END_STATE_WIDTH 1 | |
135 | #define M98925_THERMWARN_BGN_STATE_MASK (1<<2) | |
136 | #define M98925_THERMWARN_BGN_STATE_SHIFT 1 | |
137 | #define M98925_THERMWARN_BGN_STATE_WIDTH 1 | |
138 | #define M98925_THERMSHDN_END_STATE_MASK (1<<1) | |
139 | #define M98925_THERMSHDN_END_STATE_SHIFT 1 | |
140 | #define M98925_THERMSHDN_END_STATE_WIDTH 1 | |
141 | #define M98925_THERMSHDN_BGN_STATE_MASK (1<<0) | |
142 | #define M98925_THERMSHDN_BGN_STATE_SHIFT 0 | |
143 | #define M98925_THERMSHDN_BGN_STATE_WIDTH 1 | |
144 | ||
145 | /* MAX98925_R006_STATE1 */ | |
146 | #define M98925_SPRCURNT_STATE_MASK (1<<5) | |
147 | #define M98925_SPRCURNT_STATE_SHIFT 5 | |
148 | #define M98925_SPRCURNT_STATE_WIDTH 1 | |
149 | #define M98925_WATCHFAIL_STATE_MASK (1<<4) | |
150 | #define M98925_WATCHFAIL_STATE_SHIFT 4 | |
151 | #define M98925_WATCHFAIL_STATE_WIDTH 1 | |
152 | #define M98925_ALCINFH_STATE_MASK (1<<3) | |
153 | #define M98925_ALCINFH_STATE_SHIFT 3 | |
154 | #define M98925_ALCINFH_STATE_WIDTH 1 | |
155 | #define M98925_ALCACT_STATE_MASK (1<<2) | |
156 | #define M98925_ALCACT_STATE_SHIFT 2 | |
157 | #define M98925_ALCACT_STATE_WIDTH 1 | |
158 | #define M98925_ALCMUT_STATE_MASK (1<<1) | |
159 | #define M98925_ALCMUT_STATE_SHIFT 1 | |
160 | #define M98925_ALCMUT_STATE_WIDTH 1 | |
161 | #define M98925_ALCP_STATE_MASK (1<<0) | |
162 | #define M98925_ALCP_STATE_SHIFT 0 | |
163 | #define M98925_ALCP_STATE_WIDTH 1 | |
164 | ||
165 | /* MAX98925_R007_STATE2 */ | |
166 | #define M98925_SLOTOVRN_STATE_MASK (1<<6) | |
167 | #define M98925_SLOTOVRN_STATE_SHIFT 6 | |
168 | #define M98925_SLOTOVRN_STATE_WIDTH 1 | |
169 | #define M98925_INVALSLOT_STATE_MASK (1<<5) | |
170 | #define M98925_INVALSLOT_STATE_SHIFT 5 | |
171 | #define M98925_INVALSLOT_STATE_WIDTH 1 | |
172 | #define M98925_SLOTCNFLT_STATE_MASK (1<<4) | |
173 | #define M98925_SLOTCNFLT_STATE_SHIFT 4 | |
174 | #define M98925_SLOTCNFLT_STATE_WIDTH 1 | |
175 | #define M98925_VBSTOVFL_STATE_MASK (1<<3) | |
176 | #define M98925_VBSTOVFL_STATE_SHIFT 3 | |
177 | #define M98925_VBSTOVFL_STATE_WIDTH 1 | |
178 | #define M98925_VBATOVFL_STATE_MASK (1<<2) | |
179 | #define M98925_VBATOVFL_STATE_SHIFT 2 | |
180 | #define M98925_VBATOVFL_STATE_WIDTH 1 | |
181 | #define M98925_IMONOVFL_STATE_MASK (1<<1) | |
182 | #define M98925_IMONOVFL_STATE_SHIFT 1 | |
183 | #define M98925_IMONOVFL_STATE_WIDTH 1 | |
184 | #define M98925_VMONOVFL_STATE_MASK (1<<0) | |
185 | #define M98925_VMONOVFL_STATE_SHIFT 0 | |
186 | #define M98925_VMONOVFL_STATE_WIDTH 1 | |
187 | ||
188 | /* MAX98925_R008_FLAG0 */ | |
189 | #define M98925_THERMWARN_END_FLAG_MASK (1<<3) | |
190 | #define M98925_THERMWARN_END_FLAG_SHIFT 3 | |
191 | #define M98925_THERMWARN_END_FLAG_WIDTH 1 | |
192 | #define M98925_THERMWARN_BGN_FLAG_MASK (1<<2) | |
193 | #define M98925_THERMWARN_BGN_FLAG_SHIFT 2 | |
194 | #define M98925_THERMWARN_BGN_FLAG_WIDTH 1 | |
195 | #define M98925_THERMSHDN_END_FLAG_MASK (1<<1) | |
196 | #define M98925_THERMSHDN_END_FLAG_SHIFT 1 | |
197 | #define M98925_THERMSHDN_END_FLAG_WIDTH 1 | |
198 | #define M98925_THERMSHDN_BGN_FLAG_MASK (1<<0) | |
199 | #define M98925_THERMSHDN_BGN_FLAG_SHIFT 0 | |
200 | #define M98925_THERMSHDN_BGN_FLAG_WIDTH 1 | |
201 | ||
202 | /* MAX98925_R009_FLAG1 */ | |
203 | #define M98925_SPKCURNT_FLAG_MASK (1<<5) | |
204 | #define M98925_SPKCURNT_FLAG_SHIFT 5 | |
205 | #define M98925_SPKCURNT_FLAG_WIDTH 1 | |
206 | #define M98925_WATCHFAIL_FLAG_MASK (1<<4) | |
207 | #define M98925_WATCHFAIL_FLAG_SHIFT 4 | |
208 | #define M98925_WATCHFAIL_FLAG_WIDTH 1 | |
209 | #define M98925_ALCINFH_FLAG_MASK (1<<3) | |
210 | #define M98925_ALCINFH_FLAG_SHIFT 3 | |
211 | #define M98925_ALCINFH_FLAG_WIDTH 1 | |
212 | #define M98925_ALCACT_FLAG_MASK (1<<2) | |
213 | #define M98925_ALCACT_FLAG_SHIFT 2 | |
214 | #define M98925_ALCACT_FLAG_WIDTH 1 | |
215 | #define M98925_ALCMUT_FLAG_MASK (1<<1) | |
216 | #define M98925_ALCMUT_FLAG_SHIFT 1 | |
217 | #define M98925_ALCMUT_FLAG_WIDTH 1 | |
218 | #define M98925_ALCP_FLAG_MASK (1<<0) | |
219 | #define M98925_ALCP_FLAG_SHIFT 0 | |
220 | #define M98925_ALCP_FLAG_WIDTH 1 | |
221 | ||
222 | /* MAX98925_R00A_FLAG2 */ | |
223 | #define M98925_SLOTOVRN_FLAG_MASK (1<<6) | |
224 | #define M98925_SLOTOVRN_FLAG_SHIFT 6 | |
225 | #define M98925_SLOTOVRN_FLAG_WIDTH 1 | |
226 | #define M98925_INVALSLOT_FLAG_MASK (1<<5) | |
227 | #define M98925_INVALSLOT_FLAG_SHIFT 5 | |
228 | #define M98925_INVALSLOT_FLAG_WIDTH 1 | |
229 | #define M98925_SLOTCNFLT_FLAG_MASK (1<<4) | |
230 | #define M98925_SLOTCNFLT_FLAG_SHIFT 4 | |
231 | #define M98925_SLOTCNFLT_FLAG_WIDTH 1 | |
232 | #define M98925_VBSTOVFL_FLAG_MASK (1<<3) | |
233 | #define M98925_VBSTOVFL_FLAG_SHIFT 3 | |
234 | #define M98925_VBSTOVFL_FLAG_WIDTH 1 | |
235 | #define M98925_VBATOVFL_FLAG_MASK (1<<2) | |
236 | #define M98925_VBATOVFL_FLAG_SHIFT 2 | |
237 | #define M98925_VBATOVFL_FLAG_WIDTH 1 | |
238 | #define M98925_IMONOVFL_FLAG_MASK (1<<1) | |
239 | #define M98925_IMONOVFL_FLAG_SHIFT 1 | |
240 | #define M98925_IMONOVFL_FLAG_WIDTH 1 | |
241 | #define M98925_VMONOVFL_FLAG_MASK (1<<0) | |
242 | #define M98925_VMONOVFL_FLAG_SHIFT 0 | |
243 | #define M98925_VMONOVFL_FLAG_WIDTH 1 | |
244 | ||
245 | /* MAX98925_R00B_IRQ_ENABLE0 */ | |
246 | #define M98925_THERMWARN_END_EN_MASK (1<<3) | |
247 | #define M98925_THERMWARN_END_EN_SHIFT 3 | |
248 | #define M98925_THERMWARN_END_EN_WIDTH 1 | |
249 | #define M98925_THERMWARN_BGN_EN_MASK (1<<2) | |
250 | #define M98925_THERMWARN_BGN_EN_SHIFT 2 | |
251 | #define M98925_THERMWARN_BGN_EN_WIDTH 1 | |
252 | #define M98925_THERMSHDN_END_EN_MASK (1<<1) | |
253 | #define M98925_THERMSHDN_END_EN_SHIFT 1 | |
254 | #define M98925_THERMSHDN_END_EN_WIDTH 1 | |
255 | #define M98925_THERMSHDN_BGN_EN_MASK (1<<0) | |
256 | #define M98925_THERMSHDN_BGN_EN_SHIFT 0 | |
257 | #define M98925_THERMSHDN_BGN_EN_WIDTH 1 | |
258 | ||
259 | /* MAX98925_R00C_IRQ_ENABLE1 */ | |
260 | #define M98925_SPKCURNT_EN_MASK (1<<5) | |
261 | #define M98925_SPKCURNT_EN_SHIFT 5 | |
262 | #define M98925_SPKCURNT_EN_WIDTH 1 | |
263 | #define M98925_WATCHFAIL_EN_MASK (1<<4) | |
264 | #define M98925_WATCHFAIL_EN_SHIFT 4 | |
265 | #define M98925_WATCHFAIL_EN_WIDTH 1 | |
266 | #define M98925_ALCINFH_EN_MASK (1<<3) | |
267 | #define M98925_ALCINFH_EN_SHIFT 3 | |
268 | #define M98925_ALCINFH_EN_WIDTH 1 | |
269 | #define M98925_ALCACT_EN_MASK (1<<2) | |
270 | #define M98925_ALCACT_EN_SHIFT 2 | |
271 | #define M98925_ALCACT_EN_WIDTH 1 | |
272 | #define M98925_ALCMUT_EN_MASK (1<<1) | |
273 | #define M98925_ALCMUT_EN_SHIFT 1 | |
274 | #define M98925_ALCMUT_EN_WIDTH 1 | |
275 | #define M98925_ALCP_EN_MASK (1<<0) | |
276 | #define M98925_ALCP_EN_SHIFT 0 | |
277 | #define M98925_ALCP_EN_WIDTH 1 | |
278 | ||
279 | /* MAX98925_R00D_IRQ_ENABLE2 */ | |
280 | #define M98925_SLOTOVRN_EN_MASK (1<<6) | |
281 | #define M98925_SLOTOVRN_EN_SHIFT 6 | |
282 | #define M98925_SLOTOVRN_EN_WIDTH 1 | |
283 | #define M98925_INVALSLOT_EN_MASK (1<<5) | |
284 | #define M98925_INVALSLOT_EN_SHIFT 5 | |
285 | #define M98925_INVALSLOT_EN_WIDTH 1 | |
286 | #define M98925_SLOTCNFLT_EN_MASK (1<<4) | |
287 | #define M98925_SLOTCNFLT_EN_SHIFT 4 | |
288 | #define M98925_SLOTCNFLT_EN_WIDTH 1 | |
289 | #define M98925_VBSTOVFL_EN_MASK (1<<3) | |
290 | #define M98925_VBSTOVFL_EN_SHIFT 3 | |
291 | #define M98925_VBSTOVFL_EN_WIDTH 1 | |
292 | #define M98925_VBATOVFL_EN_MASK (1<<2) | |
293 | #define M98925_VBATOVFL_EN_SHIFT 2 | |
294 | #define M98925_VBATOVFL_EN_WIDTH 1 | |
295 | #define M98925_IMONOVFL_EN_MASK (1<<1) | |
296 | #define M98925_IMONOVFL_EN_SHIFT 1 | |
297 | #define M98925_IMONOVFL_EN_WIDTH 1 | |
298 | #define M98925_VMONOVFL_EN_MASK (1<<0) | |
299 | #define M98925_VMONOVFL_EN_SHIFT 0 | |
300 | #define M98925_VMONOVFL_EN_WIDTH 1 | |
301 | ||
302 | /* MAX98925_R00E_IRQ_CLEAR0 */ | |
303 | #define M98925_THERMWARN_END_CLR_MASK (1<<3) | |
304 | #define M98925_THERMWARN_END_CLR_SHIFT 3 | |
305 | #define M98925_THERMWARN_END_CLR_WIDTH 1 | |
306 | #define M98925_THERMWARN_BGN_CLR_MASK (1<<2) | |
307 | #define M98925_THERMWARN_BGN_CLR_SHIFT 2 | |
308 | #define M98925_THERMWARN_BGN_CLR_WIDTH 1 | |
309 | #define M98925_THERMSHDN_END_CLR_MASK (1<<1) | |
310 | #define M98925_THERMSHDN_END_CLR_SHIFT 1 | |
311 | #define M98925_THERMSHDN_END_CLR_WIDTH 1 | |
312 | #define M98925_THERMSHDN_BGN_CLR_MASK (1<<0) | |
313 | #define M98925_THERMSHDN_BGN_CLR_SHIFT 0 | |
314 | #define M98925_THERMSHDN_BGN_CLR_WIDTH 1 | |
315 | ||
316 | /* MAX98925_R00F_IRQ_CLEAR1 */ | |
317 | #define M98925_SPKCURNT_CLR_MASK (1<<5) | |
318 | #define M98925_SPKCURNT_CLR_SHIFT 5 | |
319 | #define M98925_SPKCURNT_CLR_WIDTH 1 | |
320 | #define M98925_WATCHFAIL_CLR_MASK (1<<4) | |
321 | #define M98925_WATCHFAIL_CLR_SHIFT 4 | |
322 | #define M98925_WATCHFAIL_CLR_WIDTH 1 | |
323 | #define M98925_ALCINFH_CLR_MASK (1<<3) | |
324 | #define M98925_ALCINFH_CLR_SHIFT 3 | |
325 | #define M98925_ALCINFH_CLR_WIDTH 1 | |
326 | #define M98925_ALCACT_CLR_MASK (1<<2) | |
327 | #define M98925_ALCACT_CLR_SHIFT 2 | |
328 | #define M98925_ALCACT_CLR_WIDTH 1 | |
329 | #define M98925_ALCMUT_CLR_MASK (1<<1) | |
330 | #define M98925_ALCMUT_CLR_SHIFT 1 | |
331 | #define M98925_ALCMUT_CLR_WIDTH 1 | |
332 | #define M98925_ALCP_CLR_MASK (1<<0) | |
333 | #define M98925_ALCP_CLR_SHIFT 0 | |
334 | #define M98925_ALCP_CLR_WIDTH 1 | |
335 | ||
336 | /* MAX98925_R010_IRQ_CLEAR2 */ | |
337 | #define M98925_SLOTOVRN_CLR_MASK (1<<6) | |
338 | #define M98925_SLOTOVRN_CLR_SHIFT 6 | |
339 | #define M98925_SLOTOVRN_CLR_WIDTH 1 | |
340 | #define M98925_INVALSLOT_CLR_MASK (1<<5) | |
341 | #define M98925_INVALSLOT_CLR_SHIFT 5 | |
342 | #define M98925_INVALSLOT_CLR_WIDTH 1 | |
343 | #define M98925_SLOTCNFLT_CLR_MASK (1<<4) | |
344 | #define M98925_SLOTCNFLT_CLR_SHIFT 4 | |
345 | #define M98925_SLOTCNFLT_CLR_WIDTH 1 | |
346 | #define M98925_VBSTOVFL_CLR_MASK (1<<3) | |
347 | #define M98925_VBSTOVFL_CLR_SHIFT 3 | |
348 | #define M98925_VBSTOVFL_CLR_WIDTH 1 | |
349 | #define M98925_VBATOVFL_CLR_MASK (1<<2) | |
350 | #define M98925_VBATOVFL_CLR_SHIFT 2 | |
351 | #define M98925_VBATOVFL_CLR_WIDTH 1 | |
352 | #define M98925_IMONOVFL_CLR_MASK (1<<1) | |
353 | #define M98925_IMONOVFL_CLR_SHIFT 1 | |
354 | #define M98925_IMONOVFL_CLR_WIDTH 1 | |
355 | #define M98925_VMONOVFL_CLR_MASK (1<<0) | |
356 | #define M98925_VMONOVFL_CLR_SHIFT 0 | |
357 | #define M98925_VMONOVFL_CLR_WIDTH 1 | |
358 | ||
359 | /* MAX98925_R011_MAP0 */ | |
360 | #define M98925_ER_THERMWARN_EN_MASK (1<<7) | |
361 | #define M98925_ER_THERMWARN_EN_SHIFT 7 | |
362 | #define M98925_ER_THERMWARN_EN_WIDTH 1 | |
363 | #define M98925_ER_THERMWARN_MAP_MASK (0x07<<4) | |
364 | #define M98925_ER_THERMWARN_MAP_SHIFT 4 | |
365 | #define M98925_ER_THERMWARN_MAP_WIDTH 3 | |
366 | ||
367 | /* MAX98925_R012_MAP1 */ | |
368 | #define M98925_ER_ALCMUT_EN_MASK (1<<7) | |
369 | #define M98925_ER_ALCMUT_EN_SHIFT 7 | |
370 | #define M98925_ER_ALCMUT_EN_WIDTH 1 | |
371 | #define M98925_ER_ALCMUT_MAP_MASK (0x07<<4) | |
372 | #define M98925_ER_ALCMUT_MAP_SHIFT 4 | |
373 | #define M98925_ER_ALCMUT_MAP_WIDTH 3 | |
374 | #define M98925_ER_ALCP_EN_MASK (1<<3) | |
375 | #define M98925_ER_ALCP_EN_SHIFT 3 | |
376 | #define M98925_ER_ALCP_EN_WIDTH 1 | |
377 | #define M98925_ER_ALCP_MAP_MASK (0x07<<0) | |
378 | #define M98925_ER_ALCP_MAP_SHIFT 0 | |
379 | #define M98925_ER_ALCP_MAP_WIDTH 3 | |
380 | ||
381 | /* MAX98925_R013_MAP2 */ | |
382 | #define M98925_ER_ALCINFH_EN_MASK (1<<7) | |
383 | #define M98925_ER_ALCINFH_EN_SHIFT 7 | |
384 | #define M98925_ER_ALCINFH_EN_WIDTH 1 | |
385 | #define M98925_ER_ALCINFH_MAP_MASK (0x07<<4) | |
386 | #define M98925_ER_ALCINFH_MAP_SHIFT 4 | |
387 | #define M98925_ER_ALCINFH_MAP_WIDTH 3 | |
388 | #define M98925_ER_ALCACT_EN_MASK (1<<3) | |
389 | #define M98925_ER_ALCACT_EN_SHIFT 3 | |
390 | #define M98925_ER_ALCACT_EN_WIDTH 1 | |
391 | #define M98925_ER_ALCACT_MAP_MASK (0x07<<0) | |
392 | #define M98925_ER_ALCACT_MAP_SHIFT 0 | |
393 | #define M98925_ER_ALCACT_MAP_WIDTH 3 | |
394 | ||
395 | /* MAX98925_R014_MAP3 */ | |
396 | #define M98925_ER_SPKCURNT_EN_MASK (1<<7) | |
397 | #define M98925_ER_SPKCURNT_EN_SHIFT 7 | |
398 | #define M98925_ER_SPKCURNT_EN_WIDTH 1 | |
399 | #define M98925_ER_SPKCURNT_MAP_MASK (0x07<<4) | |
400 | #define M98925_ER_SPKCURNT_MAP_SHIFT 4 | |
401 | #define M98925_ER_SPKCURNT_MAP_WIDTH 3 | |
402 | ||
403 | /* MAX98925_R015_MAP4 */ | |
404 | /* RESERVED */ | |
405 | ||
406 | /* MAX98925_R016_MAP5 */ | |
407 | #define M98925_ER_IMONOVFL_EN_MASK (1<<7) | |
408 | #define M98925_ER_IMONOVFL_EN_SHIFT 7 | |
409 | #define M98925_ER_IMONOVFL_EN_WIDTH 1 | |
410 | #define M98925_ER_IMONOVFL_MAP_MASK (0x07<<4) | |
411 | #define M98925_ER_IMONOVFL_MAP_SHIFT 4 | |
412 | #define M98925_ER_IMONOVFL_MAP_WIDTH 3 | |
413 | #define M98925_ER_VMONOVFL_EN_MASK (1<<3) | |
414 | #define M98925_ER_VMONOVFL_EN_SHIFT 3 | |
415 | #define M98925_ER_VMONOVFL_EN_WIDTH 1 | |
416 | #define M98925_ER_VMONOVFL_MAP_MASK (0x07<<0) | |
417 | #define M98925_ER_VMONOVFL_MAP_SHIFT 0 | |
418 | #define M98925_ER_VMONOVFL_MAP_WIDTH 3 | |
419 | ||
420 | /* MAX98925_R017_MAP6 */ | |
421 | #define M98925_ER_VBSTOVFL_EN_MASK (1<<7) | |
422 | #define M98925_ER_VBSTOVFL_EN_SHIFT 7 | |
423 | #define M98925_ER_VBSTOVFL_EN_WIDTH 1 | |
424 | #define M98925_ER_VBSTOVFL_MAP_MASK (0x07<<4) | |
425 | #define M98925_ER_VBSTOVFL_MAP_SHIFT 4 | |
426 | #define M98925_ER_VBSTOVFL_MAP_WIDTH 3 | |
427 | #define M98925_ER_VBATOVFL_EN_MASK (1<<3) | |
428 | #define M98925_ER_VBATOVFL_EN_SHIFT 3 | |
429 | #define M98925_ER_VBATOVFL_EN_WIDTH 1 | |
430 | #define M98925_ER_VBATOVFL_MAP_MASK (0x07<<0) | |
431 | #define M98925_ER_VBATOVFL_MAP_SHIFT 0 | |
432 | #define M98925_ER_VBATOVFL_MAP_WIDTH 3 | |
433 | ||
434 | /* MAX98925_R018_MAP7 */ | |
435 | #define M98925_ER_INVALSLOT_EN_MASK (1<<7) | |
436 | #define M98925_ER_INVALSLOT_EN_SHIFT 7 | |
437 | #define M98925_ER_INVALSLOT_EN_WIDTH 1 | |
438 | #define M98925_ER_INVALSLOT_MAP_MASK (0x07<<4) | |
439 | #define M98925_ER_INVALSLOT_MAP_SHIFT 4 | |
440 | #define M98925_ER_INVALSLOT_MAP_WIDTH 3 | |
441 | #define M98925_ER_SLOTCNFLT_EN_MASK (1<<3) | |
442 | #define M98925_ER_SLOTCNFLT_EN_SHIFT 3 | |
443 | #define M98925_ER_SLOTCNFLT_EN_WIDTH 1 | |
444 | #define M98925_ER_SLOTCNFLT_MAP_MASK (0x07<<0) | |
445 | #define M98925_ER_SLOTCNFLT_MAP_SHIFT 0 | |
446 | #define M98925_ER_SLOTCNFLT_MAP_WIDTH 3 | |
447 | ||
448 | /* MAX98925_R019_MAP8 */ | |
449 | #define M98925_ER_SLOTOVRN_EN_MASK (1<<3) | |
450 | #define M98925_ER_SLOTOVRN_EN_SHIFT 3 | |
451 | #define M98925_ER_SLOTOVRN_EN_WIDTH 1 | |
452 | #define M98925_ER_SLOTOVRN_MAP_MASK (0x07<<0) | |
453 | #define M98925_ER_SLOTOVRN_MAP_SHIFT 0 | |
454 | #define M98925_ER_SLOTOVRN_MAP_WIDTH 3 | |
455 | ||
456 | /* MAX98925_R01A_DAI_CLK_MODE1 */ | |
457 | #define M98925_DAI_CLK_SOURCE_MASK (1<<6) | |
458 | #define M98925_DAI_CLK_SOURCE_SHIFT 6 | |
459 | #define M98925_DAI_CLK_SOURCE_WIDTH 1 | |
460 | #define M98925_MDLL_MULT_MASK (0x0F<<0) | |
461 | #define M98925_MDLL_MULT_SHIFT 0 | |
462 | #define M98925_MDLL_MULT_WIDTH 4 | |
463 | ||
464 | #define M98925_MDLL_MULT_MCLKx8 6 | |
465 | #define M98925_MDLL_MULT_MCLKx16 8 | |
466 | ||
467 | /* MAX98925_R01B_DAI_CLK_MODE2 */ | |
468 | #define M98925_DAI_SR_MASK (0x0F<<4) | |
469 | #define M98925_DAI_SR_SHIFT 4 | |
470 | #define M98925_DAI_SR_WIDTH 4 | |
471 | #define M98925_DAI_MAS_MASK (1<<3) | |
472 | #define M98925_DAI_MAS_SHIFT 3 | |
473 | #define M98925_DAI_MAS_WIDTH 1 | |
474 | #define M98925_DAI_BSEL_MASK (0x07<<0) | |
475 | #define M98925_DAI_BSEL_SHIFT 0 | |
476 | #define M98925_DAI_BSEL_WIDTH 3 | |
477 | ||
478 | #define M98925_DAI_BSEL_32 (0 << M98925_DAI_BSEL_SHIFT) | |
479 | #define M98925_DAI_BSEL_48 (1 << M98925_DAI_BSEL_SHIFT) | |
480 | #define M98925_DAI_BSEL_64 (2 << M98925_DAI_BSEL_SHIFT) | |
481 | #define M98925_DAI_BSEL_256 (6 << M98925_DAI_BSEL_SHIFT) | |
482 | ||
483 | /* MAX98925_R01C_DAI_CLK_DIV_M_MSBS */ | |
484 | #define M98925_DAI_M_MSBS_MASK (0xFF<<0) | |
485 | #define M98925_DAI_M_MSBS_SHIFT 0 | |
486 | #define M98925_DAI_M_MSBS_WIDTH 8 | |
487 | ||
488 | /* MAX98925_R01D_DAI_CLK_DIV_M_LSBS */ | |
489 | #define M98925_DAI_M_LSBS_MASK (0xFF<<0) | |
490 | #define M98925_DAI_M_LSBS_SHIFT 0 | |
491 | #define M98925_DAI_M_LSBS_WIDTH 8 | |
492 | ||
493 | /* MAX98925_R01E_DAI_CLK_DIV_N_MSBS */ | |
494 | #define M98925_DAI_N_MSBS_MASK (0x7F<<0) | |
495 | #define M98925_DAI_N_MSBS_SHIFT 0 | |
496 | #define M98925_DAI_N_MSBS_WIDTH 7 | |
497 | ||
498 | /* MAX98925_R01F_DAI_CLK_DIV_N_LSBS */ | |
499 | #define M98925_DAI_N_LSBS_MASK (0xFF<<0) | |
500 | #define M98925_DAI_N_LSBS_SHIFT 0 | |
501 | #define M98925_DAI_N_LSBS_WIDTH 8 | |
502 | ||
503 | /* MAX98925_R020_FORMAT */ | |
504 | #define M98925_DAI_CHANSZ_MASK (0x03<<6) | |
505 | #define M98925_DAI_CHANSZ_SHIFT 6 | |
506 | #define M98925_DAI_CHANSZ_WIDTH 2 | |
507 | #define M98925_DAI_EXTBCLK_HIZ_MASK (1<<4) | |
508 | #define M98925_DAI_EXTBCLK_HIZ_SHIFT 4 | |
509 | #define M98925_DAI_EXTBCLK_HIZ_WIDTH 1 | |
510 | #define M98925_DAI_WCI_MASK (1<<3) | |
511 | #define M98925_DAI_WCI_SHIFT 3 | |
512 | #define M98925_DAI_WCI_WIDTH 1 | |
513 | #define M98925_DAI_BCI_MASK (1<<2) | |
514 | #define M98925_DAI_BCI_SHIFT 2 | |
515 | #define M98925_DAI_BCI_WIDTH 1 | |
516 | #define M98925_DAI_DLY_MASK (1<<1) | |
517 | #define M98925_DAI_DLY_SHIFT 1 | |
518 | #define M98925_DAI_DLY_WIDTH 1 | |
519 | #define M98925_DAI_TDM_MASK (1<<0) | |
520 | #define M98925_DAI_TDM_SHIFT 0 | |
521 | #define M98925_DAI_TDM_WIDTH 1 | |
522 | ||
523 | #define M98925_DAI_CHANSZ_16 (1 << M98925_DAI_CHANSZ_SHIFT) | |
524 | #define M98925_DAI_CHANSZ_24 (2 << M98925_DAI_CHANSZ_SHIFT) | |
525 | #define M98925_DAI_CHANSZ_32 (3 << M98925_DAI_CHANSZ_SHIFT) | |
526 | ||
527 | /* MAX98925_R021_TDM_SLOT_SELECT */ | |
528 | #define M98925_DAI_DO_EN_MASK (1<<7) | |
529 | #define M98925_DAI_DO_EN_SHIFT 7 | |
530 | #define M98925_DAI_DO_EN_WIDTH 1 | |
531 | #define M98925_DAI_DIN_EN_MASK (1<<6) | |
532 | #define M98925_DAI_DIN_EN_SHIFT 6 | |
533 | #define M98925_DAI_DIN_EN_WIDTH 1 | |
534 | #define M98925_DAI_INR_SOURCE_MASK (0x07<<3) | |
535 | #define M98925_DAI_INR_SOURCE_SHIFT 3 | |
536 | #define M98925_DAI_INR_SOURCE_WIDTH 3 | |
537 | #define M98925_DAI_INL_SOURCE_MASK (0x07<<0) | |
538 | #define M98925_DAI_INL_SOURCE_SHIFT 0 | |
539 | #define M98925_DAI_INL_SOURCE_WIDTH 3 | |
540 | ||
541 | /* MAX98925_R022_DOUT_CFG_VMON */ | |
542 | #define M98925_DAI_VMON_EN_MASK (1<<5) | |
543 | #define M98925_DAI_VMON_EN_SHIFT 5 | |
544 | #define M98925_DAI_VMON_EN_WIDTH 1 | |
545 | #define M98925_DAI_VMON_SLOT_MASK (0x1F<<0) | |
546 | #define M98925_DAI_VMON_SLOT_SHIFT 0 | |
547 | #define M98925_DAI_VMON_SLOT_WIDTH 5 | |
548 | ||
549 | #define M98925_DAI_VMON_SLOT_00_01 (0 << M98925_DAI_VMON_SLOT_SHIFT) | |
550 | #define M98925_DAI_VMON_SLOT_01_02 (1 << M98925_DAI_VMON_SLOT_SHIFT) | |
551 | #define M98925_DAI_VMON_SLOT_02_03 (2 << M98925_DAI_VMON_SLOT_SHIFT) | |
552 | #define M98925_DAI_VMON_SLOT_03_04 (3 << M98925_DAI_VMON_SLOT_SHIFT) | |
553 | #define M98925_DAI_VMON_SLOT_04_05 (4 << M98925_DAI_VMON_SLOT_SHIFT) | |
554 | #define M98925_DAI_VMON_SLOT_05_06 (5 << M98925_DAI_VMON_SLOT_SHIFT) | |
555 | #define M98925_DAI_VMON_SLOT_06_07 (6 << M98925_DAI_VMON_SLOT_SHIFT) | |
556 | #define M98925_DAI_VMON_SLOT_07_08 (7 << M98925_DAI_VMON_SLOT_SHIFT) | |
557 | #define M98925_DAI_VMON_SLOT_08_09 (8 << M98925_DAI_VMON_SLOT_SHIFT) | |
558 | #define M98925_DAI_VMON_SLOT_09_0A (9 << M98925_DAI_VMON_SLOT_SHIFT) | |
559 | #define M98925_DAI_VMON_SLOT_0A_0B (10 << M98925_DAI_VMON_SLOT_SHIFT) | |
560 | #define M98925_DAI_VMON_SLOT_0B_0C (11 << M98925_DAI_VMON_SLOT_SHIFT) | |
561 | #define M98925_DAI_VMON_SLOT_0C_0D (12 << M98925_DAI_VMON_SLOT_SHIFT) | |
562 | #define M98925_DAI_VMON_SLOT_0D_0E (13 << M98925_DAI_VMON_SLOT_SHIFT) | |
563 | #define M98925_DAI_VMON_SLOT_0E_0F (14 << M98925_DAI_VMON_SLOT_SHIFT) | |
564 | #define M98925_DAI_VMON_SLOT_0F_10 (15 << M98925_DAI_VMON_SLOT_SHIFT) | |
565 | #define M98925_DAI_VMON_SLOT_10_11 (16 << M98925_DAI_VMON_SLOT_SHIFT) | |
566 | #define M98925_DAI_VMON_SLOT_11_12 (17 << M98925_DAI_VMON_SLOT_SHIFT) | |
567 | #define M98925_DAI_VMON_SLOT_12_13 (18 << M98925_DAI_VMON_SLOT_SHIFT) | |
568 | #define M98925_DAI_VMON_SLOT_13_14 (19 << M98925_DAI_VMON_SLOT_SHIFT) | |
569 | #define M98925_DAI_VMON_SLOT_14_15 (20 << M98925_DAI_VMON_SLOT_SHIFT) | |
570 | #define M98925_DAI_VMON_SLOT_15_16 (21 << M98925_DAI_VMON_SLOT_SHIFT) | |
571 | #define M98925_DAI_VMON_SLOT_16_17 (22 << M98925_DAI_VMON_SLOT_SHIFT) | |
572 | #define M98925_DAI_VMON_SLOT_17_18 (23 << M98925_DAI_VMON_SLOT_SHIFT) | |
573 | #define M98925_DAI_VMON_SLOT_18_19 (24 << M98925_DAI_VMON_SLOT_SHIFT) | |
574 | #define M98925_DAI_VMON_SLOT_19_1A (25 << M98925_DAI_VMON_SLOT_SHIFT) | |
575 | #define M98925_DAI_VMON_SLOT_1A_1B (26 << M98925_DAI_VMON_SLOT_SHIFT) | |
576 | #define M98925_DAI_VMON_SLOT_1B_1C (27 << M98925_DAI_VMON_SLOT_SHIFT) | |
577 | #define M98925_DAI_VMON_SLOT_1C_1D (28 << M98925_DAI_VMON_SLOT_SHIFT) | |
578 | #define M98925_DAI_VMON_SLOT_1D_1E (29 << M98925_DAI_VMON_SLOT_SHIFT) | |
579 | #define M98925_DAI_VMON_SLOT_1E_1F (30 << M98925_DAI_VMON_SLOT_SHIFT) | |
580 | ||
581 | /* MAX98925_R023_DOUT_CFG_IMON */ | |
582 | #define M98925_DAI_IMON_EN_MASK (1<<5) | |
583 | #define M98925_DAI_IMON_EN_SHIFT 5 | |
584 | #define M98925_DAI_IMON_EN_WIDTH 1 | |
585 | #define M98925_DAI_IMON_SLOT_MASK (0x1F<<0) | |
586 | #define M98925_DAI_IMON_SLOT_SHIFT 0 | |
587 | #define M98925_DAI_IMON_SLOT_WIDTH 5 | |
588 | ||
589 | #define M98925_DAI_IMON_SLOT_00_01 (0 << M98925_DAI_IMON_SLOT_SHIFT) | |
590 | #define M98925_DAI_IMON_SLOT_01_02 (1 << M98925_DAI_IMON_SLOT_SHIFT) | |
591 | #define M98925_DAI_IMON_SLOT_02_03 (2 << M98925_DAI_IMON_SLOT_SHIFT) | |
592 | #define M98925_DAI_IMON_SLOT_03_04 (3 << M98925_DAI_IMON_SLOT_SHIFT) | |
593 | #define M98925_DAI_IMON_SLOT_04_05 (4 << M98925_DAI_IMON_SLOT_SHIFT) | |
594 | #define M98925_DAI_IMON_SLOT_05_06 (5 << M98925_DAI_IMON_SLOT_SHIFT) | |
595 | #define M98925_DAI_IMON_SLOT_06_07 (6 << M98925_DAI_IMON_SLOT_SHIFT) | |
596 | #define M98925_DAI_IMON_SLOT_07_08 (7 << M98925_DAI_IMON_SLOT_SHIFT) | |
597 | #define M98925_DAI_IMON_SLOT_08_09 (8 << M98925_DAI_IMON_SLOT_SHIFT) | |
598 | #define M98925_DAI_IMON_SLOT_09_0A (9 << M98925_DAI_IMON_SLOT_SHIFT) | |
599 | #define M98925_DAI_IMON_SLOT_0A_0B (10 << M98925_DAI_IMON_SLOT_SHIFT) | |
600 | #define M98925_DAI_IMON_SLOT_0B_0C (11 << M98925_DAI_IMON_SLOT_SHIFT) | |
601 | #define M98925_DAI_IMON_SLOT_0C_0D (12 << M98925_DAI_IMON_SLOT_SHIFT) | |
602 | #define M98925_DAI_IMON_SLOT_0D_0E (13 << M98925_DAI_IMON_SLOT_SHIFT) | |
603 | #define M98925_DAI_IMON_SLOT_0E_0F (14 << M98925_DAI_IMON_SLOT_SHIFT) | |
604 | #define M98925_DAI_IMON_SLOT_0F_10 (15 << M98925_DAI_IMON_SLOT_SHIFT) | |
605 | #define M98925_DAI_IMON_SLOT_10_11 (16 << M98925_DAI_IMON_SLOT_SHIFT) | |
606 | #define M98925_DAI_IMON_SLOT_11_12 (17 << M98925_DAI_IMON_SLOT_SHIFT) | |
607 | #define M98925_DAI_IMON_SLOT_12_13 (18 << M98925_DAI_IMON_SLOT_SHIFT) | |
608 | #define M98925_DAI_IMON_SLOT_13_14 (19 << M98925_DAI_IMON_SLOT_SHIFT) | |
609 | #define M98925_DAI_IMON_SLOT_14_15 (20 << M98925_DAI_IMON_SLOT_SHIFT) | |
610 | #define M98925_DAI_IMON_SLOT_15_16 (21 << M98925_DAI_IMON_SLOT_SHIFT) | |
611 | #define M98925_DAI_IMON_SLOT_16_17 (22 << M98925_DAI_IMON_SLOT_SHIFT) | |
612 | #define M98925_DAI_IMON_SLOT_17_18 (23 << M98925_DAI_IMON_SLOT_SHIFT) | |
613 | #define M98925_DAI_IMON_SLOT_18_19 (24 << M98925_DAI_IMON_SLOT_SHIFT) | |
614 | #define M98925_DAI_IMON_SLOT_19_1A (25 << M98925_DAI_IMON_SLOT_SHIFT) | |
615 | #define M98925_DAI_IMON_SLOT_1A_1B (26 << M98925_DAI_IMON_SLOT_SHIFT) | |
616 | #define M98925_DAI_IMON_SLOT_1B_1C (27 << M98925_DAI_IMON_SLOT_SHIFT) | |
617 | #define M98925_DAI_IMON_SLOT_1C_1D (28 << M98925_DAI_IMON_SLOT_SHIFT) | |
618 | #define M98925_DAI_IMON_SLOT_1D_1E (29 << M98925_DAI_IMON_SLOT_SHIFT) | |
619 | #define M98925_DAI_IMON_SLOT_1E_1F (30 << M98925_DAI_IMON_SLOT_SHIFT) | |
620 | ||
621 | /* MAX98925_R024_DOUT_CFG_VBAT */ | |
622 | #define M98925_DAI_VBAT_EN_MASK (1<<5) | |
623 | #define M98925_DAI_VBAT_EN_SHIFT 5 | |
624 | #define M98925_DAI_VBAT_EN_WIDTH 1 | |
625 | #define M98925_DAI_VBAT_SLOT_MASK (0x1F<<0) | |
626 | #define M98925_DAI_VBAT_SLOT_SHIFT 0 | |
627 | #define M98925_DAI_VBAT_SLOT_WIDTH 5 | |
628 | ||
629 | /* MAX98925_R025_DOUT_CFG_VBST */ | |
630 | #define M98925_DAI_VBST_EN_MASK (1<<5) | |
631 | #define M98925_DAI_VBST_EN_SHIFT 5 | |
632 | #define M98925_DAI_VBST_EN_WIDTH 1 | |
633 | #define M98925_DAI_VBST_SLOT_MASK (0x1F<<0) | |
634 | #define M98925_DAI_VBST_SLOT_SHIFT 0 | |
635 | #define M98925_DAI_VBST_SLOT_WIDTH 5 | |
636 | ||
637 | /* MAX98925_R026_DOUT_CFG_FLAG */ | |
638 | #define M98925_DAI_FLAG_EN_MASK (1<<5) | |
639 | #define M98925_DAI_FLAG_EN_SHIFT 5 | |
640 | #define M98925_DAI_FLAG_EN_WIDTH 1 | |
641 | #define M98925_DAI_FLAG_SLOT_MASK (0x1F<<0) | |
642 | #define M98925_DAI_FLAG_SLOT_SHIFT 0 | |
643 | #define M98925_DAI_FLAG_SLOT_WIDTH 5 | |
644 | ||
645 | /* MAX98925_R027_DOUT_HIZ_CFG1 */ | |
646 | #define M98925_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0) | |
647 | #define M98925_DAI_SLOT_HIZ_CFG1_SHIFT 0 | |
648 | #define M98925_DAI_SLOT_HIZ_CFG1_WIDTH 8 | |
649 | ||
650 | /* MAX98925_R028_DOUT_HIZ_CFG2 */ | |
651 | #define M98925_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0) | |
652 | #define M98925_DAI_SLOT_HIZ_CFG2_SHIFT 0 | |
653 | #define M98925_DAI_SLOT_HIZ_CFG2_WIDTH 8 | |
654 | ||
655 | /* MAX98925_R029_DOUT_HIZ_CFG3 */ | |
656 | #define M98925_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0) | |
657 | #define M98925_DAI_SLOT_HIZ_CFG3_SHIFT 0 | |
658 | #define M98925_DAI_SLOT_HIZ_CFG3_WIDTH 8 | |
659 | ||
660 | /* MAX98925_R02A_DOUT_HIZ_CFG4 */ | |
661 | #define M98925_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0) | |
662 | #define M98925_DAI_SLOT_HIZ_CFG4_SHIFT 0 | |
663 | #define M98925_DAI_SLOT_HIZ_CFG4_WIDTH 8 | |
664 | ||
665 | /* MAX98925_R02B_DOUT_DRV_STRENGTH */ | |
666 | #define M98925_DAI_OUT_DRIVE_MASK (0x03<<0) | |
667 | #define M98925_DAI_OUT_DRIVE_SHIFT 0 | |
668 | #define M98925_DAI_OUT_DRIVE_WIDTH 2 | |
669 | ||
670 | /* MAX98925_R02C_FILTERS */ | |
671 | #define M98925_ADC_DITHER_EN_MASK (1<<7) | |
672 | #define M98925_ADC_DITHER_EN_SHIFT 7 | |
673 | #define M98925_ADC_DITHER_EN_WIDTH 1 | |
674 | #define M98925_IV_DCB_EN_MASK (1<<6) | |
675 | #define M98925_IV_DCB_EN_SHIFT 6 | |
676 | #define M98925_IV_DCB_EN_WIDTH 1 | |
677 | #define M98925_DAC_DITHER_EN_MASK (1<<4) | |
678 | #define M98925_DAC_DITHER_EN_SHIFT 4 | |
679 | #define M98925_DAC_DITHER_EN_WIDTH 1 | |
680 | #define M98925_DAC_FILTER_MODE_MASK (1<<3) | |
681 | #define M98925_DAC_FILTER_MODE_SHIFT 3 | |
682 | #define M98925_DAC_FILTER_MODE_WIDTH 1 | |
683 | #define M98925_DAC_HPF_MASK (0x07<<0) | |
684 | #define M98925_DAC_HPF_SHIFT 0 | |
685 | #define M98925_DAC_HPF_WIDTH 3 | |
686 | #define M98925_DAC_HPF_DISABLE (0 << M98925_DAC_HPF_SHIFT) | |
687 | #define M98925_DAC_HPF_DC_BLOCK (1 << M98925_DAC_HPF_SHIFT) | |
688 | #define M98925_DAC_HPF_EN_100 (2 << M98925_DAC_HPF_SHIFT) | |
689 | #define M98925_DAC_HPF_EN_200 (3 << M98925_DAC_HPF_SHIFT) | |
690 | #define M98925_DAC_HPF_EN_400 (4 << M98925_DAC_HPF_SHIFT) | |
691 | #define M98925_DAC_HPF_EN_800 (5 << M98925_DAC_HPF_SHIFT) | |
692 | ||
693 | /* MAX98925_R02D_GAIN */ | |
694 | #define M98925_DAC_IN_SEL_MASK (0x03<<5) | |
695 | #define M98925_DAC_IN_SEL_SHIFT 5 | |
696 | #define M98925_DAC_IN_SEL_WIDTH 2 | |
697 | #define M98925_SPK_GAIN_MASK (0x1F<<0) | |
698 | #define M98925_SPK_GAIN_SHIFT 0 | |
699 | #define M98925_SPK_GAIN_WIDTH 5 | |
700 | ||
701 | #define M98925_DAC_IN_SEL_LEFT_DAI (0 << M98925_DAC_IN_SEL_SHIFT) | |
702 | #define M98925_DAC_IN_SEL_RIGHT_DAI (1 << M98925_DAC_IN_SEL_SHIFT) | |
703 | #define M98925_DAC_IN_SEL_SUMMED_DAI (2 << M98925_DAC_IN_SEL_SHIFT) | |
704 | #define M98925_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << M98925_DAC_IN_SEL_SHIFT) | |
705 | ||
706 | /* MAX98925_R02E_GAIN_RAMPING */ | |
707 | #define M98925_SPK_RMP_EN_MASK (1<<1) | |
708 | #define M98925_SPK_RMP_EN_SHIFT 1 | |
709 | #define M98925_SPK_RMP_EN_WIDTH 1 | |
710 | #define M98925_SPK_ZCD_EN_MASK (1<<0) | |
711 | #define M98925_SPK_ZCD_EN_SHIFT 0 | |
712 | #define M98925_SPK_ZCD_EN_WIDTH 1 | |
713 | ||
714 | /* MAX98925_R02F_SPK_AMP */ | |
715 | #define M98925_SPK_MODE_MASK (1<<0) | |
716 | #define M98925_SPK_MODE_SHIFT 0 | |
717 | #define M98925_SPK_MODE_WIDTH 1 | |
718 | ||
719 | /* MAX98925_R030_THRESHOLD */ | |
720 | #define M98925_ALC_EN_MASK (1<<5) | |
721 | #define M98925_ALC_EN_SHIFT 5 | |
722 | #define M98925_ALC_EN_WIDTH 1 | |
723 | #define M98925_ALC_TH_MASK (0x1F<<0) | |
724 | #define M98925_ALC_TH_SHIFT 0 | |
725 | #define M98925_ALC_TH_WIDTH 5 | |
726 | ||
727 | /* MAX98925_R031_ALC_ATTACK */ | |
728 | #define M98925_ALC_ATK_STEP_MASK (0x0F<<4) | |
729 | #define M98925_ALC_ATK_STEP_SHIFT 4 | |
730 | #define M98925_ALC_ATK_STEP_WIDTH 4 | |
731 | #define M98925_ALC_ATK_RATE_MASK (0x7<<0) | |
732 | #define M98925_ALC_ATK_RATE_SHIFT 0 | |
733 | #define M98925_ALC_ATK_RATE_WIDTH 3 | |
734 | ||
735 | /* MAX98925_R032_ALC_ATTEN_RLS */ | |
736 | #define M98925_ALC_MAX_ATTEN_MASK (0x0F<<4) | |
737 | #define M98925_ALC_MAX_ATTEN_SHIFT 4 | |
738 | #define M98925_ALC_MAX_ATTEN_WIDTH 4 | |
739 | #define M98925_ALC_RLS_RATE_MASK (0x7<<0) | |
740 | #define M98925_ALC_RLS_RATE_SHIFT 0 | |
741 | #define M98925_ALC_RLS_RATE_WIDTH 3 | |
742 | ||
743 | /* MAX98925_R033_ALC_HOLD_RLS */ | |
744 | #define M98925_ALC_RLS_TGR_MASK (1<<0) | |
745 | #define M98925_ALC_RLS_TGR_SHIFT 0 | |
746 | #define M98925_ALC_RLS_TGR_WIDTH 1 | |
747 | ||
748 | /* MAX98925_R034_ALC_CONFIGURATION */ | |
749 | #define M98925_ALC_MUTE_EN_MASK (1<<7) | |
750 | #define M98925_ALC_MUTE_EN_SHIFT 7 | |
751 | #define M98925_ALC_MUTE_EN_WIDTH 1 | |
752 | #define M98925_ALC_MUTE_DLY_MASK (0x07<<4) | |
753 | #define M98925_ALC_MUTE_DLY_SHIFT 4 | |
754 | #define M98925_ALC_MUTE_DLY_WIDTH 3 | |
755 | #define M98925_ALC_RLS_DBT_MASK (0x07<<0) | |
756 | #define M98925_ALC_RLS_DBT_SHIFT 0 | |
757 | #define M98925_ALC_RLS_DBT_WIDTH 3 | |
758 | ||
759 | /* MAX98925_R035_BOOST_CONVERTER */ | |
760 | #define M98925_BST_SYNC_MASK (1<<7) | |
761 | #define M98925_BST_SYNC_SHIFT 7 | |
762 | #define M98925_BST_SYNC_WIDTH 1 | |
763 | #define M98925_BST_PHASE_MASK (0x03<<4) | |
764 | #define M98925_BST_PHASE_SHIFT 4 | |
765 | #define M98925_BST_PHASE_WIDTH 2 | |
766 | #define M98925_BST_SKIP_MODE_MASK (0x03<<0) | |
767 | #define M98925_BST_SKIP_MODE_SHIFT 0 | |
768 | #define M98925_BST_SKIP_MODE_WIDTH 2 | |
769 | ||
770 | /* MAX98925_R036_BLOCK_ENABLE */ | |
771 | #define M98925_BST_EN_MASK (1<<7) | |
772 | #define M98925_BST_EN_SHIFT 7 | |
773 | #define M98925_BST_EN_WIDTH 1 | |
774 | #define M98925_WATCH_EN_MASK (1<<6) | |
775 | #define M98925_WATCH_EN_SHIFT 6 | |
776 | #define M98925_WATCH_EN_WIDTH 1 | |
777 | #define M98925_CLKMON_EN_MASK (1<<5) | |
778 | #define M98925_CLKMON_EN_SHIFT 5 | |
779 | #define M98925_CLKMON_EN_WIDTH 1 | |
780 | #define M98925_SPK_EN_MASK (1<<4) | |
781 | #define M98925_SPK_EN_SHIFT 4 | |
782 | #define M98925_SPK_EN_WIDTH 1 | |
783 | #define M98925_ADC_VBST_EN_MASK (1<<3) | |
784 | #define M98925_ADC_VBST_EN_SHIFT 3 | |
785 | #define M98925_ADC_VBST_EN_WIDTH 1 | |
786 | #define M98925_ADC_VBAT_EN_MASK (1<<2) | |
787 | #define M98925_ADC_VBAT_EN_SHIFT 2 | |
788 | #define M98925_ADC_VBAT_EN_WIDTH 1 | |
789 | #define M98925_ADC_IMON_EN_MASK (1<<1) | |
790 | #define M98925_ADC_IMON_EN_SHIFT 1 | |
791 | #define M98925_ADC_IMON_EN_WIDTH 1 | |
792 | #define M98925_ADC_VMON_EN_MASK (1<<0) | |
793 | #define M98925_ADC_VMON_EN_SHIFT 0 | |
794 | #define M98925_ADC_VMON_EN_WIDTH 1 | |
795 | ||
796 | /* MAX98925_R037_CONFIGURATION */ | |
797 | #define M98925_BST_VOUT_MASK (0x0F<<4) | |
798 | #define M98925_BST_VOUT_SHIFT 4 | |
799 | #define M98925_BST_VOUT_WIDTH 4 | |
800 | #define M98925_THERMWARN_LEVEL_MASK (0x03<<2) | |
801 | #define M98925_THERMWARN_LEVEL_SHIFT 2 | |
802 | #define M98925_THERMWARN_LEVEL_WIDTH 2 | |
803 | #define M98925_WATCH_TIME_MASK (0x03<<0) | |
804 | #define M98925_WATCH_TIME_SHIFT 0 | |
805 | #define M98925_WATCH_TIME_WIDTH 2 | |
806 | ||
807 | /* MAX98925_R038_GLOBAL_ENABLE */ | |
808 | #define M98925_EN_MASK (1<<7) | |
809 | #define M98925_EN_SHIFT 7 | |
810 | #define M98925_EN_WIDTH 1 | |
811 | ||
812 | /* MAX98925_R03A_BOOST_LIMITER */ | |
813 | #define M98925_BST_ILIM_MASK (0x1F<<3) | |
814 | #define M98925_BST_ILIM_SHIFT 3 | |
815 | #define M98925_BST_ILIM_WIDTH 5 | |
816 | ||
817 | /* MAX98925_R0FF_VERSION */ | |
818 | #define M98925_REV_ID_MASK (0xFF<<0) | |
819 | #define M98925_REV_ID_SHIFT 0 | |
820 | #define M98925_REV_ID_WIDTH 8 | |
821 | ||
822 | struct max98925_priv { | |
823 | struct regmap *regmap; | |
824 | struct snd_soc_codec *codec; | |
825 | struct max98925_pdata *pdata; | |
826 | unsigned int sysclk; | |
827 | unsigned int v_slot; | |
828 | unsigned int i_slot; | |
829 | unsigned int spk_gain; | |
830 | unsigned int ch_size; | |
831 | }; | |
832 | #endif |