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ASoC: nau8825: fix bug in playback when suspend
[deliverable/linux.git] / sound / soc / codecs / nau8825.c
CommitLineData
34ca27f3
AP		 1/*
2 * Nuvoton NAU8825 audio codec driver
3 *
4 * Copyright 2015 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
6 * Copyright 2015 Nuvoton Technology Corp.
7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
8 *
9 * Licensed under the GPL-2.
10 */
11
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/i2c.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <linux/clk.h>
b3681308 19#include <linux/acpi.h>
c86ba612 20#include <linux/math64.h>
b50455fa 21#include <linux/semaphore.h>
34ca27f3
AP		 22
23#include <sound/initval.h>
24#include <sound/tlv.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/jack.h>
30
31
32#include "nau8825.h"
33
2ec30f60
JH		 34
35#define NUVOTON_CODEC_DAI "nau8825-hifi"
36
c86ba612 37#define NAU_FREF_MAX 13500000
407c71b6 38#define NAU_FVCO_MAX 124000000
c86ba612
BZ		 39#define NAU_FVCO_MIN 90000000
40
b50455fa
JH		 41/* cross talk suppression detection */
42#define LOG10_MAGIC 646456993
43#define GAIN_AUGMENT 22500
44#define SIDETONE_BASE 207000
45
46
2ec30f60
JH		 47static int nau8825_configure_sysclk(struct nau8825 *nau8825,
48 int clk_id, unsigned int freq);
49
c86ba612
BZ		 50struct nau8825_fll {
51 int mclk_src;
52 int ratio;
53 int fll_frac;
54 int fll_int;
55 int clk_ref_div;
56};
57
58struct nau8825_fll_attr {
59 unsigned int param;
60 unsigned int val;
61};
62
63/* scaling for mclk from sysclk_src output */
64static const struct nau8825_fll_attr mclk_src_scaling[] = {
65 { 1, 0x0 },
66 { 2, 0x2 },
67 { 4, 0x3 },
68 { 8, 0x4 },
69 { 16, 0x5 },
70 { 32, 0x6 },
71 { 3, 0x7 },
72 { 6, 0xa },
73 { 12, 0xb },
74 { 24, 0xc },
75 { 48, 0xd },
76 { 96, 0xe },
77 { 5, 0xf },
78};
79
80/* ratio for input clk freq */
81static const struct nau8825_fll_attr fll_ratio[] = {
82 { 512000, 0x01 },
83 { 256000, 0x02 },
84 { 128000, 0x04 },
85 { 64000, 0x08 },
86 { 32000, 0x10 },
87 { 8000, 0x20 },
88 { 4000, 0x40 },
89};
90
91static const struct nau8825_fll_attr fll_pre_scalar[] = {
92 { 1, 0x0 },
93 { 2, 0x1 },
94 { 4, 0x2 },
95 { 8, 0x3 },
96};
97
34ca27f3
AP		 98static const struct reg_default nau8825_reg_defaults[] = {
99 { NAU8825_REG_ENA_CTRL, 0x00ff },
45d5eb3a 100 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
34ca27f3
AP		 101 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
102 { NAU8825_REG_FLL1, 0x0 },
103 { NAU8825_REG_FLL2, 0x3126 },
104 { NAU8825_REG_FLL3, 0x0008 },
105 { NAU8825_REG_FLL4, 0x0010 },
106 { NAU8825_REG_FLL5, 0x0 },
107 { NAU8825_REG_FLL6, 0x6000 },
108 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
109 { NAU8825_REG_HSD_CTRL, 0x000c },
110 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
111 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
112 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
113 { NAU8825_REG_SAR_CTRL, 0x0015 },
114 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
115 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
116 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
117 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
118 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
119 { NAU8825_REG_GPIO34_CTRL, 0x0 },
120 { NAU8825_REG_GPIO12_CTRL, 0x0 },
121 { NAU8825_REG_TDM_CTRL, 0x0 },
122 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
123 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
124 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
125 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
126 { NAU8825_REG_BIQ_CTRL, 0x0 },
127 { NAU8825_REG_BIQ_COF1, 0x0 },
128 { NAU8825_REG_BIQ_COF2, 0x0 },
129 { NAU8825_REG_BIQ_COF3, 0x0 },
130 { NAU8825_REG_BIQ_COF4, 0x0 },
131 { NAU8825_REG_BIQ_COF5, 0x0 },
132 { NAU8825_REG_BIQ_COF6, 0x0 },
133 { NAU8825_REG_BIQ_COF7, 0x0 },
134 { NAU8825_REG_BIQ_COF8, 0x0 },
135 { NAU8825_REG_BIQ_COF9, 0x0 },
136 { NAU8825_REG_BIQ_COF10, 0x0 },
137 { NAU8825_REG_ADC_RATE, 0x0010 },
138 { NAU8825_REG_DAC_CTRL1, 0x0001 },
139 { NAU8825_REG_DAC_CTRL2, 0x0 },
140 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
141 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
142 { NAU8825_REG_MUTE_CTRL, 0x0 },
143 { NAU8825_REG_HSVOL_CTRL, 0x0 },
144 { NAU8825_REG_DACL_CTRL, 0x02cf },
145 { NAU8825_REG_DACR_CTRL, 0x00cf },
146 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
147 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
148 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
149 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
150 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
151 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
152 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
153 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
154 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
155 { NAU8825_REG_CLASSG_CTRL, 0x0 },
156 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
157 { NAU8825_REG_MISC_CTRL, 0x0 },
158 { NAU8825_REG_BIAS_ADJ, 0x0 },
159 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
160 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
161 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
162 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
163 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
164 { NAU8825_REG_RDAC, 0x0008 },
165 { NAU8825_REG_MIC_BIAS, 0x0006 },
166 { NAU8825_REG_BOOST, 0x0 },
167 { NAU8825_REG_FEPGA, 0x0 },
168 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
169 { NAU8825_REG_CHARGE_PUMP, 0x0 },
170};
171
b50455fa
JH		 172/* register backup table when cross talk detection */
173static struct reg_default nau8825_xtalk_baktab[] = {
174 { NAU8825_REG_ADC_DGAIN_CTRL, 0 },
175 { NAU8825_REG_HSVOL_CTRL, 0 },
176 { NAU8825_REG_DACL_CTRL, 0 },
177 { NAU8825_REG_DACR_CTRL, 0 },
178};
179
180static const unsigned short logtable[256] = {
181 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
182 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
183 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
184 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
185 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
186 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
187 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
188 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
189 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
190 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
191 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
192 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
193 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
194 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
195 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
196 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
197 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
198 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
199 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
200 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
201 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
202 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
203 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
204 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
205 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
206 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
207 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
208 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
209 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
210 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
211 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
212 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
213};
214
b50455fa
JH		 215/**
216 * nau8825_sema_acquire - acquire the semaphore of nau88l25
217 * @nau8825: component to register the codec private data with
218 * @timeout: how long in jiffies to wait before failure or zero to wait
219 * until release
220 *
221 * Attempts to acquire the semaphore with number of jiffies. If no more
222 * tasks are allowed to acquire the semaphore, calling this function will
223 * put the task to sleep. If the semaphore is not released within the
224 * specified number of jiffies, this function returns.
225 * Acquires the semaphore without jiffies. If no more tasks are allowed
226 * to acquire the semaphore, calling this function will put the task to
227 * sleep until the semaphore is released.
228 * It returns if the semaphore was acquired.
229 */
230static void nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
231{
232 int ret;
233
234 if (timeout)
235 ret = down_timeout(&nau8825->xtalk_sem, timeout);
236 else
237 ret = down_interruptible(&nau8825->xtalk_sem);
238
239 if (ret < 0)
240 dev_warn(nau8825->dev, "Acquire semaphone fail\n");
241}
242
243/**
244 * nau8825_sema_release - release the semaphore of nau88l25
245 * @nau8825: component to register the codec private data with
246 *
247 * Release the semaphore which may be called from any context and
248 * even by tasks which have never called down().
249 */
250static inline void nau8825_sema_release(struct nau8825 *nau8825)
251{
252 up(&nau8825->xtalk_sem);
253}
254
255/**
256 * nau8825_sema_reset - reset the semaphore for nau88l25
257 * @nau8825: component to register the codec private data with
258 *
259 * Reset the counter of the semaphore. Call this function to restart
260 * a new round task management.
261 */
262static inline void nau8825_sema_reset(struct nau8825 *nau8825)
263{
264 nau8825->xtalk_sem.count = 1;
265}
266
267/**
268 * Ramp up the headphone volume change gradually to target level.
269 *
270 * @nau8825: component to register the codec private data with
271 * @vol_from: the volume to start up
272 * @vol_to: the target volume
273 * @step: the volume span to move on
274 *
275 * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
276 * If the volume changes sharp, there is a pop noise heard in headphone. We
277 * provide the function to ramp up the volume up or down by delaying 10ms
278 * per step.
279 */
280static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
281 unsigned int vol_from, unsigned int vol_to, unsigned int step)
282{
283 unsigned int value, volume, ramp_up, from, to;
284
285 if (vol_from == vol_to || step == 0) {
286 return;
287 } else if (vol_from < vol_to) {
288 ramp_up = true;
289 from = vol_from;
290 to = vol_to;
291 } else {
292 ramp_up = false;
293 from = vol_to;
294 to = vol_from;
295 }
296 /* only handle volume from 0dB to minimum -54dB */
297 if (to > NAU8825_HP_VOL_MIN)
298 to = NAU8825_HP_VOL_MIN;
299
300 for (volume = from; volume < to; volume += step) {
301 if (ramp_up)
302 value = volume;
303 else
304 value = to - volume + from;
305 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
306 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
307 (value << NAU8825_HPL_VOL_SFT) | value);
308 usleep_range(10000, 10500);
309 }
310 if (ramp_up)
311 value = to;
312 else
313 value = from;
314 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
315 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
316 (value << NAU8825_HPL_VOL_SFT) | value);
317}
318
319/**
320 * Computes log10 of a value; the result is round off to 3 decimal. This func-
321 * tion takes reference to dvb-math. The source code locates as the following.
322 * Linux/drivers/media/dvb-core/dvb_math.c
323 *
324 * return log10(value) * 1000
325 */
326static u32 nau8825_intlog10_dec3(u32 value)
327{
328 u32 msb, logentry, significand, interpolation, log10val;
329 u64 log2val;
330
331 /* first detect the msb (count begins at 0) */
332 msb = fls(value) - 1;
333 /**
334 * now we use a logtable after the following method:
335 *
336 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
337 * where x = msb and therefore 1 <= y < 2
338 * first y is determined by shifting the value left
339 * so that msb is bit 31
340 * 0x00231f56 -> 0x8C7D5800
341 * the result is y * 2^31 -> "significand"
342 * then the highest 9 bits are used for a table lookup
343 * the highest bit is discarded because it's always set
344 * the highest nine bits in our example are 100011000
345 * so we would use the entry 0x18
346 */
347 significand = value << (31 - msb);
348 logentry = (significand >> 23) & 0xff;
349 /**
350 * last step we do is interpolation because of the
351 * limitations of the log table the error is that part of
352 * the significand which isn't used for lookup then we
353 * compute the ratio between the error and the next table entry
354 * and interpolate it between the log table entry used and the
355 * next one the biggest error possible is 0x7fffff
356 * (in our example it's 0x7D5800)
357 * needed value for next table entry is 0x800000
358 * so the interpolation is
359 * (error / 0x800000) * (logtable_next - logtable_current)
360 * in the implementation the division is moved to the end for
361 * better accuracy there is also an overflow correction if
362 * logtable_next is 256
363 */
364 interpolation = ((significand & 0x7fffff) *
365 ((logtable[(logentry + 1) & 0xff] -
366 logtable[logentry]) & 0xffff)) >> 15;
367
368 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
369 /**
370 * log10(x) = log2(x) * log10(2)
371 */
372 log10val = (log2val * LOG10_MAGIC) >> 31;
373 /**
374 * the result is round off to 3 decimal
375 */
376 return log10val / ((1 << 24) / 1000);
377}
378
379/**
380 * computes cross talk suppression sidetone gain.
381 *
382 * @sig_org: orignal signal level
383 * @sig_cros: cross talk signal level
384 *
385 * The orignal and cross talk signal vlues need to be characterized.
386 * Once these values have been characterized, this sidetone value
387 * can be converted to decibel with the equation below.
388 * sidetone = 20 * log (original signal level / crosstalk signal level)
389 *
390 * return cross talk sidetone gain
391 */
392static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
393{
394 u32 gain, sidetone;
395
396 if (unlikely(sig_org == 0) || unlikely(sig_cros == 0)) {
397 WARN_ON(1);
398 return 0;
399 }
400
401 sig_org = nau8825_intlog10_dec3(sig_org);
402 sig_cros = nau8825_intlog10_dec3(sig_cros);
403 if (sig_org >= sig_cros)
404 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
405 else
406 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
407 sidetone = SIDETONE_BASE - gain * 2;
408 sidetone /= 1000;
409
410 return sidetone;
411}
412
413static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
414{
415 int index;
416
417 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
418 if (nau8825_xtalk_baktab[index].reg == reg)
419 return index;
420 return -EINVAL;
421}
422
423static void nau8825_xtalk_backup(struct nau8825 *nau8825)
424{
425 int i;
426
427 /* Backup some register values to backup table */
428 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
429 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
430 &nau8825_xtalk_baktab[i].def);
431}
432
433static void nau8825_xtalk_restore(struct nau8825 *nau8825)
434{
435 int i, volume;
436
437 /* Restore register values from backup table; When the driver restores
438 * the headphone volumem, it needs recover to original level gradually
439 * with 3dB per step for less pop noise.
440 */
441 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
442 if (nau8825_xtalk_baktab[i].reg == NAU8825_REG_HSVOL_CTRL) {
443 /* Ramping up the volume change to reduce pop noise */
444 volume = nau8825_xtalk_baktab[i].def &
445 NAU8825_HPR_VOL_MASK;
446 nau8825_hpvol_ramp(nau8825, 0, volume, 3);
447 continue;
448 }
449 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
450 nau8825_xtalk_baktab[i].def);
451 }
452}
453
454static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
455{
456 /* Enable power of DAC path */
457 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
458 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
459 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
460 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
461 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
462 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
463 /* Prevent startup click by letting charge pump to ramp up and
464 * change bump enable
465 */
466 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
467 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
468 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
469 /* Enable clock sync of DAC and DAC clock */
470 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
471 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
472 NAU8825_RDAC_FS_BCLK_ENB,
473 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
474 /* Power up output driver with 2 stage */
475 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
476 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
477 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
478 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
479 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
480 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
481 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
482 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
483 /* HP outputs not shouted to ground */
484 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
485 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
486 /* Enable HP boost driver */
487 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
488 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
489 /* Enable class G compare path to supply 1.8V or 0.9V. */
490 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
491 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
492 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
493}
494
495static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
496{
497 /* Power up left ADC and raise 5dB than Vmid for Vref */
498 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
499 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
500 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
501}
502
503static void nau8825_xtalk_clock(struct nau8825 *nau8825)
504{
505 /* Recover FLL default value */
506 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
507 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
508 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
509 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
510 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
511 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
512 /* Enable internal VCO clock for detection signal generated */
513 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
514 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
515 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
516 NAU8825_DCO_EN);
517 /* Given specific clock frequency of internal clock to
518 * generate signal.
519 */
520 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
521 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
522 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
523 NAU8825_FLL_RATIO_MASK, 0x10);
524}
525
526static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
527{
528 int volume, index;
529
530 /* Backup those registers changed by cross talk detection */
531 nau8825_xtalk_backup(nau8825);
532 /* Config IIS as master to output signal by codec */
533 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
534 NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
535 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
536 (0x2 << NAU8825_I2S_DRV_SFT) | 0x1);
537 /* Ramp up headphone volume to 0dB to get better performance and
538 * avoid pop noise in headphone.
539 */
540 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
541 if (index != -EINVAL) {
542 volume = nau8825_xtalk_baktab[index].def &
543 NAU8825_HPR_VOL_MASK;
544 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
545 }
546 nau8825_xtalk_clock(nau8825);
547 nau8825_xtalk_prepare_dac(nau8825);
548 nau8825_xtalk_prepare_adc(nau8825);
549 /* Config channel path and digital gain */
550 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
551 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
552 NAU8825_DACL_CH_SEL_L | 0xab);
553 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
554 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
555 NAU8825_DACR_CH_SEL_R | 0xab);
556 /* Config cross talk parameters and generate the 23Hz sine wave with
557 * 1/16 full scale of signal level for impedance measurement.
558 */
559 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
560 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
561 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
562 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
563 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
564 /* RMS intrruption enable */
565 regmap_update_bits(nau8825->regmap,
566 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
567 /* Power up left and right DAC */
568 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
569 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
570}
571
572static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
573{
574 /* Disable HP boost driver */
575 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
576 NAU8825_HP_BOOST_DIS, 0);
577 /* HP outputs shouted to ground */
578 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
579 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
580 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
581 /* Power down left and right DAC */
582 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
583 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
584 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
585 /* Enable the TESTDAC and disable L/R HP impedance */
586 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
587 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
588 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
589 /* Power down output driver with 2 stage */
590 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
591 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
592 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
593 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
594 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
595 /* Disable clock sync of DAC and DAC clock */
596 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
597 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
598 /* Disable charge pump ramp up function and change bump */
599 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
600 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
601 /* Disable power of DAC path */
602 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
603 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
604 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
605 if (!nau8825->irq)
606 regmap_update_bits(nau8825->regmap,
607 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
608}
609
610static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
611{
612 /* Power down left ADC and restore voltage to Vmid */
613 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
614 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
615}
616
617static void nau8825_xtalk_clean(struct nau8825 *nau8825)
618{
619 /* Enable internal VCO needed for interruptions */
620 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
621 nau8825_xtalk_clean_dac(nau8825);
622 nau8825_xtalk_clean_adc(nau8825);
623 /* Clear cross talk parameters and disable */
624 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
625 /* RMS intrruption disable */
626 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
627 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
628 /* Recover default value for IIS */
629 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
630 NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
631 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
632 /* Restore value of specific register for cross talk */
633 nau8825_xtalk_restore(nau8825);
634}
635
636static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
637{
638 /* Apply ADC volume for better cross talk performance */
639 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
640 NAU8825_ADC_DIG_VOL_MASK, vol);
641 /* Disables JKTIP(HPL) DAC channel for right to left measurement.
642 * Do it before sending signal in order to erase pop noise.
643 */
644 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
645 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
646 NAU8825_BIAS_TESTDACL_EN);
647 switch (nau8825->xtalk_state) {
648 case NAU8825_XTALK_HPR_R2L:
649 /* Enable right headphone impedance */
650 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
651 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
652 NAU8825_BIAS_HPR_IMP);
653 break;
654 case NAU8825_XTALK_HPL_R2L:
655 /* Enable left headphone impedance */
656 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
657 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
658 NAU8825_BIAS_HPL_IMP);
659 break;
660 default:
661 break;
662 }
663 msleep(100);
664 /* Impedance measurement mode enable */
665 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
666 NAU8825_IMM_EN, NAU8825_IMM_EN);
667}
668
669static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
670{
671 /* Impedance measurement mode disable */
672 regmap_update_bits(nau8825->regmap,
673 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
674}
675
676/* The cross talk measurement function can reduce cross talk across the
677 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
678 * level to determine what cross talk reduction gain is. This system works by
679 * sending a 23Hz -24dBV sine wave into the headset output DAC and through
680 * the PGA. The output of the PGA is then connected to an internal current
681 * sense which measures the attenuated 23Hz signal and passing the output to
682 * an ADC which converts the measurement to a binary code. With two separated
683 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
684 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
685 * Thus, the measurement function has four states to complete whole sequence.
686 * 1. Prepare state : Prepare the resource for detection and transfer to HPR
687 * IMM stat to make JKR1(HPR) impedance measure.
688 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
689 * to HPL IMM state to make JKTIP(HPL) impedance measure.
690 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
691 * transfer to IMM state to determine suppression sidetone gain.
692 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
693 * and cross talk signal level. Apply this gain and then restore codec
694 * configuration. Then transfer to Done state for ending.
695 */
696static void nau8825_xtalk_measure(struct nau8825 *nau8825)
697{
698 u32 sidetone;
699
700 switch (nau8825->xtalk_state) {
701 case NAU8825_XTALK_PREPARE:
702 /* In prepare state, set up clock, intrruption, DAC path, ADC
703 * path and cross talk detection parameters for preparation.
704 */
705 nau8825_xtalk_prepare(nau8825);
706 msleep(280);
707 /* Trigger right headphone impedance detection */
708 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
709 nau8825_xtalk_imm_start(nau8825, 0x00d2);
710 break;
711 case NAU8825_XTALK_HPR_R2L:
712 /* In right headphone IMM state, read out right headphone
713 * impedance measure result, and then start up left side.
714 */
715 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
716 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
717 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
718 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
719 /* Disable then re-enable IMM mode to update */
720 nau8825_xtalk_imm_stop(nau8825);
721 /* Trigger left headphone impedance detection */
722 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
723 nau8825_xtalk_imm_start(nau8825, 0x00ff);
724 break;
725 case NAU8825_XTALK_HPL_R2L:
726 /* In left headphone IMM state, read out left headphone
727 * impedance measure result, and delay some time to wait
728 * detection sine wave output finish. Then, we can calculate
729 * the cross talk suppresstion side tone according to the L/R
730 * headphone imedance.
731 */
732 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
733 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
734 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
735 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
736 nau8825_xtalk_imm_stop(nau8825);
737 msleep(150);
738 nau8825->xtalk_state = NAU8825_XTALK_IMM;
739 break;
740 case NAU8825_XTALK_IMM:
741 /* In impedance measure state, the orignal and cross talk
742 * signal level vlues are ready. The side tone gain is deter-
743 * mined with these signal level. After all, restore codec
744 * configuration.
745 */
746 sidetone = nau8825_xtalk_sidetone(
747 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
748 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
749 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
750 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
751 (sidetone << 8) | sidetone);
752 nau8825_xtalk_clean(nau8825);
753 nau8825->xtalk_state = NAU8825_XTALK_DONE;
754 break;
755 default:
756 break;
757 }
758}
759
760static void nau8825_xtalk_work(struct work_struct *work)
761{
762 struct nau8825 *nau8825 = container_of(
763 work, struct nau8825, xtalk_work);
764
765 nau8825_xtalk_measure(nau8825);
766 /* To determine the cross talk side tone gain when reach
767 * the impedance measure state.
768 */
769 if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
770 nau8825_xtalk_measure(nau8825);
771
772 /* Delay jack report until cross talk detection process
773 * completed. It can avoid application to do playback
774 * preparation before cross talk detection is still working.
775 * Meanwhile, the protection of the cross talk detection
776 * is released.
777 */
778 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
779 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
780 nau8825->xtalk_event_mask);
781 nau8825_sema_release(nau8825);
782 nau8825->xtalk_protect = false;
783 }
784}
785
786static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
787{
788 /* If the xtalk_protect is true, that means the process is still
789 * on going. The driver forces to cancel the cross talk task and
790 * restores the configuration to original status.
791 */
792 if (nau8825->xtalk_protect) {
793 cancel_work_sync(&nau8825->xtalk_work);
794 nau8825_xtalk_clean(nau8825);
795 }
796 /* Reset parameters for cross talk suppression function */
797 nau8825_sema_reset(nau8825);
798 nau8825->xtalk_state = NAU8825_XTALK_DONE;
799 nau8825->xtalk_protect = false;
800}
801
34ca27f3
AP		 802static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
803{
804 switch (reg) {
45d5eb3a 805 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
34ca27f3
AP		 806 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
807 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
808 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
809 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
810 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
811 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
812 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
813 case NAU8825_REG_MISC_CTRL:
814 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
815 case NAU8825_REG_BIAS_ADJ:
816 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
817 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
818 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
819 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
820 return true;
821 default:
822 return false;
823 }
824
825}
826
827static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
828{
829 switch (reg) {
45d5eb3a 830 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
34ca27f3
AP		 831 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
832 case NAU8825_REG_INTERRUPT_MASK:
833 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
834 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
835 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
836 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
837 case NAU8825_REG_IMM_MODE_CTRL:
838 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
839 case NAU8825_REG_MISC_CTRL:
840 case NAU8825_REG_BIAS_ADJ:
841 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
842 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
843 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
844 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
845 return true;
846 default:
847 return false;
848 }
849}
850
851static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
852{
853 switch (reg) {
854 case NAU8825_REG_RESET:
855 case NAU8825_REG_IRQ_STATUS:
856 case NAU8825_REG_INT_CLR_KEY_STATUS:
857 case NAU8825_REG_IMM_RMS_L:
858 case NAU8825_REG_IMM_RMS_R:
859 case NAU8825_REG_I2C_DEVICE_ID:
860 case NAU8825_REG_SARDOUT_RAM_STATUS:
861 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
862 case NAU8825_REG_GENERAL_STATUS:
18d8306d 863 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
34ca27f3
AP		 864 return true;
865 default:
866 return false;
867 }
868}
869
eeef16ac
JH		 870static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
871 struct snd_kcontrol *kcontrol, int event)
872{
873 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
874 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
875
876 switch (event) {
877 case SND_SOC_DAPM_POST_PMU:
878 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
879 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
880 break;
881 case SND_SOC_DAPM_POST_PMD:
882 if (!nau8825->irq)
883 regmap_update_bits(nau8825->regmap,
884 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
885 break;
886 default:
887 return -EINVAL;
888 }
889
890 return 0;
891}
892
34ca27f3
AP		 893static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
894 struct snd_kcontrol *kcontrol, int event)
895{
45d5eb3a
JH		 896 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
897 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
898
34ca27f3
AP		 899 switch (event) {
900 case SND_SOC_DAPM_POST_PMU:
901 /* Prevent startup click by letting charge pump to ramp up */
902 msleep(10);
45d5eb3a
JH		 903 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
904 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
905 break;
906 case SND_SOC_DAPM_PRE_PMD:
907 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
908 NAU8825_JAMNODCLOW, 0);
909 break;
910 default:
911 return -EINVAL;
912 }
913
914 return 0;
915}
916
917static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
918 struct snd_kcontrol *kcontrol, int event)
919{
920 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
921 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
922
923 switch (event) {
924 case SND_SOC_DAPM_PRE_PMU:
925 /* Disables the TESTDAC to let DAC signal pass through. */
926 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
927 NAU8825_BIAS_TESTDAC_EN, 0);
928 break;
929 case SND_SOC_DAPM_POST_PMD:
930 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
931 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
34ca27f3
AP		 932 break;
933 default:
934 return -EINVAL;
935 }
936
937 return 0;
938}
939
18d8306d
JH		 940static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
941 struct snd_ctl_elem_value *ucontrol)
942{
943 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
944 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
945
946 if (!component->regmap)
947 return -EINVAL;
948
949 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
950 ucontrol->value.bytes.data, params->max);
951 return 0;
952}
953
954static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
955 struct snd_ctl_elem_value *ucontrol)
956{
957 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
958 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
959 void *data;
960
961 if (!component->regmap)
962 return -EINVAL;
963
964 data = kmemdup(ucontrol->value.bytes.data,
965 params->max, GFP_KERNEL | GFP_DMA);
966 if (!data)
967 return -ENOMEM;
968
969 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
970 NAU8825_BIQ_WRT_EN, 0);
971 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
972 data, params->max);
973 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
974 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
975
976 kfree(data);
977 return 0;
978}
979
980static const char * const nau8825_biq_path[] = {
981 "ADC", "DAC"
982};
983
984static const struct soc_enum nau8825_biq_path_enum =
985 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
986 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
987
34ca27f3
AP		 988static const char * const nau8825_adc_decimation[] = {
989 "32", "64", "128", "256"
990};
991
992static const struct soc_enum nau8825_adc_decimation_enum =
993 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
994 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
995
996static const char * const nau8825_dac_oversampl[] = {
997 "64", "256", "128", "", "32"
998};
999
1000static const struct soc_enum nau8825_dac_oversampl_enum =
1001 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1002 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1003
1004static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1005static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1006static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1007static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1008static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1009
1010static const struct snd_kcontrol_new nau8825_controls[] = {
1011 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1012 0, 0xff, 0, adc_vol_tlv),
1013 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1014 12, 8, 0x0f, 0, sidetone_vol_tlv),
1015 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1016 6, 0, 0x3f, 1, dac_vol_tlv),
1017 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1018 8, 37, 0, fepga_gain_tlv),
1019 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1020 0, 8, 0xff, 0, crosstalk_vol_tlv),
1021
1022 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1023 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
18d8306d
JH		 1024 /* programmable biquad filter */
1025 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
0cbeccdf 1026 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
18d8306d 1027 nau8825_biq_coeff_get, nau8825_biq_coeff_put),
34ca27f3
AP		 1028};
1029
1030/* DAC Mux 0x33[9] and 0x34[9] */
1031static const char * const nau8825_dac_src[] = {
1032 "DACL", "DACR",
1033};
1034
1035static SOC_ENUM_SINGLE_DECL(
1036 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1037 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1038
1039static SOC_ENUM_SINGLE_DECL(
1040 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1041 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1042
1043static const struct snd_kcontrol_new nau8825_dacl_mux =
1044 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1045
1046static const struct snd_kcontrol_new nau8825_dacr_mux =
1047 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1048
1049
1050static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1051 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1052 15, 1),
1053
1054 SND_SOC_DAPM_INPUT("MIC"),
1055 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1056
1057 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1058 NULL, 0),
1059
eeef16ac
JH		 1060 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1061 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1062 SND_SOC_DAPM_POST_PMD),
34ca27f3
AP		 1063 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1064 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1065 0),
1066
e6cee900
BZ		 1067 /* ADC for button press detection. A dapm supply widget is used to
1068 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1069 * during suspend.
1070 */
1071 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1072 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
34ca27f3 1073
45d5eb3a
JH		 1074 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1075 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1076 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1077 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
34ca27f3
AP		 1078
1079 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1080 NAU8825_ENABLE_DACR_SFT, 0),
1081 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1082 NAU8825_ENABLE_DACL_SFT, 0),
1083 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1084
1085 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1086 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1087
45d5eb3a
JH		 1088 SND_SOC_DAPM_PGA_S("HP amp L", 0,
1089 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1090 SND_SOC_DAPM_PGA_S("HP amp R", 0,
1091 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
34ca27f3 1092
45d5eb3a
JH		 1093 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1094 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1095 SND_SOC_DAPM_PRE_PMD),
34ca27f3 1096
45d5eb3a 1097 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
34ca27f3 1098 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
45d5eb3a 1099 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
34ca27f3 1100 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
45d5eb3a 1101 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
34ca27f3 1102 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
45d5eb3a 1103 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
34ca27f3 1104 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
45d5eb3a 1105 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
34ca27f3 1106 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
45d5eb3a 1107 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
34ca27f3
AP		 1108 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1109
45d5eb3a
JH		 1110 SND_SOC_DAPM_PGA_S("Output DACL", 7,
1111 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1112 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1113 SND_SOC_DAPM_PGA_S("Output DACR", 7,
1114 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1115 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1116
1117 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1118 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1119 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1120 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1121 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1122
1123 /* High current HPOL/R boost driver */
1124 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1125 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1126
1127 /* Class G operation control*/
1128 SND_SOC_DAPM_PGA_S("Class G", 10,
1129 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
34ca27f3
AP		 1130
1131 SND_SOC_DAPM_OUTPUT("HPOL"),
1132 SND_SOC_DAPM_OUTPUT("HPOR"),
1133};
1134
1135static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1136 {"Frontend PGA", NULL, "MIC"},
1137 {"ADC", NULL, "Frontend PGA"},
1138 {"ADC", NULL, "ADC Clock"},
1139 {"ADC", NULL, "ADC Power"},
1140 {"AIFTX", NULL, "ADC"},
1141
1142 {"DDACL", NULL, "Playback"},
1143 {"DDACR", NULL, "Playback"},
1144 {"DDACL", NULL, "DDAC Clock"},
1145 {"DDACR", NULL, "DDAC Clock"},
1146 {"DACL Mux", "DACL", "DDACL"},
1147 {"DACL Mux", "DACR", "DDACR"},
1148 {"DACR Mux", "DACL", "DDACL"},
1149 {"DACR Mux", "DACR", "DDACR"},
1150 {"HP amp L", NULL, "DACL Mux"},
1151 {"HP amp R", NULL, "DACR Mux"},
45d5eb3a
JH		 1152 {"Charge Pump", NULL, "HP amp L"},
1153 {"Charge Pump", NULL, "HP amp R"},
1154 {"ADACL", NULL, "Charge Pump"},
1155 {"ADACR", NULL, "Charge Pump"},
1156 {"ADACL Clock", NULL, "ADACL"},
1157 {"ADACR Clock", NULL, "ADACR"},
1158 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1159 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
34ca27f3
AP		 1160 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1161 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1162 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1163 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1164 {"Output DACL", NULL, "Output Driver L Stage 3"},
1165 {"Output DACR", NULL, "Output Driver R Stage 3"},
45d5eb3a
JH		 1166 {"HPOL Pulldown", NULL, "Output DACL"},
1167 {"HPOR Pulldown", NULL, "Output DACR"},
1168 {"HP Boost Driver", NULL, "HPOL Pulldown"},
1169 {"HP Boost Driver", NULL, "HPOR Pulldown"},
1170 {"Class G", NULL, "HP Boost Driver"},
1171 {"HPOL", NULL, "Class G"},
1172 {"HPOR", NULL, "Class G"},
34ca27f3
AP		 1173};
1174
1175static int nau8825_hw_params(struct snd_pcm_substream *substream,
1176 struct snd_pcm_hw_params *params,
1177 struct snd_soc_dai *dai)
1178{
1179 struct snd_soc_codec *codec = dai->codec;
1180 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1181 unsigned int val_len = 0;
1182
ca6ac305
JH		 1183 nau8825_sema_acquire(nau8825, 2 * HZ);
1184
34ca27f3
AP		 1185 switch (params_width(params)) {
1186 case 16:
1187 val_len |= NAU8825_I2S_DL_16;
1188 break;
1189 case 20:
1190 val_len |= NAU8825_I2S_DL_20;
1191 break;
1192 case 24:
1193 val_len |= NAU8825_I2S_DL_24;
1194 break;
1195 case 32:
1196 val_len |= NAU8825_I2S_DL_32;
1197 break;
1198 default:
1199 return -EINVAL;
1200 }
1201
1202 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1203 NAU8825_I2S_DL_MASK, val_len);
1204
ca6ac305
JH		 1205 /* Release the semaphone. */
1206 nau8825_sema_release(nau8825);
1207
34ca27f3
AP		 1208 return 0;
1209}
1210
1211static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1212{
1213 struct snd_soc_codec *codec = codec_dai->codec;
1214 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1215 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1216
ca6ac305
JH		 1217 nau8825_sema_acquire(nau8825, 2 * HZ);
1218
34ca27f3
AP		 1219 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1220 case SND_SOC_DAIFMT_CBM_CFM:
1221 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1222 break;
1223 case SND_SOC_DAIFMT_CBS_CFS:
1224 break;
1225 default:
1226 return -EINVAL;
1227 }
1228
1229 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1230 case SND_SOC_DAIFMT_NB_NF:
1231 break;
1232 case SND_SOC_DAIFMT_IB_NF:
1233 ctrl1_val |= NAU8825_I2S_BP_INV;
1234 break;
1235 default:
1236 return -EINVAL;
1237 }
1238
1239 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1240 case SND_SOC_DAIFMT_I2S:
1241 ctrl1_val |= NAU8825_I2S_DF_I2S;
1242 break;
1243 case SND_SOC_DAIFMT_LEFT_J:
1244 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1245 break;
1246 case SND_SOC_DAIFMT_RIGHT_J:
1247 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1248 break;
1249 case SND_SOC_DAIFMT_DSP_A:
1250 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1251 break;
1252 case SND_SOC_DAIFMT_DSP_B:
1253 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1254 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1255 break;
1256 default:
1257 return -EINVAL;
1258 }
1259
1260 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1261 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1262 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1263 ctrl1_val);
1264 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1265 NAU8825_I2S_MS_MASK, ctrl2_val);
1266
ca6ac305
JH		 1267 /* Release the semaphone. */
1268 nau8825_sema_release(nau8825);
1269
34ca27f3
AP		 1270 return 0;
1271}
1272
1273static const struct snd_soc_dai_ops nau8825_dai_ops = {
1274 .hw_params = nau8825_hw_params,
1275 .set_fmt = nau8825_set_dai_fmt,
1276};
1277
1278#define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
1279#define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1280 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1281
1282static struct snd_soc_dai_driver nau8825_dai = {
1283 .name = "nau8825-hifi",
1284 .playback = {
1285 .stream_name = "Playback",
1286 .channels_min = 1,
1287 .channels_max = 2,
1288 .rates = NAU8825_RATES,
1289 .formats = NAU8825_FORMATS,
1290 },
1291 .capture = {
1292 .stream_name = "Capture",
1293 .channels_min = 1,
1294 .channels_max = 1,
1295 .rates = NAU8825_RATES,
1296 .formats = NAU8825_FORMATS,
1297 },
1298 .ops = &nau8825_dai_ops,
1299};
1300
1301/**
1302 * nau8825_enable_jack_detect - Specify a jack for event reporting
1303 *
1304 * @component: component to register the jack with
1305 * @jack: jack to use to report headset and button events on
1306 *
1307 * After this function has been called the headset insert/remove and button
1308 * events will be routed to the given jack. Jack can be null to stop
1309 * reporting.
1310 */
1311int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
1312 struct snd_soc_jack *jack)
1313{
1314 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1315 struct regmap *regmap = nau8825->regmap;
1316
1317 nau8825->jack = jack;
1318
1319 /* Ground HP Outputs[1:0], needed for headset auto detection
1320 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1321 */
1322 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1323 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1324 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1325
34ca27f3
AP		 1326 return 0;
1327}
1328EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1329
1330
1331static bool nau8825_is_jack_inserted(struct regmap *regmap)
1332{
bff03e81
JH		 1333 bool active_high, is_high;
1334 int status, jkdet;
34ca27f3 1335
bff03e81 1336 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
308e3e0b 1337 active_high = jkdet & NAU8825_JACK_POLARITY;
34ca27f3 1338 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
308e3e0b 1339 is_high = status & NAU8825_GPIO2JD1;
bff03e81
JH		 1340 /* return jack connection status according to jack insertion logic
1341 * active high or active low.
1342 */
1343 return active_high == is_high;
34ca27f3
AP		 1344}
1345
1346static void nau8825_restart_jack_detection(struct regmap *regmap)
1347{
1348 /* this will restart the entire jack detection process including MIC/GND
1349 * switching and create interrupts. We have to go from 0 to 1 and back
1350 * to 0 to restart.
1351 */
1352 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1353 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1354 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1355 NAU8825_JACK_DET_RESTART, 0);
1356}
1357
2ec30f60
JH		 1358static void nau8825_int_status_clear_all(struct regmap *regmap)
1359{
1360 int active_irq, clear_irq, i;
1361
1362 /* Reset the intrruption status from rightmost bit if the corres-
1363 * ponding irq event occurs.
1364 */
1365 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1366 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1367 clear_irq = (0x1 << i);
1368 if (active_irq & clear_irq)
1369 regmap_write(regmap,
1370 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1371 }
1372}
1373
34ca27f3
AP		 1374static void nau8825_eject_jack(struct nau8825 *nau8825)
1375{
1376 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1377 struct regmap *regmap = nau8825->regmap;
1378
b50455fa
JH		 1379 /* Force to cancel the cross talk detection process */
1380 nau8825_xtalk_cancel(nau8825);
1381
34ca27f3
AP		 1382 snd_soc_dapm_disable_pin(dapm, "SAR");
1383 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1384 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1385 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1386 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1387 /* ground HPL/HPR, MICGRND1/2 */
1388 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1389
1390 snd_soc_dapm_sync(dapm);
2ec30f60
JH		 1391
1392 /* Clear all interruption status */
1393 nau8825_int_status_clear_all(regmap);
1394
1395 /* Enable the insertion interruption, disable the ejection inter-
1396 * ruption, and then bypass de-bounce circuit.
1397 */
1398 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1399 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1400 NAU8825_IRQ_EJECT_DIS);
1401 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1402 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1403 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1404 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1405 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1406 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1407 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1408
1409 /* Disable ADC needed for interruptions at audo mode */
1410 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1411 NAU8825_ENABLE_ADC, 0);
1412
1413 /* Close clock for jack type detection at manual mode */
1414 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1415}
1416
1417/* Enable audo mode interruptions with internal clock. */
1418static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1419{
1420 struct regmap *regmap = nau8825->regmap;
1421
1422 /* Enable headset jack type detection complete interruption and
1423 * jack ejection interruption.
1424 */
1425 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1426 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1427
1428 /* Enable internal VCO needed for interruptions */
1429 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1430
1431 /* Enable ADC needed for interruptions */
1432 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1433 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1434
1435 /* Chip needs one FSCLK cycle in order to generate interruptions,
1436 * as we cannot guarantee one will be provided by the system. Turning
1437 * master mode on then off enables us to generate that FSCLK cycle
1438 * with a minimum of contention on the clock bus.
1439 */
1440 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1441 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1442 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1443 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1444
1445 /* Not bypass de-bounce circuit */
1446 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1447 NAU8825_JACK_DET_DB_BYPASS, 0);
1448
1449 /* Unmask all interruptions */
1450 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1451
1452 /* Restart the jack detection process at auto mode */
1453 nau8825_restart_jack_detection(regmap);
34ca27f3
AP		 1454}
1455
1456static int nau8825_button_decode(int value)
1457{
1458 int buttons = 0;
1459
1460 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1461 if (value & BIT(0))
1462 buttons |= SND_JACK_BTN_0;
1463 if (value & BIT(1))
1464 buttons |= SND_JACK_BTN_1;
1465 if (value & BIT(2))
1466 buttons |= SND_JACK_BTN_2;
1467 if (value & BIT(3))
1468 buttons |= SND_JACK_BTN_3;
1469 if (value & BIT(4))
1470 buttons |= SND_JACK_BTN_4;
1471 if (value & BIT(5))
1472 buttons |= SND_JACK_BTN_5;
1473
1474 return buttons;
1475}
1476
1477static int nau8825_jack_insert(struct nau8825 *nau8825)
1478{
1479 struct regmap *regmap = nau8825->regmap;
1480 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1481 int jack_status_reg, mic_detected;
1482 int type = 0;
1483
1484 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1485 mic_detected = (jack_status_reg >> 10) & 3;
b50455fa
JH		 1486 /* The JKSLV and JKR2 all detected in high impedance headset */
1487 if (mic_detected == 0x3)
1488 nau8825->high_imped = true;
1489 else
1490 nau8825->high_imped = false;
34ca27f3
AP		 1491
1492 switch (mic_detected) {
1493 case 0:
1494 /* no mic */
1495 type = SND_JACK_HEADPHONE;
1496 break;
1497 case 1:
1498 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1499 type = SND_JACK_HEADSET;
1500
1501 /* Unground MICGND1 */
1502 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1503 1 << 2);
1504 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1505 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1506 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1507 NAU8825_MICBIAS_JKR2);
1508 /* Attach SARADC to MICGND1 */
1509 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1510 NAU8825_SAR_INPUT_MASK,
1511 NAU8825_SAR_INPUT_JKR2);
1512
1513 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1514 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1515 snd_soc_dapm_sync(dapm);
1516 break;
1517 case 2:
1518 case 3:
1519 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1520 type = SND_JACK_HEADSET;
1521
1522 /* Unground MICGND2 */
1523 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1524 2 << 2);
1525 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1526 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1527 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1528 NAU8825_MICBIAS_JKSLV);
1529 /* Attach SARADC to MICGND2 */
1530 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1531 NAU8825_SAR_INPUT_MASK,
1532 NAU8825_SAR_INPUT_JKSLV);
1533
1534 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1535 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1536 snd_soc_dapm_sync(dapm);
1537 break;
1538 }
1539
45d5eb3a
JH		 1540 /* Leaving HPOL/R grounded after jack insert by default. They will be
1541 * ungrounded as part of the widget power up sequence at the beginning
1542 * of playback to reduce pop.
1543 */
34ca27f3
AP		 1544 return type;
1545}
1546
1547#define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1548 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1549
1550static irqreturn_t nau8825_interrupt(int irq, void *data)
1551{
1552 struct nau8825 *nau8825 = (struct nau8825 *)data;
1553 struct regmap *regmap = nau8825->regmap;
1554 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1555
e6cee900
BZ		 1556 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1557 dev_err(nau8825->dev, "failed to read irq status\n");
1558 return IRQ_NONE;
1559 }
34ca27f3
AP		 1560
1561 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1562 NAU8825_JACK_EJECTION_DETECTED) {
1563
1564 nau8825_eject_jack(nau8825);
1565 event_mask |= SND_JACK_HEADSET;
1566 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1567 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1568 int key_status;
1569
1570 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1571 &key_status);
1572
1573 /* upper 8 bits of the register are for short pressed keys,
1574 * lower 8 bits - for long pressed buttons
1575 */
1576 nau8825->button_pressed = nau8825_button_decode(
1577 key_status >> 8);
1578
1579 event |= nau8825->button_pressed;
1580 event_mask |= NAU8825_BUTTONS;
1581 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1582 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1583 event_mask = NAU8825_BUTTONS;
1584 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1585 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1586 if (nau8825_is_jack_inserted(regmap)) {
1587 event |= nau8825_jack_insert(nau8825);
b50455fa
JH		 1588 if (!nau8825->high_imped) {
1589 /* Apply the cross talk suppression in the
1590 * headset without high impedance.
1591 */
1592 if (!nau8825->xtalk_protect) {
1593 /* Raise protection for cross talk de-
1594 * tection if no protection before.
1595 * The driver has to cancel the pro-
1596 * cess and restore changes if process
1597 * is ongoing when ejection.
1598 */
1599 nau8825->xtalk_protect = true;
1600 nau8825_sema_acquire(nau8825, 0);
1601 }
1602 /* Startup cross talk detection process */
1603 nau8825->xtalk_state = NAU8825_XTALK_PREPARE;
1604 schedule_work(&nau8825->xtalk_work);
1605 } else {
1606 /* The cross talk suppression shouldn't apply
1607 * in the headset with high impedance. Thus,
1608 * relieve the protection raised before.
1609 */
1610 if (nau8825->xtalk_protect) {
1611 nau8825_sema_release(nau8825);
1612 nau8825->xtalk_protect = false;
1613 }
1614 }
34ca27f3
AP		 1615 } else {
1616 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
1617 nau8825_eject_jack(nau8825);
1618 }
1619
1620 event_mask |= SND_JACK_HEADSET;
1621 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
b50455fa
JH		 1622 /* Record the interruption report event for driver to report
1623 * the event later. The jack report will delay until cross
1624 * talk detection process is done.
1625 */
1626 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
1627 nau8825->xtalk_event = event;
1628 nau8825->xtalk_event_mask = event_mask;
1629 }
1630 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
1631 schedule_work(&nau8825->xtalk_work);
1632 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
2ec30f60
JH		 1633 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
1634 NAU8825_JACK_INSERTION_DETECTED) {
1635 /* One more step to check GPIO status directly. Thus, the
1636 * driver can confirm the real insertion interruption because
1637 * the intrruption at manual mode has bypassed debounce
1638 * circuit which can get rid of unstable status.
1639 */
1640 if (nau8825_is_jack_inserted(regmap)) {
1641 /* Turn off insertion interruption at manual mode */
1642 regmap_update_bits(regmap,
1643 NAU8825_REG_INTERRUPT_DIS_CTRL,
1644 NAU8825_IRQ_INSERT_DIS,
1645 NAU8825_IRQ_INSERT_DIS);
1646 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1647 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
1648 /* Enable interruption for jack type detection at audo
1649 * mode which can detect microphone and jack type.
1650 */
1651 nau8825_setup_auto_irq(nau8825);
1652 }
34ca27f3
AP		 1653 }
1654
1655 if (!clear_irq)
1656 clear_irq = active_irq;
1657 /* clears the rightmost interruption */
1658 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1659
b50455fa
JH		 1660 /* Delay jack report until cross talk detection is done. It can avoid
1661 * application to do playback preparation when cross talk detection
1662 * process is still working. Otherwise, the resource like clock and
1663 * power will be issued by them at the same time and conflict happens.
1664 */
1665 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
34ca27f3
AP		 1666 snd_soc_jack_report(nau8825->jack, event, event_mask);
1667
1668 return IRQ_HANDLED;
1669}
1670
1671static void nau8825_setup_buttons(struct nau8825 *nau8825)
1672{
1673 struct regmap *regmap = nau8825->regmap;
1674
1675 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1676 NAU8825_SAR_TRACKING_GAIN_MASK,
1677 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1678 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1679 NAU8825_SAR_COMPARE_TIME_MASK,
1680 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
1681 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1682 NAU8825_SAR_SAMPLING_TIME_MASK,
1683 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
1684
1685 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1686 NAU8825_KEYDET_LEVELS_NR_MASK,
1687 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
1688 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1689 NAU8825_KEYDET_HYSTERESIS_MASK,
1690 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
1691 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1692 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
1693 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
1694
1695 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
1696 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
1697 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
1698 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
1699 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
1700 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
1701 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
1702 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
1703
1704 /* Enable short press and release interruptions */
1705 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1706 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
1707 0);
1708}
1709
1710static void nau8825_init_regs(struct nau8825 *nau8825)
1711{
1712 struct regmap *regmap = nau8825->regmap;
1713
45d5eb3a
JH		 1714 /* Latch IIC LSB value */
1715 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
34ca27f3
AP		 1716 /* Enable Bias/Vmid */
1717 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1718 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
1719 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
1720 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
1721
1722 /* VMID Tieoff */
1723 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
1724 NAU8825_BIAS_VMID_SEL_MASK,
1725 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
1726 /* Disable Boost Driver, Automatic Short circuit protection enable */
1727 regmap_update_bits(regmap, NAU8825_REG_BOOST,
45d5eb3a
JH		 1728 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1729 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
1730 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1731 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
34ca27f3
AP		 1732
1733 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1734 NAU8825_JKDET_OUTPUT_EN,
1735 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
1736 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1737 NAU8825_JKDET_PULL_EN,
1738 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
1739 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1740 NAU8825_JKDET_PULL_UP,
1741 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
1742 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1743 NAU8825_JACK_POLARITY,
1744 /* jkdet_polarity - 1 is for active-low */
1745 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
1746
1747 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1748 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
1749 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
1750 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1751 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
1752 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
1753
1754 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1755 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
1756
1757 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1758 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1759
1760 if (nau8825->sar_threshold_num)
1761 nau8825_setup_buttons(nau8825);
1762
1763 /* Default oversampling/decimations settings are unusable
1764 * (audible hiss). Set it to something better.
1765 */
1766 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
1767 NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_128);
1768 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1769 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_128);
45d5eb3a
JH		 1770 /* Disable DACR/L power */
1771 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
1772 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1773 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1774 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1775 * signal to avoid any glitches due to power up transients in both
1776 * the analog and digital DAC circuit.
1777 */
1778 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1779 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1780 /* CICCLP off */
1781 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1782 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
1783
1784 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1785 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
1786 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1787 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
1788 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1789 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
1790 /* Class G timer 64ms */
1791 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
1792 NAU8825_CLASSG_TIMER_MASK,
1793 0x20 << NAU8825_CLASSG_TIMER_SFT);
1794 /* DAC clock delay 2ns, VREF */
1795 regmap_update_bits(regmap, NAU8825_REG_RDAC,
1796 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
1797 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
1798 (0x3 << NAU8825_RDAC_VREF_SFT));
3f039169
JH		 1799 /* Config L/R channel */
1800 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
1801 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
1802 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
1803 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
34ca27f3
AP		 1804}
1805
1806static const struct regmap_config nau8825_regmap_config = {
2ec30f60
JH		 1807 .val_bits = NAU8825_REG_DATA_LEN,
1808 .reg_bits = NAU8825_REG_ADDR_LEN,
34ca27f3
AP		 1809
1810 .max_register = NAU8825_REG_MAX,
1811 .readable_reg = nau8825_readable_reg,
1812 .writeable_reg = nau8825_writeable_reg,
1813 .volatile_reg = nau8825_volatile_reg,
1814
1815 .cache_type = REGCACHE_RBTREE,
1816 .reg_defaults = nau8825_reg_defaults,
1817 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
1818};
1819
1820static int nau8825_codec_probe(struct snd_soc_codec *codec)
1821{
1822 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1823 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1824
1825 nau8825->dapm = dapm;
1826
34ca27f3
AP		 1827 return 0;
1828}
1829
b50455fa
JH		 1830static int nau8825_codec_remove(struct snd_soc_codec *codec)
1831{
1832 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1833
1834 /* Cancel and reset cross tak suppresstion detection funciton */
1835 nau8825_xtalk_cancel(nau8825);
1836
1837 return 0;
1838}
1839
c86ba612
BZ		 1840/**
1841 * nau8825_calc_fll_param - Calculate FLL parameters.
1842 * @fll_in: external clock provided to codec.
1843 * @fs: sampling rate.
1844 * @fll_param: Pointer to structure of FLL parameters.
1845 *
1846 * Calculate FLL parameters to configure codec.
1847 *
1848 * Returns 0 for success or negative error code.
1849 */
1850static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
1851 struct nau8825_fll *fll_param)
1852{
407c71b6
JH		 1853 u64 fvco, fvco_max;
1854 unsigned int fref, i, fvco_sel;
c86ba612
BZ		 1855
1856 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1857 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1858 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
1859 */
1860 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1861 fref = fll_in / fll_pre_scalar[i].param;
1862 if (fref <= NAU_FREF_MAX)
1863 break;
1864 }
1865 if (i == ARRAY_SIZE(fll_pre_scalar))
1866 return -EINVAL;
1867 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1868
1869 /* Choose the FLL ratio based on FREF */
1870 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1871 if (fref >= fll_ratio[i].param)
1872 break;
1873 }
1874 if (i == ARRAY_SIZE(fll_ratio))
1875 return -EINVAL;
1876 fll_param->ratio = fll_ratio[i].val;
1877
1878 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
407c71b6 1879 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
c86ba612
BZ		 1880 * guaranteed across the full range of operation.
1881 * FDCO = freq_out * 2 * mclk_src_scaling
1882 */
407c71b6
JH		 1883 fvco_max = 0;
1884 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
c86ba612
BZ		 1885 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1886 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
407c71b6
JH		 1887 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1888 fvco_max < fvco) {
1889 fvco_max = fvco;
1890 fvco_sel = i;
1891 }
c86ba612 1892 }
407c71b6 1893 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
c86ba612 1894 return -EINVAL;
407c71b6 1895 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
c86ba612
BZ		 1896
1897 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1898 * input based on FDCO, FREF and FLL ratio.
1899 */
1900 fvco = div_u64(fvco << 16, fref * fll_param->ratio);
1901 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1902 fll_param->fll_frac = fvco & 0xFFFF;
1903 return 0;
1904}
1905
1906static void nau8825_fll_apply(struct nau8825 *nau8825,
1907 struct nau8825_fll *fll_param)
1908{
1909 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
407c71b6
JH		 1910 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
1911 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
c86ba612
BZ		 1912 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
1913 NAU8825_FLL_RATIO_MASK, fll_param->ratio);
1914 /* FLL 16-bit fractional input */
1915 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
1916 /* FLL 10-bit integer input */
1917 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
1918 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
1919 /* FLL pre-scaler */
1920 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
1921 NAU8825_FLL_REF_DIV_MASK, fll_param->clk_ref_div);
1922 /* select divided VCO input */
1923 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
407c71b6
JH		 1924 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
1925 /* Disable free-running mode */
1926 regmap_update_bits(nau8825->regmap,
1927 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
1928 if (fll_param->fll_frac) {
1929 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1930 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1931 NAU8825_FLL_FTR_SW_MASK,
1932 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1933 NAU8825_FLL_FTR_SW_FILTER);
1934 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
1935 NAU8825_SDM_EN, NAU8825_SDM_EN);
1936 } else {
1937 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1938 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1939 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
1940 regmap_update_bits(nau8825->regmap,
1941 NAU8825_REG_FLL6, NAU8825_SDM_EN, 0);
1942 }
c86ba612
BZ		 1943}
1944
1945/* freq_out must be 256*Fs in order to achieve the best performance */
1946static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
1947 unsigned int freq_in, unsigned int freq_out)
1948{
1949 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1950 struct nau8825_fll fll_param;
1951 int ret, fs;
1952
1953 fs = freq_out / 256;
1954 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
1955 if (ret < 0) {
1956 dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
1957 return ret;
1958 }
1959 dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1960 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1961 fll_param.fll_int, fll_param.clk_ref_div);
1962
1963 nau8825_fll_apply(nau8825, &fll_param);
1964 mdelay(2);
1965 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1966 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
1967 return 0;
1968}
1969
70543c30
JH		 1970static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
1971{
1972 int ret = 0;
1973
1974 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
1975 if (IS_ERR(nau8825->mclk)) {
1976 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
1977 return 0;
1978 }
1979
1980 if (!nau8825->mclk_freq) {
1981 ret = clk_prepare_enable(nau8825->mclk);
1982 if (ret) {
1983 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
1984 return ret;
1985 }
1986 }
1987
1988 if (nau8825->mclk_freq != freq) {
1989 freq = clk_round_rate(nau8825->mclk, freq);
1990 ret = clk_set_rate(nau8825->mclk, freq);
1991 if (ret) {
1992 dev_err(nau8825->dev, "Unable to set mclk rate\n");
1993 return ret;
1994 }
1995 nau8825->mclk_freq = freq;
1996 }
1997
1998 return 0;
1999}
2000
2ec30f60
JH		 2001static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2002{
2003 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2004 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2005 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2006 NAU8825_DCO_EN, 0);
2007}
2008
34ca27f3
AP		 2009static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2010 unsigned int freq)
2011{
2012 struct regmap *regmap = nau8825->regmap;
2013 int ret;
2014
2015 switch (clk_id) {
2ec30f60
JH		 2016 case NAU8825_CLK_DIS:
2017 /* Clock provided externally and disable internal VCO clock */
2018 nau8825_configure_mclk_as_sysclk(regmap);
2019 if (nau8825->mclk_freq) {
2020 clk_disable_unprepare(nau8825->mclk);
2021 nau8825->mclk_freq = 0;
2022 }
2023
2024 break;
34ca27f3 2025 case NAU8825_CLK_MCLK:
b50455fa
JH		 2026 /* Acquire the semaphone to synchronize the playback and
2027 * interrupt handler. In order to avoid the playback inter-
2028 * fered by cross talk process, the driver make the playback
2029 * preparation halted until cross talk process finish.
2030 */
2031 nau8825_sema_acquire(nau8825, 2 * HZ);
2ec30f60 2032 nau8825_configure_mclk_as_sysclk(regmap);
3a561035
JH		 2033 /* MCLK not changed by clock tree */
2034 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2035 NAU8825_CLK_MCLK_SRC_MASK, 0);
b50455fa
JH		 2036 /* Release the semaphone. */
2037 nau8825_sema_release(nau8825);
2038
70543c30
JH		 2039 ret = nau8825_mclk_prepare(nau8825, freq);
2040 if (ret)
2041 return ret;
34ca27f3
AP		 2042
2043 break;
2044 case NAU8825_CLK_INTERNAL:
2ec30f60
JH		 2045 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2046 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2047 NAU8825_DCO_EN, NAU8825_DCO_EN);
2048 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2049 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2050 /* Decrease the VCO frequency for power saving */
2051 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2052 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2053 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2054 NAU8825_FLL_RATIO_MASK, 0x10);
2055 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2056 NAU8825_SDM_EN, NAU8825_SDM_EN);
2057 } else {
2058 /* The clock turns off intentionally for power saving
2059 * when no headset connected.
2060 */
2061 nau8825_configure_mclk_as_sysclk(regmap);
2062 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2063 }
70543c30
JH		 2064 if (nau8825->mclk_freq) {
2065 clk_disable_unprepare(nau8825->mclk);
2066 nau8825->mclk_freq = 0;
2067 }
2068
2069 break;
2070 case NAU8825_CLK_FLL_MCLK:
b50455fa
JH		 2071 /* Acquire the semaphone to synchronize the playback and
2072 * interrupt handler. In order to avoid the playback inter-
2073 * fered by cross talk process, the driver make the playback
2074 * preparation halted until cross talk process finish.
2075 */
2076 nau8825_sema_acquire(nau8825, 2 * HZ);
70543c30
JH		 2077 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2078 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK);
b50455fa
JH		 2079 /* Release the semaphone. */
2080 nau8825_sema_release(nau8825);
2081
70543c30
JH		 2082 ret = nau8825_mclk_prepare(nau8825, freq);
2083 if (ret)
2084 return ret;
2085
2086 break;
2087 case NAU8825_CLK_FLL_BLK:
b50455fa
JH		 2088 /* Acquire the semaphone to synchronize the playback and
2089 * interrupt handler. In order to avoid the playback inter-
2090 * fered by cross talk process, the driver make the playback
2091 * preparation halted until cross talk process finish.
2092 */
2093 nau8825_sema_acquire(nau8825, 2 * HZ);
70543c30
JH		 2094 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2095 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK);
b50455fa
JH		 2096 /* Release the semaphone. */
2097 nau8825_sema_release(nau8825);
2098
70543c30
JH		 2099 if (nau8825->mclk_freq) {
2100 clk_disable_unprepare(nau8825->mclk);
2101 nau8825->mclk_freq = 0;
2102 }
34ca27f3 2103
70543c30
JH		 2104 break;
2105 case NAU8825_CLK_FLL_FS:
b50455fa
JH		 2106 /* Acquire the semaphone to synchronize the playback and
2107 * interrupt handler. In order to avoid the playback inter-
2108 * fered by cross talk process, the driver make the playback
2109 * preparation halted until cross talk process finish.
2110 */
2111 nau8825_sema_acquire(nau8825, 2 * HZ);
70543c30
JH		 2112 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2113 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS);
b50455fa
JH		 2114 /* Release the semaphone. */
2115 nau8825_sema_release(nau8825);
2116
34ca27f3
AP		 2117 if (nau8825->mclk_freq) {
2118 clk_disable_unprepare(nau8825->mclk);
2119 nau8825->mclk_freq = 0;
2120 }
2121
2122 break;
2123 default:
2124 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2125 return -EINVAL;
2126 }
2127
2128 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2129 clk_id);
2130 return 0;
2131}
2132
2133static int nau8825_set_sysclk(struct snd_soc_codec *codec, int clk_id,
2134 int source, unsigned int freq, int dir)
2135{
2136 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2137
2138 return nau8825_configure_sysclk(nau8825, clk_id, freq);
2139}
2140
2ec30f60
JH		 2141static int nau8825_resume_setup(struct nau8825 *nau8825)
2142{
2143 struct regmap *regmap = nau8825->regmap;
2144
2145 /* Close clock when jack type detection at manual mode */
2146 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2147
2148 /* Clear all interruption status */
2149 nau8825_int_status_clear_all(regmap);
2150
2151 /* Enable both insertion and ejection interruptions, and then
2152 * bypass de-bounce circuit.
2153 */
2154 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2155 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2156 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2157 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2158 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2159 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2160 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2161 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2162
2163 return 0;
2164}
2165
34ca27f3
AP		 2166static int nau8825_set_bias_level(struct snd_soc_codec *codec,
2167 enum snd_soc_bias_level level)
2168{
2169 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2170 int ret;
2171
2172 switch (level) {
2173 case SND_SOC_BIAS_ON:
2174 break;
2175
2176 case SND_SOC_BIAS_PREPARE:
2177 break;
2178
2179 case SND_SOC_BIAS_STANDBY:
2180 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
2181 if (nau8825->mclk_freq) {
2182 ret = clk_prepare_enable(nau8825->mclk);
2183 if (ret) {
2184 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2185 return ret;
2186 }
2187 }
2ec30f60
JH		 2188 /* Setup codec configuration after resume */
2189 nau8825_resume_setup(nau8825);
34ca27f3 2190 }
34ca27f3
AP		 2191 break;
2192
2193 case SND_SOC_BIAS_OFF:
b50455fa
JH		 2194 /* Cancel and reset cross talk detection funciton */
2195 nau8825_xtalk_cancel(nau8825);
2ec30f60
JH		 2196 /* Turn off all interruptions before system shutdown. Keep the
2197 * interruption quiet before resume setup completes.
2198 */
2199 regmap_write(nau8825->regmap,
2200 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2201 /* Disable ADC needed for interruptions at audo mode */
2202 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2203 NAU8825_ENABLE_ADC, 0);
34ca27f3
AP		 2204 if (nau8825->mclk_freq)
2205 clk_disable_unprepare(nau8825->mclk);
34ca27f3
AP		 2206 break;
2207 }
2208 return 0;
2209}
2210
4983d325 2211static int __maybe_unused nau8825_suspend(struct snd_soc_codec *codec)
e6cee900
BZ		 2212{
2213 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2214
2215 disable_irq(nau8825->irq);
2ec30f60 2216 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
e6cee900
BZ		 2217 regcache_cache_only(nau8825->regmap, true);
2218 regcache_mark_dirty(nau8825->regmap);
2219
2220 return 0;
2221}
2222
4983d325 2223static int __maybe_unused nau8825_resume(struct snd_soc_codec *codec)
e6cee900
BZ		 2224{
2225 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2226
e6cee900
BZ		 2227 regcache_cache_only(nau8825->regmap, false);
2228 regcache_sync(nau8825->regmap);
ca6ac305
JH		 2229 nau8825->xtalk_protect = true;
2230 nau8825_sema_acquire(nau8825, 0);
e6cee900
BZ		 2231 enable_irq(nau8825->irq);
2232
e6cee900
BZ		 2233 return 0;
2234}
e6cee900 2235
34ca27f3
AP		 2236static struct snd_soc_codec_driver nau8825_codec_driver = {
2237 .probe = nau8825_codec_probe,
b50455fa 2238 .remove = nau8825_codec_remove,
34ca27f3 2239 .set_sysclk = nau8825_set_sysclk,
c86ba612 2240 .set_pll = nau8825_set_pll,
34ca27f3
AP		 2241 .set_bias_level = nau8825_set_bias_level,
2242 .suspend_bias_off = true,
e6cee900
BZ		 2243 .suspend = nau8825_suspend,
2244 .resume = nau8825_resume,
34ca27f3
AP		 2245
2246 .controls = nau8825_controls,
2247 .num_controls = ARRAY_SIZE(nau8825_controls),
2248 .dapm_widgets = nau8825_dapm_widgets,
2249 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
2250 .dapm_routes = nau8825_dapm_routes,
2251 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
2252};
2253
2254static void nau8825_reset_chip(struct regmap *regmap)
2255{
2256 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2257 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2258}
2259
218d2ce2
BZ		 2260static void nau8825_print_device_properties(struct nau8825 *nau8825)
2261{
2262 int i;
2263 struct device *dev = nau8825->dev;
2264
2265 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
2266 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
2267 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
2268 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
2269 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
2270 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
2271
2272 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
2273 for (i = 0; i < nau8825->sar_threshold_num; i++)
2274 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2275 nau8825->sar_threshold[i]);
2276
2277 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
2278 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
2279 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
2280 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
2281 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
2282 dev_dbg(dev, "jack-insert-debounce: %d\n",
2283 nau8825->jack_insert_debounce);
2284 dev_dbg(dev, "jack-eject-debounce: %d\n",
2285 nau8825->jack_eject_debounce);
2286}
2287
34ca27f3
AP		 2288static int nau8825_read_device_properties(struct device *dev,
2289 struct nau8825 *nau8825) {
2290
2291 nau8825->jkdet_enable = device_property_read_bool(dev,
2292 "nuvoton,jkdet-enable");
2293 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2294 "nuvoton,jkdet-pull-enable");
2295 nau8825->jkdet_pull_up = device_property_read_bool(dev,
2296 "nuvoton,jkdet-pull-up");
2297 device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2298 &nau8825->jkdet_polarity);
2299 device_property_read_u32(dev, "nuvoton,micbias-voltage",
2300 &nau8825->micbias_voltage);
2301 device_property_read_u32(dev, "nuvoton,vref-impedance",
2302 &nau8825->vref_impedance);
2303 device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2304 &nau8825->sar_threshold_num);
2305 device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2306 nau8825->sar_threshold, nau8825->sar_threshold_num);
2307 device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2308 &nau8825->sar_hysteresis);
2309 device_property_read_u32(dev, "nuvoton,sar-voltage",
2310 &nau8825->sar_voltage);
2311 device_property_read_u32(dev, "nuvoton,sar-compare-time",
2312 &nau8825->sar_compare_time);
2313 device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2314 &nau8825->sar_sampling_time);
2315 device_property_read_u32(dev, "nuvoton,short-key-debounce",
2316 &nau8825->key_debounce);
2317 device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2318 &nau8825->jack_insert_debounce);
2319 device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2320 &nau8825->jack_eject_debounce);
2321
2322 nau8825->mclk = devm_clk_get(dev, "mclk");
2323 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
2324 return -EPROBE_DEFER;
2325 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
2326 /* The MCLK is managed externally or not used at all */
2327 nau8825->mclk = NULL;
2328 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2329 } else if (IS_ERR(nau8825->mclk)) {
2330 return -EINVAL;
2331 }
2332
2333 return 0;
2334}
2335
2336static int nau8825_setup_irq(struct nau8825 *nau8825)
2337{
34ca27f3
AP		 2338 int ret;
2339
34ca27f3
AP		 2340 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2341 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2342 "nau8825", nau8825);
2343
2344 if (ret) {
2345 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2346 nau8825->irq, ret);
2347 return ret;
2348 }
2349
2350 return 0;
2351}
2352
2353static int nau8825_i2c_probe(struct i2c_client *i2c,
2354 const struct i2c_device_id *id)
2355{
2356 struct device *dev = &i2c->dev;
2357 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2358 int ret, value;
2359
2360 if (!nau8825) {
2361 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2362 if (!nau8825)
2363 return -ENOMEM;
2364 ret = nau8825_read_device_properties(dev, nau8825);
2365 if (ret)
2366 return ret;
2367 }
2368
2369 i2c_set_clientdata(i2c, nau8825);
2370
2371 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2372 if (IS_ERR(nau8825->regmap))
2373 return PTR_ERR(nau8825->regmap);
2374 nau8825->dev = dev;
2375 nau8825->irq = i2c->irq;
b50455fa
JH		 2376 /* Initiate parameters, semaphone and work queue which are needed in
2377 * cross talk suppression measurment function.
2378 */
2379 nau8825->xtalk_state = NAU8825_XTALK_DONE;
2380 nau8825->xtalk_protect = false;
2381 sema_init(&nau8825->xtalk_sem, 1);
2382 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
34ca27f3 2383
218d2ce2
BZ		 2384 nau8825_print_device_properties(nau8825);
2385
34ca27f3
AP		 2386 nau8825_reset_chip(nau8825->regmap);
2387 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2388 if (ret < 0) {
2389 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2390 ret);
2391 return ret;
2392 }
2393 if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2394 NAU8825_SOFTWARE_ID_NAU8825) {
2395 dev_err(dev, "Not a NAU8825 chip\n");
2396 return -ENODEV;
2397 }
2398
2399 nau8825_init_regs(nau8825);
2400
2401 if (i2c->irq)
2402 nau8825_setup_irq(nau8825);
2403
2404 return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver,
2405 &nau8825_dai, 1);
2406}
2407
2408static int nau8825_i2c_remove(struct i2c_client *client)
2409{
2410 snd_soc_unregister_codec(&client->dev);
2411 return 0;
2412}
2413
2414static const struct i2c_device_id nau8825_i2c_ids[] = {
2415 { "nau8825", 0 },
2416 { }
2417};
ffd72505 2418MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
34ca27f3
AP		 2419
2420#ifdef CONFIG_OF
2421static const struct of_device_id nau8825_of_ids[] = {
2422 { .compatible = "nuvoton,nau8825", },
2423 {}
2424};
2425MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2426#endif
2427
b3681308
FY		 2428#ifdef CONFIG_ACPI
2429static const struct acpi_device_id nau8825_acpi_match[] = {
2430 { "10508825", 0 },
2431 {},
2432};
2433MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2434#endif
2435
34ca27f3
AP		 2436static struct i2c_driver nau8825_driver = {
2437 .driver = {
2438 .name = "nau8825",
34ca27f3 2439 .of_match_table = of_match_ptr(nau8825_of_ids),
b3681308 2440 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
34ca27f3
AP		 2441 },
2442 .probe = nau8825_i2c_probe,
2443 .remove = nau8825_i2c_remove,
2444 .id_table = nau8825_i2c_ids,
2445};
2446module_i2c_driver(nau8825_driver);
2447
2448MODULE_DESCRIPTION("ASoC nau8825 driver");
2449MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2450MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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