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1 | /* |
2 | * PCM3168A codec driver | |
3 | * | |
4 | * Copyright (C) 2015 Imagination Technologies Ltd. | |
5 | * | |
6 | * Author: Damien Horsley <Damien.Horsley@imgtec.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/pm_runtime.h> | |
17 | #include <linux/regulator/consumer.h> | |
18 | ||
19 | #include <sound/pcm_params.h> | |
20 | #include <sound/soc.h> | |
21 | #include <sound/tlv.h> | |
22 | ||
23 | #include "pcm3168a.h" | |
24 | ||
25 | #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ | |
26 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
27 | SNDRV_PCM_FMTBIT_S24_LE | \ | |
28 | SNDRV_PCM_FMTBIT_S32_LE) | |
29 | ||
30 | #define PCM3168A_FMT_I2S 0x0 | |
31 | #define PCM3168A_FMT_LEFT_J 0x1 | |
32 | #define PCM3168A_FMT_RIGHT_J 0x2 | |
33 | #define PCM3168A_FMT_RIGHT_J_16 0x3 | |
34 | #define PCM3168A_FMT_DSP_A 0x4 | |
35 | #define PCM3168A_FMT_DSP_B 0x5 | |
36 | #define PCM3168A_FMT_DSP_MASK 0x4 | |
37 | ||
38 | #define PCM3168A_NUM_SUPPLIES 6 | |
39 | static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = { | |
40 | "VDD1", | |
41 | "VDD2", | |
42 | "VCCAD1", | |
43 | "VCCAD2", | |
44 | "VCCDA1", | |
45 | "VCCDA2" | |
46 | }; | |
47 | ||
48 | struct pcm3168a_priv { | |
49 | struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES]; | |
50 | struct regmap *regmap; | |
51 | struct clk *scki; | |
52 | bool adc_master_mode; | |
53 | bool dac_master_mode; | |
54 | unsigned long sysclk; | |
55 | unsigned int adc_fmt; | |
56 | unsigned int dac_fmt; | |
57 | }; | |
58 | ||
59 | static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" }; | |
60 | ||
61 | static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT, | |
62 | PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off); | |
63 | static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT, | |
64 | PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off); | |
65 | static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT, | |
66 | PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off); | |
67 | static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT, | |
68 | PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off); | |
69 | ||
70 | static const char *const pcm3168a_volume_type[] = { | |
71 | "Individual", "Master + Individual" }; | |
72 | ||
73 | static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF, | |
74 | PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type); | |
75 | ||
76 | static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" }; | |
77 | ||
78 | static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF, | |
79 | PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult); | |
80 | ||
81 | static const char *const pcm3168a_demp[] = { | |
82 | "Disabled", "48khz", "44.1khz", "32khz" }; | |
83 | ||
84 | static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF, | |
85 | PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp); | |
86 | ||
87 | static const char *const pcm3168a_zf_func[] = { | |
88 | "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND", | |
89 | "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" }; | |
90 | ||
91 | static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF, | |
92 | PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func); | |
93 | ||
94 | static const char *const pcm3168a_pol[] = { "Active High", "Active Low" }; | |
95 | ||
96 | static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF, | |
97 | PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol); | |
98 | ||
99 | static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" }; | |
100 | ||
101 | static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD, | |
102 | 0, 1, pcm3168a_con); | |
103 | static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD, | |
104 | 2, 3, pcm3168a_con); | |
105 | static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD, | |
106 | 4, 5, pcm3168a_con); | |
107 | ||
108 | static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF, | |
109 | PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type); | |
110 | ||
111 | static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF, | |
112 | PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult); | |
113 | ||
114 | static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF, | |
115 | PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol); | |
116 | ||
117 | /* -100db to 0db, register values 0-54 cause mute */ | |
118 | static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1); | |
119 | ||
120 | /* -100db to 20db, register values 0-14 cause mute */ | |
121 | static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1); | |
122 | ||
123 | static const struct snd_kcontrol_new pcm3168a_snd_controls[] = { | |
124 | SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT, | |
125 | PCM3168A_DAC_PSMDA_SHIFT, 1, 1), | |
126 | SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off), | |
127 | SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off), | |
128 | SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off), | |
129 | SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off), | |
130 | SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0), | |
131 | SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0), | |
132 | SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0), | |
133 | SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0), | |
134 | SOC_DOUBLE_STS("DAC1 Zero Flag", PCM3168A_DAC_ZERO, 0, 1, 1, 0), | |
135 | SOC_DOUBLE_STS("DAC2 Zero Flag", PCM3168A_DAC_ZERO, 2, 3, 1, 0), | |
136 | SOC_DOUBLE_STS("DAC3 Zero Flag", PCM3168A_DAC_ZERO, 4, 5, 1, 0), | |
137 | SOC_DOUBLE_STS("DAC4 Zero Flag", PCM3168A_DAC_ZERO, 6, 7, 1, 0), | |
138 | SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type), | |
139 | SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult), | |
140 | SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp), | |
141 | SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func), | |
142 | SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol), | |
143 | SOC_SINGLE_RANGE_TLV("Master Playback Volume", | |
144 | PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0, | |
145 | pcm3168a_dac_tlv), | |
146 | SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume", | |
147 | PCM3168A_DAC_VOL_CHAN_START, | |
148 | PCM3168A_DAC_VOL_CHAN_START + 1, | |
149 | 0, 54, 255, 0, pcm3168a_dac_tlv), | |
150 | SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume", | |
151 | PCM3168A_DAC_VOL_CHAN_START + 2, | |
152 | PCM3168A_DAC_VOL_CHAN_START + 3, | |
153 | 0, 54, 255, 0, pcm3168a_dac_tlv), | |
154 | SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume", | |
155 | PCM3168A_DAC_VOL_CHAN_START + 4, | |
156 | PCM3168A_DAC_VOL_CHAN_START + 5, | |
157 | 0, 54, 255, 0, pcm3168a_dac_tlv), | |
158 | SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume", | |
159 | PCM3168A_DAC_VOL_CHAN_START + 6, | |
160 | PCM3168A_DAC_VOL_CHAN_START + 7, | |
161 | 0, 54, 255, 0, pcm3168a_dac_tlv), | |
162 | SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, | |
163 | PCM3168A_ADC_BYP_SHIFT, 1, 1), | |
164 | SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, | |
165 | PCM3168A_ADC_BYP_SHIFT + 1, 1, 1), | |
166 | SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB, | |
167 | PCM3168A_ADC_BYP_SHIFT + 2, 1, 1), | |
168 | SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con), | |
169 | SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con), | |
170 | SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con), | |
171 | SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0), | |
172 | SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0), | |
173 | SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0), | |
174 | SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0), | |
175 | SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0), | |
176 | SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0), | |
177 | SOC_DOUBLE_STS("ADC1 Overflow Flag", PCM3168A_ADC_OV, 0, 1, 1, 0), | |
178 | SOC_DOUBLE_STS("ADC2 Overflow Flag", PCM3168A_ADC_OV, 2, 3, 1, 0), | |
179 | SOC_DOUBLE_STS("ADC3 Overflow Flag", PCM3168A_ADC_OV, 4, 5, 1, 0), | |
180 | SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type), | |
181 | SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult), | |
182 | SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol), | |
183 | SOC_SINGLE_RANGE_TLV("Master Capture Volume", | |
184 | PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0, | |
185 | pcm3168a_adc_tlv), | |
186 | SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume", | |
187 | PCM3168A_ADC_VOL_CHAN_START, | |
188 | PCM3168A_ADC_VOL_CHAN_START + 1, | |
189 | 0, 14, 255, 0, pcm3168a_adc_tlv), | |
190 | SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume", | |
191 | PCM3168A_ADC_VOL_CHAN_START + 2, | |
192 | PCM3168A_ADC_VOL_CHAN_START + 3, | |
193 | 0, 14, 255, 0, pcm3168a_adc_tlv), | |
194 | SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume", | |
195 | PCM3168A_ADC_VOL_CHAN_START + 4, | |
196 | PCM3168A_ADC_VOL_CHAN_START + 5, | |
197 | 0, 14, 255, 0, pcm3168a_adc_tlv) | |
198 | }; | |
199 | ||
200 | static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = { | |
201 | SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT, | |
202 | PCM3168A_DAC_OPEDA_SHIFT, 1), | |
203 | SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT, | |
204 | PCM3168A_DAC_OPEDA_SHIFT + 1, 1), | |
205 | SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT, | |
206 | PCM3168A_DAC_OPEDA_SHIFT + 2, 1), | |
207 | SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT, | |
208 | PCM3168A_DAC_OPEDA_SHIFT + 3, 1), | |
209 | ||
210 | SND_SOC_DAPM_OUTPUT("AOUT1L"), | |
211 | SND_SOC_DAPM_OUTPUT("AOUT1R"), | |
212 | SND_SOC_DAPM_OUTPUT("AOUT2L"), | |
213 | SND_SOC_DAPM_OUTPUT("AOUT2R"), | |
214 | SND_SOC_DAPM_OUTPUT("AOUT3L"), | |
215 | SND_SOC_DAPM_OUTPUT("AOUT3R"), | |
216 | SND_SOC_DAPM_OUTPUT("AOUT4L"), | |
217 | SND_SOC_DAPM_OUTPUT("AOUT4R"), | |
218 | ||
219 | SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB, | |
220 | PCM3168A_ADC_PSVAD_SHIFT, 1), | |
221 | SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB, | |
222 | PCM3168A_ADC_PSVAD_SHIFT + 1, 1), | |
223 | SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB, | |
224 | PCM3168A_ADC_PSVAD_SHIFT + 2, 1), | |
225 | ||
226 | SND_SOC_DAPM_INPUT("AIN1L"), | |
227 | SND_SOC_DAPM_INPUT("AIN1R"), | |
228 | SND_SOC_DAPM_INPUT("AIN2L"), | |
229 | SND_SOC_DAPM_INPUT("AIN2R"), | |
230 | SND_SOC_DAPM_INPUT("AIN3L"), | |
231 | SND_SOC_DAPM_INPUT("AIN3R") | |
232 | }; | |
233 | ||
234 | static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = { | |
235 | /* Playback */ | |
236 | { "AOUT1L", NULL, "DAC1" }, | |
237 | { "AOUT1R", NULL, "DAC1" }, | |
238 | ||
239 | { "AOUT2L", NULL, "DAC2" }, | |
240 | { "AOUT2R", NULL, "DAC2" }, | |
241 | ||
242 | { "AOUT3L", NULL, "DAC3" }, | |
243 | { "AOUT3R", NULL, "DAC3" }, | |
244 | ||
245 | { "AOUT4L", NULL, "DAC4" }, | |
246 | { "AOUT4R", NULL, "DAC4" }, | |
247 | ||
248 | /* Capture */ | |
249 | { "ADC1", NULL, "AIN1L" }, | |
250 | { "ADC1", NULL, "AIN1R" }, | |
251 | ||
252 | { "ADC2", NULL, "AIN2L" }, | |
253 | { "ADC2", NULL, "AIN2R" }, | |
254 | ||
255 | { "ADC3", NULL, "AIN3L" }, | |
256 | { "ADC3", NULL, "AIN3R" } | |
257 | }; | |
258 | ||
259 | static unsigned int pcm3168a_scki_ratios[] = { | |
260 | 768, | |
261 | 512, | |
262 | 384, | |
263 | 256, | |
264 | 192, | |
265 | 128 | |
266 | }; | |
267 | ||
268 | #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios) | |
269 | #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2) | |
270 | ||
271 | #define PCM1368A_MAX_SYSCLK 36864000 | |
272 | ||
273 | static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a) | |
274 | { | |
275 | int ret; | |
276 | ||
277 | ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0); | |
278 | if (ret) | |
279 | return ret; | |
280 | ||
281 | /* Internal reset is de-asserted after 3846 SCKI cycles */ | |
282 | msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk)); | |
283 | ||
284 | return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, | |
285 | PCM3168A_MRST_MASK | PCM3168A_SRST_MASK); | |
286 | } | |
287 | ||
288 | static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute) | |
289 | { | |
290 | struct snd_soc_codec *codec = dai->codec; | |
291 | struct pcm3168a_priv *pcm3168a = snd_soc_codec_get_drvdata(codec); | |
292 | ||
293 | regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai, | |
299 | int clk_id, unsigned int freq, int dir) | |
300 | { | |
301 | struct pcm3168a_priv *pcm3168a = snd_soc_codec_get_drvdata(dai->codec); | |
f1188b89 | 302 | int ret; |
a9b17a63 DH |
303 | |
304 | if (freq > PCM1368A_MAX_SYSCLK) | |
305 | return -EINVAL; | |
306 | ||
f1188b89 DH |
307 | ret = clk_set_rate(pcm3168a->scki, freq); |
308 | if (ret) | |
309 | return ret; | |
310 | ||
a9b17a63 DH |
311 | pcm3168a->sysclk = freq; |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai, | |
317 | unsigned int format, bool dac) | |
318 | { | |
319 | struct snd_soc_codec *codec = dai->codec; | |
320 | struct pcm3168a_priv *pcm3168a = snd_soc_codec_get_drvdata(codec); | |
321 | u32 fmt, reg, mask, shift; | |
322 | bool master_mode; | |
323 | ||
324 | switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { | |
325 | case SND_SOC_DAIFMT_LEFT_J: | |
326 | fmt = PCM3168A_FMT_LEFT_J; | |
327 | break; | |
328 | case SND_SOC_DAIFMT_I2S: | |
329 | fmt = PCM3168A_FMT_I2S; | |
330 | break; | |
331 | case SND_SOC_DAIFMT_RIGHT_J: | |
332 | fmt = PCM3168A_FMT_RIGHT_J; | |
333 | break; | |
334 | case SND_SOC_DAIFMT_DSP_A: | |
335 | fmt = PCM3168A_FMT_DSP_A; | |
336 | break; | |
337 | case SND_SOC_DAIFMT_DSP_B: | |
338 | fmt = PCM3168A_FMT_DSP_B; | |
339 | break; | |
340 | default: | |
341 | dev_err(codec->dev, "unsupported dai format\n"); | |
342 | return -EINVAL; | |
343 | } | |
344 | ||
345 | switch (format & SND_SOC_DAIFMT_MASTER_MASK) { | |
346 | case SND_SOC_DAIFMT_CBS_CFS: | |
347 | master_mode = false; | |
348 | break; | |
349 | case SND_SOC_DAIFMT_CBM_CFM: | |
350 | master_mode = true; | |
351 | break; | |
352 | default: | |
353 | dev_err(codec->dev, "unsupported master/slave mode\n"); | |
354 | return -EINVAL; | |
355 | } | |
356 | ||
357 | switch (format & SND_SOC_DAIFMT_INV_MASK) { | |
358 | case SND_SOC_DAIFMT_NB_NF: | |
359 | break; | |
360 | default: | |
361 | return -EINVAL; | |
362 | } | |
363 | ||
364 | if (dac) { | |
365 | reg = PCM3168A_DAC_PWR_MST_FMT; | |
366 | mask = PCM3168A_DAC_FMT_MASK; | |
367 | shift = PCM3168A_DAC_FMT_SHIFT; | |
368 | pcm3168a->dac_master_mode = master_mode; | |
369 | pcm3168a->dac_fmt = fmt; | |
370 | } else { | |
371 | reg = PCM3168A_ADC_MST_FMT; | |
372 | mask = PCM3168A_ADC_FMTAD_MASK; | |
373 | shift = PCM3168A_ADC_FMTAD_SHIFT; | |
374 | pcm3168a->adc_master_mode = master_mode; | |
375 | pcm3168a->adc_fmt = fmt; | |
376 | } | |
377 | ||
378 | regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static int pcm3168a_set_dai_fmt_dac(struct snd_soc_dai *dai, | |
384 | unsigned int format) | |
385 | { | |
386 | return pcm3168a_set_dai_fmt(dai, format, true); | |
387 | } | |
388 | ||
389 | static int pcm3168a_set_dai_fmt_adc(struct snd_soc_dai *dai, | |
390 | unsigned int format) | |
391 | { | |
392 | return pcm3168a_set_dai_fmt(dai, format, false); | |
393 | } | |
394 | ||
395 | static int pcm3168a_hw_params(struct snd_pcm_substream *substream, | |
396 | struct snd_pcm_hw_params *params, | |
397 | struct snd_soc_dai *dai) | |
398 | { | |
399 | struct snd_soc_codec *codec = dai->codec; | |
400 | struct pcm3168a_priv *pcm3168a = snd_soc_codec_get_drvdata(codec); | |
401 | bool tx, master_mode; | |
402 | u32 val, mask, shift, reg; | |
e7a508f2 | 403 | unsigned int rate, fmt, ratio, max_ratio; |
a9b17a63 DH |
404 | int i, min_frame_size; |
405 | snd_pcm_format_t format; | |
406 | ||
407 | rate = params_rate(params); | |
408 | format = params_format(params); | |
a9b17a63 DH |
409 | |
410 | ratio = pcm3168a->sysclk / rate; | |
411 | ||
412 | tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
413 | if (tx) { | |
414 | max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC; | |
415 | reg = PCM3168A_DAC_PWR_MST_FMT; | |
416 | mask = PCM3168A_DAC_MSDA_MASK; | |
417 | shift = PCM3168A_DAC_MSDA_SHIFT; | |
418 | master_mode = pcm3168a->dac_master_mode; | |
419 | fmt = pcm3168a->dac_fmt; | |
420 | } else { | |
421 | max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC; | |
422 | reg = PCM3168A_ADC_MST_FMT; | |
423 | mask = PCM3168A_ADC_MSAD_MASK; | |
424 | shift = PCM3168A_ADC_MSAD_SHIFT; | |
425 | master_mode = pcm3168a->adc_master_mode; | |
426 | fmt = pcm3168a->adc_fmt; | |
427 | } | |
428 | ||
429 | for (i = 0; i < max_ratio; i++) { | |
430 | if (pcm3168a_scki_ratios[i] == ratio) | |
431 | break; | |
432 | } | |
433 | ||
434 | if (i == max_ratio) { | |
435 | dev_err(codec->dev, "unsupported sysclk ratio\n"); | |
436 | return -EINVAL; | |
437 | } | |
438 | ||
439 | min_frame_size = params_width(params) * 2; | |
440 | switch (min_frame_size) { | |
441 | case 32: | |
442 | if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) { | |
443 | dev_err(codec->dev, "32-bit frames are supported only for slave mode using right justified\n"); | |
444 | return -EINVAL; | |
445 | } | |
446 | fmt = PCM3168A_FMT_RIGHT_J_16; | |
447 | break; | |
448 | case 48: | |
449 | if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) { | |
450 | dev_err(codec->dev, "48-bit frames not supported in master mode, or slave mode using DSP\n"); | |
451 | return -EINVAL; | |
452 | } | |
453 | break; | |
454 | case 64: | |
455 | break; | |
456 | default: | |
457 | dev_err(codec->dev, "unsupported frame size: %d\n", min_frame_size); | |
458 | return -EINVAL; | |
459 | } | |
460 | ||
461 | if (master_mode) | |
462 | val = ((i + 1) << shift); | |
463 | else | |
464 | val = 0; | |
465 | ||
466 | regmap_update_bits(pcm3168a->regmap, reg, mask, val); | |
467 | ||
468 | if (tx) { | |
469 | mask = PCM3168A_DAC_FMT_MASK; | |
470 | shift = PCM3168A_DAC_FMT_SHIFT; | |
471 | } else { | |
472 | mask = PCM3168A_ADC_FMTAD_MASK; | |
473 | shift = PCM3168A_ADC_FMTAD_SHIFT; | |
474 | } | |
475 | ||
476 | regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
481 | static const struct snd_soc_dai_ops pcm3168a_dac_dai_ops = { | |
482 | .set_fmt = pcm3168a_set_dai_fmt_dac, | |
483 | .set_sysclk = pcm3168a_set_dai_sysclk, | |
484 | .hw_params = pcm3168a_hw_params, | |
485 | .digital_mute = pcm3168a_digital_mute | |
486 | }; | |
487 | ||
488 | static const struct snd_soc_dai_ops pcm3168a_adc_dai_ops = { | |
489 | .set_fmt = pcm3168a_set_dai_fmt_adc, | |
490 | .set_sysclk = pcm3168a_set_dai_sysclk, | |
491 | .hw_params = pcm3168a_hw_params | |
492 | }; | |
493 | ||
494 | static struct snd_soc_dai_driver pcm3168a_dais[] = { | |
495 | { | |
496 | .name = "pcm3168a-dac", | |
497 | .playback = { | |
498 | .stream_name = "Playback", | |
499 | .channels_min = 1, | |
500 | .channels_max = 8, | |
501 | .rates = SNDRV_PCM_RATE_8000_192000, | |
502 | .formats = PCM3168A_FORMATS | |
503 | }, | |
504 | .ops = &pcm3168a_dac_dai_ops | |
505 | }, | |
506 | { | |
507 | .name = "pcm3168a-adc", | |
508 | .capture = { | |
509 | .stream_name = "Capture", | |
510 | .channels_min = 1, | |
511 | .channels_max = 6, | |
512 | .rates = SNDRV_PCM_RATE_8000_96000, | |
513 | .formats = PCM3168A_FORMATS | |
514 | }, | |
515 | .ops = &pcm3168a_adc_dai_ops | |
516 | }, | |
517 | }; | |
518 | ||
519 | static const struct reg_default pcm3168a_reg_default[] = { | |
520 | { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK }, | |
521 | { PCM3168A_DAC_PWR_MST_FMT, 0x00 }, | |
522 | { PCM3168A_DAC_OP_FLT, 0x00 }, | |
523 | { PCM3168A_DAC_INV, 0x00 }, | |
524 | { PCM3168A_DAC_MUTE, 0x00 }, | |
525 | { PCM3168A_DAC_ZERO, 0x00 }, | |
526 | { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 }, | |
527 | { PCM3168A_DAC_VOL_MASTER, 0xff }, | |
528 | { PCM3168A_DAC_VOL_CHAN_START, 0xff }, | |
529 | { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff }, | |
530 | { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff }, | |
531 | { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff }, | |
532 | { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff }, | |
533 | { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff }, | |
534 | { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff }, | |
535 | { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff }, | |
536 | { PCM3168A_ADC_SMODE, 0x00 }, | |
537 | { PCM3168A_ADC_MST_FMT, 0x00 }, | |
538 | { PCM3168A_ADC_PWR_HPFB, 0x00 }, | |
539 | { PCM3168A_ADC_SEAD, 0x00 }, | |
540 | { PCM3168A_ADC_INV, 0x00 }, | |
541 | { PCM3168A_ADC_MUTE, 0x00 }, | |
542 | { PCM3168A_ADC_OV, 0x00 }, | |
543 | { PCM3168A_ADC_ATT_OVF, 0x00 }, | |
544 | { PCM3168A_ADC_VOL_MASTER, 0xd3 }, | |
545 | { PCM3168A_ADC_VOL_CHAN_START, 0xd3 }, | |
546 | { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 }, | |
547 | { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 }, | |
548 | { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 }, | |
549 | { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 }, | |
550 | { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 } | |
551 | }; | |
552 | ||
553 | static bool pcm3168a_readable_register(struct device *dev, unsigned int reg) | |
554 | { | |
555 | if (reg >= PCM3168A_RST_SMODE) | |
556 | return true; | |
557 | else | |
558 | return false; | |
559 | } | |
560 | ||
561 | static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg) | |
562 | { | |
563 | switch (reg) { | |
564 | case PCM3168A_DAC_ZERO: | |
565 | case PCM3168A_ADC_OV: | |
566 | return true; | |
567 | default: | |
568 | return false; | |
569 | } | |
570 | } | |
571 | ||
572 | static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg) | |
573 | { | |
574 | if (reg < PCM3168A_RST_SMODE) | |
575 | return false; | |
576 | ||
577 | switch (reg) { | |
578 | case PCM3168A_DAC_ZERO: | |
579 | case PCM3168A_ADC_OV: | |
580 | return false; | |
581 | default: | |
582 | return true; | |
583 | } | |
584 | } | |
585 | ||
586 | const struct regmap_config pcm3168a_regmap = { | |
587 | .reg_bits = 8, | |
588 | .val_bits = 8, | |
589 | ||
590 | .max_register = PCM3168A_ADC_VOL_CHAN_START + 5, | |
591 | .reg_defaults = pcm3168a_reg_default, | |
592 | .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default), | |
593 | .readable_reg = pcm3168a_readable_register, | |
594 | .volatile_reg = pcm3168a_volatile_register, | |
595 | .writeable_reg = pcm3168a_writeable_register, | |
596 | .cache_type = REGCACHE_FLAT | |
597 | }; | |
598 | EXPORT_SYMBOL_GPL(pcm3168a_regmap); | |
599 | ||
600 | static const struct snd_soc_codec_driver pcm3168a_driver = { | |
601 | .idle_bias_off = true, | |
602 | .controls = pcm3168a_snd_controls, | |
603 | .num_controls = ARRAY_SIZE(pcm3168a_snd_controls), | |
604 | .dapm_widgets = pcm3168a_dapm_widgets, | |
605 | .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets), | |
606 | .dapm_routes = pcm3168a_dapm_routes, | |
607 | .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes) | |
608 | }; | |
609 | ||
610 | int pcm3168a_probe(struct device *dev, struct regmap *regmap) | |
611 | { | |
612 | struct pcm3168a_priv *pcm3168a; | |
613 | int ret, i; | |
614 | ||
615 | pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL); | |
616 | if (pcm3168a == NULL) | |
617 | return -ENOMEM; | |
618 | ||
619 | dev_set_drvdata(dev, pcm3168a); | |
620 | ||
621 | pcm3168a->scki = devm_clk_get(dev, "scki"); | |
622 | if (IS_ERR(pcm3168a->scki)) { | |
623 | ret = PTR_ERR(pcm3168a->scki); | |
624 | if (ret != -EPROBE_DEFER) | |
625 | dev_err(dev, "failed to acquire clock 'scki': %d\n", ret); | |
626 | return ret; | |
627 | } | |
628 | ||
629 | ret = clk_prepare_enable(pcm3168a->scki); | |
630 | if (ret) { | |
631 | dev_err(dev, "Failed to enable mclk: %d\n", ret); | |
632 | return ret; | |
633 | } | |
634 | ||
635 | pcm3168a->sysclk = clk_get_rate(pcm3168a->scki); | |
636 | ||
637 | for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++) | |
638 | pcm3168a->supplies[i].supply = pcm3168a_supply_names[i]; | |
639 | ||
640 | ret = devm_regulator_bulk_get(dev, | |
641 | ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies); | |
642 | if (ret) { | |
643 | if (ret != -EPROBE_DEFER) | |
644 | dev_err(dev, "failed to request supplies: %d\n", ret); | |
645 | goto err_clk; | |
646 | } | |
647 | ||
648 | ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), | |
649 | pcm3168a->supplies); | |
650 | if (ret) { | |
651 | dev_err(dev, "failed to enable supplies: %d\n", ret); | |
652 | goto err_clk; | |
653 | } | |
654 | ||
655 | pcm3168a->regmap = regmap; | |
656 | if (IS_ERR(pcm3168a->regmap)) { | |
657 | ret = PTR_ERR(pcm3168a->regmap); | |
658 | dev_err(dev, "failed to allocate regmap: %d\n", ret); | |
659 | goto err_regulator; | |
660 | } | |
661 | ||
662 | ret = pcm3168a_reset(pcm3168a); | |
663 | if (ret) { | |
664 | dev_err(dev, "Failed to reset device: %d\n", ret); | |
665 | goto err_regulator; | |
666 | } | |
667 | ||
668 | pm_runtime_set_active(dev); | |
669 | pm_runtime_enable(dev); | |
670 | pm_runtime_idle(dev); | |
671 | ||
672 | ret = snd_soc_register_codec(dev, &pcm3168a_driver, pcm3168a_dais, | |
673 | ARRAY_SIZE(pcm3168a_dais)); | |
674 | if (ret) { | |
675 | dev_err(dev, "failed to register codec: %d\n", ret); | |
676 | goto err_regulator; | |
677 | } | |
678 | ||
679 | return 0; | |
680 | ||
681 | err_regulator: | |
682 | regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), | |
683 | pcm3168a->supplies); | |
684 | err_clk: | |
685 | clk_disable_unprepare(pcm3168a->scki); | |
686 | ||
687 | return ret; | |
688 | } | |
689 | EXPORT_SYMBOL_GPL(pcm3168a_probe); | |
690 | ||
691 | void pcm3168a_remove(struct device *dev) | |
692 | { | |
693 | struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); | |
694 | ||
695 | snd_soc_unregister_codec(dev); | |
696 | pm_runtime_disable(dev); | |
697 | regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), | |
698 | pcm3168a->supplies); | |
699 | clk_disable_unprepare(pcm3168a->scki); | |
700 | } | |
701 | EXPORT_SYMBOL_GPL(pcm3168a_remove); | |
702 | ||
703 | #ifdef CONFIG_PM | |
704 | static int pcm3168a_rt_resume(struct device *dev) | |
705 | { | |
706 | struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); | |
707 | int ret; | |
708 | ||
709 | ret = clk_prepare_enable(pcm3168a->scki); | |
710 | if (ret) { | |
711 | dev_err(dev, "Failed to enable mclk: %d\n", ret); | |
712 | return ret; | |
713 | } | |
714 | ||
715 | ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies), | |
716 | pcm3168a->supplies); | |
717 | if (ret) { | |
718 | dev_err(dev, "Failed to enable supplies: %d\n", ret); | |
719 | goto err_clk; | |
720 | } | |
721 | ||
722 | ret = pcm3168a_reset(pcm3168a); | |
723 | if (ret) { | |
724 | dev_err(dev, "Failed to reset device: %d\n", ret); | |
725 | goto err_regulator; | |
726 | } | |
727 | ||
728 | regcache_cache_only(pcm3168a->regmap, false); | |
729 | ||
730 | regcache_mark_dirty(pcm3168a->regmap); | |
731 | ||
732 | ret = regcache_sync(pcm3168a->regmap); | |
733 | if (ret) { | |
734 | dev_err(dev, "Failed to sync regmap: %d\n", ret); | |
735 | goto err_regulator; | |
736 | } | |
737 | ||
738 | return 0; | |
739 | ||
740 | err_regulator: | |
741 | regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), | |
742 | pcm3168a->supplies); | |
743 | err_clk: | |
744 | clk_disable_unprepare(pcm3168a->scki); | |
745 | ||
746 | return ret; | |
747 | } | |
748 | ||
749 | static int pcm3168a_rt_suspend(struct device *dev) | |
750 | { | |
751 | struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev); | |
752 | ||
753 | regcache_cache_only(pcm3168a->regmap, true); | |
754 | ||
755 | regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies), | |
756 | pcm3168a->supplies); | |
757 | ||
758 | clk_disable_unprepare(pcm3168a->scki); | |
759 | ||
760 | return 0; | |
761 | } | |
762 | #endif | |
763 | ||
764 | const struct dev_pm_ops pcm3168a_pm_ops = { | |
765 | SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL) | |
766 | }; | |
767 | EXPORT_SYMBOL_GPL(pcm3168a_pm_ops); | |
768 | ||
769 | MODULE_DESCRIPTION("PCM3168A codec driver"); | |
770 | MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>"); | |
771 | MODULE_LICENSE("GPL v2"); |