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07cf7cba BL |
1 | /* |
2 | * rt286.c -- RT286 ALSA SoC audio codec driver | |
3 | * | |
4 | * Copyright 2013 Realtek Semiconductor Corp. | |
5 | * Author: Bard Liao <bardliao@realtek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/spi/spi.h> | |
6c67cde2 | 20 | #include <linux/dmi.h> |
07cf7cba BL |
21 | #include <linux/acpi.h> |
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/soc-dapm.h> | |
27 | #include <sound/initval.h> | |
28 | #include <sound/tlv.h> | |
29 | #include <sound/jack.h> | |
30 | #include <linux/workqueue.h> | |
31 | #include <sound/rt286.h> | |
32 | #include <sound/hda_verbs.h> | |
33 | ||
34 | #include "rt286.h" | |
35 | ||
36 | #define RT286_VENDOR_ID 0x10ec0286 | |
37 | ||
38 | struct rt286_priv { | |
39 | struct regmap *regmap; | |
6879db76 | 40 | struct snd_soc_codec *codec; |
07cf7cba BL |
41 | struct rt286_platform_data pdata; |
42 | struct i2c_client *i2c; | |
43 | struct snd_soc_jack *jack; | |
44 | struct delayed_work jack_detect_work; | |
45 | int sys_clk; | |
6879db76 | 46 | int clk_id; |
07cf7cba BL |
47 | struct reg_default *index_cache; |
48 | }; | |
49 | ||
50 | static struct reg_default rt286_index_def[] = { | |
51 | { 0x01, 0xaaaa }, | |
52 | { 0x02, 0x8aaa }, | |
53 | { 0x03, 0x0002 }, | |
54 | { 0x04, 0xaf01 }, | |
55 | { 0x08, 0x000d }, | |
56 | { 0x09, 0xd810 }, | |
b7a29767 | 57 | { 0x0a, 0x0120 }, |
07cf7cba | 58 | { 0x0b, 0x0000 }, |
bc6c4e45 | 59 | { 0x0d, 0x2800 }, |
07cf7cba BL |
60 | { 0x0f, 0x0000 }, |
61 | { 0x19, 0x0a17 }, | |
62 | { 0x20, 0x0020 }, | |
63 | { 0x33, 0x0208 }, | |
64 | { 0x49, 0x0004 }, | |
65 | { 0x4f, 0x50e9 }, | |
b7a29767 | 66 | { 0x50, 0x2000 }, |
07cf7cba | 67 | { 0x63, 0x2902 }, |
bc6c4e45 BL |
68 | { 0x67, 0x1111 }, |
69 | { 0x68, 0x1016 }, | |
70 | { 0x69, 0x273f }, | |
07cf7cba BL |
71 | }; |
72 | #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def) | |
73 | ||
74 | static const struct reg_default rt286_reg[] = { | |
75 | { 0x00170500, 0x00000400 }, | |
76 | { 0x00220000, 0x00000031 }, | |
77 | { 0x00239000, 0x0000007f }, | |
78 | { 0x0023a000, 0x0000007f }, | |
79 | { 0x00270500, 0x00000400 }, | |
80 | { 0x00370500, 0x00000400 }, | |
81 | { 0x00870500, 0x00000400 }, | |
82 | { 0x00920000, 0x00000031 }, | |
83 | { 0x00935000, 0x000000c3 }, | |
84 | { 0x00936000, 0x000000c3 }, | |
85 | { 0x00970500, 0x00000400 }, | |
86 | { 0x00b37000, 0x00000097 }, | |
87 | { 0x00b37200, 0x00000097 }, | |
88 | { 0x00b37300, 0x00000097 }, | |
89 | { 0x00c37000, 0x00000000 }, | |
90 | { 0x00c37100, 0x00000080 }, | |
91 | { 0x01270500, 0x00000400 }, | |
92 | { 0x01370500, 0x00000400 }, | |
93 | { 0x01371f00, 0x411111f0 }, | |
94 | { 0x01439000, 0x00000080 }, | |
95 | { 0x0143a000, 0x00000080 }, | |
96 | { 0x01470700, 0x00000000 }, | |
97 | { 0x01470500, 0x00000400 }, | |
98 | { 0x01470c00, 0x00000000 }, | |
99 | { 0x01470100, 0x00000000 }, | |
100 | { 0x01837000, 0x00000000 }, | |
101 | { 0x01870500, 0x00000400 }, | |
102 | { 0x02050000, 0x00000000 }, | |
103 | { 0x02139000, 0x00000080 }, | |
104 | { 0x0213a000, 0x00000080 }, | |
105 | { 0x02170100, 0x00000000 }, | |
106 | { 0x02170500, 0x00000400 }, | |
107 | { 0x02170700, 0x00000000 }, | |
108 | { 0x02270100, 0x00000000 }, | |
109 | { 0x02370100, 0x00000000 }, | |
07cf7cba BL |
110 | { 0x01870700, 0x00000020 }, |
111 | { 0x00830000, 0x000000c3 }, | |
112 | { 0x00930000, 0x000000c3 }, | |
113 | { 0x01270700, 0x00000000 }, | |
114 | }; | |
115 | ||
116 | static bool rt286_volatile_register(struct device *dev, unsigned int reg) | |
117 | { | |
118 | switch (reg) { | |
119 | case 0 ... 0xff: | |
120 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
121 | case RT286_GET_HP_SENSE: | |
122 | case RT286_GET_MIC1_SENSE: | |
123 | case RT286_PROC_COEF: | |
124 | return true; | |
125 | default: | |
126 | return false; | |
127 | } | |
128 | ||
129 | ||
130 | } | |
131 | ||
132 | static bool rt286_readable_register(struct device *dev, unsigned int reg) | |
133 | { | |
134 | switch (reg) { | |
135 | case 0 ... 0xff: | |
136 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
137 | case RT286_GET_HP_SENSE: | |
138 | case RT286_GET_MIC1_SENSE: | |
139 | case RT286_SET_AUDIO_POWER: | |
140 | case RT286_SET_HPO_POWER: | |
141 | case RT286_SET_SPK_POWER: | |
142 | case RT286_SET_DMIC1_POWER: | |
143 | case RT286_SPK_MUX: | |
144 | case RT286_HPO_MUX: | |
145 | case RT286_ADC0_MUX: | |
146 | case RT286_ADC1_MUX: | |
147 | case RT286_SET_MIC1: | |
148 | case RT286_SET_PIN_HPO: | |
149 | case RT286_SET_PIN_SPK: | |
150 | case RT286_SET_PIN_DMIC1: | |
151 | case RT286_SPK_EAPD: | |
152 | case RT286_SET_AMP_GAIN_HPO: | |
153 | case RT286_SET_DMIC2_DEFAULT: | |
154 | case RT286_DACL_GAIN: | |
155 | case RT286_DACR_GAIN: | |
156 | case RT286_ADCL_GAIN: | |
157 | case RT286_ADCR_GAIN: | |
158 | case RT286_MIC_GAIN: | |
159 | case RT286_SPOL_GAIN: | |
160 | case RT286_SPOR_GAIN: | |
161 | case RT286_HPOL_GAIN: | |
162 | case RT286_HPOR_GAIN: | |
163 | case RT286_F_DAC_SWITCH: | |
164 | case RT286_F_RECMIX_SWITCH: | |
165 | case RT286_REC_MIC_SWITCH: | |
166 | case RT286_REC_I2S_SWITCH: | |
167 | case RT286_REC_LINE_SWITCH: | |
168 | case RT286_REC_BEEP_SWITCH: | |
169 | case RT286_DAC_FORMAT: | |
170 | case RT286_ADC_FORMAT: | |
171 | case RT286_COEF_INDEX: | |
172 | case RT286_PROC_COEF: | |
173 | case RT286_SET_AMP_GAIN_ADC_IN1: | |
174 | case RT286_SET_AMP_GAIN_ADC_IN2: | |
175 | case RT286_SET_POWER(RT286_DAC_OUT1): | |
176 | case RT286_SET_POWER(RT286_DAC_OUT2): | |
177 | case RT286_SET_POWER(RT286_ADC_IN1): | |
178 | case RT286_SET_POWER(RT286_ADC_IN2): | |
179 | case RT286_SET_POWER(RT286_DMIC2): | |
180 | case RT286_SET_POWER(RT286_MIC1): | |
181 | return true; | |
182 | default: | |
183 | return false; | |
184 | } | |
185 | } | |
186 | ||
187 | static int rt286_hw_write(void *context, unsigned int reg, unsigned int value) | |
188 | { | |
189 | struct i2c_client *client = context; | |
190 | struct rt286_priv *rt286 = i2c_get_clientdata(client); | |
191 | u8 data[4]; | |
192 | int ret, i; | |
193 | ||
f8c101bc | 194 | /* handle index registers */ |
07cf7cba BL |
195 | if (reg <= 0xff) { |
196 | rt286_hw_write(client, RT286_COEF_INDEX, reg); | |
07cf7cba BL |
197 | for (i = 0; i < INDEX_CACHE_SIZE; i++) { |
198 | if (reg == rt286->index_cache[i].reg) { | |
199 | rt286->index_cache[i].def = value; | |
200 | break; | |
201 | } | |
202 | ||
203 | } | |
66d627d5 | 204 | reg = RT286_PROC_COEF; |
07cf7cba BL |
205 | } |
206 | ||
207 | data[0] = (reg >> 24) & 0xff; | |
208 | data[1] = (reg >> 16) & 0xff; | |
209 | /* | |
210 | * 4 bit VID: reg should be 0 | |
211 | * 12 bit VID: value should be 0 | |
212 | * So we use an OR operator to handle it rather than use if condition. | |
213 | */ | |
214 | data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff); | |
215 | data[3] = value & 0xff; | |
216 | ||
217 | ret = i2c_master_send(client, data, 4); | |
218 | ||
219 | if (ret == 4) | |
220 | return 0; | |
221 | else | |
222 | pr_err("ret=%d\n", ret); | |
223 | if (ret < 0) | |
224 | return ret; | |
225 | else | |
226 | return -EIO; | |
227 | } | |
228 | ||
229 | static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value) | |
230 | { | |
231 | struct i2c_client *client = context; | |
232 | struct i2c_msg xfer[2]; | |
233 | int ret; | |
234 | __be32 be_reg; | |
235 | unsigned int index, vid, buf = 0x0; | |
236 | ||
f8c101bc | 237 | /* handle index registers */ |
07cf7cba BL |
238 | if (reg <= 0xff) { |
239 | rt286_hw_write(client, RT286_COEF_INDEX, reg); | |
240 | reg = RT286_PROC_COEF; | |
241 | } | |
242 | ||
243 | reg = reg | 0x80000; | |
244 | vid = (reg >> 8) & 0xfff; | |
245 | ||
246 | if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) { | |
247 | index = (reg >> 8) & 0xf; | |
248 | reg = (reg & ~0xf0f) | index; | |
249 | } | |
250 | be_reg = cpu_to_be32(reg); | |
251 | ||
252 | /* Write register */ | |
253 | xfer[0].addr = client->addr; | |
254 | xfer[0].flags = 0; | |
255 | xfer[0].len = 4; | |
256 | xfer[0].buf = (u8 *)&be_reg; | |
257 | ||
258 | /* Read data */ | |
259 | xfer[1].addr = client->addr; | |
260 | xfer[1].flags = I2C_M_RD; | |
261 | xfer[1].len = 4; | |
262 | xfer[1].buf = (u8 *)&buf; | |
263 | ||
264 | ret = i2c_transfer(client->adapter, xfer, 2); | |
265 | if (ret < 0) | |
266 | return ret; | |
267 | else if (ret != 2) | |
268 | return -EIO; | |
269 | ||
270 | *value = be32_to_cpu(buf); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
81f3dfe1 | 275 | #ifdef CONFIG_PM |
07cf7cba BL |
276 | static void rt286_index_sync(struct snd_soc_codec *codec) |
277 | { | |
278 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
279 | int i; | |
280 | ||
281 | for (i = 0; i < INDEX_CACHE_SIZE; i++) { | |
282 | snd_soc_write(codec, rt286->index_cache[i].reg, | |
283 | rt286->index_cache[i].def); | |
284 | } | |
285 | } | |
81f3dfe1 | 286 | #endif |
07cf7cba BL |
287 | |
288 | static int rt286_support_power_controls[] = { | |
289 | RT286_DAC_OUT1, | |
290 | RT286_DAC_OUT2, | |
291 | RT286_ADC_IN1, | |
292 | RT286_ADC_IN2, | |
293 | RT286_MIC1, | |
294 | RT286_DMIC1, | |
295 | RT286_DMIC2, | |
296 | RT286_SPK_OUT, | |
297 | RT286_HP_OUT, | |
298 | }; | |
299 | #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls) | |
300 | ||
90f601ef | 301 | static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic) |
07cf7cba | 302 | { |
07cf7cba | 303 | unsigned int val, buf; |
07cf7cba BL |
304 | |
305 | *hp = false; | |
306 | *mic = false; | |
307 | ||
308 | if (rt286->pdata.cbj_en) { | |
90f601ef | 309 | regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf); |
07cf7cba BL |
310 | *hp = buf & 0x80000000; |
311 | if (*hp) { | |
312 | /* power on HV,VERF */ | |
90f601ef | 313 | regmap_update_bits(rt286->regmap, |
6879db76 BL |
314 | RT286_DC_GAIN, 0x200, 0x200); |
315 | ||
316 | snd_soc_dapm_force_enable_pin(&rt286->codec->dapm, | |
317 | "HV"); | |
318 | snd_soc_dapm_force_enable_pin(&rt286->codec->dapm, | |
319 | "VREF"); | |
07cf7cba | 320 | /* power LDO1 */ |
6879db76 BL |
321 | snd_soc_dapm_force_enable_pin(&rt286->codec->dapm, |
322 | "LDO1"); | |
323 | snd_soc_dapm_sync(&rt286->codec->dapm); | |
07cf7cba | 324 | |
6879db76 BL |
325 | regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24); |
326 | msleep(50); | |
07cf7cba | 327 | |
6879db76 BL |
328 | regmap_update_bits(rt286->regmap, |
329 | RT286_CBJ_CTRL1, 0xfcc0, 0xd400); | |
330 | msleep(300); | |
331 | regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val); | |
07cf7cba | 332 | |
6879db76 | 333 | if (0x0070 == (val & 0x0070)) { |
07cf7cba | 334 | *mic = true; |
07cf7cba | 335 | } else { |
6879db76 BL |
336 | regmap_update_bits(rt286->regmap, |
337 | RT286_CBJ_CTRL1, 0xfcc0, 0xe400); | |
338 | msleep(300); | |
339 | regmap_read(rt286->regmap, | |
340 | RT286_CBJ_CTRL2, &val); | |
341 | if (0x0070 == (val & 0x0070)) | |
342 | *mic = true; | |
343 | else | |
344 | *mic = false; | |
07cf7cba | 345 | } |
90f601ef | 346 | regmap_update_bits(rt286->regmap, |
6879db76 | 347 | RT286_DC_GAIN, 0x200, 0x0); |
07cf7cba | 348 | |
6879db76 | 349 | } else { |
07cf7cba | 350 | *mic = false; |
6879db76 | 351 | regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20); |
07cf7cba BL |
352 | } |
353 | } else { | |
90f601ef | 354 | regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf); |
07cf7cba | 355 | *hp = buf & 0x80000000; |
90f601ef | 356 | regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf); |
07cf7cba BL |
357 | *mic = buf & 0x80000000; |
358 | } | |
359 | ||
6879db76 BL |
360 | snd_soc_dapm_disable_pin(&rt286->codec->dapm, "HV"); |
361 | snd_soc_dapm_disable_pin(&rt286->codec->dapm, "VREF"); | |
362 | if (!*hp) | |
363 | snd_soc_dapm_disable_pin(&rt286->codec->dapm, "LDO1"); | |
364 | snd_soc_dapm_sync(&rt286->codec->dapm); | |
365 | ||
07cf7cba BL |
366 | return 0; |
367 | } | |
368 | ||
369 | static void rt286_jack_detect_work(struct work_struct *work) | |
370 | { | |
371 | struct rt286_priv *rt286 = | |
372 | container_of(work, struct rt286_priv, jack_detect_work.work); | |
373 | int status = 0; | |
374 | bool hp = false; | |
375 | bool mic = false; | |
376 | ||
90f601ef | 377 | rt286_jack_detect(rt286, &hp, &mic); |
07cf7cba BL |
378 | |
379 | if (hp == true) | |
380 | status |= SND_JACK_HEADPHONE; | |
381 | ||
382 | if (mic == true) | |
383 | status |= SND_JACK_MICROPHONE; | |
384 | ||
385 | snd_soc_jack_report(rt286->jack, status, | |
386 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
387 | } | |
388 | ||
389 | int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) | |
390 | { | |
391 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
392 | ||
393 | rt286->jack = jack; | |
394 | ||
395 | /* Send an initial empty report */ | |
396 | snd_soc_jack_report(rt286->jack, 0, | |
397 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
398 | ||
399 | return 0; | |
400 | } | |
401 | EXPORT_SYMBOL_GPL(rt286_mic_detect); | |
402 | ||
6879db76 BL |
403 | static int is_mclk_mode(struct snd_soc_dapm_widget *source, |
404 | struct snd_soc_dapm_widget *sink) | |
405 | { | |
406 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(source->codec); | |
407 | ||
408 | if (rt286->clk_id == RT286_SCLK_S_MCLK) | |
409 | return 1; | |
410 | else | |
411 | return 0; | |
412 | } | |
413 | ||
07cf7cba BL |
414 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); |
415 | static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); | |
416 | ||
417 | static const struct snd_kcontrol_new rt286_snd_controls[] = { | |
418 | SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN, | |
419 | RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
420 | SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN, | |
421 | RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
422 | SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN, | |
423 | 0, 0x3, 0, mic_vol_tlv), | |
424 | SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN, | |
425 | RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1), | |
426 | }; | |
427 | ||
428 | /* Digital Mixer */ | |
429 | static const struct snd_kcontrol_new rt286_front_mix[] = { | |
430 | SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH, | |
431 | RT286_MUTE_SFT, 1, 1), | |
432 | SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH, | |
433 | RT286_MUTE_SFT, 1, 1), | |
434 | }; | |
435 | ||
436 | /* Analog Input Mixer */ | |
437 | static const struct snd_kcontrol_new rt286_rec_mix[] = { | |
438 | SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH, | |
439 | RT286_MUTE_SFT, 1, 1), | |
440 | SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH, | |
441 | RT286_MUTE_SFT, 1, 1), | |
442 | SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH, | |
443 | RT286_MUTE_SFT, 1, 1), | |
444 | SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH, | |
445 | RT286_MUTE_SFT, 1, 1), | |
446 | }; | |
447 | ||
448 | static const struct snd_kcontrol_new spo_enable_control = | |
449 | SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK, | |
450 | RT286_SET_PIN_SFT, 1, 0); | |
451 | ||
452 | static const struct snd_kcontrol_new hpol_enable_control = | |
453 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN, | |
454 | RT286_MUTE_SFT, 1, 1); | |
455 | ||
456 | static const struct snd_kcontrol_new hpor_enable_control = | |
457 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN, | |
458 | RT286_MUTE_SFT, 1, 1); | |
459 | ||
460 | /* ADC0 source */ | |
461 | static const char * const rt286_adc_src[] = { | |
462 | "Mic", "RECMIX", "Dmic" | |
463 | }; | |
464 | ||
465 | static const int rt286_adc_values[] = { | |
466 | 0, 4, 5, | |
467 | }; | |
468 | ||
469 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
470 | rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT, | |
471 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
472 | ||
473 | static const struct snd_kcontrol_new rt286_adc0_mux = | |
474 | SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum); | |
475 | ||
476 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
477 | rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT, | |
478 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
479 | ||
480 | static const struct snd_kcontrol_new rt286_adc1_mux = | |
481 | SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum); | |
482 | ||
483 | static const char * const rt286_dac_src[] = { | |
484 | "Front", "Surround" | |
485 | }; | |
486 | /* HP-OUT source */ | |
487 | static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX, | |
488 | 0, rt286_dac_src); | |
489 | ||
490 | static const struct snd_kcontrol_new rt286_hpo_mux = | |
491 | SOC_DAPM_ENUM("HPO source", rt286_hpo_enum); | |
492 | ||
493 | /* SPK-OUT source */ | |
494 | static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX, | |
495 | 0, rt286_dac_src); | |
496 | ||
497 | static const struct snd_kcontrol_new rt286_spo_mux = | |
498 | SOC_DAPM_ENUM("SPO source", rt286_spo_enum); | |
499 | ||
500 | static int rt286_spk_event(struct snd_soc_dapm_widget *w, | |
501 | struct snd_kcontrol *kcontrol, int event) | |
502 | { | |
503 | struct snd_soc_codec *codec = w->codec; | |
504 | ||
505 | switch (event) { | |
506 | case SND_SOC_DAPM_POST_PMU: | |
507 | snd_soc_write(codec, | |
508 | RT286_SPK_EAPD, RT286_SET_EAPD_HIGH); | |
509 | break; | |
510 | case SND_SOC_DAPM_PRE_PMD: | |
511 | snd_soc_write(codec, | |
512 | RT286_SPK_EAPD, RT286_SET_EAPD_LOW); | |
513 | break; | |
514 | ||
515 | default: | |
516 | return 0; | |
517 | } | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w, | |
523 | struct snd_kcontrol *kcontrol, int event) | |
524 | { | |
525 | struct snd_soc_codec *codec = w->codec; | |
526 | ||
527 | switch (event) { | |
528 | case SND_SOC_DAPM_POST_PMU: | |
529 | snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20); | |
530 | break; | |
531 | case SND_SOC_DAPM_PRE_PMD: | |
532 | snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0); | |
533 | break; | |
534 | default: | |
535 | return 0; | |
536 | } | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | static int rt286_adc_event(struct snd_soc_dapm_widget *w, | |
542 | struct snd_kcontrol *kcontrol, int event) | |
543 | { | |
544 | struct snd_soc_codec *codec = w->codec; | |
545 | unsigned int nid; | |
546 | ||
547 | nid = (w->reg >> 20) & 0xff; | |
548 | ||
549 | switch (event) { | |
550 | case SND_SOC_DAPM_POST_PMU: | |
551 | snd_soc_update_bits(codec, | |
552 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), | |
553 | 0x7080, 0x7000); | |
554 | break; | |
555 | case SND_SOC_DAPM_PRE_PMD: | |
556 | snd_soc_update_bits(codec, | |
557 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), | |
558 | 0x7080, 0x7080); | |
559 | break; | |
560 | default: | |
561 | return 0; | |
562 | } | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
6879db76 BL |
567 | static int rt286_vref_event(struct snd_soc_dapm_widget *w, |
568 | struct snd_kcontrol *kcontrol, int event) | |
569 | { | |
570 | struct snd_soc_codec *codec = w->codec; | |
571 | ||
572 | switch (event) { | |
573 | case SND_SOC_DAPM_PRE_PMU: | |
574 | snd_soc_update_bits(codec, | |
575 | RT286_CBJ_CTRL1, 0x0400, 0x0000); | |
576 | mdelay(50); | |
577 | break; | |
578 | default: | |
579 | return 0; | |
580 | } | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | static int rt286_ldo2_event(struct snd_soc_dapm_widget *w, | |
586 | struct snd_kcontrol *kcontrol, int event) | |
587 | { | |
588 | struct snd_soc_codec *codec = w->codec; | |
589 | ||
590 | switch (event) { | |
591 | case SND_SOC_DAPM_POST_PMU: | |
592 | snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08); | |
593 | break; | |
594 | case SND_SOC_DAPM_PRE_PMD: | |
595 | snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30); | |
596 | break; | |
597 | default: | |
598 | return 0; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | static int rt286_mic1_event(struct snd_soc_dapm_widget *w, | |
605 | struct snd_kcontrol *kcontrol, int event) | |
606 | { | |
607 | struct snd_soc_codec *codec = w->codec; | |
608 | ||
609 | switch (event) { | |
610 | case SND_SOC_DAPM_PRE_PMU: | |
611 | snd_soc_update_bits(codec, | |
612 | RT286_A_BIAS_CTRL3, 0xc000, 0x8000); | |
613 | snd_soc_update_bits(codec, | |
614 | RT286_A_BIAS_CTRL2, 0xc000, 0x8000); | |
615 | break; | |
616 | case SND_SOC_DAPM_POST_PMD: | |
617 | snd_soc_update_bits(codec, | |
618 | RT286_A_BIAS_CTRL3, 0xc000, 0x0000); | |
619 | snd_soc_update_bits(codec, | |
620 | RT286_A_BIAS_CTRL2, 0xc000, 0x0000); | |
621 | break; | |
622 | default: | |
623 | return 0; | |
624 | } | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
07cf7cba | 629 | static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = { |
6879db76 BL |
630 | SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1, |
631 | 12, 1, NULL, 0), | |
632 | SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1, | |
633 | 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU), | |
634 | SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2, | |
635 | 2, 0, NULL, 0), | |
636 | SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1, | |
637 | 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD | | |
638 | SND_SOC_DAPM_POST_PMU), | |
639 | SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1, | |
640 | 5, 0, NULL, 0), | |
641 | SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM, | |
642 | 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU | | |
643 | SND_SOC_DAPM_POST_PMD), | |
644 | ||
07cf7cba BL |
645 | /* Input Lines */ |
646 | SND_SOC_DAPM_INPUT("DMIC1 Pin"), | |
647 | SND_SOC_DAPM_INPUT("DMIC2 Pin"), | |
648 | SND_SOC_DAPM_INPUT("MIC1"), | |
649 | SND_SOC_DAPM_INPUT("LINE1"), | |
650 | SND_SOC_DAPM_INPUT("Beep"), | |
651 | ||
652 | /* DMIC */ | |
653 | SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1, | |
654 | NULL, 0, rt286_set_dmic1_event, | |
655 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
656 | SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1, | |
657 | NULL, 0), | |
658 | SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM, | |
659 | 0, 0, NULL, 0), | |
660 | ||
661 | /* REC Mixer */ | |
662 | SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0, | |
663 | rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)), | |
664 | ||
665 | /* ADCs */ | |
666 | SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0), | |
667 | SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0), | |
668 | ||
669 | /* ADC Mux */ | |
670 | SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1, | |
671 | &rt286_adc0_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD | | |
672 | SND_SOC_DAPM_POST_PMU), | |
673 | SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1, | |
674 | &rt286_adc1_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD | | |
675 | SND_SOC_DAPM_POST_PMU), | |
676 | ||
677 | /* Audio Interface */ | |
678 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
679 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
680 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
681 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
682 | ||
683 | /* Output Side */ | |
684 | /* DACs */ | |
685 | SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0), | |
686 | SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0), | |
687 | ||
688 | /* Output Mux */ | |
689 | SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux), | |
690 | SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux), | |
691 | ||
692 | SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO, | |
693 | RT286_SET_PIN_SFT, 0, NULL, 0), | |
694 | ||
695 | /* Output Mixer */ | |
696 | SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1, | |
697 | rt286_front_mix, ARRAY_SIZE(rt286_front_mix)), | |
698 | SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1, | |
699 | NULL, 0), | |
700 | ||
701 | /* Output Pga */ | |
702 | SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0, | |
703 | &spo_enable_control, rt286_spk_event, | |
704 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
705 | SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, | |
706 | &hpol_enable_control), | |
707 | SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, | |
708 | &hpor_enable_control), | |
709 | ||
710 | /* Output Lines */ | |
711 | SND_SOC_DAPM_OUTPUT("SPOL"), | |
712 | SND_SOC_DAPM_OUTPUT("SPOR"), | |
713 | SND_SOC_DAPM_OUTPUT("HPO Pin"), | |
714 | SND_SOC_DAPM_OUTPUT("SPDIF"), | |
715 | }; | |
716 | ||
717 | static const struct snd_soc_dapm_route rt286_dapm_routes[] = { | |
6879db76 BL |
718 | {"ADC 0", NULL, "MCLK MODE", is_mclk_mode}, |
719 | {"ADC 1", NULL, "MCLK MODE", is_mclk_mode}, | |
720 | {"Front", NULL, "MCLK MODE", is_mclk_mode}, | |
721 | {"Surround", NULL, "MCLK MODE", is_mclk_mode}, | |
722 | ||
723 | {"HP Power", NULL, "LDO1"}, | |
724 | {"HP Power", NULL, "LDO2"}, | |
725 | ||
726 | {"MIC1", NULL, "LDO1"}, | |
727 | {"MIC1", NULL, "LDO2"}, | |
728 | {"MIC1", NULL, "HV"}, | |
729 | {"MIC1", NULL, "VREF"}, | |
730 | {"MIC1", NULL, "MIC1 Input Buffer"}, | |
731 | ||
732 | {"SPO", NULL, "LDO1"}, | |
733 | {"SPO", NULL, "LDO2"}, | |
734 | {"SPO", NULL, "HV"}, | |
735 | {"SPO", NULL, "VREF"}, | |
736 | ||
07cf7cba BL |
737 | {"DMIC1", NULL, "DMIC1 Pin"}, |
738 | {"DMIC2", NULL, "DMIC2 Pin"}, | |
739 | {"DMIC1", NULL, "DMIC Receiver"}, | |
740 | {"DMIC2", NULL, "DMIC Receiver"}, | |
741 | ||
742 | {"RECMIX", "Beep Switch", "Beep"}, | |
743 | {"RECMIX", "Line1 Switch", "LINE1"}, | |
744 | {"RECMIX", "Mic1 Switch", "MIC1"}, | |
745 | ||
746 | {"ADC 0 Mux", "Dmic", "DMIC1"}, | |
747 | {"ADC 0 Mux", "RECMIX", "RECMIX"}, | |
748 | {"ADC 0 Mux", "Mic", "MIC1"}, | |
749 | {"ADC 1 Mux", "Dmic", "DMIC2"}, | |
750 | {"ADC 1 Mux", "RECMIX", "RECMIX"}, | |
751 | {"ADC 1 Mux", "Mic", "MIC1"}, | |
752 | ||
753 | {"ADC 0", NULL, "ADC 0 Mux"}, | |
754 | {"ADC 1", NULL, "ADC 1 Mux"}, | |
755 | ||
756 | {"AIF1TX", NULL, "ADC 0"}, | |
757 | {"AIF2TX", NULL, "ADC 1"}, | |
758 | ||
759 | {"DAC 0", NULL, "AIF1RX"}, | |
760 | {"DAC 1", NULL, "AIF2RX"}, | |
761 | ||
762 | {"Front", "DAC Switch", "DAC 0"}, | |
763 | {"Front", "RECMIX Switch", "RECMIX"}, | |
764 | ||
765 | {"Surround", NULL, "DAC 1"}, | |
766 | ||
767 | {"SPK Mux", "Front", "Front"}, | |
768 | {"SPK Mux", "Surround", "Surround"}, | |
769 | ||
770 | {"HPO Mux", "Front", "Front"}, | |
771 | {"HPO Mux", "Surround", "Surround"}, | |
772 | ||
773 | {"SPO", "Switch", "SPK Mux"}, | |
774 | {"HPO L", "Switch", "HPO Mux"}, | |
775 | {"HPO R", "Switch", "HPO Mux"}, | |
776 | {"HPO L", NULL, "HP Power"}, | |
777 | {"HPO R", NULL, "HP Power"}, | |
778 | ||
779 | {"SPOL", NULL, "SPO"}, | |
780 | {"SPOR", NULL, "SPO"}, | |
781 | {"HPO Pin", NULL, "HPO L"}, | |
782 | {"HPO Pin", NULL, "HPO R"}, | |
783 | }; | |
784 | ||
785 | static int rt286_hw_params(struct snd_pcm_substream *substream, | |
786 | struct snd_pcm_hw_params *params, | |
787 | struct snd_soc_dai *dai) | |
788 | { | |
789 | struct snd_soc_codec *codec = dai->codec; | |
790 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
791 | unsigned int val = 0; | |
792 | int d_len_code; | |
793 | ||
794 | switch (params_rate(params)) { | |
795 | /* bit 14 0:48K 1:44.1K */ | |
796 | case 44100: | |
797 | val |= 0x4000; | |
798 | break; | |
799 | case 48000: | |
800 | break; | |
801 | default: | |
802 | dev_err(codec->dev, "Unsupported sample rate %d\n", | |
803 | params_rate(params)); | |
804 | return -EINVAL; | |
805 | } | |
806 | switch (rt286->sys_clk) { | |
807 | case 12288000: | |
808 | case 24576000: | |
809 | if (params_rate(params) != 48000) { | |
810 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
811 | params_rate(params), rt286->sys_clk); | |
812 | return -EINVAL; | |
813 | } | |
814 | break; | |
815 | case 11289600: | |
816 | case 22579200: | |
817 | if (params_rate(params) != 44100) { | |
818 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
819 | params_rate(params), rt286->sys_clk); | |
820 | return -EINVAL; | |
821 | } | |
822 | break; | |
823 | } | |
824 | ||
825 | if (params_channels(params) <= 16) { | |
826 | /* bit 3:0 Number of Channel */ | |
827 | val |= (params_channels(params) - 1); | |
828 | } else { | |
829 | dev_err(codec->dev, "Unsupported channels %d\n", | |
830 | params_channels(params)); | |
831 | return -EINVAL; | |
832 | } | |
833 | ||
834 | d_len_code = 0; | |
835 | switch (params_width(params)) { | |
836 | /* bit 6:4 Bits per Sample */ | |
837 | case 16: | |
838 | d_len_code = 0; | |
839 | val |= (0x1 << 4); | |
840 | break; | |
841 | case 32: | |
842 | d_len_code = 2; | |
843 | val |= (0x4 << 4); | |
844 | break; | |
845 | case 20: | |
846 | d_len_code = 1; | |
847 | val |= (0x2 << 4); | |
848 | break; | |
849 | case 24: | |
850 | d_len_code = 2; | |
851 | val |= (0x3 << 4); | |
852 | break; | |
853 | case 8: | |
854 | d_len_code = 3; | |
855 | break; | |
856 | default: | |
857 | return -EINVAL; | |
858 | } | |
859 | ||
860 | snd_soc_update_bits(codec, | |
861 | RT286_I2S_CTRL1, 0x0018, d_len_code << 3); | |
862 | dev_dbg(codec->dev, "format val = 0x%x\n", val); | |
863 | ||
864 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
865 | snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val); | |
866 | else | |
867 | snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val); | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
873 | { | |
874 | struct snd_soc_codec *codec = dai->codec; | |
875 | ||
876 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
877 | case SND_SOC_DAIFMT_CBM_CFM: | |
878 | snd_soc_update_bits(codec, | |
879 | RT286_I2S_CTRL1, 0x800, 0x800); | |
880 | break; | |
881 | case SND_SOC_DAIFMT_CBS_CFS: | |
882 | snd_soc_update_bits(codec, | |
883 | RT286_I2S_CTRL1, 0x800, 0x0); | |
884 | break; | |
885 | default: | |
886 | return -EINVAL; | |
887 | } | |
888 | ||
889 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
890 | case SND_SOC_DAIFMT_I2S: | |
891 | snd_soc_update_bits(codec, | |
892 | RT286_I2S_CTRL1, 0x300, 0x0); | |
893 | break; | |
894 | case SND_SOC_DAIFMT_LEFT_J: | |
895 | snd_soc_update_bits(codec, | |
896 | RT286_I2S_CTRL1, 0x300, 0x1 << 8); | |
897 | break; | |
898 | case SND_SOC_DAIFMT_DSP_A: | |
899 | snd_soc_update_bits(codec, | |
900 | RT286_I2S_CTRL1, 0x300, 0x2 << 8); | |
901 | break; | |
902 | case SND_SOC_DAIFMT_DSP_B: | |
903 | snd_soc_update_bits(codec, | |
904 | RT286_I2S_CTRL1, 0x300, 0x3 << 8); | |
905 | break; | |
906 | default: | |
907 | return -EINVAL; | |
908 | } | |
909 | /* bit 15 Stream Type 0:PCM 1:Non-PCM */ | |
910 | snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0); | |
911 | snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0); | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
916 | static int rt286_set_dai_sysclk(struct snd_soc_dai *dai, | |
917 | int clk_id, unsigned int freq, int dir) | |
918 | { | |
919 | struct snd_soc_codec *codec = dai->codec; | |
920 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
921 | ||
922 | dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq); | |
923 | ||
924 | if (RT286_SCLK_S_MCLK == clk_id) { | |
925 | snd_soc_update_bits(codec, | |
926 | RT286_I2S_CTRL2, 0x0100, 0x0); | |
927 | snd_soc_update_bits(codec, | |
928 | RT286_PLL_CTRL1, 0x20, 0x20); | |
929 | } else { | |
930 | snd_soc_update_bits(codec, | |
931 | RT286_I2S_CTRL2, 0x0100, 0x0100); | |
932 | snd_soc_update_bits(codec, | |
933 | RT286_PLL_CTRL, 0x4, 0x4); | |
934 | snd_soc_update_bits(codec, | |
935 | RT286_PLL_CTRL1, 0x20, 0x0); | |
936 | } | |
937 | ||
938 | switch (freq) { | |
939 | case 19200000: | |
940 | if (RT286_SCLK_S_MCLK == clk_id) { | |
941 | dev_err(codec->dev, "Should not use MCLK\n"); | |
942 | return -EINVAL; | |
943 | } | |
944 | snd_soc_update_bits(codec, | |
945 | RT286_I2S_CTRL2, 0x40, 0x40); | |
946 | break; | |
947 | case 24000000: | |
948 | if (RT286_SCLK_S_MCLK == clk_id) { | |
949 | dev_err(codec->dev, "Should not use MCLK\n"); | |
950 | return -EINVAL; | |
951 | } | |
952 | snd_soc_update_bits(codec, | |
953 | RT286_I2S_CTRL2, 0x40, 0x0); | |
954 | break; | |
955 | case 12288000: | |
956 | case 11289600: | |
957 | snd_soc_update_bits(codec, | |
958 | RT286_I2S_CTRL2, 0x8, 0x0); | |
959 | snd_soc_update_bits(codec, | |
960 | RT286_CLK_DIV, 0xfc1e, 0x0004); | |
961 | break; | |
962 | case 24576000: | |
963 | case 22579200: | |
964 | snd_soc_update_bits(codec, | |
965 | RT286_I2S_CTRL2, 0x8, 0x8); | |
966 | snd_soc_update_bits(codec, | |
967 | RT286_CLK_DIV, 0xfc1e, 0x5406); | |
968 | break; | |
969 | default: | |
970 | dev_err(codec->dev, "Unsupported system clock\n"); | |
971 | return -EINVAL; | |
972 | } | |
973 | ||
974 | rt286->sys_clk = freq; | |
6879db76 | 975 | rt286->clk_id = clk_id; |
07cf7cba BL |
976 | |
977 | return 0; | |
978 | } | |
979 | ||
980 | static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) | |
981 | { | |
982 | struct snd_soc_codec *codec = dai->codec; | |
983 | ||
984 | dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio); | |
985 | if (50 == ratio) | |
986 | snd_soc_update_bits(codec, | |
987 | RT286_I2S_CTRL1, 0x1000, 0x1000); | |
988 | else | |
989 | snd_soc_update_bits(codec, | |
990 | RT286_I2S_CTRL1, 0x1000, 0x0); | |
991 | ||
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
996 | static int rt286_set_bias_level(struct snd_soc_codec *codec, | |
997 | enum snd_soc_bias_level level) | |
998 | { | |
999 | switch (level) { | |
1000 | case SND_SOC_BIAS_PREPARE: | |
bc6c4e45 | 1001 | if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) { |
07cf7cba BL |
1002 | snd_soc_write(codec, |
1003 | RT286_SET_AUDIO_POWER, AC_PWRST_D0); | |
bc6c4e45 BL |
1004 | snd_soc_update_bits(codec, |
1005 | RT286_DC_GAIN, 0x200, 0x200); | |
1006 | } | |
1007 | break; | |
1008 | ||
1009 | case SND_SOC_BIAS_ON: | |
1010 | mdelay(10); | |
6879db76 BL |
1011 | snd_soc_update_bits(codec, |
1012 | RT286_CBJ_CTRL1, 0x0400, 0x0400); | |
1013 | snd_soc_update_bits(codec, | |
1014 | RT286_DC_GAIN, 0x200, 0x0); | |
1015 | ||
07cf7cba BL |
1016 | break; |
1017 | ||
1018 | case SND_SOC_BIAS_STANDBY: | |
1019 | snd_soc_write(codec, | |
1020 | RT286_SET_AUDIO_POWER, AC_PWRST_D3); | |
bc6c4e45 | 1021 | snd_soc_update_bits(codec, |
6879db76 | 1022 | RT286_CBJ_CTRL1, 0x0400, 0x0000); |
07cf7cba BL |
1023 | break; |
1024 | ||
1025 | default: | |
1026 | break; | |
1027 | } | |
1028 | codec->dapm.bias_level = level; | |
1029 | ||
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | static irqreturn_t rt286_irq(int irq, void *data) | |
1034 | { | |
1035 | struct rt286_priv *rt286 = data; | |
1036 | bool hp = false; | |
1037 | bool mic = false; | |
1038 | int status = 0; | |
1039 | ||
90f601ef | 1040 | rt286_jack_detect(rt286, &hp, &mic); |
07cf7cba BL |
1041 | |
1042 | /* Clear IRQ */ | |
90f601ef | 1043 | regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1); |
07cf7cba BL |
1044 | |
1045 | if (hp == true) | |
1046 | status |= SND_JACK_HEADPHONE; | |
1047 | ||
1048 | if (mic == true) | |
1049 | status |= SND_JACK_MICROPHONE; | |
1050 | ||
1051 | snd_soc_jack_report(rt286->jack, status, | |
1052 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
1053 | ||
1054 | pm_wakeup_event(&rt286->i2c->dev, 300); | |
1055 | ||
1056 | return IRQ_HANDLED; | |
1057 | } | |
1058 | ||
1059 | static int rt286_probe(struct snd_soc_codec *codec) | |
1060 | { | |
1061 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
07cf7cba | 1062 | |
6879db76 | 1063 | rt286->codec = codec; |
07cf7cba | 1064 | codec->dapm.bias_level = SND_SOC_BIAS_OFF; |
90f601ef BL |
1065 | |
1066 | if (rt286->i2c->irq) { | |
1067 | regmap_update_bits(rt286->regmap, | |
1068 | RT286_IRQ_CTRL, 0x2, 0x2); | |
1069 | ||
1070 | INIT_DELAYED_WORK(&rt286->jack_detect_work, | |
1071 | rt286_jack_detect_work); | |
1072 | schedule_delayed_work(&rt286->jack_detect_work, | |
1073 | msecs_to_jiffies(1250)); | |
1074 | } | |
07cf7cba | 1075 | |
07cf7cba BL |
1076 | return 0; |
1077 | } | |
1078 | ||
1079 | static int rt286_remove(struct snd_soc_codec *codec) | |
1080 | { | |
1081 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
1082 | ||
1083 | cancel_delayed_work_sync(&rt286->jack_detect_work); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | #ifdef CONFIG_PM | |
1089 | static int rt286_suspend(struct snd_soc_codec *codec) | |
1090 | { | |
1091 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
1092 | ||
1093 | regcache_cache_only(rt286->regmap, true); | |
1094 | regcache_mark_dirty(rt286->regmap); | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | static int rt286_resume(struct snd_soc_codec *codec) | |
1100 | { | |
1101 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
1102 | ||
1103 | regcache_cache_only(rt286->regmap, false); | |
1104 | rt286_index_sync(codec); | |
1105 | regcache_sync(rt286->regmap); | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | #else | |
1110 | #define rt286_suspend NULL | |
1111 | #define rt286_resume NULL | |
1112 | #endif | |
1113 | ||
1114 | #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) | |
1115 | #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
1116 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | |
1117 | ||
1118 | static const struct snd_soc_dai_ops rt286_aif_dai_ops = { | |
1119 | .hw_params = rt286_hw_params, | |
1120 | .set_fmt = rt286_set_dai_fmt, | |
1121 | .set_sysclk = rt286_set_dai_sysclk, | |
1122 | .set_bclk_ratio = rt286_set_bclk_ratio, | |
1123 | }; | |
1124 | ||
1125 | static struct snd_soc_dai_driver rt286_dai[] = { | |
1126 | { | |
1127 | .name = "rt286-aif1", | |
1128 | .id = RT286_AIF1, | |
1129 | .playback = { | |
1130 | .stream_name = "AIF1 Playback", | |
1131 | .channels_min = 1, | |
1132 | .channels_max = 2, | |
1133 | .rates = RT286_STEREO_RATES, | |
1134 | .formats = RT286_FORMATS, | |
1135 | }, | |
1136 | .capture = { | |
1137 | .stream_name = "AIF1 Capture", | |
1138 | .channels_min = 1, | |
1139 | .channels_max = 2, | |
1140 | .rates = RT286_STEREO_RATES, | |
1141 | .formats = RT286_FORMATS, | |
1142 | }, | |
1143 | .ops = &rt286_aif_dai_ops, | |
1144 | .symmetric_rates = 1, | |
1145 | }, | |
1146 | { | |
1147 | .name = "rt286-aif2", | |
1148 | .id = RT286_AIF2, | |
1149 | .playback = { | |
1150 | .stream_name = "AIF2 Playback", | |
1151 | .channels_min = 1, | |
1152 | .channels_max = 2, | |
1153 | .rates = RT286_STEREO_RATES, | |
1154 | .formats = RT286_FORMATS, | |
1155 | }, | |
1156 | .capture = { | |
1157 | .stream_name = "AIF2 Capture", | |
1158 | .channels_min = 1, | |
1159 | .channels_max = 2, | |
1160 | .rates = RT286_STEREO_RATES, | |
1161 | .formats = RT286_FORMATS, | |
1162 | }, | |
1163 | .ops = &rt286_aif_dai_ops, | |
1164 | .symmetric_rates = 1, | |
1165 | }, | |
1166 | ||
1167 | }; | |
1168 | ||
1169 | static struct snd_soc_codec_driver soc_codec_dev_rt286 = { | |
1170 | .probe = rt286_probe, | |
1171 | .remove = rt286_remove, | |
1172 | .suspend = rt286_suspend, | |
1173 | .resume = rt286_resume, | |
1174 | .set_bias_level = rt286_set_bias_level, | |
1175 | .idle_bias_off = true, | |
1176 | .controls = rt286_snd_controls, | |
1177 | .num_controls = ARRAY_SIZE(rt286_snd_controls), | |
1178 | .dapm_widgets = rt286_dapm_widgets, | |
1179 | .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets), | |
1180 | .dapm_routes = rt286_dapm_routes, | |
1181 | .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes), | |
1182 | }; | |
1183 | ||
1184 | static const struct regmap_config rt286_regmap = { | |
1185 | .reg_bits = 32, | |
1186 | .val_bits = 32, | |
1187 | .max_register = 0x02370100, | |
1188 | .volatile_reg = rt286_volatile_register, | |
1189 | .readable_reg = rt286_readable_register, | |
1190 | .reg_write = rt286_hw_write, | |
1191 | .reg_read = rt286_hw_read, | |
1192 | .cache_type = REGCACHE_RBTREE, | |
1193 | .reg_defaults = rt286_reg, | |
1194 | .num_reg_defaults = ARRAY_SIZE(rt286_reg), | |
1195 | }; | |
1196 | ||
1197 | static const struct i2c_device_id rt286_i2c_id[] = { | |
1198 | {"rt286", 0}, | |
1199 | {} | |
1200 | }; | |
1201 | MODULE_DEVICE_TABLE(i2c, rt286_i2c_id); | |
1202 | ||
1203 | static const struct acpi_device_id rt286_acpi_match[] = { | |
1204 | { "INT343A", 0 }, | |
1205 | {}, | |
1206 | }; | |
1207 | MODULE_DEVICE_TABLE(acpi, rt286_acpi_match); | |
1208 | ||
a5a267cf | 1209 | static struct dmi_system_id force_combo_jack_table[] = { |
6c67cde2 BL |
1210 | { |
1211 | .ident = "Intel Wilson Beach", | |
1212 | .matches = { | |
1213 | DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS") | |
1214 | } | |
1215 | }, | |
1216 | { } | |
1217 | }; | |
1218 | ||
07cf7cba BL |
1219 | static int rt286_i2c_probe(struct i2c_client *i2c, |
1220 | const struct i2c_device_id *id) | |
1221 | { | |
1222 | struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev); | |
1223 | struct rt286_priv *rt286; | |
61a414c4 | 1224 | int i, ret; |
07cf7cba BL |
1225 | |
1226 | rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286), | |
1227 | GFP_KERNEL); | |
1228 | if (NULL == rt286) | |
1229 | return -ENOMEM; | |
1230 | ||
1231 | rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap); | |
1232 | if (IS_ERR(rt286->regmap)) { | |
1233 | ret = PTR_ERR(rt286->regmap); | |
1234 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
1235 | ret); | |
1236 | return ret; | |
1237 | } | |
1238 | ||
4b21768a BL |
1239 | regmap_read(rt286->regmap, |
1240 | RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret); | |
1241 | if (ret != RT286_VENDOR_ID) { | |
1242 | dev_err(&i2c->dev, | |
1243 | "Device with ID register %x is not rt286\n", ret); | |
1244 | return -ENODEV; | |
1245 | } | |
1246 | ||
07cf7cba BL |
1247 | rt286->index_cache = rt286_index_def; |
1248 | rt286->i2c = i2c; | |
1249 | i2c_set_clientdata(i2c, rt286); | |
1250 | ||
1251 | if (pdata) | |
1252 | rt286->pdata = *pdata; | |
1253 | ||
6c67cde2 BL |
1254 | if (dmi_check_system(force_combo_jack_table)) |
1255 | rt286->pdata.cbj_en = true; | |
1256 | ||
61a414c4 BL |
1257 | regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3); |
1258 | ||
1259 | for (i = 0; i < RT286_POWER_REG_LEN; i++) | |
1260 | regmap_write(rt286->regmap, | |
1261 | RT286_SET_POWER(rt286_support_power_controls[i]), | |
1262 | AC_PWRST_D1); | |
1263 | ||
1264 | if (!rt286->pdata.cbj_en) { | |
1265 | regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000); | |
1266 | regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816); | |
61a414c4 BL |
1267 | regmap_update_bits(rt286->regmap, |
1268 | RT286_CBJ_CTRL1, 0xf000, 0xb000); | |
1269 | } else { | |
1270 | regmap_update_bits(rt286->regmap, | |
1271 | RT286_CBJ_CTRL1, 0xf000, 0x5000); | |
1272 | } | |
1273 | ||
1274 | mdelay(10); | |
1275 | ||
1276 | if (!rt286->pdata.gpio2_en) | |
1277 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000); | |
1278 | else | |
1279 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0); | |
1280 | ||
1281 | mdelay(10); | |
1282 | ||
6879db76 | 1283 | regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000); |
f8c101bc | 1284 | /* Power down LDO, VREF */ |
6879db76 BL |
1285 | regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0); |
1286 | regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001); | |
61a414c4 | 1287 | |
f8c101bc | 1288 | /* Set depop parameter */ |
bc6c4e45 BL |
1289 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a); |
1290 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737); | |
1291 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f); | |
1292 | ||
61a414c4 | 1293 | if (rt286->i2c->irq) { |
61a414c4 BL |
1294 | ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, |
1295 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286); | |
1296 | if (ret != 0) { | |
1297 | dev_err(&i2c->dev, | |
1298 | "Failed to reguest IRQ: %d\n", ret); | |
1299 | return ret; | |
1300 | } | |
1301 | } | |
1302 | ||
07cf7cba BL |
1303 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286, |
1304 | rt286_dai, ARRAY_SIZE(rt286_dai)); | |
1305 | ||
1306 | return ret; | |
1307 | } | |
1308 | ||
1309 | static int rt286_i2c_remove(struct i2c_client *i2c) | |
1310 | { | |
1311 | struct rt286_priv *rt286 = i2c_get_clientdata(i2c); | |
1312 | ||
1313 | if (i2c->irq) | |
1314 | free_irq(i2c->irq, rt286); | |
1315 | snd_soc_unregister_codec(&i2c->dev); | |
1316 | ||
1317 | return 0; | |
1318 | } | |
1319 | ||
1320 | ||
23c4fd5c | 1321 | static struct i2c_driver rt286_i2c_driver = { |
07cf7cba BL |
1322 | .driver = { |
1323 | .name = "rt286", | |
1324 | .owner = THIS_MODULE, | |
1325 | .acpi_match_table = ACPI_PTR(rt286_acpi_match), | |
1326 | }, | |
1327 | .probe = rt286_i2c_probe, | |
1328 | .remove = rt286_i2c_remove, | |
1329 | .id_table = rt286_i2c_id, | |
1330 | }; | |
1331 | ||
1332 | module_i2c_driver(rt286_i2c_driver); | |
1333 | ||
1334 | MODULE_DESCRIPTION("ASoC RT286 driver"); | |
1335 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); | |
1336 | MODULE_LICENSE("GPL"); |