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07cf7cba BL |
1 | /* |
2 | * rt286.c -- RT286 ALSA SoC audio codec driver | |
3 | * | |
4 | * Copyright 2013 Realtek Semiconductor Corp. | |
5 | * Author: Bard Liao <bardliao@realtek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/spi/spi.h> | |
6c67cde2 | 20 | #include <linux/dmi.h> |
07cf7cba BL |
21 | #include <linux/acpi.h> |
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/soc-dapm.h> | |
27 | #include <sound/initval.h> | |
28 | #include <sound/tlv.h> | |
29 | #include <sound/jack.h> | |
30 | #include <linux/workqueue.h> | |
31 | #include <sound/rt286.h> | |
07cf7cba | 32 | |
bc08f96b | 33 | #include "rl6347a.h" |
07cf7cba BL |
34 | #include "rt286.h" |
35 | ||
36 | #define RT286_VENDOR_ID 0x10ec0286 | |
3ab888db | 37 | #define RT288_VENDOR_ID 0x10ec0288 |
07cf7cba BL |
38 | |
39 | struct rt286_priv { | |
dc6d84c6 | 40 | struct reg_default *index_cache; |
bc08f96b | 41 | int index_cache_size; |
07cf7cba | 42 | struct regmap *regmap; |
6879db76 | 43 | struct snd_soc_codec *codec; |
07cf7cba BL |
44 | struct rt286_platform_data pdata; |
45 | struct i2c_client *i2c; | |
46 | struct snd_soc_jack *jack; | |
47 | struct delayed_work jack_detect_work; | |
48 | int sys_clk; | |
6879db76 | 49 | int clk_id; |
07cf7cba BL |
50 | }; |
51 | ||
c418a84a | 52 | static const struct reg_default rt286_index_def[] = { |
07cf7cba BL |
53 | { 0x01, 0xaaaa }, |
54 | { 0x02, 0x8aaa }, | |
55 | { 0x03, 0x0002 }, | |
56 | { 0x04, 0xaf01 }, | |
57 | { 0x08, 0x000d }, | |
58 | { 0x09, 0xd810 }, | |
b7a29767 | 59 | { 0x0a, 0x0120 }, |
07cf7cba | 60 | { 0x0b, 0x0000 }, |
bc6c4e45 | 61 | { 0x0d, 0x2800 }, |
07cf7cba BL |
62 | { 0x0f, 0x0000 }, |
63 | { 0x19, 0x0a17 }, | |
64 | { 0x20, 0x0020 }, | |
65 | { 0x33, 0x0208 }, | |
66 | { 0x49, 0x0004 }, | |
67 | { 0x4f, 0x50e9 }, | |
b7a29767 | 68 | { 0x50, 0x2000 }, |
07cf7cba | 69 | { 0x63, 0x2902 }, |
bc6c4e45 BL |
70 | { 0x67, 0x1111 }, |
71 | { 0x68, 0x1016 }, | |
72 | { 0x69, 0x273f }, | |
07cf7cba BL |
73 | }; |
74 | #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def) | |
75 | ||
76 | static const struct reg_default rt286_reg[] = { | |
77 | { 0x00170500, 0x00000400 }, | |
78 | { 0x00220000, 0x00000031 }, | |
79 | { 0x00239000, 0x0000007f }, | |
80 | { 0x0023a000, 0x0000007f }, | |
81 | { 0x00270500, 0x00000400 }, | |
82 | { 0x00370500, 0x00000400 }, | |
83 | { 0x00870500, 0x00000400 }, | |
84 | { 0x00920000, 0x00000031 }, | |
85 | { 0x00935000, 0x000000c3 }, | |
86 | { 0x00936000, 0x000000c3 }, | |
87 | { 0x00970500, 0x00000400 }, | |
88 | { 0x00b37000, 0x00000097 }, | |
89 | { 0x00b37200, 0x00000097 }, | |
90 | { 0x00b37300, 0x00000097 }, | |
91 | { 0x00c37000, 0x00000000 }, | |
92 | { 0x00c37100, 0x00000080 }, | |
93 | { 0x01270500, 0x00000400 }, | |
94 | { 0x01370500, 0x00000400 }, | |
95 | { 0x01371f00, 0x411111f0 }, | |
96 | { 0x01439000, 0x00000080 }, | |
97 | { 0x0143a000, 0x00000080 }, | |
98 | { 0x01470700, 0x00000000 }, | |
99 | { 0x01470500, 0x00000400 }, | |
100 | { 0x01470c00, 0x00000000 }, | |
101 | { 0x01470100, 0x00000000 }, | |
102 | { 0x01837000, 0x00000000 }, | |
103 | { 0x01870500, 0x00000400 }, | |
104 | { 0x02050000, 0x00000000 }, | |
105 | { 0x02139000, 0x00000080 }, | |
106 | { 0x0213a000, 0x00000080 }, | |
107 | { 0x02170100, 0x00000000 }, | |
108 | { 0x02170500, 0x00000400 }, | |
109 | { 0x02170700, 0x00000000 }, | |
110 | { 0x02270100, 0x00000000 }, | |
111 | { 0x02370100, 0x00000000 }, | |
07cf7cba BL |
112 | { 0x01870700, 0x00000020 }, |
113 | { 0x00830000, 0x000000c3 }, | |
114 | { 0x00930000, 0x000000c3 }, | |
115 | { 0x01270700, 0x00000000 }, | |
116 | }; | |
117 | ||
118 | static bool rt286_volatile_register(struct device *dev, unsigned int reg) | |
119 | { | |
120 | switch (reg) { | |
121 | case 0 ... 0xff: | |
122 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
123 | case RT286_GET_HP_SENSE: | |
124 | case RT286_GET_MIC1_SENSE: | |
125 | case RT286_PROC_COEF: | |
126 | return true; | |
127 | default: | |
128 | return false; | |
129 | } | |
130 | ||
131 | ||
132 | } | |
133 | ||
134 | static bool rt286_readable_register(struct device *dev, unsigned int reg) | |
135 | { | |
136 | switch (reg) { | |
137 | case 0 ... 0xff: | |
138 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
139 | case RT286_GET_HP_SENSE: | |
140 | case RT286_GET_MIC1_SENSE: | |
141 | case RT286_SET_AUDIO_POWER: | |
142 | case RT286_SET_HPO_POWER: | |
143 | case RT286_SET_SPK_POWER: | |
144 | case RT286_SET_DMIC1_POWER: | |
145 | case RT286_SPK_MUX: | |
146 | case RT286_HPO_MUX: | |
147 | case RT286_ADC0_MUX: | |
148 | case RT286_ADC1_MUX: | |
149 | case RT286_SET_MIC1: | |
150 | case RT286_SET_PIN_HPO: | |
151 | case RT286_SET_PIN_SPK: | |
152 | case RT286_SET_PIN_DMIC1: | |
153 | case RT286_SPK_EAPD: | |
154 | case RT286_SET_AMP_GAIN_HPO: | |
155 | case RT286_SET_DMIC2_DEFAULT: | |
156 | case RT286_DACL_GAIN: | |
157 | case RT286_DACR_GAIN: | |
158 | case RT286_ADCL_GAIN: | |
159 | case RT286_ADCR_GAIN: | |
160 | case RT286_MIC_GAIN: | |
161 | case RT286_SPOL_GAIN: | |
162 | case RT286_SPOR_GAIN: | |
163 | case RT286_HPOL_GAIN: | |
164 | case RT286_HPOR_GAIN: | |
165 | case RT286_F_DAC_SWITCH: | |
166 | case RT286_F_RECMIX_SWITCH: | |
167 | case RT286_REC_MIC_SWITCH: | |
168 | case RT286_REC_I2S_SWITCH: | |
169 | case RT286_REC_LINE_SWITCH: | |
170 | case RT286_REC_BEEP_SWITCH: | |
171 | case RT286_DAC_FORMAT: | |
172 | case RT286_ADC_FORMAT: | |
173 | case RT286_COEF_INDEX: | |
174 | case RT286_PROC_COEF: | |
175 | case RT286_SET_AMP_GAIN_ADC_IN1: | |
176 | case RT286_SET_AMP_GAIN_ADC_IN2: | |
177 | case RT286_SET_POWER(RT286_DAC_OUT1): | |
178 | case RT286_SET_POWER(RT286_DAC_OUT2): | |
179 | case RT286_SET_POWER(RT286_ADC_IN1): | |
180 | case RT286_SET_POWER(RT286_ADC_IN2): | |
181 | case RT286_SET_POWER(RT286_DMIC2): | |
182 | case RT286_SET_POWER(RT286_MIC1): | |
183 | return true; | |
184 | default: | |
185 | return false; | |
186 | } | |
187 | } | |
188 | ||
81f3dfe1 | 189 | #ifdef CONFIG_PM |
07cf7cba BL |
190 | static void rt286_index_sync(struct snd_soc_codec *codec) |
191 | { | |
192 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
193 | int i; | |
194 | ||
195 | for (i = 0; i < INDEX_CACHE_SIZE; i++) { | |
196 | snd_soc_write(codec, rt286->index_cache[i].reg, | |
197 | rt286->index_cache[i].def); | |
198 | } | |
199 | } | |
81f3dfe1 | 200 | #endif |
07cf7cba BL |
201 | |
202 | static int rt286_support_power_controls[] = { | |
203 | RT286_DAC_OUT1, | |
204 | RT286_DAC_OUT2, | |
205 | RT286_ADC_IN1, | |
206 | RT286_ADC_IN2, | |
207 | RT286_MIC1, | |
208 | RT286_DMIC1, | |
209 | RT286_DMIC2, | |
210 | RT286_SPK_OUT, | |
211 | RT286_HP_OUT, | |
212 | }; | |
213 | #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls) | |
214 | ||
90f601ef | 215 | static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic) |
07cf7cba | 216 | { |
b1cd8457 | 217 | struct snd_soc_dapm_context *dapm; |
07cf7cba | 218 | unsigned int val, buf; |
07cf7cba BL |
219 | |
220 | *hp = false; | |
221 | *mic = false; | |
222 | ||
28d1ad09 BL |
223 | if (!rt286->codec) |
224 | return -EINVAL; | |
b1cd8457 LPC |
225 | |
226 | dapm = snd_soc_codec_get_dapm(rt286->codec); | |
227 | ||
07cf7cba | 228 | if (rt286->pdata.cbj_en) { |
90f601ef | 229 | regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf); |
07cf7cba BL |
230 | *hp = buf & 0x80000000; |
231 | if (*hp) { | |
232 | /* power on HV,VERF */ | |
90f601ef | 233 | regmap_update_bits(rt286->regmap, |
6879db76 BL |
234 | RT286_DC_GAIN, 0x200, 0x200); |
235 | ||
b1cd8457 LPC |
236 | snd_soc_dapm_force_enable_pin(dapm, "HV"); |
237 | snd_soc_dapm_force_enable_pin(dapm, "VREF"); | |
07cf7cba | 238 | /* power LDO1 */ |
b1cd8457 LPC |
239 | snd_soc_dapm_force_enable_pin(dapm, "LDO1"); |
240 | snd_soc_dapm_sync(dapm); | |
07cf7cba | 241 | |
6879db76 BL |
242 | regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24); |
243 | msleep(50); | |
07cf7cba | 244 | |
6879db76 BL |
245 | regmap_update_bits(rt286->regmap, |
246 | RT286_CBJ_CTRL1, 0xfcc0, 0xd400); | |
247 | msleep(300); | |
248 | regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val); | |
07cf7cba | 249 | |
6879db76 | 250 | if (0x0070 == (val & 0x0070)) { |
07cf7cba | 251 | *mic = true; |
07cf7cba | 252 | } else { |
6879db76 BL |
253 | regmap_update_bits(rt286->regmap, |
254 | RT286_CBJ_CTRL1, 0xfcc0, 0xe400); | |
255 | msleep(300); | |
256 | regmap_read(rt286->regmap, | |
257 | RT286_CBJ_CTRL2, &val); | |
258 | if (0x0070 == (val & 0x0070)) | |
259 | *mic = true; | |
260 | else | |
261 | *mic = false; | |
07cf7cba | 262 | } |
90f601ef | 263 | regmap_update_bits(rt286->regmap, |
6879db76 | 264 | RT286_DC_GAIN, 0x200, 0x0); |
07cf7cba | 265 | |
6879db76 | 266 | } else { |
07cf7cba | 267 | *mic = false; |
6879db76 | 268 | regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20); |
07cf7cba BL |
269 | } |
270 | } else { | |
90f601ef | 271 | regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf); |
07cf7cba | 272 | *hp = buf & 0x80000000; |
90f601ef | 273 | regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf); |
07cf7cba BL |
274 | *mic = buf & 0x80000000; |
275 | } | |
276 | ||
b1cd8457 LPC |
277 | snd_soc_dapm_disable_pin(dapm, "HV"); |
278 | snd_soc_dapm_disable_pin(dapm, "VREF"); | |
6879db76 | 279 | if (!*hp) |
b1cd8457 LPC |
280 | snd_soc_dapm_disable_pin(dapm, "LDO1"); |
281 | snd_soc_dapm_sync(dapm); | |
6879db76 | 282 | |
07cf7cba BL |
283 | return 0; |
284 | } | |
285 | ||
286 | static void rt286_jack_detect_work(struct work_struct *work) | |
287 | { | |
288 | struct rt286_priv *rt286 = | |
289 | container_of(work, struct rt286_priv, jack_detect_work.work); | |
290 | int status = 0; | |
291 | bool hp = false; | |
292 | bool mic = false; | |
293 | ||
90f601ef | 294 | rt286_jack_detect(rt286, &hp, &mic); |
07cf7cba BL |
295 | |
296 | if (hp == true) | |
297 | status |= SND_JACK_HEADPHONE; | |
298 | ||
299 | if (mic == true) | |
300 | status |= SND_JACK_MICROPHONE; | |
301 | ||
302 | snd_soc_jack_report(rt286->jack, status, | |
303 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
304 | } | |
305 | ||
306 | int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) | |
307 | { | |
b1cd8457 | 308 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
07cf7cba BL |
309 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); |
310 | ||
311 | rt286->jack = jack; | |
312 | ||
e2cef68d JY |
313 | if (jack) { |
314 | /* enable IRQ */ | |
5af76d5c | 315 | if (rt286->jack->status & SND_JACK_HEADPHONE) |
b1cd8457 | 316 | snd_soc_dapm_force_enable_pin(dapm, "LDO1"); |
e2cef68d JY |
317 | regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2); |
318 | /* Send an initial empty report */ | |
319 | snd_soc_jack_report(rt286->jack, rt286->jack->status, | |
320 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
321 | } else { | |
322 | /* disable IRQ */ | |
323 | regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0); | |
b1cd8457 | 324 | snd_soc_dapm_disable_pin(dapm, "LDO1"); |
e2cef68d | 325 | } |
b1cd8457 | 326 | snd_soc_dapm_sync(dapm); |
07cf7cba BL |
327 | |
328 | return 0; | |
329 | } | |
330 | EXPORT_SYMBOL_GPL(rt286_mic_detect); | |
331 | ||
6879db76 BL |
332 | static int is_mclk_mode(struct snd_soc_dapm_widget *source, |
333 | struct snd_soc_dapm_widget *sink) | |
334 | { | |
76f17f18 LPC |
335 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
336 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
6879db76 BL |
337 | |
338 | if (rt286->clk_id == RT286_SCLK_S_MCLK) | |
339 | return 1; | |
340 | else | |
341 | return 0; | |
342 | } | |
343 | ||
07cf7cba BL |
344 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); |
345 | static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); | |
346 | ||
347 | static const struct snd_kcontrol_new rt286_snd_controls[] = { | |
348 | SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN, | |
349 | RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
54d96a40 BL |
350 | SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN, |
351 | RT286_ADCR_GAIN, 7, 1, 1), | |
07cf7cba BL |
352 | SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN, |
353 | RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
354 | SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN, | |
355 | 0, 0x3, 0, mic_vol_tlv), | |
356 | SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN, | |
357 | RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1), | |
358 | }; | |
359 | ||
360 | /* Digital Mixer */ | |
361 | static const struct snd_kcontrol_new rt286_front_mix[] = { | |
362 | SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH, | |
363 | RT286_MUTE_SFT, 1, 1), | |
364 | SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH, | |
365 | RT286_MUTE_SFT, 1, 1), | |
366 | }; | |
367 | ||
368 | /* Analog Input Mixer */ | |
369 | static const struct snd_kcontrol_new rt286_rec_mix[] = { | |
370 | SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH, | |
371 | RT286_MUTE_SFT, 1, 1), | |
372 | SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH, | |
373 | RT286_MUTE_SFT, 1, 1), | |
374 | SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH, | |
375 | RT286_MUTE_SFT, 1, 1), | |
376 | SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH, | |
377 | RT286_MUTE_SFT, 1, 1), | |
378 | }; | |
379 | ||
380 | static const struct snd_kcontrol_new spo_enable_control = | |
381 | SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK, | |
382 | RT286_SET_PIN_SFT, 1, 0); | |
383 | ||
384 | static const struct snd_kcontrol_new hpol_enable_control = | |
385 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN, | |
386 | RT286_MUTE_SFT, 1, 1); | |
387 | ||
388 | static const struct snd_kcontrol_new hpor_enable_control = | |
389 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN, | |
390 | RT286_MUTE_SFT, 1, 1); | |
391 | ||
392 | /* ADC0 source */ | |
393 | static const char * const rt286_adc_src[] = { | |
394 | "Mic", "RECMIX", "Dmic" | |
395 | }; | |
396 | ||
397 | static const int rt286_adc_values[] = { | |
398 | 0, 4, 5, | |
399 | }; | |
400 | ||
401 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
402 | rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT, | |
403 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
404 | ||
405 | static const struct snd_kcontrol_new rt286_adc0_mux = | |
406 | SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum); | |
407 | ||
408 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
409 | rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT, | |
410 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
411 | ||
412 | static const struct snd_kcontrol_new rt286_adc1_mux = | |
413 | SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum); | |
414 | ||
415 | static const char * const rt286_dac_src[] = { | |
416 | "Front", "Surround" | |
417 | }; | |
418 | /* HP-OUT source */ | |
419 | static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX, | |
420 | 0, rt286_dac_src); | |
421 | ||
422 | static const struct snd_kcontrol_new rt286_hpo_mux = | |
423 | SOC_DAPM_ENUM("HPO source", rt286_hpo_enum); | |
424 | ||
425 | /* SPK-OUT source */ | |
426 | static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX, | |
427 | 0, rt286_dac_src); | |
428 | ||
429 | static const struct snd_kcontrol_new rt286_spo_mux = | |
430 | SOC_DAPM_ENUM("SPO source", rt286_spo_enum); | |
431 | ||
432 | static int rt286_spk_event(struct snd_soc_dapm_widget *w, | |
433 | struct snd_kcontrol *kcontrol, int event) | |
434 | { | |
76f17f18 | 435 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
07cf7cba BL |
436 | |
437 | switch (event) { | |
438 | case SND_SOC_DAPM_POST_PMU: | |
439 | snd_soc_write(codec, | |
440 | RT286_SPK_EAPD, RT286_SET_EAPD_HIGH); | |
441 | break; | |
442 | case SND_SOC_DAPM_PRE_PMD: | |
443 | snd_soc_write(codec, | |
444 | RT286_SPK_EAPD, RT286_SET_EAPD_LOW); | |
445 | break; | |
446 | ||
447 | default: | |
448 | return 0; | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w, | |
455 | struct snd_kcontrol *kcontrol, int event) | |
456 | { | |
76f17f18 | 457 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
07cf7cba BL |
458 | |
459 | switch (event) { | |
460 | case SND_SOC_DAPM_POST_PMU: | |
461 | snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20); | |
462 | break; | |
463 | case SND_SOC_DAPM_PRE_PMD: | |
464 | snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0); | |
465 | break; | |
466 | default: | |
467 | return 0; | |
468 | } | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
6879db76 BL |
473 | static int rt286_vref_event(struct snd_soc_dapm_widget *w, |
474 | struct snd_kcontrol *kcontrol, int event) | |
475 | { | |
76f17f18 | 476 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
6879db76 BL |
477 | |
478 | switch (event) { | |
479 | case SND_SOC_DAPM_PRE_PMU: | |
480 | snd_soc_update_bits(codec, | |
481 | RT286_CBJ_CTRL1, 0x0400, 0x0000); | |
482 | mdelay(50); | |
483 | break; | |
484 | default: | |
485 | return 0; | |
486 | } | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
491 | static int rt286_ldo2_event(struct snd_soc_dapm_widget *w, | |
492 | struct snd_kcontrol *kcontrol, int event) | |
493 | { | |
76f17f18 | 494 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
6879db76 BL |
495 | |
496 | switch (event) { | |
497 | case SND_SOC_DAPM_POST_PMU: | |
498 | snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08); | |
499 | break; | |
500 | case SND_SOC_DAPM_PRE_PMD: | |
501 | snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30); | |
502 | break; | |
503 | default: | |
504 | return 0; | |
505 | } | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static int rt286_mic1_event(struct snd_soc_dapm_widget *w, | |
511 | struct snd_kcontrol *kcontrol, int event) | |
512 | { | |
76f17f18 | 513 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
6879db76 BL |
514 | |
515 | switch (event) { | |
516 | case SND_SOC_DAPM_PRE_PMU: | |
517 | snd_soc_update_bits(codec, | |
518 | RT286_A_BIAS_CTRL3, 0xc000, 0x8000); | |
519 | snd_soc_update_bits(codec, | |
520 | RT286_A_BIAS_CTRL2, 0xc000, 0x8000); | |
521 | break; | |
522 | case SND_SOC_DAPM_POST_PMD: | |
523 | snd_soc_update_bits(codec, | |
524 | RT286_A_BIAS_CTRL3, 0xc000, 0x0000); | |
525 | snd_soc_update_bits(codec, | |
526 | RT286_A_BIAS_CTRL2, 0xc000, 0x0000); | |
527 | break; | |
528 | default: | |
529 | return 0; | |
530 | } | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
07cf7cba | 535 | static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = { |
6879db76 BL |
536 | SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1, |
537 | 12, 1, NULL, 0), | |
538 | SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1, | |
539 | 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU), | |
540 | SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2, | |
541 | 2, 0, NULL, 0), | |
542 | SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1, | |
543 | 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD | | |
544 | SND_SOC_DAPM_POST_PMU), | |
545 | SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1, | |
546 | 5, 0, NULL, 0), | |
547 | SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM, | |
548 | 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU | | |
549 | SND_SOC_DAPM_POST_PMD), | |
550 | ||
07cf7cba BL |
551 | /* Input Lines */ |
552 | SND_SOC_DAPM_INPUT("DMIC1 Pin"), | |
553 | SND_SOC_DAPM_INPUT("DMIC2 Pin"), | |
554 | SND_SOC_DAPM_INPUT("MIC1"), | |
555 | SND_SOC_DAPM_INPUT("LINE1"), | |
556 | SND_SOC_DAPM_INPUT("Beep"), | |
557 | ||
558 | /* DMIC */ | |
559 | SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1, | |
560 | NULL, 0, rt286_set_dmic1_event, | |
561 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
562 | SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1, | |
563 | NULL, 0), | |
564 | SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM, | |
565 | 0, 0, NULL, 0), | |
566 | ||
567 | /* REC Mixer */ | |
568 | SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0, | |
569 | rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)), | |
570 | ||
571 | /* ADCs */ | |
572 | SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0), | |
573 | SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0), | |
574 | ||
575 | /* ADC Mux */ | |
54d96a40 BL |
576 | SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1, |
577 | &rt286_adc0_mux), | |
578 | SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1, | |
579 | &rt286_adc1_mux), | |
07cf7cba BL |
580 | |
581 | /* Audio Interface */ | |
582 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
583 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
584 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
585 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
586 | ||
587 | /* Output Side */ | |
588 | /* DACs */ | |
589 | SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0), | |
590 | SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0), | |
591 | ||
592 | /* Output Mux */ | |
593 | SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux), | |
594 | SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux), | |
595 | ||
596 | SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO, | |
597 | RT286_SET_PIN_SFT, 0, NULL, 0), | |
598 | ||
599 | /* Output Mixer */ | |
600 | SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1, | |
601 | rt286_front_mix, ARRAY_SIZE(rt286_front_mix)), | |
602 | SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1, | |
603 | NULL, 0), | |
604 | ||
605 | /* Output Pga */ | |
606 | SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0, | |
607 | &spo_enable_control, rt286_spk_event, | |
608 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
609 | SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, | |
610 | &hpol_enable_control), | |
611 | SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, | |
612 | &hpor_enable_control), | |
613 | ||
614 | /* Output Lines */ | |
615 | SND_SOC_DAPM_OUTPUT("SPOL"), | |
616 | SND_SOC_DAPM_OUTPUT("SPOR"), | |
617 | SND_SOC_DAPM_OUTPUT("HPO Pin"), | |
618 | SND_SOC_DAPM_OUTPUT("SPDIF"), | |
619 | }; | |
620 | ||
621 | static const struct snd_soc_dapm_route rt286_dapm_routes[] = { | |
6879db76 BL |
622 | {"ADC 0", NULL, "MCLK MODE", is_mclk_mode}, |
623 | {"ADC 1", NULL, "MCLK MODE", is_mclk_mode}, | |
624 | {"Front", NULL, "MCLK MODE", is_mclk_mode}, | |
625 | {"Surround", NULL, "MCLK MODE", is_mclk_mode}, | |
626 | ||
627 | {"HP Power", NULL, "LDO1"}, | |
628 | {"HP Power", NULL, "LDO2"}, | |
629 | ||
630 | {"MIC1", NULL, "LDO1"}, | |
631 | {"MIC1", NULL, "LDO2"}, | |
632 | {"MIC1", NULL, "HV"}, | |
633 | {"MIC1", NULL, "VREF"}, | |
634 | {"MIC1", NULL, "MIC1 Input Buffer"}, | |
635 | ||
636 | {"SPO", NULL, "LDO1"}, | |
637 | {"SPO", NULL, "LDO2"}, | |
638 | {"SPO", NULL, "HV"}, | |
639 | {"SPO", NULL, "VREF"}, | |
640 | ||
07cf7cba BL |
641 | {"DMIC1", NULL, "DMIC1 Pin"}, |
642 | {"DMIC2", NULL, "DMIC2 Pin"}, | |
643 | {"DMIC1", NULL, "DMIC Receiver"}, | |
644 | {"DMIC2", NULL, "DMIC Receiver"}, | |
645 | ||
646 | {"RECMIX", "Beep Switch", "Beep"}, | |
647 | {"RECMIX", "Line1 Switch", "LINE1"}, | |
648 | {"RECMIX", "Mic1 Switch", "MIC1"}, | |
649 | ||
650 | {"ADC 0 Mux", "Dmic", "DMIC1"}, | |
651 | {"ADC 0 Mux", "RECMIX", "RECMIX"}, | |
652 | {"ADC 0 Mux", "Mic", "MIC1"}, | |
653 | {"ADC 1 Mux", "Dmic", "DMIC2"}, | |
654 | {"ADC 1 Mux", "RECMIX", "RECMIX"}, | |
655 | {"ADC 1 Mux", "Mic", "MIC1"}, | |
656 | ||
657 | {"ADC 0", NULL, "ADC 0 Mux"}, | |
658 | {"ADC 1", NULL, "ADC 1 Mux"}, | |
659 | ||
660 | {"AIF1TX", NULL, "ADC 0"}, | |
661 | {"AIF2TX", NULL, "ADC 1"}, | |
662 | ||
663 | {"DAC 0", NULL, "AIF1RX"}, | |
664 | {"DAC 1", NULL, "AIF2RX"}, | |
665 | ||
666 | {"Front", "DAC Switch", "DAC 0"}, | |
667 | {"Front", "RECMIX Switch", "RECMIX"}, | |
668 | ||
669 | {"Surround", NULL, "DAC 1"}, | |
670 | ||
671 | {"SPK Mux", "Front", "Front"}, | |
672 | {"SPK Mux", "Surround", "Surround"}, | |
673 | ||
674 | {"HPO Mux", "Front", "Front"}, | |
675 | {"HPO Mux", "Surround", "Surround"}, | |
676 | ||
677 | {"SPO", "Switch", "SPK Mux"}, | |
678 | {"HPO L", "Switch", "HPO Mux"}, | |
679 | {"HPO R", "Switch", "HPO Mux"}, | |
680 | {"HPO L", NULL, "HP Power"}, | |
681 | {"HPO R", NULL, "HP Power"}, | |
682 | ||
683 | {"SPOL", NULL, "SPO"}, | |
684 | {"SPOR", NULL, "SPO"}, | |
685 | {"HPO Pin", NULL, "HPO L"}, | |
686 | {"HPO Pin", NULL, "HPO R"}, | |
687 | }; | |
688 | ||
689 | static int rt286_hw_params(struct snd_pcm_substream *substream, | |
690 | struct snd_pcm_hw_params *params, | |
691 | struct snd_soc_dai *dai) | |
692 | { | |
693 | struct snd_soc_codec *codec = dai->codec; | |
694 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
695 | unsigned int val = 0; | |
696 | int d_len_code; | |
697 | ||
698 | switch (params_rate(params)) { | |
699 | /* bit 14 0:48K 1:44.1K */ | |
700 | case 44100: | |
701 | val |= 0x4000; | |
702 | break; | |
703 | case 48000: | |
704 | break; | |
705 | default: | |
706 | dev_err(codec->dev, "Unsupported sample rate %d\n", | |
707 | params_rate(params)); | |
708 | return -EINVAL; | |
709 | } | |
710 | switch (rt286->sys_clk) { | |
711 | case 12288000: | |
712 | case 24576000: | |
713 | if (params_rate(params) != 48000) { | |
714 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
715 | params_rate(params), rt286->sys_clk); | |
716 | return -EINVAL; | |
717 | } | |
718 | break; | |
719 | case 11289600: | |
720 | case 22579200: | |
721 | if (params_rate(params) != 44100) { | |
722 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
723 | params_rate(params), rt286->sys_clk); | |
724 | return -EINVAL; | |
725 | } | |
726 | break; | |
727 | } | |
728 | ||
729 | if (params_channels(params) <= 16) { | |
730 | /* bit 3:0 Number of Channel */ | |
731 | val |= (params_channels(params) - 1); | |
732 | } else { | |
733 | dev_err(codec->dev, "Unsupported channels %d\n", | |
734 | params_channels(params)); | |
735 | return -EINVAL; | |
736 | } | |
737 | ||
738 | d_len_code = 0; | |
739 | switch (params_width(params)) { | |
740 | /* bit 6:4 Bits per Sample */ | |
741 | case 16: | |
742 | d_len_code = 0; | |
743 | val |= (0x1 << 4); | |
744 | break; | |
745 | case 32: | |
746 | d_len_code = 2; | |
747 | val |= (0x4 << 4); | |
748 | break; | |
749 | case 20: | |
750 | d_len_code = 1; | |
751 | val |= (0x2 << 4); | |
752 | break; | |
753 | case 24: | |
754 | d_len_code = 2; | |
755 | val |= (0x3 << 4); | |
756 | break; | |
757 | case 8: | |
758 | d_len_code = 3; | |
759 | break; | |
760 | default: | |
761 | return -EINVAL; | |
762 | } | |
763 | ||
764 | snd_soc_update_bits(codec, | |
765 | RT286_I2S_CTRL1, 0x0018, d_len_code << 3); | |
766 | dev_dbg(codec->dev, "format val = 0x%x\n", val); | |
767 | ||
45437fa5 BL |
768 | snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val); |
769 | snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val); | |
07cf7cba BL |
770 | |
771 | return 0; | |
772 | } | |
773 | ||
774 | static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
775 | { | |
776 | struct snd_soc_codec *codec = dai->codec; | |
777 | ||
778 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
779 | case SND_SOC_DAIFMT_CBM_CFM: | |
780 | snd_soc_update_bits(codec, | |
781 | RT286_I2S_CTRL1, 0x800, 0x800); | |
782 | break; | |
783 | case SND_SOC_DAIFMT_CBS_CFS: | |
784 | snd_soc_update_bits(codec, | |
785 | RT286_I2S_CTRL1, 0x800, 0x0); | |
786 | break; | |
787 | default: | |
788 | return -EINVAL; | |
789 | } | |
790 | ||
791 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
792 | case SND_SOC_DAIFMT_I2S: | |
793 | snd_soc_update_bits(codec, | |
794 | RT286_I2S_CTRL1, 0x300, 0x0); | |
795 | break; | |
796 | case SND_SOC_DAIFMT_LEFT_J: | |
797 | snd_soc_update_bits(codec, | |
798 | RT286_I2S_CTRL1, 0x300, 0x1 << 8); | |
799 | break; | |
800 | case SND_SOC_DAIFMT_DSP_A: | |
801 | snd_soc_update_bits(codec, | |
802 | RT286_I2S_CTRL1, 0x300, 0x2 << 8); | |
803 | break; | |
804 | case SND_SOC_DAIFMT_DSP_B: | |
805 | snd_soc_update_bits(codec, | |
806 | RT286_I2S_CTRL1, 0x300, 0x3 << 8); | |
807 | break; | |
808 | default: | |
809 | return -EINVAL; | |
810 | } | |
811 | /* bit 15 Stream Type 0:PCM 1:Non-PCM */ | |
812 | snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0); | |
813 | snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0); | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
818 | static int rt286_set_dai_sysclk(struct snd_soc_dai *dai, | |
819 | int clk_id, unsigned int freq, int dir) | |
820 | { | |
821 | struct snd_soc_codec *codec = dai->codec; | |
822 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
823 | ||
824 | dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq); | |
825 | ||
826 | if (RT286_SCLK_S_MCLK == clk_id) { | |
827 | snd_soc_update_bits(codec, | |
828 | RT286_I2S_CTRL2, 0x0100, 0x0); | |
829 | snd_soc_update_bits(codec, | |
830 | RT286_PLL_CTRL1, 0x20, 0x20); | |
831 | } else { | |
832 | snd_soc_update_bits(codec, | |
833 | RT286_I2S_CTRL2, 0x0100, 0x0100); | |
834 | snd_soc_update_bits(codec, | |
835 | RT286_PLL_CTRL, 0x4, 0x4); | |
836 | snd_soc_update_bits(codec, | |
837 | RT286_PLL_CTRL1, 0x20, 0x0); | |
838 | } | |
839 | ||
840 | switch (freq) { | |
841 | case 19200000: | |
842 | if (RT286_SCLK_S_MCLK == clk_id) { | |
843 | dev_err(codec->dev, "Should not use MCLK\n"); | |
844 | return -EINVAL; | |
845 | } | |
846 | snd_soc_update_bits(codec, | |
847 | RT286_I2S_CTRL2, 0x40, 0x40); | |
848 | break; | |
849 | case 24000000: | |
850 | if (RT286_SCLK_S_MCLK == clk_id) { | |
851 | dev_err(codec->dev, "Should not use MCLK\n"); | |
852 | return -EINVAL; | |
853 | } | |
854 | snd_soc_update_bits(codec, | |
855 | RT286_I2S_CTRL2, 0x40, 0x0); | |
856 | break; | |
857 | case 12288000: | |
858 | case 11289600: | |
859 | snd_soc_update_bits(codec, | |
860 | RT286_I2S_CTRL2, 0x8, 0x0); | |
861 | snd_soc_update_bits(codec, | |
862 | RT286_CLK_DIV, 0xfc1e, 0x0004); | |
863 | break; | |
864 | case 24576000: | |
865 | case 22579200: | |
866 | snd_soc_update_bits(codec, | |
867 | RT286_I2S_CTRL2, 0x8, 0x8); | |
868 | snd_soc_update_bits(codec, | |
869 | RT286_CLK_DIV, 0xfc1e, 0x5406); | |
870 | break; | |
871 | default: | |
872 | dev_err(codec->dev, "Unsupported system clock\n"); | |
873 | return -EINVAL; | |
874 | } | |
875 | ||
876 | rt286->sys_clk = freq; | |
6879db76 | 877 | rt286->clk_id = clk_id; |
07cf7cba BL |
878 | |
879 | return 0; | |
880 | } | |
881 | ||
882 | static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) | |
883 | { | |
884 | struct snd_soc_codec *codec = dai->codec; | |
885 | ||
886 | dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio); | |
887 | if (50 == ratio) | |
888 | snd_soc_update_bits(codec, | |
889 | RT286_I2S_CTRL1, 0x1000, 0x1000); | |
890 | else | |
891 | snd_soc_update_bits(codec, | |
892 | RT286_I2S_CTRL1, 0x1000, 0x0); | |
893 | ||
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
898 | static int rt286_set_bias_level(struct snd_soc_codec *codec, | |
899 | enum snd_soc_bias_level level) | |
900 | { | |
901 | switch (level) { | |
902 | case SND_SOC_BIAS_PREPARE: | |
b1cd8457 | 903 | if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) { |
07cf7cba BL |
904 | snd_soc_write(codec, |
905 | RT286_SET_AUDIO_POWER, AC_PWRST_D0); | |
bc6c4e45 BL |
906 | snd_soc_update_bits(codec, |
907 | RT286_DC_GAIN, 0x200, 0x200); | |
908 | } | |
909 | break; | |
910 | ||
911 | case SND_SOC_BIAS_ON: | |
912 | mdelay(10); | |
6879db76 BL |
913 | snd_soc_update_bits(codec, |
914 | RT286_CBJ_CTRL1, 0x0400, 0x0400); | |
915 | snd_soc_update_bits(codec, | |
916 | RT286_DC_GAIN, 0x200, 0x0); | |
917 | ||
07cf7cba BL |
918 | break; |
919 | ||
920 | case SND_SOC_BIAS_STANDBY: | |
921 | snd_soc_write(codec, | |
922 | RT286_SET_AUDIO_POWER, AC_PWRST_D3); | |
bc6c4e45 | 923 | snd_soc_update_bits(codec, |
6879db76 | 924 | RT286_CBJ_CTRL1, 0x0400, 0x0000); |
07cf7cba BL |
925 | break; |
926 | ||
927 | default: | |
928 | break; | |
929 | } | |
07cf7cba BL |
930 | |
931 | return 0; | |
932 | } | |
933 | ||
934 | static irqreturn_t rt286_irq(int irq, void *data) | |
935 | { | |
936 | struct rt286_priv *rt286 = data; | |
937 | bool hp = false; | |
938 | bool mic = false; | |
939 | int status = 0; | |
940 | ||
90f601ef | 941 | rt286_jack_detect(rt286, &hp, &mic); |
07cf7cba BL |
942 | |
943 | /* Clear IRQ */ | |
90f601ef | 944 | regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1); |
07cf7cba BL |
945 | |
946 | if (hp == true) | |
947 | status |= SND_JACK_HEADPHONE; | |
948 | ||
949 | if (mic == true) | |
950 | status |= SND_JACK_MICROPHONE; | |
951 | ||
952 | snd_soc_jack_report(rt286->jack, status, | |
953 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
954 | ||
955 | pm_wakeup_event(&rt286->i2c->dev, 300); | |
956 | ||
957 | return IRQ_HANDLED; | |
958 | } | |
959 | ||
960 | static int rt286_probe(struct snd_soc_codec *codec) | |
961 | { | |
962 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
07cf7cba | 963 | |
6879db76 | 964 | rt286->codec = codec; |
90f601ef BL |
965 | |
966 | if (rt286->i2c->irq) { | |
967 | regmap_update_bits(rt286->regmap, | |
968 | RT286_IRQ_CTRL, 0x2, 0x2); | |
969 | ||
970 | INIT_DELAYED_WORK(&rt286->jack_detect_work, | |
971 | rt286_jack_detect_work); | |
972 | schedule_delayed_work(&rt286->jack_detect_work, | |
973 | msecs_to_jiffies(1250)); | |
974 | } | |
07cf7cba | 975 | |
07cf7cba BL |
976 | return 0; |
977 | } | |
978 | ||
979 | static int rt286_remove(struct snd_soc_codec *codec) | |
980 | { | |
981 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
982 | ||
983 | cancel_delayed_work_sync(&rt286->jack_detect_work); | |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
988 | #ifdef CONFIG_PM | |
989 | static int rt286_suspend(struct snd_soc_codec *codec) | |
990 | { | |
991 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
992 | ||
993 | regcache_cache_only(rt286->regmap, true); | |
994 | regcache_mark_dirty(rt286->regmap); | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
999 | static int rt286_resume(struct snd_soc_codec *codec) | |
1000 | { | |
1001 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
1002 | ||
1003 | regcache_cache_only(rt286->regmap, false); | |
1004 | rt286_index_sync(codec); | |
1005 | regcache_sync(rt286->regmap); | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | #else | |
1010 | #define rt286_suspend NULL | |
1011 | #define rt286_resume NULL | |
1012 | #endif | |
1013 | ||
1014 | #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) | |
1015 | #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
1016 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | |
1017 | ||
1018 | static const struct snd_soc_dai_ops rt286_aif_dai_ops = { | |
1019 | .hw_params = rt286_hw_params, | |
1020 | .set_fmt = rt286_set_dai_fmt, | |
1021 | .set_sysclk = rt286_set_dai_sysclk, | |
1022 | .set_bclk_ratio = rt286_set_bclk_ratio, | |
1023 | }; | |
1024 | ||
1025 | static struct snd_soc_dai_driver rt286_dai[] = { | |
1026 | { | |
1027 | .name = "rt286-aif1", | |
1028 | .id = RT286_AIF1, | |
1029 | .playback = { | |
1030 | .stream_name = "AIF1 Playback", | |
1031 | .channels_min = 1, | |
1032 | .channels_max = 2, | |
1033 | .rates = RT286_STEREO_RATES, | |
1034 | .formats = RT286_FORMATS, | |
1035 | }, | |
1036 | .capture = { | |
1037 | .stream_name = "AIF1 Capture", | |
1038 | .channels_min = 1, | |
1039 | .channels_max = 2, | |
1040 | .rates = RT286_STEREO_RATES, | |
1041 | .formats = RT286_FORMATS, | |
1042 | }, | |
1043 | .ops = &rt286_aif_dai_ops, | |
1044 | .symmetric_rates = 1, | |
1045 | }, | |
1046 | { | |
1047 | .name = "rt286-aif2", | |
1048 | .id = RT286_AIF2, | |
1049 | .playback = { | |
1050 | .stream_name = "AIF2 Playback", | |
1051 | .channels_min = 1, | |
1052 | .channels_max = 2, | |
1053 | .rates = RT286_STEREO_RATES, | |
1054 | .formats = RT286_FORMATS, | |
1055 | }, | |
1056 | .capture = { | |
1057 | .stream_name = "AIF2 Capture", | |
1058 | .channels_min = 1, | |
1059 | .channels_max = 2, | |
1060 | .rates = RT286_STEREO_RATES, | |
1061 | .formats = RT286_FORMATS, | |
1062 | }, | |
1063 | .ops = &rt286_aif_dai_ops, | |
1064 | .symmetric_rates = 1, | |
1065 | }, | |
1066 | ||
1067 | }; | |
1068 | ||
1069 | static struct snd_soc_codec_driver soc_codec_dev_rt286 = { | |
1070 | .probe = rt286_probe, | |
1071 | .remove = rt286_remove, | |
1072 | .suspend = rt286_suspend, | |
1073 | .resume = rt286_resume, | |
1074 | .set_bias_level = rt286_set_bias_level, | |
1075 | .idle_bias_off = true, | |
1076 | .controls = rt286_snd_controls, | |
1077 | .num_controls = ARRAY_SIZE(rt286_snd_controls), | |
1078 | .dapm_widgets = rt286_dapm_widgets, | |
1079 | .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets), | |
1080 | .dapm_routes = rt286_dapm_routes, | |
1081 | .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes), | |
1082 | }; | |
1083 | ||
1084 | static const struct regmap_config rt286_regmap = { | |
1085 | .reg_bits = 32, | |
1086 | .val_bits = 32, | |
1087 | .max_register = 0x02370100, | |
1088 | .volatile_reg = rt286_volatile_register, | |
1089 | .readable_reg = rt286_readable_register, | |
bc08f96b OC |
1090 | .reg_write = rl6347a_hw_write, |
1091 | .reg_read = rl6347a_hw_read, | |
07cf7cba BL |
1092 | .cache_type = REGCACHE_RBTREE, |
1093 | .reg_defaults = rt286_reg, | |
1094 | .num_reg_defaults = ARRAY_SIZE(rt286_reg), | |
1095 | }; | |
1096 | ||
1097 | static const struct i2c_device_id rt286_i2c_id[] = { | |
1098 | {"rt286", 0}, | |
3ab888db | 1099 | {"rt288", 0}, |
07cf7cba BL |
1100 | {} |
1101 | }; | |
1102 | MODULE_DEVICE_TABLE(i2c, rt286_i2c_id); | |
1103 | ||
1104 | static const struct acpi_device_id rt286_acpi_match[] = { | |
1105 | { "INT343A", 0 }, | |
1106 | {}, | |
1107 | }; | |
1108 | MODULE_DEVICE_TABLE(acpi, rt286_acpi_match); | |
1109 | ||
a5afdc5b | 1110 | static const struct dmi_system_id force_combo_jack_table[] = { |
6c67cde2 BL |
1111 | { |
1112 | .ident = "Intel Wilson Beach", | |
1113 | .matches = { | |
1114 | DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS") | |
1115 | } | |
1116 | }, | |
1117 | { } | |
1118 | }; | |
1119 | ||
a5afdc5b | 1120 | static const struct dmi_system_id dmi_dell_dino[] = { |
2cc3f234 BL |
1121 | { |
1122 | .ident = "Dell Dino", | |
1123 | .matches = { | |
1124 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
a4ee5561 | 1125 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9343") |
2cc3f234 BL |
1126 | } |
1127 | }, | |
1128 | { } | |
1129 | }; | |
1130 | ||
07cf7cba BL |
1131 | static int rt286_i2c_probe(struct i2c_client *i2c, |
1132 | const struct i2c_device_id *id) | |
1133 | { | |
1134 | struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev); | |
1135 | struct rt286_priv *rt286; | |
143526ee | 1136 | int i, ret, val; |
07cf7cba BL |
1137 | |
1138 | rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286), | |
1139 | GFP_KERNEL); | |
1140 | if (NULL == rt286) | |
1141 | return -ENOMEM; | |
1142 | ||
1143 | rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap); | |
1144 | if (IS_ERR(rt286->regmap)) { | |
1145 | ret = PTR_ERR(rt286->regmap); | |
1146 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
1147 | ret); | |
1148 | return ret; | |
1149 | } | |
1150 | ||
143526ee BL |
1151 | ret = regmap_read(rt286->regmap, |
1152 | RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val); | |
1153 | if (ret != 0) { | |
1154 | dev_err(&i2c->dev, "I2C error %d\n", ret); | |
1155 | return ret; | |
1156 | } | |
1157 | if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) { | |
4b21768a | 1158 | dev_err(&i2c->dev, |
e608aaef | 1159 | "Device with ID register %#x is not rt286\n", val); |
4b21768a BL |
1160 | return -ENODEV; |
1161 | } | |
1162 | ||
dc6d84c6 AL |
1163 | rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def, |
1164 | sizeof(rt286_index_def), GFP_KERNEL); | |
1165 | if (!rt286->index_cache) | |
1166 | return -ENOMEM; | |
1167 | ||
bc08f96b | 1168 | rt286->index_cache_size = INDEX_CACHE_SIZE; |
07cf7cba BL |
1169 | rt286->i2c = i2c; |
1170 | i2c_set_clientdata(i2c, rt286); | |
1171 | ||
d53d59ec BL |
1172 | /* restore codec default */ |
1173 | for (i = 0; i < INDEX_CACHE_SIZE; i++) | |
1174 | regmap_write(rt286->regmap, rt286->index_cache[i].reg, | |
1175 | rt286->index_cache[i].def); | |
1176 | for (i = 0; i < ARRAY_SIZE(rt286_reg); i++) | |
1177 | regmap_write(rt286->regmap, rt286_reg[i].reg, | |
1178 | rt286_reg[i].def); | |
1179 | ||
07cf7cba BL |
1180 | if (pdata) |
1181 | rt286->pdata = *pdata; | |
1182 | ||
2cc3f234 BL |
1183 | if (dmi_check_system(force_combo_jack_table) || |
1184 | dmi_check_system(dmi_dell_dino)) | |
6c67cde2 BL |
1185 | rt286->pdata.cbj_en = true; |
1186 | ||
61a414c4 BL |
1187 | regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3); |
1188 | ||
1189 | for (i = 0; i < RT286_POWER_REG_LEN; i++) | |
1190 | regmap_write(rt286->regmap, | |
1191 | RT286_SET_POWER(rt286_support_power_controls[i]), | |
1192 | AC_PWRST_D1); | |
1193 | ||
1194 | if (!rt286->pdata.cbj_en) { | |
1195 | regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000); | |
1196 | regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816); | |
61a414c4 BL |
1197 | regmap_update_bits(rt286->regmap, |
1198 | RT286_CBJ_CTRL1, 0xf000, 0xb000); | |
1199 | } else { | |
1200 | regmap_update_bits(rt286->regmap, | |
1201 | RT286_CBJ_CTRL1, 0xf000, 0x5000); | |
1202 | } | |
1203 | ||
1204 | mdelay(10); | |
1205 | ||
1206 | if (!rt286->pdata.gpio2_en) | |
1207 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000); | |
1208 | else | |
1209 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0); | |
1210 | ||
1211 | mdelay(10); | |
1212 | ||
6879db76 | 1213 | regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000); |
f8c101bc | 1214 | /* Power down LDO, VREF */ |
6879db76 BL |
1215 | regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0); |
1216 | regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001); | |
61a414c4 | 1217 | |
f8c101bc | 1218 | /* Set depop parameter */ |
bc6c4e45 BL |
1219 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a); |
1220 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737); | |
1221 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f); | |
1222 | ||
2cc3f234 BL |
1223 | if (dmi_check_system(dmi_dell_dino)) { |
1224 | regmap_update_bits(rt286->regmap, | |
1225 | RT286_SET_GPIO_MASK, 0x40, 0x40); | |
1226 | regmap_update_bits(rt286->regmap, | |
1227 | RT286_SET_GPIO_DIRECTION, 0x40, 0x40); | |
1228 | regmap_update_bits(rt286->regmap, | |
1229 | RT286_SET_GPIO_DATA, 0x40, 0x40); | |
1230 | regmap_update_bits(rt286->regmap, | |
1231 | RT286_GPIO_CTRL, 0xc, 0x8); | |
1232 | } | |
1233 | ||
61a414c4 | 1234 | if (rt286->i2c->irq) { |
61a414c4 BL |
1235 | ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, |
1236 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286); | |
1237 | if (ret != 0) { | |
1238 | dev_err(&i2c->dev, | |
1239 | "Failed to reguest IRQ: %d\n", ret); | |
1240 | return ret; | |
1241 | } | |
1242 | } | |
1243 | ||
07cf7cba BL |
1244 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286, |
1245 | rt286_dai, ARRAY_SIZE(rt286_dai)); | |
1246 | ||
1247 | return ret; | |
1248 | } | |
1249 | ||
1250 | static int rt286_i2c_remove(struct i2c_client *i2c) | |
1251 | { | |
1252 | struct rt286_priv *rt286 = i2c_get_clientdata(i2c); | |
1253 | ||
1254 | if (i2c->irq) | |
1255 | free_irq(i2c->irq, rt286); | |
1256 | snd_soc_unregister_codec(&i2c->dev); | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
1261 | ||
23c4fd5c | 1262 | static struct i2c_driver rt286_i2c_driver = { |
07cf7cba BL |
1263 | .driver = { |
1264 | .name = "rt286", | |
07cf7cba BL |
1265 | .acpi_match_table = ACPI_PTR(rt286_acpi_match), |
1266 | }, | |
1267 | .probe = rt286_i2c_probe, | |
1268 | .remove = rt286_i2c_remove, | |
1269 | .id_table = rt286_i2c_id, | |
1270 | }; | |
1271 | ||
1272 | module_i2c_driver(rt286_i2c_driver); | |
1273 | ||
1274 | MODULE_DESCRIPTION("ASoC RT286 driver"); | |
1275 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); | |
1276 | MODULE_LICENSE("GPL"); |