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07cf7cba BL |
1 | /* |
2 | * rt286.c -- RT286 ALSA SoC audio codec driver | |
3 | * | |
4 | * Copyright 2013 Realtek Semiconductor Corp. | |
5 | * Author: Bard Liao <bardliao@realtek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/spi/spi.h> | |
20 | #include <linux/acpi.h> | |
21 | #include <sound/core.h> | |
22 | #include <sound/pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | #include <sound/soc.h> | |
25 | #include <sound/soc-dapm.h> | |
26 | #include <sound/initval.h> | |
27 | #include <sound/tlv.h> | |
28 | #include <sound/jack.h> | |
29 | #include <linux/workqueue.h> | |
30 | #include <sound/rt286.h> | |
31 | #include <sound/hda_verbs.h> | |
32 | ||
33 | #include "rt286.h" | |
34 | ||
35 | #define RT286_VENDOR_ID 0x10ec0286 | |
36 | ||
37 | struct rt286_priv { | |
38 | struct regmap *regmap; | |
07cf7cba BL |
39 | struct rt286_platform_data pdata; |
40 | struct i2c_client *i2c; | |
41 | struct snd_soc_jack *jack; | |
42 | struct delayed_work jack_detect_work; | |
43 | int sys_clk; | |
44 | struct reg_default *index_cache; | |
45 | }; | |
46 | ||
47 | static struct reg_default rt286_index_def[] = { | |
48 | { 0x01, 0xaaaa }, | |
49 | { 0x02, 0x8aaa }, | |
50 | { 0x03, 0x0002 }, | |
51 | { 0x04, 0xaf01 }, | |
52 | { 0x08, 0x000d }, | |
53 | { 0x09, 0xd810 }, | |
b7a29767 | 54 | { 0x0a, 0x0120 }, |
07cf7cba | 55 | { 0x0b, 0x0000 }, |
bc6c4e45 | 56 | { 0x0d, 0x2800 }, |
07cf7cba BL |
57 | { 0x0f, 0x0000 }, |
58 | { 0x19, 0x0a17 }, | |
59 | { 0x20, 0x0020 }, | |
60 | { 0x33, 0x0208 }, | |
61 | { 0x49, 0x0004 }, | |
62 | { 0x4f, 0x50e9 }, | |
b7a29767 | 63 | { 0x50, 0x2000 }, |
07cf7cba | 64 | { 0x63, 0x2902 }, |
bc6c4e45 BL |
65 | { 0x67, 0x1111 }, |
66 | { 0x68, 0x1016 }, | |
67 | { 0x69, 0x273f }, | |
07cf7cba BL |
68 | }; |
69 | #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def) | |
70 | ||
71 | static const struct reg_default rt286_reg[] = { | |
72 | { 0x00170500, 0x00000400 }, | |
73 | { 0x00220000, 0x00000031 }, | |
74 | { 0x00239000, 0x0000007f }, | |
75 | { 0x0023a000, 0x0000007f }, | |
76 | { 0x00270500, 0x00000400 }, | |
77 | { 0x00370500, 0x00000400 }, | |
78 | { 0x00870500, 0x00000400 }, | |
79 | { 0x00920000, 0x00000031 }, | |
80 | { 0x00935000, 0x000000c3 }, | |
81 | { 0x00936000, 0x000000c3 }, | |
82 | { 0x00970500, 0x00000400 }, | |
83 | { 0x00b37000, 0x00000097 }, | |
84 | { 0x00b37200, 0x00000097 }, | |
85 | { 0x00b37300, 0x00000097 }, | |
86 | { 0x00c37000, 0x00000000 }, | |
87 | { 0x00c37100, 0x00000080 }, | |
88 | { 0x01270500, 0x00000400 }, | |
89 | { 0x01370500, 0x00000400 }, | |
90 | { 0x01371f00, 0x411111f0 }, | |
91 | { 0x01439000, 0x00000080 }, | |
92 | { 0x0143a000, 0x00000080 }, | |
93 | { 0x01470700, 0x00000000 }, | |
94 | { 0x01470500, 0x00000400 }, | |
95 | { 0x01470c00, 0x00000000 }, | |
96 | { 0x01470100, 0x00000000 }, | |
97 | { 0x01837000, 0x00000000 }, | |
98 | { 0x01870500, 0x00000400 }, | |
99 | { 0x02050000, 0x00000000 }, | |
100 | { 0x02139000, 0x00000080 }, | |
101 | { 0x0213a000, 0x00000080 }, | |
102 | { 0x02170100, 0x00000000 }, | |
103 | { 0x02170500, 0x00000400 }, | |
104 | { 0x02170700, 0x00000000 }, | |
105 | { 0x02270100, 0x00000000 }, | |
106 | { 0x02370100, 0x00000000 }, | |
07cf7cba BL |
107 | { 0x01870700, 0x00000020 }, |
108 | { 0x00830000, 0x000000c3 }, | |
109 | { 0x00930000, 0x000000c3 }, | |
110 | { 0x01270700, 0x00000000 }, | |
111 | }; | |
112 | ||
113 | static bool rt286_volatile_register(struct device *dev, unsigned int reg) | |
114 | { | |
115 | switch (reg) { | |
116 | case 0 ... 0xff: | |
117 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
118 | case RT286_GET_HP_SENSE: | |
119 | case RT286_GET_MIC1_SENSE: | |
120 | case RT286_PROC_COEF: | |
121 | return true; | |
122 | default: | |
123 | return false; | |
124 | } | |
125 | ||
126 | ||
127 | } | |
128 | ||
129 | static bool rt286_readable_register(struct device *dev, unsigned int reg) | |
130 | { | |
131 | switch (reg) { | |
132 | case 0 ... 0xff: | |
133 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
134 | case RT286_GET_HP_SENSE: | |
135 | case RT286_GET_MIC1_SENSE: | |
136 | case RT286_SET_AUDIO_POWER: | |
137 | case RT286_SET_HPO_POWER: | |
138 | case RT286_SET_SPK_POWER: | |
139 | case RT286_SET_DMIC1_POWER: | |
140 | case RT286_SPK_MUX: | |
141 | case RT286_HPO_MUX: | |
142 | case RT286_ADC0_MUX: | |
143 | case RT286_ADC1_MUX: | |
144 | case RT286_SET_MIC1: | |
145 | case RT286_SET_PIN_HPO: | |
146 | case RT286_SET_PIN_SPK: | |
147 | case RT286_SET_PIN_DMIC1: | |
148 | case RT286_SPK_EAPD: | |
149 | case RT286_SET_AMP_GAIN_HPO: | |
150 | case RT286_SET_DMIC2_DEFAULT: | |
151 | case RT286_DACL_GAIN: | |
152 | case RT286_DACR_GAIN: | |
153 | case RT286_ADCL_GAIN: | |
154 | case RT286_ADCR_GAIN: | |
155 | case RT286_MIC_GAIN: | |
156 | case RT286_SPOL_GAIN: | |
157 | case RT286_SPOR_GAIN: | |
158 | case RT286_HPOL_GAIN: | |
159 | case RT286_HPOR_GAIN: | |
160 | case RT286_F_DAC_SWITCH: | |
161 | case RT286_F_RECMIX_SWITCH: | |
162 | case RT286_REC_MIC_SWITCH: | |
163 | case RT286_REC_I2S_SWITCH: | |
164 | case RT286_REC_LINE_SWITCH: | |
165 | case RT286_REC_BEEP_SWITCH: | |
166 | case RT286_DAC_FORMAT: | |
167 | case RT286_ADC_FORMAT: | |
168 | case RT286_COEF_INDEX: | |
169 | case RT286_PROC_COEF: | |
170 | case RT286_SET_AMP_GAIN_ADC_IN1: | |
171 | case RT286_SET_AMP_GAIN_ADC_IN2: | |
172 | case RT286_SET_POWER(RT286_DAC_OUT1): | |
173 | case RT286_SET_POWER(RT286_DAC_OUT2): | |
174 | case RT286_SET_POWER(RT286_ADC_IN1): | |
175 | case RT286_SET_POWER(RT286_ADC_IN2): | |
176 | case RT286_SET_POWER(RT286_DMIC2): | |
177 | case RT286_SET_POWER(RT286_MIC1): | |
178 | return true; | |
179 | default: | |
180 | return false; | |
181 | } | |
182 | } | |
183 | ||
184 | static int rt286_hw_write(void *context, unsigned int reg, unsigned int value) | |
185 | { | |
186 | struct i2c_client *client = context; | |
187 | struct rt286_priv *rt286 = i2c_get_clientdata(client); | |
188 | u8 data[4]; | |
189 | int ret, i; | |
190 | ||
191 | /*handle index registers*/ | |
192 | if (reg <= 0xff) { | |
193 | rt286_hw_write(client, RT286_COEF_INDEX, reg); | |
194 | reg = RT286_PROC_COEF; | |
195 | for (i = 0; i < INDEX_CACHE_SIZE; i++) { | |
196 | if (reg == rt286->index_cache[i].reg) { | |
197 | rt286->index_cache[i].def = value; | |
198 | break; | |
199 | } | |
200 | ||
201 | } | |
202 | } | |
203 | ||
204 | data[0] = (reg >> 24) & 0xff; | |
205 | data[1] = (reg >> 16) & 0xff; | |
206 | /* | |
207 | * 4 bit VID: reg should be 0 | |
208 | * 12 bit VID: value should be 0 | |
209 | * So we use an OR operator to handle it rather than use if condition. | |
210 | */ | |
211 | data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff); | |
212 | data[3] = value & 0xff; | |
213 | ||
214 | ret = i2c_master_send(client, data, 4); | |
215 | ||
216 | if (ret == 4) | |
217 | return 0; | |
218 | else | |
219 | pr_err("ret=%d\n", ret); | |
220 | if (ret < 0) | |
221 | return ret; | |
222 | else | |
223 | return -EIO; | |
224 | } | |
225 | ||
226 | static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value) | |
227 | { | |
228 | struct i2c_client *client = context; | |
229 | struct i2c_msg xfer[2]; | |
230 | int ret; | |
231 | __be32 be_reg; | |
232 | unsigned int index, vid, buf = 0x0; | |
233 | ||
234 | /*handle index registers*/ | |
235 | if (reg <= 0xff) { | |
236 | rt286_hw_write(client, RT286_COEF_INDEX, reg); | |
237 | reg = RT286_PROC_COEF; | |
238 | } | |
239 | ||
240 | reg = reg | 0x80000; | |
241 | vid = (reg >> 8) & 0xfff; | |
242 | ||
243 | if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) { | |
244 | index = (reg >> 8) & 0xf; | |
245 | reg = (reg & ~0xf0f) | index; | |
246 | } | |
247 | be_reg = cpu_to_be32(reg); | |
248 | ||
249 | /* Write register */ | |
250 | xfer[0].addr = client->addr; | |
251 | xfer[0].flags = 0; | |
252 | xfer[0].len = 4; | |
253 | xfer[0].buf = (u8 *)&be_reg; | |
254 | ||
255 | /* Read data */ | |
256 | xfer[1].addr = client->addr; | |
257 | xfer[1].flags = I2C_M_RD; | |
258 | xfer[1].len = 4; | |
259 | xfer[1].buf = (u8 *)&buf; | |
260 | ||
261 | ret = i2c_transfer(client->adapter, xfer, 2); | |
262 | if (ret < 0) | |
263 | return ret; | |
264 | else if (ret != 2) | |
265 | return -EIO; | |
266 | ||
267 | *value = be32_to_cpu(buf); | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
272 | static void rt286_index_sync(struct snd_soc_codec *codec) | |
273 | { | |
274 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
275 | int i; | |
276 | ||
277 | for (i = 0; i < INDEX_CACHE_SIZE; i++) { | |
278 | snd_soc_write(codec, rt286->index_cache[i].reg, | |
279 | rt286->index_cache[i].def); | |
280 | } | |
281 | } | |
282 | ||
283 | static int rt286_support_power_controls[] = { | |
284 | RT286_DAC_OUT1, | |
285 | RT286_DAC_OUT2, | |
286 | RT286_ADC_IN1, | |
287 | RT286_ADC_IN2, | |
288 | RT286_MIC1, | |
289 | RT286_DMIC1, | |
290 | RT286_DMIC2, | |
291 | RT286_SPK_OUT, | |
292 | RT286_HP_OUT, | |
293 | }; | |
294 | #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls) | |
295 | ||
90f601ef | 296 | static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic) |
07cf7cba | 297 | { |
07cf7cba BL |
298 | unsigned int val, buf; |
299 | int i; | |
300 | ||
301 | *hp = false; | |
302 | *mic = false; | |
303 | ||
304 | if (rt286->pdata.cbj_en) { | |
90f601ef | 305 | regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf); |
07cf7cba BL |
306 | *hp = buf & 0x80000000; |
307 | if (*hp) { | |
308 | /* power on HV,VERF */ | |
90f601ef | 309 | regmap_update_bits(rt286->regmap, |
07cf7cba BL |
310 | RT286_POWER_CTRL1, 0x1001, 0x0); |
311 | /* power LDO1 */ | |
90f601ef | 312 | regmap_update_bits(rt286->regmap, |
07cf7cba | 313 | RT286_POWER_CTRL2, 0x4, 0x4); |
90f601ef BL |
314 | regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24); |
315 | regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val); | |
07cf7cba BL |
316 | |
317 | msleep(200); | |
318 | i = 40; | |
319 | while (((val & 0x0800) == 0) && (i > 0)) { | |
90f601ef BL |
320 | regmap_read(rt286->regmap, |
321 | RT286_CBJ_CTRL2, &val); | |
07cf7cba BL |
322 | i--; |
323 | msleep(20); | |
324 | } | |
325 | ||
326 | if (0x0400 == (val & 0x0700)) { | |
327 | *mic = false; | |
328 | ||
90f601ef | 329 | regmap_write(rt286->regmap, |
07cf7cba BL |
330 | RT286_SET_MIC1, 0x20); |
331 | /* power off HV,VERF */ | |
90f601ef | 332 | regmap_update_bits(rt286->regmap, |
07cf7cba | 333 | RT286_POWER_CTRL1, 0x1001, 0x1001); |
90f601ef | 334 | regmap_update_bits(rt286->regmap, |
07cf7cba | 335 | RT286_A_BIAS_CTRL3, 0xc000, 0x0000); |
90f601ef | 336 | regmap_update_bits(rt286->regmap, |
07cf7cba | 337 | RT286_CBJ_CTRL1, 0x0030, 0x0000); |
90f601ef | 338 | regmap_update_bits(rt286->regmap, |
07cf7cba BL |
339 | RT286_A_BIAS_CTRL2, 0xc000, 0x0000); |
340 | } else if ((0x0200 == (val & 0x0700)) || | |
341 | (0x0100 == (val & 0x0700))) { | |
342 | *mic = true; | |
90f601ef | 343 | regmap_update_bits(rt286->regmap, |
07cf7cba | 344 | RT286_A_BIAS_CTRL3, 0xc000, 0x8000); |
90f601ef | 345 | regmap_update_bits(rt286->regmap, |
07cf7cba | 346 | RT286_CBJ_CTRL1, 0x0030, 0x0020); |
90f601ef | 347 | regmap_update_bits(rt286->regmap, |
07cf7cba BL |
348 | RT286_A_BIAS_CTRL2, 0xc000, 0x8000); |
349 | } else { | |
350 | *mic = false; | |
351 | } | |
352 | ||
90f601ef | 353 | regmap_update_bits(rt286->regmap, |
07cf7cba BL |
354 | RT286_MISC_CTRL1, |
355 | 0x0060, 0x0000); | |
356 | } else { | |
90f601ef | 357 | regmap_update_bits(rt286->regmap, |
07cf7cba BL |
358 | RT286_MISC_CTRL1, |
359 | 0x0060, 0x0020); | |
90f601ef | 360 | regmap_update_bits(rt286->regmap, |
07cf7cba BL |
361 | RT286_A_BIAS_CTRL3, |
362 | 0xc000, 0x8000); | |
90f601ef | 363 | regmap_update_bits(rt286->regmap, |
07cf7cba BL |
364 | RT286_CBJ_CTRL1, |
365 | 0x0030, 0x0020); | |
90f601ef | 366 | regmap_update_bits(rt286->regmap, |
07cf7cba BL |
367 | RT286_A_BIAS_CTRL2, |
368 | 0xc000, 0x8000); | |
369 | ||
370 | *mic = false; | |
371 | } | |
372 | } else { | |
90f601ef | 373 | regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf); |
07cf7cba | 374 | *hp = buf & 0x80000000; |
90f601ef | 375 | regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf); |
07cf7cba BL |
376 | *mic = buf & 0x80000000; |
377 | } | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static void rt286_jack_detect_work(struct work_struct *work) | |
383 | { | |
384 | struct rt286_priv *rt286 = | |
385 | container_of(work, struct rt286_priv, jack_detect_work.work); | |
386 | int status = 0; | |
387 | bool hp = false; | |
388 | bool mic = false; | |
389 | ||
90f601ef | 390 | rt286_jack_detect(rt286, &hp, &mic); |
07cf7cba BL |
391 | |
392 | if (hp == true) | |
393 | status |= SND_JACK_HEADPHONE; | |
394 | ||
395 | if (mic == true) | |
396 | status |= SND_JACK_MICROPHONE; | |
397 | ||
398 | snd_soc_jack_report(rt286->jack, status, | |
399 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
400 | } | |
401 | ||
402 | int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) | |
403 | { | |
404 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
405 | ||
406 | rt286->jack = jack; | |
407 | ||
408 | /* Send an initial empty report */ | |
409 | snd_soc_jack_report(rt286->jack, 0, | |
410 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | EXPORT_SYMBOL_GPL(rt286_mic_detect); | |
415 | ||
416 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); | |
417 | static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); | |
418 | ||
419 | static const struct snd_kcontrol_new rt286_snd_controls[] = { | |
420 | SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN, | |
421 | RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
422 | SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN, | |
423 | RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
424 | SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN, | |
425 | 0, 0x3, 0, mic_vol_tlv), | |
426 | SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN, | |
427 | RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1), | |
428 | }; | |
429 | ||
430 | /* Digital Mixer */ | |
431 | static const struct snd_kcontrol_new rt286_front_mix[] = { | |
432 | SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH, | |
433 | RT286_MUTE_SFT, 1, 1), | |
434 | SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH, | |
435 | RT286_MUTE_SFT, 1, 1), | |
436 | }; | |
437 | ||
438 | /* Analog Input Mixer */ | |
439 | static const struct snd_kcontrol_new rt286_rec_mix[] = { | |
440 | SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH, | |
441 | RT286_MUTE_SFT, 1, 1), | |
442 | SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH, | |
443 | RT286_MUTE_SFT, 1, 1), | |
444 | SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH, | |
445 | RT286_MUTE_SFT, 1, 1), | |
446 | SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH, | |
447 | RT286_MUTE_SFT, 1, 1), | |
448 | }; | |
449 | ||
450 | static const struct snd_kcontrol_new spo_enable_control = | |
451 | SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK, | |
452 | RT286_SET_PIN_SFT, 1, 0); | |
453 | ||
454 | static const struct snd_kcontrol_new hpol_enable_control = | |
455 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN, | |
456 | RT286_MUTE_SFT, 1, 1); | |
457 | ||
458 | static const struct snd_kcontrol_new hpor_enable_control = | |
459 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN, | |
460 | RT286_MUTE_SFT, 1, 1); | |
461 | ||
462 | /* ADC0 source */ | |
463 | static const char * const rt286_adc_src[] = { | |
464 | "Mic", "RECMIX", "Dmic" | |
465 | }; | |
466 | ||
467 | static const int rt286_adc_values[] = { | |
468 | 0, 4, 5, | |
469 | }; | |
470 | ||
471 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
472 | rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT, | |
473 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
474 | ||
475 | static const struct snd_kcontrol_new rt286_adc0_mux = | |
476 | SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum); | |
477 | ||
478 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
479 | rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT, | |
480 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
481 | ||
482 | static const struct snd_kcontrol_new rt286_adc1_mux = | |
483 | SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum); | |
484 | ||
485 | static const char * const rt286_dac_src[] = { | |
486 | "Front", "Surround" | |
487 | }; | |
488 | /* HP-OUT source */ | |
489 | static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX, | |
490 | 0, rt286_dac_src); | |
491 | ||
492 | static const struct snd_kcontrol_new rt286_hpo_mux = | |
493 | SOC_DAPM_ENUM("HPO source", rt286_hpo_enum); | |
494 | ||
495 | /* SPK-OUT source */ | |
496 | static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX, | |
497 | 0, rt286_dac_src); | |
498 | ||
499 | static const struct snd_kcontrol_new rt286_spo_mux = | |
500 | SOC_DAPM_ENUM("SPO source", rt286_spo_enum); | |
501 | ||
502 | static int rt286_spk_event(struct snd_soc_dapm_widget *w, | |
503 | struct snd_kcontrol *kcontrol, int event) | |
504 | { | |
505 | struct snd_soc_codec *codec = w->codec; | |
506 | ||
507 | switch (event) { | |
508 | case SND_SOC_DAPM_POST_PMU: | |
509 | snd_soc_write(codec, | |
510 | RT286_SPK_EAPD, RT286_SET_EAPD_HIGH); | |
511 | break; | |
512 | case SND_SOC_DAPM_PRE_PMD: | |
513 | snd_soc_write(codec, | |
514 | RT286_SPK_EAPD, RT286_SET_EAPD_LOW); | |
515 | break; | |
516 | ||
517 | default: | |
518 | return 0; | |
519 | } | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w, | |
525 | struct snd_kcontrol *kcontrol, int event) | |
526 | { | |
527 | struct snd_soc_codec *codec = w->codec; | |
528 | ||
529 | switch (event) { | |
530 | case SND_SOC_DAPM_POST_PMU: | |
531 | snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20); | |
532 | break; | |
533 | case SND_SOC_DAPM_PRE_PMD: | |
534 | snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0); | |
535 | break; | |
536 | default: | |
537 | return 0; | |
538 | } | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static int rt286_adc_event(struct snd_soc_dapm_widget *w, | |
544 | struct snd_kcontrol *kcontrol, int event) | |
545 | { | |
546 | struct snd_soc_codec *codec = w->codec; | |
547 | unsigned int nid; | |
548 | ||
549 | nid = (w->reg >> 20) & 0xff; | |
550 | ||
551 | switch (event) { | |
552 | case SND_SOC_DAPM_POST_PMU: | |
553 | snd_soc_update_bits(codec, | |
554 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), | |
555 | 0x7080, 0x7000); | |
556 | break; | |
557 | case SND_SOC_DAPM_PRE_PMD: | |
558 | snd_soc_update_bits(codec, | |
559 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), | |
560 | 0x7080, 0x7080); | |
561 | break; | |
562 | default: | |
563 | return 0; | |
564 | } | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
569 | static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = { | |
570 | /* Input Lines */ | |
571 | SND_SOC_DAPM_INPUT("DMIC1 Pin"), | |
572 | SND_SOC_DAPM_INPUT("DMIC2 Pin"), | |
573 | SND_SOC_DAPM_INPUT("MIC1"), | |
574 | SND_SOC_DAPM_INPUT("LINE1"), | |
575 | SND_SOC_DAPM_INPUT("Beep"), | |
576 | ||
577 | /* DMIC */ | |
578 | SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1, | |
579 | NULL, 0, rt286_set_dmic1_event, | |
580 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
581 | SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1, | |
582 | NULL, 0), | |
583 | SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM, | |
584 | 0, 0, NULL, 0), | |
585 | ||
586 | /* REC Mixer */ | |
587 | SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0, | |
588 | rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)), | |
589 | ||
590 | /* ADCs */ | |
591 | SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0), | |
592 | SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0), | |
593 | ||
594 | /* ADC Mux */ | |
595 | SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1, | |
596 | &rt286_adc0_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD | | |
597 | SND_SOC_DAPM_POST_PMU), | |
598 | SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1, | |
599 | &rt286_adc1_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD | | |
600 | SND_SOC_DAPM_POST_PMU), | |
601 | ||
602 | /* Audio Interface */ | |
603 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
604 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
605 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
606 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
607 | ||
608 | /* Output Side */ | |
609 | /* DACs */ | |
610 | SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0), | |
611 | SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0), | |
612 | ||
613 | /* Output Mux */ | |
614 | SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux), | |
615 | SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux), | |
616 | ||
617 | SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO, | |
618 | RT286_SET_PIN_SFT, 0, NULL, 0), | |
619 | ||
620 | /* Output Mixer */ | |
621 | SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1, | |
622 | rt286_front_mix, ARRAY_SIZE(rt286_front_mix)), | |
623 | SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1, | |
624 | NULL, 0), | |
625 | ||
626 | /* Output Pga */ | |
627 | SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0, | |
628 | &spo_enable_control, rt286_spk_event, | |
629 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
630 | SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, | |
631 | &hpol_enable_control), | |
632 | SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, | |
633 | &hpor_enable_control), | |
634 | ||
635 | /* Output Lines */ | |
636 | SND_SOC_DAPM_OUTPUT("SPOL"), | |
637 | SND_SOC_DAPM_OUTPUT("SPOR"), | |
638 | SND_SOC_DAPM_OUTPUT("HPO Pin"), | |
639 | SND_SOC_DAPM_OUTPUT("SPDIF"), | |
640 | }; | |
641 | ||
642 | static const struct snd_soc_dapm_route rt286_dapm_routes[] = { | |
643 | {"DMIC1", NULL, "DMIC1 Pin"}, | |
644 | {"DMIC2", NULL, "DMIC2 Pin"}, | |
645 | {"DMIC1", NULL, "DMIC Receiver"}, | |
646 | {"DMIC2", NULL, "DMIC Receiver"}, | |
647 | ||
648 | {"RECMIX", "Beep Switch", "Beep"}, | |
649 | {"RECMIX", "Line1 Switch", "LINE1"}, | |
650 | {"RECMIX", "Mic1 Switch", "MIC1"}, | |
651 | ||
652 | {"ADC 0 Mux", "Dmic", "DMIC1"}, | |
653 | {"ADC 0 Mux", "RECMIX", "RECMIX"}, | |
654 | {"ADC 0 Mux", "Mic", "MIC1"}, | |
655 | {"ADC 1 Mux", "Dmic", "DMIC2"}, | |
656 | {"ADC 1 Mux", "RECMIX", "RECMIX"}, | |
657 | {"ADC 1 Mux", "Mic", "MIC1"}, | |
658 | ||
659 | {"ADC 0", NULL, "ADC 0 Mux"}, | |
660 | {"ADC 1", NULL, "ADC 1 Mux"}, | |
661 | ||
662 | {"AIF1TX", NULL, "ADC 0"}, | |
663 | {"AIF2TX", NULL, "ADC 1"}, | |
664 | ||
665 | {"DAC 0", NULL, "AIF1RX"}, | |
666 | {"DAC 1", NULL, "AIF2RX"}, | |
667 | ||
668 | {"Front", "DAC Switch", "DAC 0"}, | |
669 | {"Front", "RECMIX Switch", "RECMIX"}, | |
670 | ||
671 | {"Surround", NULL, "DAC 1"}, | |
672 | ||
673 | {"SPK Mux", "Front", "Front"}, | |
674 | {"SPK Mux", "Surround", "Surround"}, | |
675 | ||
676 | {"HPO Mux", "Front", "Front"}, | |
677 | {"HPO Mux", "Surround", "Surround"}, | |
678 | ||
679 | {"SPO", "Switch", "SPK Mux"}, | |
680 | {"HPO L", "Switch", "HPO Mux"}, | |
681 | {"HPO R", "Switch", "HPO Mux"}, | |
682 | {"HPO L", NULL, "HP Power"}, | |
683 | {"HPO R", NULL, "HP Power"}, | |
684 | ||
685 | {"SPOL", NULL, "SPO"}, | |
686 | {"SPOR", NULL, "SPO"}, | |
687 | {"HPO Pin", NULL, "HPO L"}, | |
688 | {"HPO Pin", NULL, "HPO R"}, | |
689 | }; | |
690 | ||
691 | static int rt286_hw_params(struct snd_pcm_substream *substream, | |
692 | struct snd_pcm_hw_params *params, | |
693 | struct snd_soc_dai *dai) | |
694 | { | |
695 | struct snd_soc_codec *codec = dai->codec; | |
696 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
697 | unsigned int val = 0; | |
698 | int d_len_code; | |
699 | ||
700 | switch (params_rate(params)) { | |
701 | /* bit 14 0:48K 1:44.1K */ | |
702 | case 44100: | |
703 | val |= 0x4000; | |
704 | break; | |
705 | case 48000: | |
706 | break; | |
707 | default: | |
708 | dev_err(codec->dev, "Unsupported sample rate %d\n", | |
709 | params_rate(params)); | |
710 | return -EINVAL; | |
711 | } | |
712 | switch (rt286->sys_clk) { | |
713 | case 12288000: | |
714 | case 24576000: | |
715 | if (params_rate(params) != 48000) { | |
716 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
717 | params_rate(params), rt286->sys_clk); | |
718 | return -EINVAL; | |
719 | } | |
720 | break; | |
721 | case 11289600: | |
722 | case 22579200: | |
723 | if (params_rate(params) != 44100) { | |
724 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
725 | params_rate(params), rt286->sys_clk); | |
726 | return -EINVAL; | |
727 | } | |
728 | break; | |
729 | } | |
730 | ||
731 | if (params_channels(params) <= 16) { | |
732 | /* bit 3:0 Number of Channel */ | |
733 | val |= (params_channels(params) - 1); | |
734 | } else { | |
735 | dev_err(codec->dev, "Unsupported channels %d\n", | |
736 | params_channels(params)); | |
737 | return -EINVAL; | |
738 | } | |
739 | ||
740 | d_len_code = 0; | |
741 | switch (params_width(params)) { | |
742 | /* bit 6:4 Bits per Sample */ | |
743 | case 16: | |
744 | d_len_code = 0; | |
745 | val |= (0x1 << 4); | |
746 | break; | |
747 | case 32: | |
748 | d_len_code = 2; | |
749 | val |= (0x4 << 4); | |
750 | break; | |
751 | case 20: | |
752 | d_len_code = 1; | |
753 | val |= (0x2 << 4); | |
754 | break; | |
755 | case 24: | |
756 | d_len_code = 2; | |
757 | val |= (0x3 << 4); | |
758 | break; | |
759 | case 8: | |
760 | d_len_code = 3; | |
761 | break; | |
762 | default: | |
763 | return -EINVAL; | |
764 | } | |
765 | ||
766 | snd_soc_update_bits(codec, | |
767 | RT286_I2S_CTRL1, 0x0018, d_len_code << 3); | |
768 | dev_dbg(codec->dev, "format val = 0x%x\n", val); | |
769 | ||
770 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
771 | snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val); | |
772 | else | |
773 | snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
779 | { | |
780 | struct snd_soc_codec *codec = dai->codec; | |
781 | ||
782 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
783 | case SND_SOC_DAIFMT_CBM_CFM: | |
784 | snd_soc_update_bits(codec, | |
785 | RT286_I2S_CTRL1, 0x800, 0x800); | |
786 | break; | |
787 | case SND_SOC_DAIFMT_CBS_CFS: | |
788 | snd_soc_update_bits(codec, | |
789 | RT286_I2S_CTRL1, 0x800, 0x0); | |
790 | break; | |
791 | default: | |
792 | return -EINVAL; | |
793 | } | |
794 | ||
795 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
796 | case SND_SOC_DAIFMT_I2S: | |
797 | snd_soc_update_bits(codec, | |
798 | RT286_I2S_CTRL1, 0x300, 0x0); | |
799 | break; | |
800 | case SND_SOC_DAIFMT_LEFT_J: | |
801 | snd_soc_update_bits(codec, | |
802 | RT286_I2S_CTRL1, 0x300, 0x1 << 8); | |
803 | break; | |
804 | case SND_SOC_DAIFMT_DSP_A: | |
805 | snd_soc_update_bits(codec, | |
806 | RT286_I2S_CTRL1, 0x300, 0x2 << 8); | |
807 | break; | |
808 | case SND_SOC_DAIFMT_DSP_B: | |
809 | snd_soc_update_bits(codec, | |
810 | RT286_I2S_CTRL1, 0x300, 0x3 << 8); | |
811 | break; | |
812 | default: | |
813 | return -EINVAL; | |
814 | } | |
815 | /* bit 15 Stream Type 0:PCM 1:Non-PCM */ | |
816 | snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0); | |
817 | snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0); | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
822 | static int rt286_set_dai_sysclk(struct snd_soc_dai *dai, | |
823 | int clk_id, unsigned int freq, int dir) | |
824 | { | |
825 | struct snd_soc_codec *codec = dai->codec; | |
826 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
827 | ||
828 | dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq); | |
829 | ||
830 | if (RT286_SCLK_S_MCLK == clk_id) { | |
831 | snd_soc_update_bits(codec, | |
832 | RT286_I2S_CTRL2, 0x0100, 0x0); | |
833 | snd_soc_update_bits(codec, | |
834 | RT286_PLL_CTRL1, 0x20, 0x20); | |
835 | } else { | |
836 | snd_soc_update_bits(codec, | |
837 | RT286_I2S_CTRL2, 0x0100, 0x0100); | |
838 | snd_soc_update_bits(codec, | |
839 | RT286_PLL_CTRL, 0x4, 0x4); | |
840 | snd_soc_update_bits(codec, | |
841 | RT286_PLL_CTRL1, 0x20, 0x0); | |
842 | } | |
843 | ||
844 | switch (freq) { | |
845 | case 19200000: | |
846 | if (RT286_SCLK_S_MCLK == clk_id) { | |
847 | dev_err(codec->dev, "Should not use MCLK\n"); | |
848 | return -EINVAL; | |
849 | } | |
850 | snd_soc_update_bits(codec, | |
851 | RT286_I2S_CTRL2, 0x40, 0x40); | |
852 | break; | |
853 | case 24000000: | |
854 | if (RT286_SCLK_S_MCLK == clk_id) { | |
855 | dev_err(codec->dev, "Should not use MCLK\n"); | |
856 | return -EINVAL; | |
857 | } | |
858 | snd_soc_update_bits(codec, | |
859 | RT286_I2S_CTRL2, 0x40, 0x0); | |
860 | break; | |
861 | case 12288000: | |
862 | case 11289600: | |
863 | snd_soc_update_bits(codec, | |
864 | RT286_I2S_CTRL2, 0x8, 0x0); | |
865 | snd_soc_update_bits(codec, | |
866 | RT286_CLK_DIV, 0xfc1e, 0x0004); | |
867 | break; | |
868 | case 24576000: | |
869 | case 22579200: | |
870 | snd_soc_update_bits(codec, | |
871 | RT286_I2S_CTRL2, 0x8, 0x8); | |
872 | snd_soc_update_bits(codec, | |
873 | RT286_CLK_DIV, 0xfc1e, 0x5406); | |
874 | break; | |
875 | default: | |
876 | dev_err(codec->dev, "Unsupported system clock\n"); | |
877 | return -EINVAL; | |
878 | } | |
879 | ||
880 | rt286->sys_clk = freq; | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
885 | static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) | |
886 | { | |
887 | struct snd_soc_codec *codec = dai->codec; | |
888 | ||
889 | dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio); | |
890 | if (50 == ratio) | |
891 | snd_soc_update_bits(codec, | |
892 | RT286_I2S_CTRL1, 0x1000, 0x1000); | |
893 | else | |
894 | snd_soc_update_bits(codec, | |
895 | RT286_I2S_CTRL1, 0x1000, 0x0); | |
896 | ||
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | static int rt286_set_bias_level(struct snd_soc_codec *codec, | |
902 | enum snd_soc_bias_level level) | |
903 | { | |
904 | switch (level) { | |
905 | case SND_SOC_BIAS_PREPARE: | |
bc6c4e45 | 906 | if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) { |
07cf7cba BL |
907 | snd_soc_write(codec, |
908 | RT286_SET_AUDIO_POWER, AC_PWRST_D0); | |
bc6c4e45 BL |
909 | snd_soc_update_bits(codec, |
910 | RT286_DC_GAIN, 0x200, 0x200); | |
911 | } | |
912 | break; | |
913 | ||
914 | case SND_SOC_BIAS_ON: | |
915 | mdelay(10); | |
07cf7cba BL |
916 | break; |
917 | ||
918 | case SND_SOC_BIAS_STANDBY: | |
919 | snd_soc_write(codec, | |
920 | RT286_SET_AUDIO_POWER, AC_PWRST_D3); | |
bc6c4e45 BL |
921 | snd_soc_update_bits(codec, |
922 | RT286_DC_GAIN, 0x200, 0x0); | |
07cf7cba BL |
923 | break; |
924 | ||
925 | default: | |
926 | break; | |
927 | } | |
928 | codec->dapm.bias_level = level; | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
933 | static irqreturn_t rt286_irq(int irq, void *data) | |
934 | { | |
935 | struct rt286_priv *rt286 = data; | |
936 | bool hp = false; | |
937 | bool mic = false; | |
938 | int status = 0; | |
939 | ||
90f601ef | 940 | rt286_jack_detect(rt286, &hp, &mic); |
07cf7cba BL |
941 | |
942 | /* Clear IRQ */ | |
90f601ef | 943 | regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1); |
07cf7cba BL |
944 | |
945 | if (hp == true) | |
946 | status |= SND_JACK_HEADPHONE; | |
947 | ||
948 | if (mic == true) | |
949 | status |= SND_JACK_MICROPHONE; | |
950 | ||
951 | snd_soc_jack_report(rt286->jack, status, | |
952 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
953 | ||
954 | pm_wakeup_event(&rt286->i2c->dev, 300); | |
955 | ||
956 | return IRQ_HANDLED; | |
957 | } | |
958 | ||
959 | static int rt286_probe(struct snd_soc_codec *codec) | |
960 | { | |
961 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
07cf7cba BL |
962 | |
963 | codec->dapm.bias_level = SND_SOC_BIAS_OFF; | |
90f601ef BL |
964 | |
965 | if (rt286->i2c->irq) { | |
966 | regmap_update_bits(rt286->regmap, | |
967 | RT286_IRQ_CTRL, 0x2, 0x2); | |
968 | ||
969 | INIT_DELAYED_WORK(&rt286->jack_detect_work, | |
970 | rt286_jack_detect_work); | |
971 | schedule_delayed_work(&rt286->jack_detect_work, | |
972 | msecs_to_jiffies(1250)); | |
973 | } | |
07cf7cba | 974 | |
07cf7cba BL |
975 | return 0; |
976 | } | |
977 | ||
978 | static int rt286_remove(struct snd_soc_codec *codec) | |
979 | { | |
980 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
981 | ||
982 | cancel_delayed_work_sync(&rt286->jack_detect_work); | |
983 | ||
984 | return 0; | |
985 | } | |
986 | ||
987 | #ifdef CONFIG_PM | |
988 | static int rt286_suspend(struct snd_soc_codec *codec) | |
989 | { | |
990 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
991 | ||
992 | regcache_cache_only(rt286->regmap, true); | |
993 | regcache_mark_dirty(rt286->regmap); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
998 | static int rt286_resume(struct snd_soc_codec *codec) | |
999 | { | |
1000 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
1001 | ||
1002 | regcache_cache_only(rt286->regmap, false); | |
1003 | rt286_index_sync(codec); | |
1004 | regcache_sync(rt286->regmap); | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | #else | |
1009 | #define rt286_suspend NULL | |
1010 | #define rt286_resume NULL | |
1011 | #endif | |
1012 | ||
1013 | #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) | |
1014 | #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
1015 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | |
1016 | ||
1017 | static const struct snd_soc_dai_ops rt286_aif_dai_ops = { | |
1018 | .hw_params = rt286_hw_params, | |
1019 | .set_fmt = rt286_set_dai_fmt, | |
1020 | .set_sysclk = rt286_set_dai_sysclk, | |
1021 | .set_bclk_ratio = rt286_set_bclk_ratio, | |
1022 | }; | |
1023 | ||
1024 | static struct snd_soc_dai_driver rt286_dai[] = { | |
1025 | { | |
1026 | .name = "rt286-aif1", | |
1027 | .id = RT286_AIF1, | |
1028 | .playback = { | |
1029 | .stream_name = "AIF1 Playback", | |
1030 | .channels_min = 1, | |
1031 | .channels_max = 2, | |
1032 | .rates = RT286_STEREO_RATES, | |
1033 | .formats = RT286_FORMATS, | |
1034 | }, | |
1035 | .capture = { | |
1036 | .stream_name = "AIF1 Capture", | |
1037 | .channels_min = 1, | |
1038 | .channels_max = 2, | |
1039 | .rates = RT286_STEREO_RATES, | |
1040 | .formats = RT286_FORMATS, | |
1041 | }, | |
1042 | .ops = &rt286_aif_dai_ops, | |
1043 | .symmetric_rates = 1, | |
1044 | }, | |
1045 | { | |
1046 | .name = "rt286-aif2", | |
1047 | .id = RT286_AIF2, | |
1048 | .playback = { | |
1049 | .stream_name = "AIF2 Playback", | |
1050 | .channels_min = 1, | |
1051 | .channels_max = 2, | |
1052 | .rates = RT286_STEREO_RATES, | |
1053 | .formats = RT286_FORMATS, | |
1054 | }, | |
1055 | .capture = { | |
1056 | .stream_name = "AIF2 Capture", | |
1057 | .channels_min = 1, | |
1058 | .channels_max = 2, | |
1059 | .rates = RT286_STEREO_RATES, | |
1060 | .formats = RT286_FORMATS, | |
1061 | }, | |
1062 | .ops = &rt286_aif_dai_ops, | |
1063 | .symmetric_rates = 1, | |
1064 | }, | |
1065 | ||
1066 | }; | |
1067 | ||
1068 | static struct snd_soc_codec_driver soc_codec_dev_rt286 = { | |
1069 | .probe = rt286_probe, | |
1070 | .remove = rt286_remove, | |
1071 | .suspend = rt286_suspend, | |
1072 | .resume = rt286_resume, | |
1073 | .set_bias_level = rt286_set_bias_level, | |
1074 | .idle_bias_off = true, | |
1075 | .controls = rt286_snd_controls, | |
1076 | .num_controls = ARRAY_SIZE(rt286_snd_controls), | |
1077 | .dapm_widgets = rt286_dapm_widgets, | |
1078 | .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets), | |
1079 | .dapm_routes = rt286_dapm_routes, | |
1080 | .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes), | |
1081 | }; | |
1082 | ||
1083 | static const struct regmap_config rt286_regmap = { | |
1084 | .reg_bits = 32, | |
1085 | .val_bits = 32, | |
1086 | .max_register = 0x02370100, | |
1087 | .volatile_reg = rt286_volatile_register, | |
1088 | .readable_reg = rt286_readable_register, | |
1089 | .reg_write = rt286_hw_write, | |
1090 | .reg_read = rt286_hw_read, | |
1091 | .cache_type = REGCACHE_RBTREE, | |
1092 | .reg_defaults = rt286_reg, | |
1093 | .num_reg_defaults = ARRAY_SIZE(rt286_reg), | |
1094 | }; | |
1095 | ||
1096 | static const struct i2c_device_id rt286_i2c_id[] = { | |
1097 | {"rt286", 0}, | |
1098 | {} | |
1099 | }; | |
1100 | MODULE_DEVICE_TABLE(i2c, rt286_i2c_id); | |
1101 | ||
1102 | static const struct acpi_device_id rt286_acpi_match[] = { | |
1103 | { "INT343A", 0 }, | |
1104 | {}, | |
1105 | }; | |
1106 | MODULE_DEVICE_TABLE(acpi, rt286_acpi_match); | |
1107 | ||
1108 | static int rt286_i2c_probe(struct i2c_client *i2c, | |
1109 | const struct i2c_device_id *id) | |
1110 | { | |
1111 | struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev); | |
1112 | struct rt286_priv *rt286; | |
61a414c4 | 1113 | int i, ret; |
07cf7cba BL |
1114 | |
1115 | rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286), | |
1116 | GFP_KERNEL); | |
1117 | if (NULL == rt286) | |
1118 | return -ENOMEM; | |
1119 | ||
1120 | rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap); | |
1121 | if (IS_ERR(rt286->regmap)) { | |
1122 | ret = PTR_ERR(rt286->regmap); | |
1123 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
1124 | ret); | |
1125 | return ret; | |
1126 | } | |
1127 | ||
4b21768a BL |
1128 | regmap_read(rt286->regmap, |
1129 | RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret); | |
1130 | if (ret != RT286_VENDOR_ID) { | |
1131 | dev_err(&i2c->dev, | |
1132 | "Device with ID register %x is not rt286\n", ret); | |
1133 | return -ENODEV; | |
1134 | } | |
1135 | ||
07cf7cba BL |
1136 | rt286->index_cache = rt286_index_def; |
1137 | rt286->i2c = i2c; | |
1138 | i2c_set_clientdata(i2c, rt286); | |
1139 | ||
1140 | if (pdata) | |
1141 | rt286->pdata = *pdata; | |
1142 | ||
61a414c4 BL |
1143 | regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3); |
1144 | ||
1145 | for (i = 0; i < RT286_POWER_REG_LEN; i++) | |
1146 | regmap_write(rt286->regmap, | |
1147 | RT286_SET_POWER(rt286_support_power_controls[i]), | |
1148 | AC_PWRST_D1); | |
1149 | ||
1150 | if (!rt286->pdata.cbj_en) { | |
1151 | regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000); | |
1152 | regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816); | |
1153 | regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000); | |
1154 | regmap_update_bits(rt286->regmap, | |
1155 | RT286_CBJ_CTRL1, 0xf000, 0xb000); | |
1156 | } else { | |
1157 | regmap_update_bits(rt286->regmap, | |
1158 | RT286_CBJ_CTRL1, 0xf000, 0x5000); | |
1159 | } | |
1160 | ||
1161 | mdelay(10); | |
1162 | ||
1163 | if (!rt286->pdata.gpio2_en) | |
1164 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000); | |
1165 | else | |
1166 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0); | |
1167 | ||
1168 | mdelay(10); | |
1169 | ||
1170 | /*Power down LDO2*/ | |
1171 | regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0x8, 0x0); | |
1172 | ||
bc6c4e45 BL |
1173 | /*Set depop parameter*/ |
1174 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a); | |
1175 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737); | |
1176 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f); | |
1177 | ||
61a414c4 | 1178 | if (rt286->i2c->irq) { |
61a414c4 BL |
1179 | ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, |
1180 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286); | |
1181 | if (ret != 0) { | |
1182 | dev_err(&i2c->dev, | |
1183 | "Failed to reguest IRQ: %d\n", ret); | |
1184 | return ret; | |
1185 | } | |
1186 | } | |
1187 | ||
07cf7cba BL |
1188 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286, |
1189 | rt286_dai, ARRAY_SIZE(rt286_dai)); | |
1190 | ||
1191 | return ret; | |
1192 | } | |
1193 | ||
1194 | static int rt286_i2c_remove(struct i2c_client *i2c) | |
1195 | { | |
1196 | struct rt286_priv *rt286 = i2c_get_clientdata(i2c); | |
1197 | ||
1198 | if (i2c->irq) | |
1199 | free_irq(i2c->irq, rt286); | |
1200 | snd_soc_unregister_codec(&i2c->dev); | |
1201 | ||
1202 | return 0; | |
1203 | } | |
1204 | ||
1205 | ||
23c4fd5c | 1206 | static struct i2c_driver rt286_i2c_driver = { |
07cf7cba BL |
1207 | .driver = { |
1208 | .name = "rt286", | |
1209 | .owner = THIS_MODULE, | |
1210 | .acpi_match_table = ACPI_PTR(rt286_acpi_match), | |
1211 | }, | |
1212 | .probe = rt286_i2c_probe, | |
1213 | .remove = rt286_i2c_remove, | |
1214 | .id_table = rt286_i2c_id, | |
1215 | }; | |
1216 | ||
1217 | module_i2c_driver(rt286_i2c_driver); | |
1218 | ||
1219 | MODULE_DESCRIPTION("ASoC RT286 driver"); | |
1220 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); | |
1221 | MODULE_LICENSE("GPL"); |