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ASoC: rt286: Restore default in probe
[deliverable/linux.git] / sound / soc / codecs / rt286.c
CommitLineData
07cf7cba
BL		 1/*
2 * rt286.c -- RT286 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
6c67cde2 20#include <linux/dmi.h>
07cf7cba
BL		 21#include <linux/acpi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <linux/workqueue.h>
31#include <sound/rt286.h>
32#include <sound/hda_verbs.h>
33
34#include "rt286.h"
35
36#define RT286_VENDOR_ID 0x10ec0286
3ab888db 37#define RT288_VENDOR_ID 0x10ec0288
07cf7cba
BL		 38
39struct rt286_priv {
40 struct regmap *regmap;
6879db76 41 struct snd_soc_codec *codec;
07cf7cba
BL		 42 struct rt286_platform_data pdata;
43 struct i2c_client *i2c;
44 struct snd_soc_jack *jack;
45 struct delayed_work jack_detect_work;
46 int sys_clk;
6879db76 47 int clk_id;
07cf7cba
BL		 48 struct reg_default *index_cache;
49};
50
51static struct reg_default rt286_index_def[] = {
52 { 0x01, 0xaaaa },
53 { 0x02, 0x8aaa },
54 { 0x03, 0x0002 },
55 { 0x04, 0xaf01 },
56 { 0x08, 0x000d },
57 { 0x09, 0xd810 },
b7a29767 58 { 0x0a, 0x0120 },
07cf7cba 59 { 0x0b, 0x0000 },
bc6c4e45 60 { 0x0d, 0x2800 },
07cf7cba
BL		 61 { 0x0f, 0x0000 },
62 { 0x19, 0x0a17 },
63 { 0x20, 0x0020 },
64 { 0x33, 0x0208 },
65 { 0x49, 0x0004 },
66 { 0x4f, 0x50e9 },
b7a29767 67 { 0x50, 0x2000 },
07cf7cba 68 { 0x63, 0x2902 },
bc6c4e45
BL		 69 { 0x67, 0x1111 },
70 { 0x68, 0x1016 },
71 { 0x69, 0x273f },
07cf7cba
BL		 72};
73#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
74
75static const struct reg_default rt286_reg[] = {
76 { 0x00170500, 0x00000400 },
77 { 0x00220000, 0x00000031 },
78 { 0x00239000, 0x0000007f },
79 { 0x0023a000, 0x0000007f },
80 { 0x00270500, 0x00000400 },
81 { 0x00370500, 0x00000400 },
82 { 0x00870500, 0x00000400 },
83 { 0x00920000, 0x00000031 },
84 { 0x00935000, 0x000000c3 },
85 { 0x00936000, 0x000000c3 },
86 { 0x00970500, 0x00000400 },
87 { 0x00b37000, 0x00000097 },
88 { 0x00b37200, 0x00000097 },
89 { 0x00b37300, 0x00000097 },
90 { 0x00c37000, 0x00000000 },
91 { 0x00c37100, 0x00000080 },
92 { 0x01270500, 0x00000400 },
93 { 0x01370500, 0x00000400 },
94 { 0x01371f00, 0x411111f0 },
95 { 0x01439000, 0x00000080 },
96 { 0x0143a000, 0x00000080 },
97 { 0x01470700, 0x00000000 },
98 { 0x01470500, 0x00000400 },
99 { 0x01470c00, 0x00000000 },
100 { 0x01470100, 0x00000000 },
101 { 0x01837000, 0x00000000 },
102 { 0x01870500, 0x00000400 },
103 { 0x02050000, 0x00000000 },
104 { 0x02139000, 0x00000080 },
105 { 0x0213a000, 0x00000080 },
106 { 0x02170100, 0x00000000 },
107 { 0x02170500, 0x00000400 },
108 { 0x02170700, 0x00000000 },
109 { 0x02270100, 0x00000000 },
110 { 0x02370100, 0x00000000 },
07cf7cba
BL		 111 { 0x01870700, 0x00000020 },
112 { 0x00830000, 0x000000c3 },
113 { 0x00930000, 0x000000c3 },
114 { 0x01270700, 0x00000000 },
115};
116
117static bool rt286_volatile_register(struct device *dev, unsigned int reg)
118{
119 switch (reg) {
120 case 0 ... 0xff:
121 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
122 case RT286_GET_HP_SENSE:
123 case RT286_GET_MIC1_SENSE:
124 case RT286_PROC_COEF:
125 return true;
126 default:
127 return false;
128 }
129
130
131}
132
133static bool rt286_readable_register(struct device *dev, unsigned int reg)
134{
135 switch (reg) {
136 case 0 ... 0xff:
137 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
138 case RT286_GET_HP_SENSE:
139 case RT286_GET_MIC1_SENSE:
140 case RT286_SET_AUDIO_POWER:
141 case RT286_SET_HPO_POWER:
142 case RT286_SET_SPK_POWER:
143 case RT286_SET_DMIC1_POWER:
144 case RT286_SPK_MUX:
145 case RT286_HPO_MUX:
146 case RT286_ADC0_MUX:
147 case RT286_ADC1_MUX:
148 case RT286_SET_MIC1:
149 case RT286_SET_PIN_HPO:
150 case RT286_SET_PIN_SPK:
151 case RT286_SET_PIN_DMIC1:
152 case RT286_SPK_EAPD:
153 case RT286_SET_AMP_GAIN_HPO:
154 case RT286_SET_DMIC2_DEFAULT:
155 case RT286_DACL_GAIN:
156 case RT286_DACR_GAIN:
157 case RT286_ADCL_GAIN:
158 case RT286_ADCR_GAIN:
159 case RT286_MIC_GAIN:
160 case RT286_SPOL_GAIN:
161 case RT286_SPOR_GAIN:
162 case RT286_HPOL_GAIN:
163 case RT286_HPOR_GAIN:
164 case RT286_F_DAC_SWITCH:
165 case RT286_F_RECMIX_SWITCH:
166 case RT286_REC_MIC_SWITCH:
167 case RT286_REC_I2S_SWITCH:
168 case RT286_REC_LINE_SWITCH:
169 case RT286_REC_BEEP_SWITCH:
170 case RT286_DAC_FORMAT:
171 case RT286_ADC_FORMAT:
172 case RT286_COEF_INDEX:
173 case RT286_PROC_COEF:
174 case RT286_SET_AMP_GAIN_ADC_IN1:
175 case RT286_SET_AMP_GAIN_ADC_IN2:
176 case RT286_SET_POWER(RT286_DAC_OUT1):
177 case RT286_SET_POWER(RT286_DAC_OUT2):
178 case RT286_SET_POWER(RT286_ADC_IN1):
179 case RT286_SET_POWER(RT286_ADC_IN2):
180 case RT286_SET_POWER(RT286_DMIC2):
181 case RT286_SET_POWER(RT286_MIC1):
182 return true;
183 default:
184 return false;
185 }
186}
187
188static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
189{
190 struct i2c_client *client = context;
191 struct rt286_priv *rt286 = i2c_get_clientdata(client);
192 u8 data[4];
193 int ret, i;
194
f8c101bc 195 /* handle index registers */
07cf7cba
BL		 196 if (reg <= 0xff) {
197 rt286_hw_write(client, RT286_COEF_INDEX, reg);
07cf7cba
BL		 198 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
199 if (reg == rt286->index_cache[i].reg) {
200 rt286->index_cache[i].def = value;
201 break;
202 }
203
204 }
66d627d5 205 reg = RT286_PROC_COEF;
07cf7cba
BL		 206 }
207
208 data[0] = (reg >> 24) & 0xff;
209 data[1] = (reg >> 16) & 0xff;
210 /*
211 * 4 bit VID: reg should be 0
212 * 12 bit VID: value should be 0
213 * So we use an OR operator to handle it rather than use if condition.
214 */
215 data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
216 data[3] = value & 0xff;
217
218 ret = i2c_master_send(client, data, 4);
219
220 if (ret == 4)
221 return 0;
222 else
223 pr_err("ret=%d\n", ret);
224 if (ret < 0)
225 return ret;
226 else
227 return -EIO;
228}
229
230static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value)
231{
232 struct i2c_client *client = context;
233 struct i2c_msg xfer[2];
234 int ret;
235 __be32 be_reg;
236 unsigned int index, vid, buf = 0x0;
237
f8c101bc 238 /* handle index registers */
07cf7cba
BL		 239 if (reg <= 0xff) {
240 rt286_hw_write(client, RT286_COEF_INDEX, reg);
241 reg = RT286_PROC_COEF;
242 }
243
244 reg = reg | 0x80000;
245 vid = (reg >> 8) & 0xfff;
246
247 if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
248 index = (reg >> 8) & 0xf;
249 reg = (reg & ~0xf0f) | index;
250 }
251 be_reg = cpu_to_be32(reg);
252
253 /* Write register */
254 xfer[0].addr = client->addr;
255 xfer[0].flags = 0;
256 xfer[0].len = 4;
257 xfer[0].buf = (u8 *)&be_reg;
258
259 /* Read data */
260 xfer[1].addr = client->addr;
261 xfer[1].flags = I2C_M_RD;
262 xfer[1].len = 4;
263 xfer[1].buf = (u8 *)&buf;
264
265 ret = i2c_transfer(client->adapter, xfer, 2);
266 if (ret < 0)
267 return ret;
268 else if (ret != 2)
269 return -EIO;
270
271 *value = be32_to_cpu(buf);
272
273 return 0;
274}
275
81f3dfe1 276#ifdef CONFIG_PM
07cf7cba
BL		 277static void rt286_index_sync(struct snd_soc_codec *codec)
278{
279 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
280 int i;
281
282 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
283 snd_soc_write(codec, rt286->index_cache[i].reg,
284 rt286->index_cache[i].def);
285 }
286}
81f3dfe1 287#endif
07cf7cba
BL		 288
289static int rt286_support_power_controls[] = {
290 RT286_DAC_OUT1,
291 RT286_DAC_OUT2,
292 RT286_ADC_IN1,
293 RT286_ADC_IN2,
294 RT286_MIC1,
295 RT286_DMIC1,
296 RT286_DMIC2,
297 RT286_SPK_OUT,
298 RT286_HP_OUT,
299};
300#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
301
90f601ef 302static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
07cf7cba 303{
07cf7cba 304 unsigned int val, buf;
07cf7cba
BL		 305
306 *hp = false;
307 *mic = false;
308
28d1ad09
BL		 309 if (!rt286->codec)
310 return -EINVAL;
07cf7cba 311 if (rt286->pdata.cbj_en) {
90f601ef 312 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
07cf7cba
BL		 313 *hp = buf & 0x80000000;
314 if (*hp) {
315 /* power on HV,VERF */
90f601ef 316 regmap_update_bits(rt286->regmap,
6879db76
BL		 317 RT286_DC_GAIN, 0x200, 0x200);
318
319 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
320 "HV");
321 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
322 "VREF");
07cf7cba 323 /* power LDO1 */
6879db76
BL		 324 snd_soc_dapm_force_enable_pin(&rt286->codec->dapm,
325 "LDO1");
326 snd_soc_dapm_sync(&rt286->codec->dapm);
07cf7cba 327
6879db76
BL		 328 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
329 msleep(50);
07cf7cba 330
6879db76
BL		 331 regmap_update_bits(rt286->regmap,
332 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
333 msleep(300);
334 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
07cf7cba 335
6879db76 336 if (0x0070 == (val & 0x0070)) {
07cf7cba 337 *mic = true;
07cf7cba 338 } else {
6879db76
BL		 339 regmap_update_bits(rt286->regmap,
340 RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
341 msleep(300);
342 regmap_read(rt286->regmap,
343 RT286_CBJ_CTRL2, &val);
344 if (0x0070 == (val & 0x0070))
345 *mic = true;
346 else
347 *mic = false;
07cf7cba 348 }
90f601ef 349 regmap_update_bits(rt286->regmap,
6879db76 350 RT286_DC_GAIN, 0x200, 0x0);
07cf7cba 351
6879db76 352 } else {
07cf7cba 353 *mic = false;
6879db76 354 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
07cf7cba
BL		 355 }
356 } else {
90f601ef 357 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
07cf7cba 358 *hp = buf & 0x80000000;
90f601ef 359 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
07cf7cba
BL		 360 *mic = buf & 0x80000000;
361 }
362
6879db76
BL		 363 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "HV");
364 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "VREF");
365 if (!*hp)
366 snd_soc_dapm_disable_pin(&rt286->codec->dapm, "LDO1");
367 snd_soc_dapm_sync(&rt286->codec->dapm);
368
07cf7cba
BL		 369 return 0;
370}
371
372static void rt286_jack_detect_work(struct work_struct *work)
373{
374 struct rt286_priv *rt286 =
375 container_of(work, struct rt286_priv, jack_detect_work.work);
376 int status = 0;
377 bool hp = false;
378 bool mic = false;
379
90f601ef 380 rt286_jack_detect(rt286, &hp, &mic);
07cf7cba
BL		 381
382 if (hp == true)
383 status |= SND_JACK_HEADPHONE;
384
385 if (mic == true)
386 status |= SND_JACK_MICROPHONE;
387
388 snd_soc_jack_report(rt286->jack, status,
389 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
390}
391
392int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
393{
394 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
395
396 rt286->jack = jack;
397
e2cef68d
JY		 398 if (jack) {
399 /* enable IRQ */
5af76d5c 400 if (rt286->jack->status & SND_JACK_HEADPHONE)
e2cef68d
JY		 401 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO1");
402 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
403 /* Send an initial empty report */
404 snd_soc_jack_report(rt286->jack, rt286->jack->status,
405 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
406 } else {
407 /* disable IRQ */
408 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
409 snd_soc_dapm_disable_pin(&codec->dapm, "LDO1");
410 }
411 snd_soc_dapm_sync(&codec->dapm);
07cf7cba
BL		 412
413 return 0;
414}
415EXPORT_SYMBOL_GPL(rt286_mic_detect);
416
6879db76
BL		 417static int is_mclk_mode(struct snd_soc_dapm_widget *source,
418 struct snd_soc_dapm_widget *sink)
419{
76f17f18
LPC		 420 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
421 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
6879db76
BL		 422
423 if (rt286->clk_id == RT286_SCLK_S_MCLK)
424 return 1;
425 else
426 return 0;
427}
428
07cf7cba
BL		 429static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
430static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
431
432static const struct snd_kcontrol_new rt286_snd_controls[] = {
433 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
434 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
54d96a40
BL		 435 SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
436 RT286_ADCR_GAIN, 7, 1, 1),
07cf7cba
BL		 437 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
438 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
439 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
440 0, 0x3, 0, mic_vol_tlv),
441 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
442 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
443};
444
445/* Digital Mixer */
446static const struct snd_kcontrol_new rt286_front_mix[] = {
447 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
448 RT286_MUTE_SFT, 1, 1),
449 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
450 RT286_MUTE_SFT, 1, 1),
451};
452
453/* Analog Input Mixer */
454static const struct snd_kcontrol_new rt286_rec_mix[] = {
455 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
456 RT286_MUTE_SFT, 1, 1),
457 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
458 RT286_MUTE_SFT, 1, 1),
459 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
460 RT286_MUTE_SFT, 1, 1),
461 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
462 RT286_MUTE_SFT, 1, 1),
463};
464
465static const struct snd_kcontrol_new spo_enable_control =
466 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
467 RT286_SET_PIN_SFT, 1, 0);
468
469static const struct snd_kcontrol_new hpol_enable_control =
470 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
471 RT286_MUTE_SFT, 1, 1);
472
473static const struct snd_kcontrol_new hpor_enable_control =
474 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
475 RT286_MUTE_SFT, 1, 1);
476
477/* ADC0 source */
478static const char * const rt286_adc_src[] = {
479 "Mic", "RECMIX", "Dmic"
480};
481
482static const int rt286_adc_values[] = {
483 0, 4, 5,
484};
485
486static SOC_VALUE_ENUM_SINGLE_DECL(
487 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
488 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
489
490static const struct snd_kcontrol_new rt286_adc0_mux =
491 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
492
493static SOC_VALUE_ENUM_SINGLE_DECL(
494 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
495 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
496
497static const struct snd_kcontrol_new rt286_adc1_mux =
498 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
499
500static const char * const rt286_dac_src[] = {
501 "Front", "Surround"
502};
503/* HP-OUT source */
504static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
505 0, rt286_dac_src);
506
507static const struct snd_kcontrol_new rt286_hpo_mux =
508SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
509
510/* SPK-OUT source */
511static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
512 0, rt286_dac_src);
513
514static const struct snd_kcontrol_new rt286_spo_mux =
515SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
516
517static int rt286_spk_event(struct snd_soc_dapm_widget *w,
518 struct snd_kcontrol *kcontrol, int event)
519{
76f17f18 520 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
07cf7cba
BL		 521
522 switch (event) {
523 case SND_SOC_DAPM_POST_PMU:
524 snd_soc_write(codec,
525 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
526 break;
527 case SND_SOC_DAPM_PRE_PMD:
528 snd_soc_write(codec,
529 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
530 break;
531
532 default:
533 return 0;
534 }
535
536 return 0;
537}
538
539static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
540 struct snd_kcontrol *kcontrol, int event)
541{
76f17f18 542 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
07cf7cba
BL		 543
544 switch (event) {
545 case SND_SOC_DAPM_POST_PMU:
546 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
547 break;
548 case SND_SOC_DAPM_PRE_PMD:
549 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
550 break;
551 default:
552 return 0;
553 }
554
555 return 0;
556}
557
6879db76
BL		 558static int rt286_vref_event(struct snd_soc_dapm_widget *w,
559 struct snd_kcontrol *kcontrol, int event)
560{
76f17f18 561 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6879db76
BL		 562
563 switch (event) {
564 case SND_SOC_DAPM_PRE_PMU:
565 snd_soc_update_bits(codec,
566 RT286_CBJ_CTRL1, 0x0400, 0x0000);
567 mdelay(50);
568 break;
569 default:
570 return 0;
571 }
572
573 return 0;
574}
575
576static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
577 struct snd_kcontrol *kcontrol, int event)
578{
76f17f18 579 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6879db76
BL		 580
581 switch (event) {
582 case SND_SOC_DAPM_POST_PMU:
583 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
584 break;
585 case SND_SOC_DAPM_PRE_PMD:
586 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
587 break;
588 default:
589 return 0;
590 }
591
592 return 0;
593}
594
595static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
596 struct snd_kcontrol *kcontrol, int event)
597{
76f17f18 598 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
6879db76
BL		 599
600 switch (event) {
601 case SND_SOC_DAPM_PRE_PMU:
602 snd_soc_update_bits(codec,
603 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
604 snd_soc_update_bits(codec,
605 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
606 break;
607 case SND_SOC_DAPM_POST_PMD:
608 snd_soc_update_bits(codec,
609 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
610 snd_soc_update_bits(codec,
611 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
612 break;
613 default:
614 return 0;
615 }
616
617 return 0;
618}
619
07cf7cba 620static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
6879db76
BL		 621 SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
622 12, 1, NULL, 0),
623 SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
624 0, 1, rt286_vref_event, SND_SOC_DAPM_PRE_PMU),
625 SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
626 2, 0, NULL, 0),
627 SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
628 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
629 SND_SOC_DAPM_POST_PMU),
630 SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
631 5, 0, NULL, 0),
632 SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
633 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
634 SND_SOC_DAPM_POST_PMD),
635
07cf7cba
BL		 636 /* Input Lines */
637 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
638 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
639 SND_SOC_DAPM_INPUT("MIC1"),
640 SND_SOC_DAPM_INPUT("LINE1"),
641 SND_SOC_DAPM_INPUT("Beep"),
642
643 /* DMIC */
644 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
645 NULL, 0, rt286_set_dmic1_event,
646 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
647 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
648 NULL, 0),
649 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
650 0, 0, NULL, 0),
651
652 /* REC Mixer */
653 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
654 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
655
656 /* ADCs */
657 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
658 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
659
660 /* ADC Mux */
54d96a40
BL		 661 SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
662 &rt286_adc0_mux),
663 SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
664 &rt286_adc1_mux),
07cf7cba
BL		 665
666 /* Audio Interface */
667 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
668 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
669 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
670 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
671
672 /* Output Side */
673 /* DACs */
674 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
675 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
676
677 /* Output Mux */
678 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
679 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
680
681 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
682 RT286_SET_PIN_SFT, 0, NULL, 0),
683
684 /* Output Mixer */
685 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
686 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
687 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
688 NULL, 0),
689
690 /* Output Pga */
691 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
692 &spo_enable_control, rt286_spk_event,
693 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
694 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
695 &hpol_enable_control),
696 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
697 &hpor_enable_control),
698
699 /* Output Lines */
700 SND_SOC_DAPM_OUTPUT("SPOL"),
701 SND_SOC_DAPM_OUTPUT("SPOR"),
702 SND_SOC_DAPM_OUTPUT("HPO Pin"),
703 SND_SOC_DAPM_OUTPUT("SPDIF"),
704};
705
706static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
6879db76
BL		 707 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
708 {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
709 {"Front", NULL, "MCLK MODE", is_mclk_mode},
710 {"Surround", NULL, "MCLK MODE", is_mclk_mode},
711
712 {"HP Power", NULL, "LDO1"},
713 {"HP Power", NULL, "LDO2"},
714
715 {"MIC1", NULL, "LDO1"},
716 {"MIC1", NULL, "LDO2"},
717 {"MIC1", NULL, "HV"},
718 {"MIC1", NULL, "VREF"},
719 {"MIC1", NULL, "MIC1 Input Buffer"},
720
721 {"SPO", NULL, "LDO1"},
722 {"SPO", NULL, "LDO2"},
723 {"SPO", NULL, "HV"},
724 {"SPO", NULL, "VREF"},
725
07cf7cba
BL		 726 {"DMIC1", NULL, "DMIC1 Pin"},
727 {"DMIC2", NULL, "DMIC2 Pin"},
728 {"DMIC1", NULL, "DMIC Receiver"},
729 {"DMIC2", NULL, "DMIC Receiver"},
730
731 {"RECMIX", "Beep Switch", "Beep"},
732 {"RECMIX", "Line1 Switch", "LINE1"},
733 {"RECMIX", "Mic1 Switch", "MIC1"},
734
735 {"ADC 0 Mux", "Dmic", "DMIC1"},
736 {"ADC 0 Mux", "RECMIX", "RECMIX"},
737 {"ADC 0 Mux", "Mic", "MIC1"},
738 {"ADC 1 Mux", "Dmic", "DMIC2"},
739 {"ADC 1 Mux", "RECMIX", "RECMIX"},
740 {"ADC 1 Mux", "Mic", "MIC1"},
741
742 {"ADC 0", NULL, "ADC 0 Mux"},
743 {"ADC 1", NULL, "ADC 1 Mux"},
744
745 {"AIF1TX", NULL, "ADC 0"},
746 {"AIF2TX", NULL, "ADC 1"},
747
748 {"DAC 0", NULL, "AIF1RX"},
749 {"DAC 1", NULL, "AIF2RX"},
750
751 {"Front", "DAC Switch", "DAC 0"},
752 {"Front", "RECMIX Switch", "RECMIX"},
753
754 {"Surround", NULL, "DAC 1"},
755
756 {"SPK Mux", "Front", "Front"},
757 {"SPK Mux", "Surround", "Surround"},
758
759 {"HPO Mux", "Front", "Front"},
760 {"HPO Mux", "Surround", "Surround"},
761
762 {"SPO", "Switch", "SPK Mux"},
763 {"HPO L", "Switch", "HPO Mux"},
764 {"HPO R", "Switch", "HPO Mux"},
765 {"HPO L", NULL, "HP Power"},
766 {"HPO R", NULL, "HP Power"},
767
768 {"SPOL", NULL, "SPO"},
769 {"SPOR", NULL, "SPO"},
770 {"HPO Pin", NULL, "HPO L"},
771 {"HPO Pin", NULL, "HPO R"},
772};
773
774static int rt286_hw_params(struct snd_pcm_substream *substream,
775 struct snd_pcm_hw_params *params,
776 struct snd_soc_dai *dai)
777{
778 struct snd_soc_codec *codec = dai->codec;
779 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
780 unsigned int val = 0;
781 int d_len_code;
782
783 switch (params_rate(params)) {
784 /* bit 14 0:48K 1:44.1K */
785 case 44100:
786 val |= 0x4000;
787 break;
788 case 48000:
789 break;
790 default:
791 dev_err(codec->dev, "Unsupported sample rate %d\n",
792 params_rate(params));
793 return -EINVAL;
794 }
795 switch (rt286->sys_clk) {
796 case 12288000:
797 case 24576000:
798 if (params_rate(params) != 48000) {
799 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
800 params_rate(params), rt286->sys_clk);
801 return -EINVAL;
802 }
803 break;
804 case 11289600:
805 case 22579200:
806 if (params_rate(params) != 44100) {
807 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
808 params_rate(params), rt286->sys_clk);
809 return -EINVAL;
810 }
811 break;
812 }
813
814 if (params_channels(params) <= 16) {
815 /* bit 3:0 Number of Channel */
816 val |= (params_channels(params) - 1);
817 } else {
818 dev_err(codec->dev, "Unsupported channels %d\n",
819 params_channels(params));
820 return -EINVAL;
821 }
822
823 d_len_code = 0;
824 switch (params_width(params)) {
825 /* bit 6:4 Bits per Sample */
826 case 16:
827 d_len_code = 0;
828 val |= (0x1 << 4);
829 break;
830 case 32:
831 d_len_code = 2;
832 val |= (0x4 << 4);
833 break;
834 case 20:
835 d_len_code = 1;
836 val |= (0x2 << 4);
837 break;
838 case 24:
839 d_len_code = 2;
840 val |= (0x3 << 4);
841 break;
842 case 8:
843 d_len_code = 3;
844 break;
845 default:
846 return -EINVAL;
847 }
848
849 snd_soc_update_bits(codec,
850 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
851 dev_dbg(codec->dev, "format val = 0x%x\n", val);
852
45437fa5
BL		 853 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
854 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
07cf7cba
BL		 855
856 return 0;
857}
858
859static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
860{
861 struct snd_soc_codec *codec = dai->codec;
862
863 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
864 case SND_SOC_DAIFMT_CBM_CFM:
865 snd_soc_update_bits(codec,
866 RT286_I2S_CTRL1, 0x800, 0x800);
867 break;
868 case SND_SOC_DAIFMT_CBS_CFS:
869 snd_soc_update_bits(codec,
870 RT286_I2S_CTRL1, 0x800, 0x0);
871 break;
872 default:
873 return -EINVAL;
874 }
875
876 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
877 case SND_SOC_DAIFMT_I2S:
878 snd_soc_update_bits(codec,
879 RT286_I2S_CTRL1, 0x300, 0x0);
880 break;
881 case SND_SOC_DAIFMT_LEFT_J:
882 snd_soc_update_bits(codec,
883 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
884 break;
885 case SND_SOC_DAIFMT_DSP_A:
886 snd_soc_update_bits(codec,
887 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
888 break;
889 case SND_SOC_DAIFMT_DSP_B:
890 snd_soc_update_bits(codec,
891 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
892 break;
893 default:
894 return -EINVAL;
895 }
896 /* bit 15 Stream Type 0:PCM 1:Non-PCM */
897 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
898 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
899
900 return 0;
901}
902
903static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
904 int clk_id, unsigned int freq, int dir)
905{
906 struct snd_soc_codec *codec = dai->codec;
907 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
908
909 dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
910
911 if (RT286_SCLK_S_MCLK == clk_id) {
912 snd_soc_update_bits(codec,
913 RT286_I2S_CTRL2, 0x0100, 0x0);
914 snd_soc_update_bits(codec,
915 RT286_PLL_CTRL1, 0x20, 0x20);
916 } else {
917 snd_soc_update_bits(codec,
918 RT286_I2S_CTRL2, 0x0100, 0x0100);
919 snd_soc_update_bits(codec,
920 RT286_PLL_CTRL, 0x4, 0x4);
921 snd_soc_update_bits(codec,
922 RT286_PLL_CTRL1, 0x20, 0x0);
923 }
924
925 switch (freq) {
926 case 19200000:
927 if (RT286_SCLK_S_MCLK == clk_id) {
928 dev_err(codec->dev, "Should not use MCLK\n");
929 return -EINVAL;
930 }
931 snd_soc_update_bits(codec,
932 RT286_I2S_CTRL2, 0x40, 0x40);
933 break;
934 case 24000000:
935 if (RT286_SCLK_S_MCLK == clk_id) {
936 dev_err(codec->dev, "Should not use MCLK\n");
937 return -EINVAL;
938 }
939 snd_soc_update_bits(codec,
940 RT286_I2S_CTRL2, 0x40, 0x0);
941 break;
942 case 12288000:
943 case 11289600:
944 snd_soc_update_bits(codec,
945 RT286_I2S_CTRL2, 0x8, 0x0);
946 snd_soc_update_bits(codec,
947 RT286_CLK_DIV, 0xfc1e, 0x0004);
948 break;
949 case 24576000:
950 case 22579200:
951 snd_soc_update_bits(codec,
952 RT286_I2S_CTRL2, 0x8, 0x8);
953 snd_soc_update_bits(codec,
954 RT286_CLK_DIV, 0xfc1e, 0x5406);
955 break;
956 default:
957 dev_err(codec->dev, "Unsupported system clock\n");
958 return -EINVAL;
959 }
960
961 rt286->sys_clk = freq;
6879db76 962 rt286->clk_id = clk_id;
07cf7cba
BL		 963
964 return 0;
965}
966
967static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
968{
969 struct snd_soc_codec *codec = dai->codec;
970
971 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
972 if (50 == ratio)
973 snd_soc_update_bits(codec,
974 RT286_I2S_CTRL1, 0x1000, 0x1000);
975 else
976 snd_soc_update_bits(codec,
977 RT286_I2S_CTRL1, 0x1000, 0x0);
978
979
980 return 0;
981}
982
983static int rt286_set_bias_level(struct snd_soc_codec *codec,
984 enum snd_soc_bias_level level)
985{
986 switch (level) {
987 case SND_SOC_BIAS_PREPARE:
bc6c4e45 988 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
07cf7cba
BL		 989 snd_soc_write(codec,
990 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
bc6c4e45
BL		 991 snd_soc_update_bits(codec,
992 RT286_DC_GAIN, 0x200, 0x200);
993 }
994 break;
995
996 case SND_SOC_BIAS_ON:
997 mdelay(10);
6879db76
BL		 998 snd_soc_update_bits(codec,
999 RT286_CBJ_CTRL1, 0x0400, 0x0400);
1000 snd_soc_update_bits(codec,
1001 RT286_DC_GAIN, 0x200, 0x0);
1002
07cf7cba
BL		 1003 break;
1004
1005 case SND_SOC_BIAS_STANDBY:
1006 snd_soc_write(codec,
1007 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
bc6c4e45 1008 snd_soc_update_bits(codec,
6879db76 1009 RT286_CBJ_CTRL1, 0x0400, 0x0000);
07cf7cba
BL		 1010 break;
1011
1012 default:
1013 break;
1014 }
1015 codec->dapm.bias_level = level;
1016
1017 return 0;
1018}
1019
1020static irqreturn_t rt286_irq(int irq, void *data)
1021{
1022 struct rt286_priv *rt286 = data;
1023 bool hp = false;
1024 bool mic = false;
1025 int status = 0;
1026
90f601ef 1027 rt286_jack_detect(rt286, &hp, &mic);
07cf7cba
BL		 1028
1029 /* Clear IRQ */
90f601ef 1030 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
07cf7cba
BL		 1031
1032 if (hp == true)
1033 status |= SND_JACK_HEADPHONE;
1034
1035 if (mic == true)
1036 status |= SND_JACK_MICROPHONE;
1037
1038 snd_soc_jack_report(rt286->jack, status,
1039 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
1040
1041 pm_wakeup_event(&rt286->i2c->dev, 300);
1042
1043 return IRQ_HANDLED;
1044}
1045
1046static int rt286_probe(struct snd_soc_codec *codec)
1047{
1048 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
07cf7cba 1049
6879db76 1050 rt286->codec = codec;
90f601ef
BL		 1051
1052 if (rt286->i2c->irq) {
1053 regmap_update_bits(rt286->regmap,
1054 RT286_IRQ_CTRL, 0x2, 0x2);
1055
1056 INIT_DELAYED_WORK(&rt286->jack_detect_work,
1057 rt286_jack_detect_work);
1058 schedule_delayed_work(&rt286->jack_detect_work,
1059 msecs_to_jiffies(1250));
1060 }
07cf7cba 1061
07cf7cba
BL		 1062 return 0;
1063}
1064
1065static int rt286_remove(struct snd_soc_codec *codec)
1066{
1067 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1068
1069 cancel_delayed_work_sync(&rt286->jack_detect_work);
1070
1071 return 0;
1072}
1073
1074#ifdef CONFIG_PM
1075static int rt286_suspend(struct snd_soc_codec *codec)
1076{
1077 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1078
1079 regcache_cache_only(rt286->regmap, true);
1080 regcache_mark_dirty(rt286->regmap);
1081
1082 return 0;
1083}
1084
1085static int rt286_resume(struct snd_soc_codec *codec)
1086{
1087 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1088
1089 regcache_cache_only(rt286->regmap, false);
1090 rt286_index_sync(codec);
1091 regcache_sync(rt286->regmap);
1092
1093 return 0;
1094}
1095#else
1096#define rt286_suspend NULL
1097#define rt286_resume NULL
1098#endif
1099
1100#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1101#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1102 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1103
1104static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1105 .hw_params = rt286_hw_params,
1106 .set_fmt = rt286_set_dai_fmt,
1107 .set_sysclk = rt286_set_dai_sysclk,
1108 .set_bclk_ratio = rt286_set_bclk_ratio,
1109};
1110
1111static struct snd_soc_dai_driver rt286_dai[] = {
1112 {
1113 .name = "rt286-aif1",
1114 .id = RT286_AIF1,
1115 .playback = {
1116 .stream_name = "AIF1 Playback",
1117 .channels_min = 1,
1118 .channels_max = 2,
1119 .rates = RT286_STEREO_RATES,
1120 .formats = RT286_FORMATS,
1121 },
1122 .capture = {
1123 .stream_name = "AIF1 Capture",
1124 .channels_min = 1,
1125 .channels_max = 2,
1126 .rates = RT286_STEREO_RATES,
1127 .formats = RT286_FORMATS,
1128 },
1129 .ops = &rt286_aif_dai_ops,
1130 .symmetric_rates = 1,
1131 },
1132 {
1133 .name = "rt286-aif2",
1134 .id = RT286_AIF2,
1135 .playback = {
1136 .stream_name = "AIF2 Playback",
1137 .channels_min = 1,
1138 .channels_max = 2,
1139 .rates = RT286_STEREO_RATES,
1140 .formats = RT286_FORMATS,
1141 },
1142 .capture = {
1143 .stream_name = "AIF2 Capture",
1144 .channels_min = 1,
1145 .channels_max = 2,
1146 .rates = RT286_STEREO_RATES,
1147 .formats = RT286_FORMATS,
1148 },
1149 .ops = &rt286_aif_dai_ops,
1150 .symmetric_rates = 1,
1151 },
1152
1153};
1154
1155static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1156 .probe = rt286_probe,
1157 .remove = rt286_remove,
1158 .suspend = rt286_suspend,
1159 .resume = rt286_resume,
1160 .set_bias_level = rt286_set_bias_level,
1161 .idle_bias_off = true,
1162 .controls = rt286_snd_controls,
1163 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1164 .dapm_widgets = rt286_dapm_widgets,
1165 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1166 .dapm_routes = rt286_dapm_routes,
1167 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1168};
1169
1170static const struct regmap_config rt286_regmap = {
1171 .reg_bits = 32,
1172 .val_bits = 32,
1173 .max_register = 0x02370100,
1174 .volatile_reg = rt286_volatile_register,
1175 .readable_reg = rt286_readable_register,
1176 .reg_write = rt286_hw_write,
1177 .reg_read = rt286_hw_read,
1178 .cache_type = REGCACHE_RBTREE,
1179 .reg_defaults = rt286_reg,
1180 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1181};
1182
1183static const struct i2c_device_id rt286_i2c_id[] = {
1184 {"rt286", 0},
3ab888db 1185 {"rt288", 0},
07cf7cba
BL		 1186 {}
1187};
1188MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1189
1190static const struct acpi_device_id rt286_acpi_match[] = {
1191 { "INT343A", 0 },
1192 {},
1193};
1194MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1195
a5a267cf 1196static struct dmi_system_id force_combo_jack_table[] = {
6c67cde2
BL		 1197 {
1198 .ident = "Intel Wilson Beach",
1199 .matches = {
1200 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1201 }
1202 },
1203 { }
1204};
1205
2cc3f234
BL		 1206static struct dmi_system_id dmi_dell_dino[] = {
1207 {
1208 .ident = "Dell Dino",
1209 .matches = {
1210 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1211 DMI_MATCH(DMI_BOARD_NAME, "0144P8")
1212 }
1213 },
1214 { }
1215};
1216
07cf7cba
BL		 1217static int rt286_i2c_probe(struct i2c_client *i2c,
1218 const struct i2c_device_id *id)
1219{
1220 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1221 struct rt286_priv *rt286;
143526ee 1222 int i, ret, val;
07cf7cba
BL		 1223
1224 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1225 GFP_KERNEL);
1226 if (NULL == rt286)
1227 return -ENOMEM;
1228
1229 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1230 if (IS_ERR(rt286->regmap)) {
1231 ret = PTR_ERR(rt286->regmap);
1232 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1233 ret);
1234 return ret;
1235 }
1236
143526ee
BL		 1237 ret = regmap_read(rt286->regmap,
1238 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
1239 if (ret != 0) {
1240 dev_err(&i2c->dev, "I2C error %d\n", ret);
1241 return ret;
1242 }
1243 if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) {
4b21768a 1244 dev_err(&i2c->dev,
143526ee 1245 "Device with ID register %x is not rt286\n", val);
4b21768a
BL		 1246 return -ENODEV;
1247 }
1248
07cf7cba
BL		 1249 rt286->index_cache = rt286_index_def;
1250 rt286->i2c = i2c;
1251 i2c_set_clientdata(i2c, rt286);
1252
d53d59ec
BL		 1253 /* restore codec default */
1254 for (i = 0; i < INDEX_CACHE_SIZE; i++)
1255 regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1256 rt286->index_cache[i].def);
1257 for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1258 regmap_write(rt286->regmap, rt286_reg[i].reg,
1259 rt286_reg[i].def);
1260
07cf7cba
BL		 1261 if (pdata)
1262 rt286->pdata = *pdata;
1263
2cc3f234
BL		 1264 if (dmi_check_system(force_combo_jack_table) ||
1265 dmi_check_system(dmi_dell_dino))
6c67cde2
BL		 1266 rt286->pdata.cbj_en = true;
1267
61a414c4
BL		 1268 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1269
1270 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1271 regmap_write(rt286->regmap,
1272 RT286_SET_POWER(rt286_support_power_controls[i]),
1273 AC_PWRST_D1);
1274
1275 if (!rt286->pdata.cbj_en) {
1276 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1277 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
61a414c4
BL		 1278 regmap_update_bits(rt286->regmap,
1279 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1280 } else {
1281 regmap_update_bits(rt286->regmap,
1282 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1283 }
1284
1285 mdelay(10);
1286
1287 if (!rt286->pdata.gpio2_en)
1288 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1289 else
1290 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1291
1292 mdelay(10);
1293
6879db76 1294 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
f8c101bc 1295 /* Power down LDO, VREF */
6879db76
BL		 1296 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1297 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
61a414c4 1298
f8c101bc 1299 /* Set depop parameter */
bc6c4e45
BL		 1300 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1301 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1302 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1303
2cc3f234
BL		 1304 if (dmi_check_system(dmi_dell_dino)) {
1305 regmap_update_bits(rt286->regmap,
1306 RT286_SET_GPIO_MASK, 0x40, 0x40);
1307 regmap_update_bits(rt286->regmap,
1308 RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1309 regmap_update_bits(rt286->regmap,
1310 RT286_SET_GPIO_DATA, 0x40, 0x40);
1311 regmap_update_bits(rt286->regmap,
1312 RT286_GPIO_CTRL, 0xc, 0x8);
1313 }
1314
61a414c4 1315 if (rt286->i2c->irq) {
61a414c4
BL		 1316 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1317 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1318 if (ret != 0) {
1319 dev_err(&i2c->dev,
1320 "Failed to reguest IRQ: %d\n", ret);
1321 return ret;
1322 }
1323 }
1324
07cf7cba
BL		 1325 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1326 rt286_dai, ARRAY_SIZE(rt286_dai));
1327
1328 return ret;
1329}
1330
1331static int rt286_i2c_remove(struct i2c_client *i2c)
1332{
1333 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1334
1335 if (i2c->irq)
1336 free_irq(i2c->irq, rt286);
1337 snd_soc_unregister_codec(&i2c->dev);
1338
1339 return 0;
1340}
1341
1342
23c4fd5c 1343static struct i2c_driver rt286_i2c_driver = {
07cf7cba
BL		 1344 .driver = {
1345 .name = "rt286",
1346 .owner = THIS_MODULE,
1347 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1348 },
1349 .probe = rt286_i2c_probe,
1350 .remove = rt286_i2c_remove,
1351 .id_table = rt286_i2c_id,
1352};
1353
1354module_i2c_driver(rt286_i2c_driver);
1355
1356MODULE_DESCRIPTION("ASoC RT286 driver");
1357MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1358MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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