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6adcafae BL |
1 | /* |
2 | * rt298.c -- RT298 ALSA SoC audio codec driver | |
3 | * | |
4 | * Copyright 2015 Realtek Semiconductor Corp. | |
5 | * Author: Bard Liao <bardliao@realtek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/spi/spi.h> | |
b9c17f13 | 20 | #include <linux/dmi.h> |
6adcafae BL |
21 | #include <linux/acpi.h> |
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/soc-dapm.h> | |
27 | #include <sound/initval.h> | |
28 | #include <sound/tlv.h> | |
29 | #include <sound/jack.h> | |
30 | #include <linux/workqueue.h> | |
31 | #include <sound/rt298.h> | |
6adcafae BL |
32 | |
33 | #include "rl6347a.h" | |
34 | #include "rt298.h" | |
35 | ||
36 | #define RT298_VENDOR_ID 0x10ec0298 | |
37 | ||
38 | struct rt298_priv { | |
39 | struct reg_default *index_cache; | |
40 | int index_cache_size; | |
41 | struct regmap *regmap; | |
42 | struct snd_soc_codec *codec; | |
43 | struct rt298_platform_data pdata; | |
44 | struct i2c_client *i2c; | |
45 | struct snd_soc_jack *jack; | |
46 | struct delayed_work jack_detect_work; | |
47 | int sys_clk; | |
48 | int clk_id; | |
49 | int is_hp_in; | |
50 | }; | |
51 | ||
3943b9ef | 52 | static const struct reg_default rt298_index_def[] = { |
7ba6e4ef BL |
53 | { 0x01, 0xa5a8 }, |
54 | { 0x02, 0x8e95 }, | |
6adcafae | 55 | { 0x03, 0x0002 }, |
7ba6e4ef BL |
56 | { 0x04, 0xaf67 }, |
57 | { 0x08, 0x200f }, | |
58 | { 0x09, 0xd010 }, | |
59 | { 0x0a, 0x0100 }, | |
6adcafae BL |
60 | { 0x0b, 0x0000 }, |
61 | { 0x0d, 0x2800 }, | |
7ba6e4ef BL |
62 | { 0x0f, 0x0022 }, |
63 | { 0x19, 0x0217 }, | |
6adcafae BL |
64 | { 0x20, 0x0020 }, |
65 | { 0x33, 0x0208 }, | |
66 | { 0x46, 0x0300 }, | |
7ba6e4ef BL |
67 | { 0x49, 0x4004 }, |
68 | { 0x4f, 0x50c9 }, | |
69 | { 0x50, 0x3000 }, | |
70 | { 0x63, 0x1b02 }, | |
6adcafae BL |
71 | { 0x67, 0x1111 }, |
72 | { 0x68, 0x1016 }, | |
73 | { 0x69, 0x273f }, | |
74 | }; | |
75 | #define INDEX_CACHE_SIZE ARRAY_SIZE(rt298_index_def) | |
76 | ||
77 | static const struct reg_default rt298_reg[] = { | |
78 | { 0x00170500, 0x00000400 }, | |
79 | { 0x00220000, 0x00000031 }, | |
80 | { 0x00239000, 0x0000007f }, | |
81 | { 0x0023a000, 0x0000007f }, | |
82 | { 0x00270500, 0x00000400 }, | |
83 | { 0x00370500, 0x00000400 }, | |
84 | { 0x00870500, 0x00000400 }, | |
85 | { 0x00920000, 0x00000031 }, | |
86 | { 0x00935000, 0x000000c3 }, | |
87 | { 0x00936000, 0x000000c3 }, | |
88 | { 0x00970500, 0x00000400 }, | |
89 | { 0x00b37000, 0x00000097 }, | |
90 | { 0x00b37200, 0x00000097 }, | |
91 | { 0x00b37300, 0x00000097 }, | |
92 | { 0x00c37000, 0x00000000 }, | |
93 | { 0x00c37100, 0x00000080 }, | |
94 | { 0x01270500, 0x00000400 }, | |
95 | { 0x01370500, 0x00000400 }, | |
96 | { 0x01371f00, 0x411111f0 }, | |
97 | { 0x01439000, 0x00000080 }, | |
98 | { 0x0143a000, 0x00000080 }, | |
99 | { 0x01470700, 0x00000000 }, | |
100 | { 0x01470500, 0x00000400 }, | |
101 | { 0x01470c00, 0x00000000 }, | |
102 | { 0x01470100, 0x00000000 }, | |
103 | { 0x01837000, 0x00000000 }, | |
104 | { 0x01870500, 0x00000400 }, | |
105 | { 0x02050000, 0x00000000 }, | |
106 | { 0x02139000, 0x00000080 }, | |
107 | { 0x0213a000, 0x00000080 }, | |
108 | { 0x02170100, 0x00000000 }, | |
109 | { 0x02170500, 0x00000400 }, | |
110 | { 0x02170700, 0x00000000 }, | |
111 | { 0x02270100, 0x00000000 }, | |
112 | { 0x02370100, 0x00000000 }, | |
113 | { 0x01870700, 0x00000020 }, | |
114 | { 0x00830000, 0x000000c3 }, | |
115 | { 0x00930000, 0x000000c3 }, | |
116 | { 0x01270700, 0x00000000 }, | |
117 | }; | |
118 | ||
119 | static bool rt298_volatile_register(struct device *dev, unsigned int reg) | |
120 | { | |
121 | switch (reg) { | |
122 | case 0 ... 0xff: | |
123 | case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
124 | case RT298_GET_HP_SENSE: | |
125 | case RT298_GET_MIC1_SENSE: | |
126 | case RT298_PROC_COEF: | |
127 | case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0): | |
128 | case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0): | |
129 | case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0): | |
130 | return true; | |
131 | default: | |
a5fe58fd | 132 | return false; |
6adcafae BL |
133 | } |
134 | ||
135 | ||
136 | } | |
137 | ||
138 | static bool rt298_readable_register(struct device *dev, unsigned int reg) | |
139 | { | |
140 | switch (reg) { | |
141 | case 0 ... 0xff: | |
142 | case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
143 | case RT298_GET_HP_SENSE: | |
144 | case RT298_GET_MIC1_SENSE: | |
145 | case RT298_SET_AUDIO_POWER: | |
146 | case RT298_SET_HPO_POWER: | |
147 | case RT298_SET_SPK_POWER: | |
148 | case RT298_SET_DMIC1_POWER: | |
149 | case RT298_SPK_MUX: | |
150 | case RT298_HPO_MUX: | |
151 | case RT298_ADC0_MUX: | |
152 | case RT298_ADC1_MUX: | |
153 | case RT298_SET_MIC1: | |
154 | case RT298_SET_PIN_HPO: | |
155 | case RT298_SET_PIN_SPK: | |
156 | case RT298_SET_PIN_DMIC1: | |
157 | case RT298_SPK_EAPD: | |
158 | case RT298_SET_AMP_GAIN_HPO: | |
159 | case RT298_SET_DMIC2_DEFAULT: | |
160 | case RT298_DACL_GAIN: | |
161 | case RT298_DACR_GAIN: | |
162 | case RT298_ADCL_GAIN: | |
163 | case RT298_ADCR_GAIN: | |
164 | case RT298_MIC_GAIN: | |
165 | case RT298_SPOL_GAIN: | |
166 | case RT298_SPOR_GAIN: | |
167 | case RT298_HPOL_GAIN: | |
168 | case RT298_HPOR_GAIN: | |
169 | case RT298_F_DAC_SWITCH: | |
170 | case RT298_F_RECMIX_SWITCH: | |
171 | case RT298_REC_MIC_SWITCH: | |
172 | case RT298_REC_I2S_SWITCH: | |
173 | case RT298_REC_LINE_SWITCH: | |
174 | case RT298_REC_BEEP_SWITCH: | |
175 | case RT298_DAC_FORMAT: | |
176 | case RT298_ADC_FORMAT: | |
177 | case RT298_COEF_INDEX: | |
178 | case RT298_PROC_COEF: | |
179 | case RT298_SET_AMP_GAIN_ADC_IN1: | |
180 | case RT298_SET_AMP_GAIN_ADC_IN2: | |
181 | case RT298_SET_POWER(RT298_DAC_OUT1): | |
182 | case RT298_SET_POWER(RT298_DAC_OUT2): | |
183 | case RT298_SET_POWER(RT298_ADC_IN1): | |
184 | case RT298_SET_POWER(RT298_ADC_IN2): | |
185 | case RT298_SET_POWER(RT298_DMIC2): | |
186 | case RT298_SET_POWER(RT298_MIC1): | |
187 | case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0): | |
188 | case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0): | |
189 | case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0): | |
190 | return true; | |
191 | default: | |
192 | return false; | |
193 | } | |
194 | } | |
195 | ||
196 | #ifdef CONFIG_PM | |
197 | static void rt298_index_sync(struct snd_soc_codec *codec) | |
198 | { | |
199 | struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); | |
200 | int i; | |
201 | ||
202 | for (i = 0; i < INDEX_CACHE_SIZE; i++) { | |
203 | snd_soc_write(codec, rt298->index_cache[i].reg, | |
204 | rt298->index_cache[i].def); | |
205 | } | |
206 | } | |
207 | #endif | |
208 | ||
209 | static int rt298_support_power_controls[] = { | |
210 | RT298_DAC_OUT1, | |
211 | RT298_DAC_OUT2, | |
212 | RT298_ADC_IN1, | |
213 | RT298_ADC_IN2, | |
214 | RT298_MIC1, | |
215 | RT298_DMIC1, | |
216 | RT298_DMIC2, | |
217 | RT298_SPK_OUT, | |
218 | RT298_HP_OUT, | |
219 | }; | |
220 | #define RT298_POWER_REG_LEN ARRAY_SIZE(rt298_support_power_controls) | |
221 | ||
222 | static int rt298_jack_detect(struct rt298_priv *rt298, bool *hp, bool *mic) | |
223 | { | |
224 | struct snd_soc_dapm_context *dapm; | |
225 | unsigned int val, buf; | |
226 | ||
227 | *hp = false; | |
228 | *mic = false; | |
229 | ||
230 | if (!rt298->codec) | |
231 | return -EINVAL; | |
232 | ||
233 | dapm = snd_soc_codec_get_dapm(rt298->codec); | |
234 | ||
235 | if (rt298->pdata.cbj_en) { | |
236 | regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf); | |
237 | *hp = buf & 0x80000000; | |
238 | if (*hp == rt298->is_hp_in) | |
239 | return -1; | |
240 | rt298->is_hp_in = *hp; | |
241 | if (*hp) { | |
242 | /* power on HV,VERF */ | |
243 | regmap_update_bits(rt298->regmap, | |
244 | RT298_DC_GAIN, 0x200, 0x200); | |
245 | ||
246 | snd_soc_dapm_force_enable_pin(dapm, "HV"); | |
247 | snd_soc_dapm_force_enable_pin(dapm, "VREF"); | |
248 | /* power LDO1 */ | |
249 | snd_soc_dapm_force_enable_pin(dapm, "LDO1"); | |
250 | snd_soc_dapm_sync(dapm); | |
251 | ||
252 | regmap_write(rt298->regmap, RT298_SET_MIC1, 0x24); | |
253 | msleep(50); | |
254 | ||
255 | regmap_update_bits(rt298->regmap, | |
256 | RT298_CBJ_CTRL1, 0xfcc0, 0xd400); | |
257 | msleep(300); | |
258 | regmap_read(rt298->regmap, RT298_CBJ_CTRL2, &val); | |
259 | ||
260 | if (0x0070 == (val & 0x0070)) { | |
261 | *mic = true; | |
262 | } else { | |
263 | regmap_update_bits(rt298->regmap, | |
264 | RT298_CBJ_CTRL1, 0xfcc0, 0xe400); | |
265 | msleep(300); | |
266 | regmap_read(rt298->regmap, | |
267 | RT298_CBJ_CTRL2, &val); | |
268 | if (0x0070 == (val & 0x0070)) | |
269 | *mic = true; | |
270 | else | |
271 | *mic = false; | |
272 | } | |
273 | regmap_update_bits(rt298->regmap, | |
274 | RT298_DC_GAIN, 0x200, 0x0); | |
275 | ||
276 | } else { | |
277 | *mic = false; | |
278 | regmap_write(rt298->regmap, RT298_SET_MIC1, 0x20); | |
9ff49ce4 BL |
279 | regmap_update_bits(rt298->regmap, |
280 | RT298_CBJ_CTRL1, 0x0400, 0x0000); | |
6adcafae BL |
281 | } |
282 | } else { | |
283 | regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf); | |
284 | *hp = buf & 0x80000000; | |
285 | regmap_read(rt298->regmap, RT298_GET_MIC1_SENSE, &buf); | |
286 | *mic = buf & 0x80000000; | |
287 | } | |
288 | ||
289 | snd_soc_dapm_disable_pin(dapm, "HV"); | |
290 | snd_soc_dapm_disable_pin(dapm, "VREF"); | |
291 | if (!*hp) | |
292 | snd_soc_dapm_disable_pin(dapm, "LDO1"); | |
293 | snd_soc_dapm_sync(dapm); | |
294 | ||
295 | pr_debug("*hp = %d *mic = %d\n", *hp, *mic); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | static void rt298_jack_detect_work(struct work_struct *work) | |
301 | { | |
302 | struct rt298_priv *rt298 = | |
303 | container_of(work, struct rt298_priv, jack_detect_work.work); | |
304 | int status = 0; | |
305 | bool hp = false; | |
306 | bool mic = false; | |
307 | ||
308 | if (rt298_jack_detect(rt298, &hp, &mic) < 0) | |
309 | return; | |
310 | ||
311 | if (hp == true) | |
312 | status |= SND_JACK_HEADPHONE; | |
313 | ||
314 | if (mic == true) | |
315 | status |= SND_JACK_MICROPHONE; | |
316 | ||
317 | snd_soc_jack_report(rt298->jack, status, | |
318 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
319 | } | |
320 | ||
321 | int rt298_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) | |
322 | { | |
323 | struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); | |
324 | ||
325 | rt298->jack = jack; | |
326 | ||
327 | /* Send an initial empty report */ | |
328 | snd_soc_jack_report(rt298->jack, 0, | |
329 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
330 | ||
331 | return 0; | |
332 | } | |
333 | EXPORT_SYMBOL_GPL(rt298_mic_detect); | |
334 | ||
335 | static int is_mclk_mode(struct snd_soc_dapm_widget *source, | |
336 | struct snd_soc_dapm_widget *sink) | |
337 | { | |
338 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); | |
339 | struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); | |
340 | ||
341 | if (rt298->clk_id == RT298_SCLK_S_MCLK) | |
342 | return 1; | |
343 | else | |
344 | return 0; | |
345 | } | |
346 | ||
347 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); | |
348 | static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); | |
349 | ||
350 | static const struct snd_kcontrol_new rt298_snd_controls[] = { | |
351 | SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT298_DACL_GAIN, | |
352 | RT298_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
353 | SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT298_ADCL_GAIN, | |
354 | RT298_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
355 | SOC_SINGLE_TLV("AMIC Volume", RT298_MIC_GAIN, | |
356 | 0, 0x3, 0, mic_vol_tlv), | |
357 | SOC_DOUBLE_R("Speaker Playback Switch", RT298_SPOL_GAIN, | |
358 | RT298_SPOR_GAIN, RT298_MUTE_SFT, 1, 1), | |
359 | }; | |
360 | ||
361 | /* Digital Mixer */ | |
362 | static const struct snd_kcontrol_new rt298_front_mix[] = { | |
363 | SOC_DAPM_SINGLE("DAC Switch", RT298_F_DAC_SWITCH, | |
364 | RT298_MUTE_SFT, 1, 1), | |
365 | SOC_DAPM_SINGLE("RECMIX Switch", RT298_F_RECMIX_SWITCH, | |
366 | RT298_MUTE_SFT, 1, 1), | |
367 | }; | |
368 | ||
369 | /* Analog Input Mixer */ | |
370 | static const struct snd_kcontrol_new rt298_rec_mix[] = { | |
371 | SOC_DAPM_SINGLE("Mic1 Switch", RT298_REC_MIC_SWITCH, | |
372 | RT298_MUTE_SFT, 1, 1), | |
373 | SOC_DAPM_SINGLE("I2S Switch", RT298_REC_I2S_SWITCH, | |
374 | RT298_MUTE_SFT, 1, 1), | |
375 | SOC_DAPM_SINGLE("Line1 Switch", RT298_REC_LINE_SWITCH, | |
376 | RT298_MUTE_SFT, 1, 1), | |
377 | SOC_DAPM_SINGLE("Beep Switch", RT298_REC_BEEP_SWITCH, | |
378 | RT298_MUTE_SFT, 1, 1), | |
379 | }; | |
380 | ||
381 | static const struct snd_kcontrol_new spo_enable_control = | |
382 | SOC_DAPM_SINGLE("Switch", RT298_SET_PIN_SPK, | |
383 | RT298_SET_PIN_SFT, 1, 0); | |
384 | ||
385 | static const struct snd_kcontrol_new hpol_enable_control = | |
386 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOL_GAIN, | |
387 | RT298_MUTE_SFT, 1, 1); | |
388 | ||
389 | static const struct snd_kcontrol_new hpor_enable_control = | |
390 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOR_GAIN, | |
391 | RT298_MUTE_SFT, 1, 1); | |
392 | ||
393 | /* ADC0 source */ | |
394 | static const char * const rt298_adc_src[] = { | |
395 | "Mic", "RECMIX", "Dmic" | |
396 | }; | |
397 | ||
398 | static const int rt298_adc_values[] = { | |
399 | 0, 4, 5, | |
400 | }; | |
401 | ||
402 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
403 | rt298_adc0_enum, RT298_ADC0_MUX, RT298_ADC_SEL_SFT, | |
404 | RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values); | |
405 | ||
406 | static const struct snd_kcontrol_new rt298_adc0_mux = | |
407 | SOC_DAPM_ENUM("ADC 0 source", rt298_adc0_enum); | |
408 | ||
409 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
410 | rt298_adc1_enum, RT298_ADC1_MUX, RT298_ADC_SEL_SFT, | |
411 | RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values); | |
412 | ||
413 | static const struct snd_kcontrol_new rt298_adc1_mux = | |
414 | SOC_DAPM_ENUM("ADC 1 source", rt298_adc1_enum); | |
415 | ||
416 | static const char * const rt298_dac_src[] = { | |
417 | "Front", "Surround" | |
418 | }; | |
419 | /* HP-OUT source */ | |
420 | static SOC_ENUM_SINGLE_DECL(rt298_hpo_enum, RT298_HPO_MUX, | |
421 | 0, rt298_dac_src); | |
422 | ||
423 | static const struct snd_kcontrol_new rt298_hpo_mux = | |
424 | SOC_DAPM_ENUM("HPO source", rt298_hpo_enum); | |
425 | ||
426 | /* SPK-OUT source */ | |
427 | static SOC_ENUM_SINGLE_DECL(rt298_spo_enum, RT298_SPK_MUX, | |
428 | 0, rt298_dac_src); | |
429 | ||
430 | static const struct snd_kcontrol_new rt298_spo_mux = | |
431 | SOC_DAPM_ENUM("SPO source", rt298_spo_enum); | |
432 | ||
433 | static int rt298_spk_event(struct snd_soc_dapm_widget *w, | |
434 | struct snd_kcontrol *kcontrol, int event) | |
435 | { | |
436 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | |
437 | ||
438 | switch (event) { | |
439 | case SND_SOC_DAPM_POST_PMU: | |
440 | snd_soc_write(codec, | |
441 | RT298_SPK_EAPD, RT298_SET_EAPD_HIGH); | |
442 | break; | |
443 | case SND_SOC_DAPM_PRE_PMD: | |
444 | snd_soc_write(codec, | |
445 | RT298_SPK_EAPD, RT298_SET_EAPD_LOW); | |
446 | break; | |
447 | ||
448 | default: | |
449 | return 0; | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | static int rt298_set_dmic1_event(struct snd_soc_dapm_widget *w, | |
456 | struct snd_kcontrol *kcontrol, int event) | |
457 | { | |
458 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | |
459 | ||
460 | switch (event) { | |
461 | case SND_SOC_DAPM_POST_PMU: | |
462 | snd_soc_write(codec, RT298_SET_PIN_DMIC1, 0x20); | |
463 | break; | |
464 | case SND_SOC_DAPM_PRE_PMD: | |
465 | snd_soc_write(codec, RT298_SET_PIN_DMIC1, 0); | |
466 | break; | |
467 | default: | |
468 | return 0; | |
469 | } | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | static int rt298_adc_event(struct snd_soc_dapm_widget *w, | |
475 | struct snd_kcontrol *kcontrol, int event) | |
476 | { | |
477 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | |
478 | unsigned int nid; | |
479 | ||
480 | nid = (w->reg >> 20) & 0xff; | |
481 | ||
482 | switch (event) { | |
483 | case SND_SOC_DAPM_POST_PMU: | |
484 | snd_soc_update_bits(codec, | |
485 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), | |
486 | 0x7080, 0x7000); | |
3c9e014c BL |
487 | /* If MCLK doesn't exist, reset AD filter */ |
488 | if (!(snd_soc_read(codec, RT298_VAD_CTRL) & 0x200)) { | |
489 | pr_info("NO MCLK\n"); | |
490 | switch (nid) { | |
491 | case RT298_ADC_IN1: | |
492 | snd_soc_update_bits(codec, | |
493 | RT298_D_FILTER_CTRL, 0x2, 0x2); | |
494 | mdelay(10); | |
495 | snd_soc_update_bits(codec, | |
496 | RT298_D_FILTER_CTRL, 0x2, 0x0); | |
497 | break; | |
498 | case RT298_ADC_IN2: | |
499 | snd_soc_update_bits(codec, | |
500 | RT298_D_FILTER_CTRL, 0x4, 0x4); | |
501 | mdelay(10); | |
502 | snd_soc_update_bits(codec, | |
503 | RT298_D_FILTER_CTRL, 0x4, 0x0); | |
504 | break; | |
505 | } | |
506 | } | |
6adcafae BL |
507 | break; |
508 | case SND_SOC_DAPM_PRE_PMD: | |
509 | snd_soc_update_bits(codec, | |
510 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), | |
511 | 0x7080, 0x7080); | |
512 | break; | |
513 | default: | |
514 | return 0; | |
515 | } | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static int rt298_mic1_event(struct snd_soc_dapm_widget *w, | |
521 | struct snd_kcontrol *kcontrol, int event) | |
522 | { | |
523 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | |
524 | ||
525 | switch (event) { | |
526 | case SND_SOC_DAPM_PRE_PMU: | |
527 | snd_soc_update_bits(codec, | |
528 | RT298_A_BIAS_CTRL3, 0xc000, 0x8000); | |
529 | snd_soc_update_bits(codec, | |
530 | RT298_A_BIAS_CTRL2, 0xc000, 0x8000); | |
531 | break; | |
532 | case SND_SOC_DAPM_POST_PMD: | |
533 | snd_soc_update_bits(codec, | |
534 | RT298_A_BIAS_CTRL3, 0xc000, 0x0000); | |
535 | snd_soc_update_bits(codec, | |
536 | RT298_A_BIAS_CTRL2, 0xc000, 0x0000); | |
537 | break; | |
538 | default: | |
539 | return 0; | |
540 | } | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
6adcafae BL |
545 | static const struct snd_soc_dapm_widget rt298_dapm_widgets[] = { |
546 | ||
547 | SND_SOC_DAPM_SUPPLY_S("HV", 1, RT298_POWER_CTRL1, | |
548 | 12, 1, NULL, 0), | |
549 | SND_SOC_DAPM_SUPPLY("VREF", RT298_POWER_CTRL1, | |
9ff49ce4 | 550 | 0, 1, NULL, 0), |
6adcafae BL |
551 | SND_SOC_DAPM_SUPPLY_S("BG_MBIAS", 1, RT298_POWER_CTRL2, |
552 | 1, 0, NULL, 0), | |
553 | SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT298_POWER_CTRL2, | |
554 | 2, 0, NULL, 0), | |
555 | SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT298_POWER_CTRL2, | |
556 | 3, 0, NULL, 0), | |
557 | SND_SOC_DAPM_SUPPLY_S("VREF1", 1, RT298_POWER_CTRL2, | |
558 | 4, 1, NULL, 0), | |
559 | SND_SOC_DAPM_SUPPLY_S("LV", 2, RT298_POWER_CTRL1, | |
560 | 13, 1, NULL, 0), | |
561 | ||
562 | ||
563 | SND_SOC_DAPM_SUPPLY("MCLK MODE", RT298_PLL_CTRL1, | |
564 | 5, 0, NULL, 0), | |
565 | SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM, | |
566 | 0, 0, rt298_mic1_event, SND_SOC_DAPM_PRE_PMU | | |
567 | SND_SOC_DAPM_POST_PMD), | |
568 | ||
569 | /* Input Lines */ | |
570 | SND_SOC_DAPM_INPUT("DMIC1 Pin"), | |
571 | SND_SOC_DAPM_INPUT("DMIC2 Pin"), | |
572 | SND_SOC_DAPM_INPUT("MIC1"), | |
573 | SND_SOC_DAPM_INPUT("LINE1"), | |
574 | SND_SOC_DAPM_INPUT("Beep"), | |
575 | ||
576 | /* DMIC */ | |
577 | SND_SOC_DAPM_PGA_E("DMIC1", RT298_SET_POWER(RT298_DMIC1), 0, 1, | |
578 | NULL, 0, rt298_set_dmic1_event, | |
579 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
580 | SND_SOC_DAPM_PGA("DMIC2", RT298_SET_POWER(RT298_DMIC2), 0, 1, | |
581 | NULL, 0), | |
582 | SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM, | |
583 | 0, 0, NULL, 0), | |
584 | ||
585 | /* REC Mixer */ | |
586 | SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0, | |
587 | rt298_rec_mix, ARRAY_SIZE(rt298_rec_mix)), | |
588 | ||
589 | /* ADCs */ | |
590 | SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0), | |
591 | SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0), | |
592 | ||
593 | /* ADC Mux */ | |
594 | SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT298_SET_POWER(RT298_ADC_IN1), 0, 1, | |
595 | &rt298_adc0_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD | | |
596 | SND_SOC_DAPM_POST_PMU), | |
597 | SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT298_SET_POWER(RT298_ADC_IN2), 0, 1, | |
598 | &rt298_adc1_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD | | |
599 | SND_SOC_DAPM_POST_PMU), | |
600 | ||
601 | /* Audio Interface */ | |
602 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
603 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
604 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
605 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
606 | ||
607 | /* Output Side */ | |
608 | /* DACs */ | |
609 | SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0), | |
610 | SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0), | |
611 | ||
612 | /* Output Mux */ | |
613 | SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt298_spo_mux), | |
614 | SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt298_hpo_mux), | |
615 | ||
616 | SND_SOC_DAPM_SUPPLY("HP Power", RT298_SET_PIN_HPO, | |
617 | RT298_SET_PIN_SFT, 0, NULL, 0), | |
618 | ||
619 | /* Output Mixer */ | |
620 | SND_SOC_DAPM_MIXER("Front", RT298_SET_POWER(RT298_DAC_OUT1), 0, 1, | |
621 | rt298_front_mix, ARRAY_SIZE(rt298_front_mix)), | |
622 | SND_SOC_DAPM_PGA("Surround", RT298_SET_POWER(RT298_DAC_OUT2), 0, 1, | |
623 | NULL, 0), | |
624 | ||
625 | /* Output Pga */ | |
626 | SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0, | |
627 | &spo_enable_control, rt298_spk_event, | |
628 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
629 | SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, | |
630 | &hpol_enable_control), | |
631 | SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, | |
632 | &hpor_enable_control), | |
633 | ||
634 | /* Output Lines */ | |
635 | SND_SOC_DAPM_OUTPUT("SPOL"), | |
636 | SND_SOC_DAPM_OUTPUT("SPOR"), | |
637 | SND_SOC_DAPM_OUTPUT("HPO Pin"), | |
638 | SND_SOC_DAPM_OUTPUT("SPDIF"), | |
639 | }; | |
640 | ||
641 | static const struct snd_soc_dapm_route rt298_dapm_routes[] = { | |
642 | ||
643 | {"ADC 0", NULL, "MCLK MODE", is_mclk_mode}, | |
644 | {"ADC 1", NULL, "MCLK MODE", is_mclk_mode}, | |
645 | {"Front", NULL, "MCLK MODE", is_mclk_mode}, | |
646 | {"Surround", NULL, "MCLK MODE", is_mclk_mode}, | |
647 | ||
648 | {"HP Power", NULL, "LDO1"}, | |
649 | {"HP Power", NULL, "LDO2"}, | |
650 | {"HP Power", NULL, "LV"}, | |
651 | {"HP Power", NULL, "VREF1"}, | |
652 | {"HP Power", NULL, "BG_MBIAS"}, | |
653 | ||
654 | {"MIC1", NULL, "LDO1"}, | |
655 | {"MIC1", NULL, "LDO2"}, | |
656 | {"MIC1", NULL, "HV"}, | |
657 | {"MIC1", NULL, "LV"}, | |
658 | {"MIC1", NULL, "VREF"}, | |
659 | {"MIC1", NULL, "VREF1"}, | |
660 | {"MIC1", NULL, "BG_MBIAS"}, | |
661 | {"MIC1", NULL, "MIC1 Input Buffer"}, | |
662 | ||
663 | {"SPO", NULL, "LDO1"}, | |
664 | {"SPO", NULL, "LDO2"}, | |
665 | {"SPO", NULL, "HV"}, | |
666 | {"SPO", NULL, "LV"}, | |
667 | {"SPO", NULL, "VREF"}, | |
668 | {"SPO", NULL, "VREF1"}, | |
669 | {"SPO", NULL, "BG_MBIAS"}, | |
670 | ||
671 | {"DMIC1", NULL, "DMIC1 Pin"}, | |
672 | {"DMIC2", NULL, "DMIC2 Pin"}, | |
673 | {"DMIC1", NULL, "DMIC Receiver"}, | |
674 | {"DMIC2", NULL, "DMIC Receiver"}, | |
675 | ||
676 | {"RECMIX", "Beep Switch", "Beep"}, | |
677 | {"RECMIX", "Line1 Switch", "LINE1"}, | |
678 | {"RECMIX", "Mic1 Switch", "MIC1"}, | |
679 | ||
680 | {"ADC 0 Mux", "Dmic", "DMIC1"}, | |
681 | {"ADC 0 Mux", "RECMIX", "RECMIX"}, | |
682 | {"ADC 0 Mux", "Mic", "MIC1"}, | |
683 | {"ADC 1 Mux", "Dmic", "DMIC2"}, | |
684 | {"ADC 1 Mux", "RECMIX", "RECMIX"}, | |
685 | {"ADC 1 Mux", "Mic", "MIC1"}, | |
686 | ||
687 | {"ADC 0", NULL, "ADC 0 Mux"}, | |
688 | {"ADC 1", NULL, "ADC 1 Mux"}, | |
689 | ||
690 | {"AIF1TX", NULL, "ADC 0"}, | |
691 | {"AIF2TX", NULL, "ADC 1"}, | |
692 | ||
693 | {"DAC 0", NULL, "AIF1RX"}, | |
694 | {"DAC 1", NULL, "AIF2RX"}, | |
695 | ||
696 | {"Front", "DAC Switch", "DAC 0"}, | |
697 | {"Front", "RECMIX Switch", "RECMIX"}, | |
698 | ||
699 | {"Surround", NULL, "DAC 1"}, | |
700 | ||
701 | {"SPK Mux", "Front", "Front"}, | |
702 | {"SPK Mux", "Surround", "Surround"}, | |
703 | ||
704 | {"HPO Mux", "Front", "Front"}, | |
705 | {"HPO Mux", "Surround", "Surround"}, | |
706 | ||
707 | {"SPO", "Switch", "SPK Mux"}, | |
708 | {"HPO L", "Switch", "HPO Mux"}, | |
709 | {"HPO R", "Switch", "HPO Mux"}, | |
710 | {"HPO L", NULL, "HP Power"}, | |
711 | {"HPO R", NULL, "HP Power"}, | |
712 | ||
713 | {"SPOL", NULL, "SPO"}, | |
714 | {"SPOR", NULL, "SPO"}, | |
715 | {"HPO Pin", NULL, "HPO L"}, | |
716 | {"HPO Pin", NULL, "HPO R"}, | |
717 | }; | |
718 | ||
719 | static int rt298_hw_params(struct snd_pcm_substream *substream, | |
720 | struct snd_pcm_hw_params *params, | |
721 | struct snd_soc_dai *dai) | |
722 | { | |
723 | struct snd_soc_codec *codec = dai->codec; | |
724 | struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); | |
725 | unsigned int val = 0; | |
726 | int d_len_code; | |
727 | ||
728 | switch (params_rate(params)) { | |
729 | /* bit 14 0:48K 1:44.1K */ | |
730 | case 44100: | |
731 | case 48000: | |
732 | break; | |
733 | default: | |
734 | dev_err(codec->dev, "Unsupported sample rate %d\n", | |
735 | params_rate(params)); | |
736 | return -EINVAL; | |
737 | } | |
738 | switch (rt298->sys_clk) { | |
739 | case 12288000: | |
740 | case 24576000: | |
741 | if (params_rate(params) != 48000) { | |
742 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
743 | params_rate(params), rt298->sys_clk); | |
744 | return -EINVAL; | |
745 | } | |
746 | break; | |
747 | case 11289600: | |
748 | case 22579200: | |
749 | if (params_rate(params) != 44100) { | |
750 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
751 | params_rate(params), rt298->sys_clk); | |
752 | return -EINVAL; | |
753 | } | |
754 | break; | |
755 | } | |
756 | ||
757 | if (params_channels(params) <= 16) { | |
758 | /* bit 3:0 Number of Channel */ | |
759 | val |= (params_channels(params) - 1); | |
760 | } else { | |
761 | dev_err(codec->dev, "Unsupported channels %d\n", | |
762 | params_channels(params)); | |
763 | return -EINVAL; | |
764 | } | |
765 | ||
766 | d_len_code = 0; | |
767 | switch (params_width(params)) { | |
768 | /* bit 6:4 Bits per Sample */ | |
769 | case 16: | |
770 | d_len_code = 0; | |
771 | val |= (0x1 << 4); | |
772 | break; | |
773 | case 32: | |
774 | d_len_code = 2; | |
775 | val |= (0x4 << 4); | |
776 | break; | |
777 | case 20: | |
778 | d_len_code = 1; | |
779 | val |= (0x2 << 4); | |
780 | break; | |
781 | case 24: | |
782 | d_len_code = 2; | |
783 | val |= (0x3 << 4); | |
784 | break; | |
785 | case 8: | |
786 | d_len_code = 3; | |
787 | break; | |
788 | default: | |
789 | return -EINVAL; | |
790 | } | |
791 | ||
792 | snd_soc_update_bits(codec, | |
793 | RT298_I2S_CTRL1, 0x0018, d_len_code << 3); | |
794 | dev_dbg(codec->dev, "format val = 0x%x\n", val); | |
795 | ||
796 | snd_soc_update_bits(codec, RT298_DAC_FORMAT, 0x407f, val); | |
797 | snd_soc_update_bits(codec, RT298_ADC_FORMAT, 0x407f, val); | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
802 | static int rt298_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
803 | { | |
804 | struct snd_soc_codec *codec = dai->codec; | |
805 | ||
806 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
807 | case SND_SOC_DAIFMT_CBM_CFM: | |
808 | snd_soc_update_bits(codec, | |
809 | RT298_I2S_CTRL1, 0x800, 0x800); | |
810 | break; | |
811 | case SND_SOC_DAIFMT_CBS_CFS: | |
812 | snd_soc_update_bits(codec, | |
813 | RT298_I2S_CTRL1, 0x800, 0x0); | |
814 | break; | |
815 | default: | |
816 | return -EINVAL; | |
817 | } | |
818 | ||
819 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
820 | case SND_SOC_DAIFMT_I2S: | |
821 | snd_soc_update_bits(codec, | |
822 | RT298_I2S_CTRL1, 0x300, 0x0); | |
823 | break; | |
824 | case SND_SOC_DAIFMT_LEFT_J: | |
825 | snd_soc_update_bits(codec, | |
826 | RT298_I2S_CTRL1, 0x300, 0x1 << 8); | |
827 | break; | |
828 | case SND_SOC_DAIFMT_DSP_A: | |
829 | snd_soc_update_bits(codec, | |
830 | RT298_I2S_CTRL1, 0x300, 0x2 << 8); | |
831 | break; | |
832 | case SND_SOC_DAIFMT_DSP_B: | |
833 | snd_soc_update_bits(codec, | |
834 | RT298_I2S_CTRL1, 0x300, 0x3 << 8); | |
835 | break; | |
836 | default: | |
837 | return -EINVAL; | |
838 | } | |
839 | /* bit 15 Stream Type 0:PCM 1:Non-PCM */ | |
840 | snd_soc_update_bits(codec, RT298_DAC_FORMAT, 0x8000, 0); | |
841 | snd_soc_update_bits(codec, RT298_ADC_FORMAT, 0x8000, 0); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | static int rt298_set_dai_sysclk(struct snd_soc_dai *dai, | |
847 | int clk_id, unsigned int freq, int dir) | |
848 | { | |
849 | struct snd_soc_codec *codec = dai->codec; | |
850 | struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); | |
851 | ||
852 | dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq); | |
853 | ||
854 | if (RT298_SCLK_S_MCLK == clk_id) { | |
855 | snd_soc_update_bits(codec, | |
856 | RT298_I2S_CTRL2, 0x0100, 0x0); | |
857 | snd_soc_update_bits(codec, | |
858 | RT298_PLL_CTRL1, 0x20, 0x20); | |
859 | } else { | |
860 | snd_soc_update_bits(codec, | |
861 | RT298_I2S_CTRL2, 0x0100, 0x0100); | |
6adcafae BL |
862 | snd_soc_update_bits(codec, |
863 | RT298_PLL_CTRL1, 0x20, 0x0); | |
864 | } | |
865 | ||
866 | switch (freq) { | |
867 | case 19200000: | |
868 | if (RT298_SCLK_S_MCLK == clk_id) { | |
869 | dev_err(codec->dev, "Should not use MCLK\n"); | |
870 | return -EINVAL; | |
871 | } | |
872 | snd_soc_update_bits(codec, | |
873 | RT298_I2S_CTRL2, 0x40, 0x40); | |
874 | break; | |
875 | case 24000000: | |
876 | if (RT298_SCLK_S_MCLK == clk_id) { | |
877 | dev_err(codec->dev, "Should not use MCLK\n"); | |
878 | return -EINVAL; | |
879 | } | |
880 | snd_soc_update_bits(codec, | |
881 | RT298_I2S_CTRL2, 0x40, 0x0); | |
882 | break; | |
883 | case 12288000: | |
884 | case 11289600: | |
885 | snd_soc_update_bits(codec, | |
886 | RT298_I2S_CTRL2, 0x8, 0x0); | |
887 | snd_soc_update_bits(codec, | |
888 | RT298_CLK_DIV, 0xfc1e, 0x0004); | |
889 | break; | |
890 | case 24576000: | |
891 | case 22579200: | |
892 | snd_soc_update_bits(codec, | |
893 | RT298_I2S_CTRL2, 0x8, 0x8); | |
894 | snd_soc_update_bits(codec, | |
895 | RT298_CLK_DIV, 0xfc1e, 0x5406); | |
896 | break; | |
897 | default: | |
898 | dev_err(codec->dev, "Unsupported system clock\n"); | |
899 | return -EINVAL; | |
900 | } | |
901 | ||
902 | rt298->sys_clk = freq; | |
903 | rt298->clk_id = clk_id; | |
904 | ||
905 | return 0; | |
906 | } | |
907 | ||
908 | static int rt298_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) | |
909 | { | |
910 | struct snd_soc_codec *codec = dai->codec; | |
911 | ||
912 | dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio); | |
913 | if (50 == ratio) | |
914 | snd_soc_update_bits(codec, | |
915 | RT298_I2S_CTRL1, 0x1000, 0x1000); | |
916 | else | |
917 | snd_soc_update_bits(codec, | |
918 | RT298_I2S_CTRL1, 0x1000, 0x0); | |
919 | ||
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
924 | static int rt298_set_bias_level(struct snd_soc_codec *codec, | |
925 | enum snd_soc_bias_level level) | |
926 | { | |
927 | switch (level) { | |
928 | case SND_SOC_BIAS_PREPARE: | |
929 | if (SND_SOC_BIAS_STANDBY == | |
930 | snd_soc_codec_get_bias_level(codec)) { | |
931 | snd_soc_write(codec, | |
932 | RT298_SET_AUDIO_POWER, AC_PWRST_D0); | |
933 | snd_soc_update_bits(codec, 0x0d, 0x200, 0x200); | |
934 | snd_soc_update_bits(codec, 0x52, 0x80, 0x0); | |
935 | mdelay(20); | |
936 | snd_soc_update_bits(codec, 0x0d, 0x200, 0x0); | |
937 | snd_soc_update_bits(codec, 0x52, 0x80, 0x80); | |
938 | } | |
939 | break; | |
940 | ||
6adcafae BL |
941 | case SND_SOC_BIAS_STANDBY: |
942 | snd_soc_write(codec, | |
943 | RT298_SET_AUDIO_POWER, AC_PWRST_D3); | |
6adcafae BL |
944 | break; |
945 | ||
946 | default: | |
947 | break; | |
948 | } | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | static irqreturn_t rt298_irq(int irq, void *data) | |
954 | { | |
955 | struct rt298_priv *rt298 = data; | |
956 | bool hp = false; | |
957 | bool mic = false; | |
958 | int ret, status = 0; | |
959 | ||
960 | ret = rt298_jack_detect(rt298, &hp, &mic); | |
961 | ||
962 | /* Clear IRQ */ | |
963 | regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x1, 0x1); | |
964 | ||
965 | if (ret == 0) { | |
966 | if (hp == true) | |
967 | status |= SND_JACK_HEADPHONE; | |
968 | ||
969 | if (mic == true) | |
970 | status |= SND_JACK_MICROPHONE; | |
971 | ||
972 | snd_soc_jack_report(rt298->jack, status, | |
973 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
974 | ||
975 | pm_wakeup_event(&rt298->i2c->dev, 300); | |
976 | } | |
977 | ||
978 | return IRQ_HANDLED; | |
979 | } | |
980 | ||
981 | static int rt298_probe(struct snd_soc_codec *codec) | |
982 | { | |
983 | struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); | |
984 | ||
985 | rt298->codec = codec; | |
986 | ||
987 | if (rt298->i2c->irq) { | |
988 | regmap_update_bits(rt298->regmap, | |
989 | RT298_IRQ_CTRL, 0x2, 0x2); | |
990 | ||
991 | INIT_DELAYED_WORK(&rt298->jack_detect_work, | |
992 | rt298_jack_detect_work); | |
993 | schedule_delayed_work(&rt298->jack_detect_work, | |
994 | msecs_to_jiffies(1250)); | |
995 | } | |
996 | ||
997 | return 0; | |
998 | } | |
999 | ||
1000 | static int rt298_remove(struct snd_soc_codec *codec) | |
1001 | { | |
1002 | struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); | |
1003 | ||
1004 | cancel_delayed_work_sync(&rt298->jack_detect_work); | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | #ifdef CONFIG_PM | |
1010 | static int rt298_suspend(struct snd_soc_codec *codec) | |
1011 | { | |
1012 | struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); | |
1013 | ||
1014 | rt298->is_hp_in = -1; | |
1015 | regcache_cache_only(rt298->regmap, true); | |
1016 | regcache_mark_dirty(rt298->regmap); | |
1017 | ||
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | static int rt298_resume(struct snd_soc_codec *codec) | |
1022 | { | |
1023 | struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec); | |
1024 | ||
1025 | regcache_cache_only(rt298->regmap, false); | |
1026 | rt298_index_sync(codec); | |
1027 | regcache_sync(rt298->regmap); | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | #else | |
1032 | #define rt298_suspend NULL | |
1033 | #define rt298_resume NULL | |
1034 | #endif | |
1035 | ||
1036 | #define RT298_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) | |
1037 | #define RT298_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
1038 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | |
1039 | ||
1040 | static const struct snd_soc_dai_ops rt298_aif_dai_ops = { | |
1041 | .hw_params = rt298_hw_params, | |
1042 | .set_fmt = rt298_set_dai_fmt, | |
1043 | .set_sysclk = rt298_set_dai_sysclk, | |
1044 | .set_bclk_ratio = rt298_set_bclk_ratio, | |
1045 | }; | |
1046 | ||
1047 | static struct snd_soc_dai_driver rt298_dai[] = { | |
1048 | { | |
1049 | .name = "rt298-aif1", | |
1050 | .id = RT298_AIF1, | |
1051 | .playback = { | |
1052 | .stream_name = "AIF1 Playback", | |
1053 | .channels_min = 1, | |
1054 | .channels_max = 2, | |
1055 | .rates = RT298_STEREO_RATES, | |
1056 | .formats = RT298_FORMATS, | |
1057 | }, | |
1058 | .capture = { | |
1059 | .stream_name = "AIF1 Capture", | |
1060 | .channels_min = 1, | |
1061 | .channels_max = 2, | |
1062 | .rates = RT298_STEREO_RATES, | |
1063 | .formats = RT298_FORMATS, | |
1064 | }, | |
1065 | .ops = &rt298_aif_dai_ops, | |
1066 | .symmetric_rates = 1, | |
1067 | }, | |
1068 | { | |
1069 | .name = "rt298-aif2", | |
1070 | .id = RT298_AIF2, | |
1071 | .playback = { | |
1072 | .stream_name = "AIF2 Playback", | |
1073 | .channels_min = 1, | |
1074 | .channels_max = 2, | |
1075 | .rates = RT298_STEREO_RATES, | |
1076 | .formats = RT298_FORMATS, | |
1077 | }, | |
1078 | .capture = { | |
1079 | .stream_name = "AIF2 Capture", | |
1080 | .channels_min = 1, | |
1081 | .channels_max = 2, | |
1082 | .rates = RT298_STEREO_RATES, | |
1083 | .formats = RT298_FORMATS, | |
1084 | }, | |
1085 | .ops = &rt298_aif_dai_ops, | |
1086 | .symmetric_rates = 1, | |
1087 | }, | |
1088 | ||
1089 | }; | |
1090 | ||
1091 | static struct snd_soc_codec_driver soc_codec_dev_rt298 = { | |
1092 | .probe = rt298_probe, | |
1093 | .remove = rt298_remove, | |
1094 | .suspend = rt298_suspend, | |
1095 | .resume = rt298_resume, | |
1096 | .set_bias_level = rt298_set_bias_level, | |
1097 | .idle_bias_off = true, | |
1098 | .controls = rt298_snd_controls, | |
1099 | .num_controls = ARRAY_SIZE(rt298_snd_controls), | |
1100 | .dapm_widgets = rt298_dapm_widgets, | |
1101 | .num_dapm_widgets = ARRAY_SIZE(rt298_dapm_widgets), | |
1102 | .dapm_routes = rt298_dapm_routes, | |
1103 | .num_dapm_routes = ARRAY_SIZE(rt298_dapm_routes), | |
1104 | }; | |
1105 | ||
1106 | static const struct regmap_config rt298_regmap = { | |
1107 | .reg_bits = 32, | |
1108 | .val_bits = 32, | |
1109 | .max_register = 0x02370100, | |
1110 | .volatile_reg = rt298_volatile_register, | |
1111 | .readable_reg = rt298_readable_register, | |
1112 | .reg_write = rl6347a_hw_write, | |
1113 | .reg_read = rl6347a_hw_read, | |
1114 | .cache_type = REGCACHE_RBTREE, | |
1115 | .reg_defaults = rt298_reg, | |
1116 | .num_reg_defaults = ARRAY_SIZE(rt298_reg), | |
1117 | }; | |
1118 | ||
1119 | static const struct i2c_device_id rt298_i2c_id[] = { | |
1120 | {"rt298", 0}, | |
1121 | {} | |
1122 | }; | |
1123 | MODULE_DEVICE_TABLE(i2c, rt298_i2c_id); | |
1124 | ||
1125 | static const struct acpi_device_id rt298_acpi_match[] = { | |
1126 | { "INT343A", 0 }, | |
1127 | {}, | |
1128 | }; | |
1129 | MODULE_DEVICE_TABLE(acpi, rt298_acpi_match); | |
1130 | ||
b9c17f13 VK |
1131 | static const struct dmi_system_id force_combo_jack_table[] = { |
1132 | { | |
1133 | .ident = "Intel Broxton P", | |
1134 | .matches = { | |
1135 | DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"), | |
1136 | DMI_MATCH(DMI_PRODUCT_NAME, "Broxton P") | |
1137 | } | |
1138 | }, | |
1139 | { } | |
1140 | }; | |
1141 | ||
6adcafae BL |
1142 | static int rt298_i2c_probe(struct i2c_client *i2c, |
1143 | const struct i2c_device_id *id) | |
1144 | { | |
1145 | struct rt298_platform_data *pdata = dev_get_platdata(&i2c->dev); | |
1146 | struct rt298_priv *rt298; | |
1147 | struct device *dev = &i2c->dev; | |
1148 | const struct acpi_device_id *acpiid; | |
1149 | int i, ret; | |
1150 | ||
6adcafae BL |
1151 | rt298 = devm_kzalloc(&i2c->dev, sizeof(*rt298), |
1152 | GFP_KERNEL); | |
1153 | if (NULL == rt298) | |
1154 | return -ENOMEM; | |
1155 | ||
1156 | rt298->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt298_regmap); | |
1157 | if (IS_ERR(rt298->regmap)) { | |
1158 | ret = PTR_ERR(rt298->regmap); | |
1159 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
1160 | ret); | |
1161 | return ret; | |
1162 | } | |
1163 | ||
1164 | regmap_read(rt298->regmap, | |
1165 | RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret); | |
1166 | if (ret != RT298_VENDOR_ID) { | |
1167 | dev_err(&i2c->dev, | |
1168 | "Device with ID register %#x is not rt298\n", ret); | |
1169 | return -ENODEV; | |
1170 | } | |
1171 | ||
3943b9ef AL |
1172 | rt298->index_cache = devm_kmemdup(&i2c->dev, rt298_index_def, |
1173 | sizeof(rt298_index_def), GFP_KERNEL); | |
1174 | if (!rt298->index_cache) | |
1175 | return -ENOMEM; | |
1176 | ||
6adcafae BL |
1177 | rt298->index_cache_size = INDEX_CACHE_SIZE; |
1178 | rt298->i2c = i2c; | |
1179 | i2c_set_clientdata(i2c, rt298); | |
1180 | ||
1181 | /* restore codec default */ | |
1182 | for (i = 0; i < INDEX_CACHE_SIZE; i++) | |
1183 | regmap_write(rt298->regmap, rt298->index_cache[i].reg, | |
1184 | rt298->index_cache[i].def); | |
1185 | for (i = 0; i < ARRAY_SIZE(rt298_reg); i++) | |
1186 | regmap_write(rt298->regmap, rt298_reg[i].reg, | |
1187 | rt298_reg[i].def); | |
1188 | ||
1189 | if (pdata) | |
1190 | rt298->pdata = *pdata; | |
1191 | ||
1192 | /* enable jack combo mode on supported devices */ | |
1193 | acpiid = acpi_match_device(dev->driver->acpi_match_table, dev); | |
bb7cb54b | 1194 | if (acpiid && acpiid->driver_data) { |
6adcafae BL |
1195 | rt298->pdata = *(struct rt298_platform_data *) |
1196 | acpiid->driver_data; | |
1197 | } | |
1198 | ||
b9c17f13 VK |
1199 | if (dmi_check_system(force_combo_jack_table)) { |
1200 | rt298->pdata.cbj_en = true; | |
1201 | rt298->pdata.gpio2_en = false; | |
1202 | } | |
1203 | ||
6adcafae BL |
1204 | /* VREF Charging */ |
1205 | regmap_update_bits(rt298->regmap, 0x04, 0x80, 0x80); | |
1206 | regmap_update_bits(rt298->regmap, 0x1b, 0x860, 0x860); | |
1207 | /* Vref2 */ | |
1208 | regmap_update_bits(rt298->regmap, 0x08, 0x20, 0x20); | |
1209 | ||
1210 | regmap_write(rt298->regmap, RT298_SET_AUDIO_POWER, AC_PWRST_D3); | |
1211 | ||
1212 | for (i = 0; i < RT298_POWER_REG_LEN; i++) | |
1213 | regmap_write(rt298->regmap, | |
1214 | RT298_SET_POWER(rt298_support_power_controls[i]), | |
1215 | AC_PWRST_D1); | |
1216 | ||
1217 | if (!rt298->pdata.cbj_en) { | |
1218 | regmap_write(rt298->regmap, RT298_CBJ_CTRL2, 0x0000); | |
1219 | regmap_write(rt298->regmap, RT298_MIC1_DET_CTRL, 0x0816); | |
1220 | regmap_update_bits(rt298->regmap, | |
1221 | RT298_CBJ_CTRL1, 0xf000, 0xb000); | |
1222 | } else { | |
1223 | regmap_update_bits(rt298->regmap, | |
1224 | RT298_CBJ_CTRL1, 0xf000, 0x5000); | |
1225 | } | |
1226 | ||
1227 | mdelay(10); | |
1228 | ||
1229 | if (!rt298->pdata.gpio2_en) | |
f8f2dc4a | 1230 | regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0x40); |
6adcafae BL |
1231 | else |
1232 | regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0); | |
1233 | ||
1234 | mdelay(10); | |
1235 | ||
1236 | regmap_write(rt298->regmap, RT298_MISC_CTRL1, 0x0000); | |
1237 | regmap_update_bits(rt298->regmap, | |
1238 | RT298_WIND_FILTER_CTRL, 0x0082, 0x0082); | |
4b2fe382 BL |
1239 | |
1240 | regmap_write(rt298->regmap, RT298_UNSOLICITED_INLINE_CMD, 0x81); | |
1241 | regmap_write(rt298->regmap, RT298_UNSOLICITED_HP_OUT, 0x82); | |
1242 | regmap_write(rt298->regmap, RT298_UNSOLICITED_MIC1, 0x84); | |
1243 | regmap_update_bits(rt298->regmap, RT298_IRQ_FLAG_CTRL, 0x2, 0x2); | |
1244 | ||
6adcafae BL |
1245 | rt298->is_hp_in = -1; |
1246 | ||
1247 | if (rt298->i2c->irq) { | |
1248 | ret = request_threaded_irq(rt298->i2c->irq, NULL, rt298_irq, | |
1249 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt298", rt298); | |
1250 | if (ret != 0) { | |
1251 | dev_err(&i2c->dev, | |
1252 | "Failed to reguest IRQ: %d\n", ret); | |
1253 | return ret; | |
1254 | } | |
1255 | } | |
1256 | ||
1257 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt298, | |
1258 | rt298_dai, ARRAY_SIZE(rt298_dai)); | |
1259 | ||
1260 | return ret; | |
1261 | } | |
1262 | ||
1263 | static int rt298_i2c_remove(struct i2c_client *i2c) | |
1264 | { | |
1265 | struct rt298_priv *rt298 = i2c_get_clientdata(i2c); | |
1266 | ||
1267 | if (i2c->irq) | |
1268 | free_irq(i2c->irq, rt298); | |
1269 | snd_soc_unregister_codec(&i2c->dev); | |
1270 | ||
1271 | return 0; | |
1272 | } | |
1273 | ||
1274 | ||
1275 | static struct i2c_driver rt298_i2c_driver = { | |
1276 | .driver = { | |
1277 | .name = "rt298", | |
6adcafae BL |
1278 | .acpi_match_table = ACPI_PTR(rt298_acpi_match), |
1279 | }, | |
1280 | .probe = rt298_i2c_probe, | |
1281 | .remove = rt298_i2c_remove, | |
1282 | .id_table = rt298_i2c_id, | |
1283 | }; | |
1284 | ||
1285 | module_i2c_driver(rt298_i2c_driver); | |
1286 | ||
1287 | MODULE_DESCRIPTION("ASoC RT298 driver"); | |
1288 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); | |
1289 | MODULE_LICENSE("GPL"); |