projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'i2c/for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
[deliverable/linux.git] / sound / soc / codecs / rt5645.c
CommitLineData
1319b2f6
OC		 1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
f3fa1bbd 20#include <linux/gpio.h>
baf2a0e1 21#include <linux/gpio/consumer.h>
3168c201 22#include <linux/acpi.h>
78c34fd4 23#include <linux/dmi.h>
9fc114c5 24#include <linux/regulator/consumer.h>
1319b2f6
OC		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
49ef7925 34#include "rl6231.h"
1319b2f6
OC		 35#include "rt5645.h"
36
37#define RT5645_DEVICE_ID 0x6308
5c4ca99d 38#define RT5650_DEVICE_ID 0x6419
1319b2f6
OC		 39
40#define RT5645_PR_RANGE_BASE (0xff + 1)
41#define RT5645_PR_SPACING 0x100
42
43#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
44
be77b38a
OC		 45#define RT5645_HWEQ_NUM 57
46
1319b2f6
OC		 47static const struct regmap_range_cfg rt5645_ranges[] = {
48 {
49 .name = "PR",
50 .range_min = RT5645_PR_BASE,
51 .range_max = RT5645_PR_BASE + 0xf8,
52 .selector_reg = RT5645_PRIV_INDEX,
53 .selector_mask = 0xff,
54 .selector_shift = 0x0,
55 .window_start = RT5645_PRIV_DATA,
56 .window_len = 0x1,
57 },
58};
59
8019ff6c 60static const struct reg_sequence init_list[] = {
1319b2f6 61 {RT5645_PR_BASE + 0x3d, 0x3600},
4809b96e
OC		 62 {RT5645_PR_BASE + 0x1c, 0xfd20},
63 {RT5645_PR_BASE + 0x20, 0x611f},
64 {RT5645_PR_BASE + 0x21, 0x4040},
65 {RT5645_PR_BASE + 0x23, 0x0004},
1319b2f6
OC		 66};
67#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
68
8019ff6c 69static const struct reg_sequence rt5650_init_list[] = {
5c4ca99d
BL		 70 {0xf6, 0x0100},
71};
72
1319b2f6
OC		 73static const struct reg_default rt5645_reg[] = {
74 { 0x00, 0x0000 },
75 { 0x01, 0xc8c8 },
76 { 0x02, 0xc8c8 },
77 { 0x03, 0xc8c8 },
78 { 0x0a, 0x0002 },
79 { 0x0b, 0x2827 },
80 { 0x0c, 0xe000 },
81 { 0x0d, 0x0000 },
82 { 0x0e, 0x0000 },
83 { 0x0f, 0x0808 },
84 { 0x14, 0x3333 },
85 { 0x16, 0x4b00 },
86 { 0x18, 0x018b },
87 { 0x19, 0xafaf },
88 { 0x1a, 0xafaf },
89 { 0x1b, 0x0001 },
90 { 0x1c, 0x2f2f },
91 { 0x1d, 0x2f2f },
92 { 0x1e, 0x0000 },
93 { 0x20, 0x0000 },
94 { 0x27, 0x7060 },
95 { 0x28, 0x7070 },
96 { 0x29, 0x8080 },
97 { 0x2a, 0x5656 },
98 { 0x2b, 0x5454 },
99 { 0x2c, 0xaaa0 },
5c4ca99d 100 { 0x2d, 0x0000 },
1319b2f6
OC		 101 { 0x2f, 0x1002 },
102 { 0x31, 0x5000 },
103 { 0x32, 0x0000 },
104 { 0x33, 0x0000 },
105 { 0x34, 0x0000 },
106 { 0x35, 0x0000 },
107 { 0x3b, 0x0000 },
108 { 0x3c, 0x007f },
109 { 0x3d, 0x0000 },
110 { 0x3e, 0x007f },
111 { 0x3f, 0x0000 },
112 { 0x40, 0x001f },
113 { 0x41, 0x0000 },
114 { 0x42, 0x001f },
115 { 0x45, 0x6000 },
116 { 0x46, 0x003e },
117 { 0x47, 0x003e },
118 { 0x48, 0xf807 },
119 { 0x4a, 0x0004 },
120 { 0x4d, 0x0000 },
121 { 0x4e, 0x0000 },
122 { 0x4f, 0x01ff },
123 { 0x50, 0x0000 },
124 { 0x51, 0x0000 },
125 { 0x52, 0x01ff },
126 { 0x53, 0xf000 },
127 { 0x56, 0x0111 },
128 { 0x57, 0x0064 },
129 { 0x58, 0xef0e },
130 { 0x59, 0xf0f0 },
131 { 0x5a, 0xef0e },
132 { 0x5b, 0xf0f0 },
133 { 0x5c, 0xef0e },
134 { 0x5d, 0xf0f0 },
135 { 0x5e, 0xf000 },
136 { 0x5f, 0x0000 },
137 { 0x61, 0x0300 },
138 { 0x62, 0x0000 },
139 { 0x63, 0x00c2 },
140 { 0x64, 0x0000 },
141 { 0x65, 0x0000 },
142 { 0x66, 0x0000 },
143 { 0x6a, 0x0000 },
144 { 0x6c, 0x0aaa },
145 { 0x70, 0x8000 },
146 { 0x71, 0x8000 },
147 { 0x72, 0x8000 },
148 { 0x73, 0x7770 },
149 { 0x74, 0x3e00 },
150 { 0x75, 0x2409 },
151 { 0x76, 0x000a },
152 { 0x77, 0x0c00 },
153 { 0x78, 0x0000 },
df078d29 154 { 0x79, 0x0123 },
1319b2f6
OC		 155 { 0x80, 0x0000 },
156 { 0x81, 0x0000 },
157 { 0x82, 0x0000 },
158 { 0x83, 0x0000 },
159 { 0x84, 0x0000 },
160 { 0x85, 0x0000 },
161 { 0x8a, 0x0000 },
162 { 0x8e, 0x0004 },
163 { 0x8f, 0x1100 },
164 { 0x90, 0x0646 },
165 { 0x91, 0x0c06 },
166 { 0x93, 0x0000 },
167 { 0x94, 0x0200 },
168 { 0x95, 0x0000 },
169 { 0x9a, 0x2184 },
170 { 0x9b, 0x010a },
171 { 0x9c, 0x0aea },
172 { 0x9d, 0x000c },
173 { 0x9e, 0x0400 },
174 { 0xa0, 0xa0a8 },
175 { 0xa1, 0x0059 },
176 { 0xa2, 0x0001 },
177 { 0xae, 0x6000 },
178 { 0xaf, 0x0000 },
179 { 0xb0, 0x6000 },
180 { 0xb1, 0x0000 },
181 { 0xb2, 0x0000 },
182 { 0xb3, 0x001f },
183 { 0xb4, 0x020c },
184 { 0xb5, 0x1f00 },
185 { 0xb6, 0x0000 },
186 { 0xbb, 0x0000 },
187 { 0xbc, 0x0000 },
188 { 0xbd, 0x0000 },
189 { 0xbe, 0x0000 },
190 { 0xbf, 0x3100 },
191 { 0xc0, 0x0000 },
192 { 0xc1, 0x0000 },
193 { 0xc2, 0x0000 },
194 { 0xc3, 0x2000 },
195 { 0xcd, 0x0000 },
196 { 0xce, 0x0000 },
197 { 0xcf, 0x1813 },
198 { 0xd0, 0x0690 },
199 { 0xd1, 0x1c17 },
200 { 0xd3, 0xb320 },
201 { 0xd4, 0x0000 },
202 { 0xd6, 0x0400 },
203 { 0xd9, 0x0809 },
204 { 0xda, 0x0000 },
205 { 0xdb, 0x0003 },
206 { 0xdc, 0x0049 },
207 { 0xdd, 0x001b },
5c4ca99d
BL		 208 { 0xdf, 0x0008 },
209 { 0xe0, 0x4000 },
1319b2f6
OC		 210 { 0xe6, 0x8000 },
211 { 0xe7, 0x0200 },
212 { 0xec, 0xb300 },
213 { 0xed, 0x0000 },
214 { 0xf0, 0x001f },
215 { 0xf1, 0x020c },
216 { 0xf2, 0x1f00 },
217 { 0xf3, 0x0000 },
218 { 0xf4, 0x4000 },
219 { 0xf8, 0x0000 },
220 { 0xf9, 0x0000 },
221 { 0xfa, 0x2060 },
222 { 0xfb, 0x4040 },
223 { 0xfc, 0x0000 },
224 { 0xfd, 0x0002 },
225 { 0xfe, 0x10ec },
226 { 0xff, 0x6308 },
227};
228
be77b38a
OC		 229struct rt5645_eq_param_s {
230 unsigned short reg;
231 unsigned short val;
232};
233
9fc114c5
KC		 234static const char *const rt5645_supply_names[] = {
235 "avdd",
236 "cpvdd",
237};
238
239struct rt5645_priv {
240 struct snd_soc_codec *codec;
241 struct rt5645_platform_data pdata;
242 struct regmap *regmap;
243 struct i2c_client *i2c;
244 struct gpio_desc *gpiod_hp_det;
245 struct snd_soc_jack *hp_jack;
246 struct snd_soc_jack *mic_jack;
247 struct snd_soc_jack *btn_jack;
7099ee85 248 struct delayed_work jack_detect_work, rcclock_work;
9fc114c5 249 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
be77b38a 250 struct rt5645_eq_param_s *eq_param;
9fc114c5
KC		 251
252 int codec_type;
253 int sysclk;
254 int sysclk_src;
255 int lrck[RT5645_AIFS];
256 int bclk[RT5645_AIFS];
257 int master[RT5645_AIFS];
258
259 int pll_src;
260 int pll_in;
261 int pll_out;
262
263 int jack_type;
264 bool en_button_func;
588cd850 265 bool hp_on;
9fc114c5
KC		 266};
267
1319b2f6
OC		 268static int rt5645_reset(struct snd_soc_codec *codec)
269{
270 return snd_soc_write(codec, RT5645_RESET, 0);
271}
272
273static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
274{
275 int i;
276
277 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
278 if (reg >= rt5645_ranges[i].range_min &&
279 reg <= rt5645_ranges[i].range_max) {
280 return true;
281 }
282 }
283
284 switch (reg) {
285 case RT5645_RESET:
286 case RT5645_PRIV_DATA:
287 case RT5645_IN1_CTRL1:
288 case RT5645_IN1_CTRL2:
289 case RT5645_IN1_CTRL3:
290 case RT5645_A_JD_CTRL1:
291 case RT5645_ADC_EQ_CTRL1:
292 case RT5645_EQ_CTRL1:
293 case RT5645_ALC_CTRL_1:
294 case RT5645_IRQ_CTRL2:
295 case RT5645_IRQ_CTRL3:
296 case RT5645_INT_IRQ_ST:
297 case RT5645_IL_CMD:
5c4ca99d 298 case RT5650_4BTN_IL_CMD1:
1319b2f6
OC		 299 case RT5645_VENDOR_ID:
300 case RT5645_VENDOR_ID1:
301 case RT5645_VENDOR_ID2:
71bfa9b4 302 return true;
1319b2f6 303 default:
71bfa9b4 304 return false;
1319b2f6
OC		 305 }
306}
307
308static bool rt5645_readable_register(struct device *dev, unsigned int reg)
309{
310 int i;
311
312 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
313 if (reg >= rt5645_ranges[i].range_min &&
314 reg <= rt5645_ranges[i].range_max) {
315 return true;
316 }
317 }
318
319 switch (reg) {
320 case RT5645_RESET:
321 case RT5645_SPK_VOL:
322 case RT5645_HP_VOL:
323 case RT5645_LOUT1:
324 case RT5645_IN1_CTRL1:
325 case RT5645_IN1_CTRL2:
326 case RT5645_IN1_CTRL3:
327 case RT5645_IN2_CTRL:
328 case RT5645_INL1_INR1_VOL:
329 case RT5645_SPK_FUNC_LIM:
330 case RT5645_ADJ_HPF_CTRL:
331 case RT5645_DAC1_DIG_VOL:
332 case RT5645_DAC2_DIG_VOL:
333 case RT5645_DAC_CTRL:
334 case RT5645_STO1_ADC_DIG_VOL:
335 case RT5645_MONO_ADC_DIG_VOL:
336 case RT5645_ADC_BST_VOL1:
337 case RT5645_ADC_BST_VOL2:
338 case RT5645_STO1_ADC_MIXER:
339 case RT5645_MONO_ADC_MIXER:
340 case RT5645_AD_DA_MIXER:
341 case RT5645_STO_DAC_MIXER:
342 case RT5645_MONO_DAC_MIXER:
343 case RT5645_DIG_MIXER:
5c4ca99d 344 case RT5650_A_DAC_SOUR:
1319b2f6
OC		 345 case RT5645_DIG_INF1_DATA:
346 case RT5645_PDM_OUT_CTRL:
347 case RT5645_REC_L1_MIXER:
348 case RT5645_REC_L2_MIXER:
349 case RT5645_REC_R1_MIXER:
350 case RT5645_REC_R2_MIXER:
351 case RT5645_HPMIXL_CTRL:
352 case RT5645_HPOMIXL_CTRL:
353 case RT5645_HPMIXR_CTRL:
354 case RT5645_HPOMIXR_CTRL:
355 case RT5645_HPO_MIXER:
356 case RT5645_SPK_L_MIXER:
357 case RT5645_SPK_R_MIXER:
358 case RT5645_SPO_MIXER:
359 case RT5645_SPO_CLSD_RATIO:
360 case RT5645_OUT_L1_MIXER:
361 case RT5645_OUT_R1_MIXER:
362 case RT5645_OUT_L_GAIN1:
363 case RT5645_OUT_L_GAIN2:
364 case RT5645_OUT_R_GAIN1:
365 case RT5645_OUT_R_GAIN2:
366 case RT5645_LOUT_MIXER:
367 case RT5645_HAPTIC_CTRL1:
368 case RT5645_HAPTIC_CTRL2:
369 case RT5645_HAPTIC_CTRL3:
370 case RT5645_HAPTIC_CTRL4:
371 case RT5645_HAPTIC_CTRL5:
372 case RT5645_HAPTIC_CTRL6:
373 case RT5645_HAPTIC_CTRL7:
374 case RT5645_HAPTIC_CTRL8:
375 case RT5645_HAPTIC_CTRL9:
376 case RT5645_HAPTIC_CTRL10:
377 case RT5645_PWR_DIG1:
378 case RT5645_PWR_DIG2:
379 case RT5645_PWR_ANLG1:
380 case RT5645_PWR_ANLG2:
381 case RT5645_PWR_MIXER:
382 case RT5645_PWR_VOL:
383 case RT5645_PRIV_INDEX:
384 case RT5645_PRIV_DATA:
385 case RT5645_I2S1_SDP:
386 case RT5645_I2S2_SDP:
387 case RT5645_ADDA_CLK1:
388 case RT5645_ADDA_CLK2:
389 case RT5645_DMIC_CTRL1:
390 case RT5645_DMIC_CTRL2:
391 case RT5645_TDM_CTRL_1:
392 case RT5645_TDM_CTRL_2:
df078d29 393 case RT5645_TDM_CTRL_3:
1fcb76db 394 case RT5650_TDM_CTRL_4:
1319b2f6
OC		 395 case RT5645_GLB_CLK:
396 case RT5645_PLL_CTRL1:
397 case RT5645_PLL_CTRL2:
398 case RT5645_ASRC_1:
399 case RT5645_ASRC_2:
400 case RT5645_ASRC_3:
401 case RT5645_ASRC_4:
402 case RT5645_DEPOP_M1:
403 case RT5645_DEPOP_M2:
404 case RT5645_DEPOP_M3:
b1d42598 405 case RT5645_CHARGE_PUMP:
1319b2f6
OC		 406 case RT5645_MICBIAS:
407 case RT5645_A_JD_CTRL1:
408 case RT5645_VAD_CTRL4:
409 case RT5645_CLSD_OUT_CTRL:
410 case RT5645_ADC_EQ_CTRL1:
411 case RT5645_ADC_EQ_CTRL2:
412 case RT5645_EQ_CTRL1:
413 case RT5645_EQ_CTRL2:
414 case RT5645_ALC_CTRL_1:
415 case RT5645_ALC_CTRL_2:
416 case RT5645_ALC_CTRL_3:
417 case RT5645_ALC_CTRL_4:
418 case RT5645_ALC_CTRL_5:
419 case RT5645_JD_CTRL:
420 case RT5645_IRQ_CTRL1:
421 case RT5645_IRQ_CTRL2:
422 case RT5645_IRQ_CTRL3:
423 case RT5645_INT_IRQ_ST:
424 case RT5645_GPIO_CTRL1:
425 case RT5645_GPIO_CTRL2:
426 case RT5645_GPIO_CTRL3:
427 case RT5645_BASS_BACK:
428 case RT5645_MP3_PLUS1:
429 case RT5645_MP3_PLUS2:
430 case RT5645_ADJ_HPF1:
431 case RT5645_ADJ_HPF2:
432 case RT5645_HP_CALIB_AMP_DET:
433 case RT5645_SV_ZCD1:
434 case RT5645_SV_ZCD2:
435 case RT5645_IL_CMD:
436 case RT5645_IL_CMD2:
437 case RT5645_IL_CMD3:
5c4ca99d
BL		 438 case RT5650_4BTN_IL_CMD1:
439 case RT5650_4BTN_IL_CMD2:
1319b2f6
OC		 440 case RT5645_DRC1_HL_CTRL1:
441 case RT5645_DRC2_HL_CTRL1:
442 case RT5645_ADC_MONO_HP_CTRL1:
443 case RT5645_ADC_MONO_HP_CTRL2:
444 case RT5645_DRC2_CTRL1:
445 case RT5645_DRC2_CTRL2:
446 case RT5645_DRC2_CTRL3:
447 case RT5645_DRC2_CTRL4:
448 case RT5645_DRC2_CTRL5:
449 case RT5645_JD_CTRL3:
450 case RT5645_JD_CTRL4:
451 case RT5645_GEN_CTRL1:
452 case RT5645_GEN_CTRL2:
453 case RT5645_GEN_CTRL3:
454 case RT5645_VENDOR_ID:
455 case RT5645_VENDOR_ID1:
456 case RT5645_VENDOR_ID2:
71bfa9b4 457 return true;
1319b2f6 458 default:
71bfa9b4 459 return false;
1319b2f6
OC		 460 }
461}
462
463static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
177e1e1f 464static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1319b2f6 465static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
177e1e1f 466static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1319b2f6
OC		 467static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
468
469/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
6d698a83 470static const DECLARE_TLV_DB_RANGE(bst_tlv,
1319b2f6
OC		 471 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
472 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
473 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
474 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
475 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
476 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
6d698a83
LPC		 477 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
478);
1319b2f6 479
e29fd55d
OC		 480/* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
481static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
482 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
483 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
484 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
485 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
486);
487
be77b38a
OC		 488static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
489 struct snd_ctl_elem_info *uinfo)
490{
491 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
492 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
493
494 return 0;
495}
496
497static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
498 struct snd_ctl_elem_value *ucontrol)
499{
500 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
501 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
502 struct rt5645_eq_param_s *eq_param =
503 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data;
504 int i;
505
506 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
507 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
508 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
509 }
510
511 return 0;
512}
513
514static bool rt5645_validate_hweq(unsigned short reg)
515{
516 if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) |
517 (reg == RT5645_EQ_CTRL2))
518 return true;
519
520 return false;
521}
522
523static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
524 struct snd_ctl_elem_value *ucontrol)
525{
526 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
527 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
528 struct rt5645_eq_param_s *eq_param =
529 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data;
530 int i;
531
532 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
533 eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
534 eq_param[i].val = be16_to_cpu(eq_param[i].val);
535 }
536
537 /* The final setting of the table should be RT5645_EQ_CTRL2 */
538 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
539 if (eq_param[i].reg == 0)
540 continue;
541 else if (eq_param[i].reg != RT5645_EQ_CTRL2)
542 return 0;
543 else
544 break;
545 }
546
547 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
548 if (!rt5645_validate_hweq(eq_param[i].reg) &&
549 eq_param[i].reg != 0)
550 return 0;
551 else if (eq_param[i].reg == 0)
552 break;
553 }
554
555 memcpy(rt5645->eq_param, eq_param,
556 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s));
557
558 return 0;
559}
560
561#define RT5645_HWEQ(xname) \
562{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
563 .info = rt5645_hweq_info, \
564 .get = rt5645_hweq_get, \
565 .put = rt5645_hweq_put \
566}
567
7099ee85
OC		 568static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
569 struct snd_ctl_elem_value *ucontrol)
570{
571 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
572 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
573 int ret;
574
575 cancel_delayed_work_sync(&rt5645->rcclock_work);
576
577 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
578 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
579
580 ret = snd_soc_put_volsw(kcontrol, ucontrol);
581
582 queue_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
583 msecs_to_jiffies(200));
584
585 return ret;
586}
587
1319b2f6
OC		 588static const struct snd_kcontrol_new rt5645_snd_controls[] = {
589 /* Speaker Output Volume */
590 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
591 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
7099ee85
OC		 592 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
593 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
594 rt5645_spk_put_volsw, out_vol_tlv),
1319b2f6 595
e29fd55d
OC		 596 /* ClassD modulator Speaker Gain Ratio */
597 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
598 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
599
1319b2f6 600 /* Headphone Output Volume */
692768c4 601 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
1319b2f6 602 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
692768c4 603 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
1319b2f6
OC		 604 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
605
606 /* OUTPUT Control */
607 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
608 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
609 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
610 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
611 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
612 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
613
614 /* DAC Digital Volume */
615 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
616 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
617 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
177e1e1f 618 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6 619 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
177e1e1f 620 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6
OC		 621
622 /* IN1/IN2 Control */
623 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
624 RT5645_BST_SFT1, 8, 0, bst_tlv),
625 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
626 RT5645_BST_SFT2, 8, 0, bst_tlv),
627
628 /* INL/INR Volume Control */
629 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
630 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
631
632 /* ADC Digital Volume Control */
633 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
634 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
635 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
177e1e1f 636 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 637 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
638 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
639 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
177e1e1f 640 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 641
642 /* ADC Boost Volume Control */
8c1a9d63 643 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
1319b2f6
OC		 644 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
645 adc_bst_tlv),
8c1a9d63
OC		 646 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
647 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
1319b2f6
OC		 648 adc_bst_tlv),
649
650 /* I2S2 function select */
651 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
652 1, 1),
be77b38a 653 RT5645_HWEQ("Speaker HWEQ"),
1319b2f6
OC		 654};
655
656/**
657 * set_dmic_clk - Set parameter of dmic.
658 *
659 * @w: DAPM widget.
660 * @kcontrol: The kcontrol of this widget.
661 * @event: Event id.
662 *
1319b2f6
OC		 663 */
664static int set_dmic_clk(struct snd_soc_dapm_widget *w,
665 struct snd_kcontrol *kcontrol, int event)
666{
c5f596cb 667 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6 668 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
00a6d6e5 669 int idx, rate;
1319b2f6 670
00a6d6e5
OC		 671 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
672 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
673 idx = rl6231_calc_dmic_clk(rate);
1319b2f6
OC		 674 if (idx < 0)
675 dev_err(codec->dev, "Failed to set DMIC clock\n");
676 else
677 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
678 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
679 return idx;
680}
681
682static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
683 struct snd_soc_dapm_widget *sink)
684{
c5f596cb 685 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1319b2f6
OC		 686 unsigned int val;
687
c5f596cb 688 val = snd_soc_read(codec, RT5645_GLB_CLK);
1319b2f6
OC		 689 val &= RT5645_SCLK_SRC_MASK;
690 if (val == RT5645_SCLK_SRC_PLL1)
691 return 1;
692 else
693 return 0;
694}
695
9e268353
BL		 696static int is_using_asrc(struct snd_soc_dapm_widget *source,
697 struct snd_soc_dapm_widget *sink)
698{
c5f596cb 699 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
9e268353
BL		 700 unsigned int reg, shift, val;
701
702 switch (source->shift) {
703 case 0:
704 reg = RT5645_ASRC_3;
705 shift = 0;
706 break;
707 case 1:
708 reg = RT5645_ASRC_3;
709 shift = 4;
710 break;
711 case 3:
712 reg = RT5645_ASRC_2;
713 shift = 0;
714 break;
715 case 8:
716 reg = RT5645_ASRC_2;
717 shift = 4;
718 break;
719 case 9:
720 reg = RT5645_ASRC_2;
721 shift = 8;
722 break;
723 case 10:
724 reg = RT5645_ASRC_2;
725 shift = 12;
726 break;
727 default:
728 return 0;
729 }
730
c5f596cb 731 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
9e268353
BL		 732 switch (val) {
733 case 1:
734 case 2:
735 case 3:
736 case 4:
737 return 1;
738 default:
739 return 0;
740 }
741
742}
743
be77b38a
OC		 744static int rt5645_enable_hweq(struct snd_soc_codec *codec)
745{
746 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
747 int i;
748
749 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
750 if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
751 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
752 rt5645->eq_param[i].val);
753 else
754 break;
755 }
756
757 return 0;
758}
759
79080a8b
FY		 760/**
761 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
762 * @codec: SoC audio codec device.
763 * @filter_mask: mask of filters.
764 * @clk_src: clock source
765 *
766 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
767 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
768 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
769 * ASRC function will track i2s clock and generate a corresponding system clock
770 * for codec. This function provides an API to select the clock source for a
771 * set of filters specified by the mask. And the codec driver will turn on ASRC
772 * for these filters if ASRC is selected as their clock source.
773 */
774int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
775 unsigned int filter_mask, unsigned int clk_src)
776{
777 unsigned int asrc2_mask = 0;
778 unsigned int asrc2_value = 0;
779 unsigned int asrc3_mask = 0;
780 unsigned int asrc3_value = 0;
781
782 switch (clk_src) {
783 case RT5645_CLK_SEL_SYS:
784 case RT5645_CLK_SEL_I2S1_ASRC:
785 case RT5645_CLK_SEL_I2S2_ASRC:
786 case RT5645_CLK_SEL_SYS2:
787 break;
788
789 default:
790 return -EINVAL;
791 }
792
793 if (filter_mask & RT5645_DA_STEREO_FILTER) {
794 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
795 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
796 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
797 }
798
799 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
800 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
801 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
802 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
803 }
804
805 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
806 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
807 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
808 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
809 }
810
811 if (filter_mask & RT5645_AD_STEREO_FILTER) {
812 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
813 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
814 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
815 }
816
817 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
818 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
819 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
820 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
821 }
822
823 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
824 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
825 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
826 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
827 }
828
829 if (asrc2_mask)
830 snd_soc_update_bits(codec, RT5645_ASRC_2,
831 asrc2_mask, asrc2_value);
832
833 if (asrc3_mask)
834 snd_soc_update_bits(codec, RT5645_ASRC_3,
835 asrc3_mask, asrc3_value);
836
837 return 0;
838}
839EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
840
1319b2f6
OC		 841/* Digital Mixer */
842static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
843 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
844 RT5645_M_ADC_L1_SFT, 1, 1),
845 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
846 RT5645_M_ADC_L2_SFT, 1, 1),
847};
848
849static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
850 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
851 RT5645_M_ADC_R1_SFT, 1, 1),
852 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
853 RT5645_M_ADC_R2_SFT, 1, 1),
854};
855
856static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
857 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
858 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
859 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
860 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
861};
862
863static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
864 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
865 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
866 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
867 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
868};
869
870static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
871 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
872 RT5645_M_ADCMIX_L_SFT, 1, 1),
21cb13e7 873 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1319b2f6
OC		 874 RT5645_M_DAC1_L_SFT, 1, 1),
875};
876
877static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
878 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
879 RT5645_M_ADCMIX_R_SFT, 1, 1),
21cb13e7 880 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1319b2f6
OC		 881 RT5645_M_DAC1_R_SFT, 1, 1),
882};
883
884static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
885 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
886 RT5645_M_DAC_L1_SFT, 1, 1),
887 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
888 RT5645_M_DAC_L2_SFT, 1, 1),
889 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
890 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
891};
892
893static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
894 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
895 RT5645_M_DAC_R1_SFT, 1, 1),
896 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
897 RT5645_M_DAC_R2_SFT, 1, 1),
898 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
899 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
900};
901
902static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
903 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
904 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
905 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
906 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
907 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
908 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
909};
910
911static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
912 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
913 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
914 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
915 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
916 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
917 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
918};
919
920static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
921 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
922 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
923 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
924 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
925 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
926 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
927};
928
929static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
930 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
931 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
932 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
933 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
934 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
935 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
936};
937
938/* Analog Input Mixer */
939static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
940 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
941 RT5645_M_HP_L_RM_L_SFT, 1, 1),
942 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
943 RT5645_M_IN_L_RM_L_SFT, 1, 1),
944 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
945 RT5645_M_BST2_RM_L_SFT, 1, 1),
946 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
947 RT5645_M_BST1_RM_L_SFT, 1, 1),
948 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
949 RT5645_M_OM_L_RM_L_SFT, 1, 1),
950};
951
952static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
953 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
954 RT5645_M_HP_R_RM_R_SFT, 1, 1),
955 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
956 RT5645_M_IN_R_RM_R_SFT, 1, 1),
957 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
958 RT5645_M_BST2_RM_R_SFT, 1, 1),
959 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
960 RT5645_M_BST1_RM_R_SFT, 1, 1),
961 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
962 RT5645_M_OM_R_RM_R_SFT, 1, 1),
963};
964
965static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
966 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
967 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
968 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
969 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
970 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
971 RT5645_M_IN_L_SM_L_SFT, 1, 1),
972 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
973 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
974};
975
976static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
977 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
978 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
979 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
980 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
981 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
982 RT5645_M_IN_R_SM_R_SFT, 1, 1),
983 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
984 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
985};
986
987static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
988 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
989 RT5645_M_BST1_OM_L_SFT, 1, 1),
990 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
991 RT5645_M_IN_L_OM_L_SFT, 1, 1),
992 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
993 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
994 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
995 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
996};
997
998static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
999 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1000 RT5645_M_BST2_OM_R_SFT, 1, 1),
1001 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1002 RT5645_M_IN_R_OM_R_SFT, 1, 1),
1003 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1004 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1005 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1006 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1007};
1008
1009static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1010 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1011 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1012 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1013 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1014 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1015 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1016 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1017 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1018};
1019
1020static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1021 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1022 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1023 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1024 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1025};
1026
1027static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1028 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1029 RT5645_M_DAC1_HM_SFT, 1, 1),
1030 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1031 RT5645_M_HPVOL_HM_SFT, 1, 1),
1032};
1033
1034static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1035 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1036 RT5645_M_DAC1_HV_SFT, 1, 1),
1037 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1038 RT5645_M_DAC2_HV_SFT, 1, 1),
1039 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1040 RT5645_M_IN_HV_SFT, 1, 1),
1041 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1042 RT5645_M_BST1_HV_SFT, 1, 1),
1043};
1044
1045static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1046 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1047 RT5645_M_DAC1_HV_SFT, 1, 1),
1048 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1049 RT5645_M_DAC2_HV_SFT, 1, 1),
1050 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1051 RT5645_M_IN_HV_SFT, 1, 1),
1052 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1053 RT5645_M_BST2_HV_SFT, 1, 1),
1054};
1055
1056static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1057 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1058 RT5645_M_DAC_L1_LM_SFT, 1, 1),
1059 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1060 RT5645_M_DAC_R1_LM_SFT, 1, 1),
1061 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1062 RT5645_M_OV_L_LM_SFT, 1, 1),
1063 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1064 RT5645_M_OV_R_LM_SFT, 1, 1),
1065};
1066
1067/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1068static const char * const rt5645_dac1_src[] = {
1069 "IF1 DAC", "IF2 DAC", "IF3 DAC"
1070};
1071
1072static SOC_ENUM_SINGLE_DECL(
1073 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1074 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1075
1076static const struct snd_kcontrol_new rt5645_dac1l_mux =
1077 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1078
1079static SOC_ENUM_SINGLE_DECL(
1080 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1081 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1082
1083static const struct snd_kcontrol_new rt5645_dac1r_mux =
1084 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1085
1086/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1087static const char * const rt5645_dac12_src[] = {
1088 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1089};
1090
1091static SOC_ENUM_SINGLE_DECL(
1092 rt5645_dac2l_enum, RT5645_DAC_CTRL,
1093 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1094
1095static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1096 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1097
1098static const char * const rt5645_dacr2_src[] = {
1099 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1100};
1101
1102static SOC_ENUM_SINGLE_DECL(
1103 rt5645_dac2r_enum, RT5645_DAC_CTRL,
1104 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1105
1106static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1107 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1108
1109
1110/* INL/R source */
1111static const char * const rt5645_inl_src[] = {
1112 "IN2P", "MonoP"
1113};
1114
1115static SOC_ENUM_SINGLE_DECL(
1116 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
1117 RT5645_INL_SEL_SFT, rt5645_inl_src);
1118
1119static const struct snd_kcontrol_new rt5645_inl_mux =
1120 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
1121
1122static const char * const rt5645_inr_src[] = {
1123 "IN2N", "MonoN"
1124};
1125
1126static SOC_ENUM_SINGLE_DECL(
1127 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
1128 RT5645_INR_SEL_SFT, rt5645_inr_src);
1129
1130static const struct snd_kcontrol_new rt5645_inr_mux =
1131 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
1132
1133/* Stereo1 ADC source */
1134/* MX-27 [12] */
1135static const char * const rt5645_stereo_adc1_src[] = {
1136 "DAC MIX", "ADC"
1137};
1138
1139static SOC_ENUM_SINGLE_DECL(
1140 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1141 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1142
1143static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1144 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1145
1146/* MX-27 [11] */
1147static const char * const rt5645_stereo_adc2_src[] = {
1148 "DAC MIX", "DMIC"
1149};
1150
1151static SOC_ENUM_SINGLE_DECL(
1152 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1153 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1154
1155static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1156 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1157
1158/* MX-27 [8] */
1159static const char * const rt5645_stereo_dmic_src[] = {
1160 "DMIC1", "DMIC2"
1161};
1162
1163static SOC_ENUM_SINGLE_DECL(
1164 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1165 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1166
1167static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1168 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1169
1170/* Mono ADC source */
1171/* MX-28 [12] */
1172static const char * const rt5645_mono_adc_l1_src[] = {
1173 "Mono DAC MIXL", "ADC"
1174};
1175
1176static SOC_ENUM_SINGLE_DECL(
1177 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1178 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1179
1180static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1181 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1182/* MX-28 [11] */
1183static const char * const rt5645_mono_adc_l2_src[] = {
1184 "Mono DAC MIXL", "DMIC"
1185};
1186
1187static SOC_ENUM_SINGLE_DECL(
1188 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1189 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1190
1191static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1192 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1193
1194/* MX-28 [8] */
1195static const char * const rt5645_mono_dmic_src[] = {
1196 "DMIC1", "DMIC2"
1197};
1198
1199static SOC_ENUM_SINGLE_DECL(
1200 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1201 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1202
1203static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1204 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1205/* MX-28 [1:0] */
1206static SOC_ENUM_SINGLE_DECL(
1207 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1208 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1209
1210static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1211 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1212/* MX-28 [4] */
1213static const char * const rt5645_mono_adc_r1_src[] = {
1214 "Mono DAC MIXR", "ADC"
1215};
1216
1217static SOC_ENUM_SINGLE_DECL(
1218 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1219 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1220
1221static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1222 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1223/* MX-28 [3] */
1224static const char * const rt5645_mono_adc_r2_src[] = {
1225 "Mono DAC MIXR", "DMIC"
1226};
1227
1228static SOC_ENUM_SINGLE_DECL(
1229 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1230 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1231
1232static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1233 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1234
1235/* MX-77 [9:8] */
1236static const char * const rt5645_if1_adc_in_src[] = {
21ab3f2b
BL		 1237 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1238 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1319b2f6
OC		 1239};
1240
1241static SOC_ENUM_SINGLE_DECL(
1242 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1243 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1244
1245static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1246 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1247
21ab3f2b
BL		 1248/* MX-78 [4:0] */
1249static const char * const rt5650_if1_adc_in_src[] = {
1250 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1251 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1252 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1253 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1254 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1255 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1256
1257 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1258 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1259 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1260 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1261 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1262 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1263
1264 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1265 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1266 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1267 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1268 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1269 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1270
1271 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1272 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1273 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1274 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1275 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1276 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1277};
1278
1279static SOC_ENUM_SINGLE_DECL(
1280 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1281 0, rt5650_if1_adc_in_src);
1282
1283static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1284 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1285
1286/* MX-78 [15:14][13:12][11:10] */
1287static const char * const rt5645_tdm_adc_swap_select[] = {
1288 "L/R", "R/L", "L/L", "R/R"
1289};
1290
1291static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1292 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1293
1294static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1295 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1296
1297static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1298 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1299
1300static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1301 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1302
1303static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1304 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1305
1306static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1307 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1308
1309/* MX-77 [7:6][5:4][3:2] */
1310static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1311 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1312
1313static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1314 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1315
1316static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1317 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1318
1319static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1320 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1321
1322static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1323 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1324
1325static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1326 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1327
1328/* MX-79 [14:12][10:8][6:4][2:0] */
1329static const char * const rt5645_tdm_dac_swap_select[] = {
1330 "Slot0", "Slot1", "Slot2", "Slot3"
1331};
1332
1333static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1334 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1335
1336static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1337 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1338
1339static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1340 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1341
1342static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1343 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1344
1345static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1346 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1347
1348static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1349 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1350
1351static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1352 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1353
1354static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1355 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1356
1357/* MX-7a [14:12][10:8][6:4][2:0] */
1358static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1359 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1360
1361static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1362 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1363
1364static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1365 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1366
1367static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1368 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1369
1370static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1371 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1372
1373static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1374 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1375
1376static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1377 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1378
1379static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1380 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1381
5c4ca99d
BL		 1382/* MX-2d [3] [2] */
1383static const char * const rt5650_a_dac1_src[] = {
1384 "DAC1", "Stereo DAC Mixer"
1385};
1386
1387static SOC_ENUM_SINGLE_DECL(
1388 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1389 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1390
1391static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1392 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1393
1394static SOC_ENUM_SINGLE_DECL(
1395 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1396 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1397
1398static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1399 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1400
1401/* MX-2d [1] [0] */
1402static const char * const rt5650_a_dac2_src[] = {
1403 "Stereo DAC Mixer", "Mono DAC Mixer"
1404};
1405
1406static SOC_ENUM_SINGLE_DECL(
1407 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1408 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1409
1410static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1411 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1412
1413static SOC_ENUM_SINGLE_DECL(
1414 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1415 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1416
1417static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1418 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1419
1319b2f6
OC		 1420/* MX-2F [13:12] */
1421static const char * const rt5645_if2_adc_in_src[] = {
1422 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1423};
1424
1425static SOC_ENUM_SINGLE_DECL(
1426 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1427 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1428
1429static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1430 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1431
1432/* MX-2F [1:0] */
1433static const char * const rt5645_if3_adc_in_src[] = {
1434 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1435};
1436
1437static SOC_ENUM_SINGLE_DECL(
1438 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1439 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1440
1441static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1442 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1443
1444/* MX-31 [15] [13] [11] [9] */
1445static const char * const rt5645_pdm_src[] = {
1446 "Mono DAC", "Stereo DAC"
1447};
1448
1449static SOC_ENUM_SINGLE_DECL(
1450 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1451 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1452
1453static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1454 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1455
1456static SOC_ENUM_SINGLE_DECL(
1457 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1458 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1459
1460static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1461 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1462
1463/* MX-9D [9:8] */
1464static const char * const rt5645_vad_adc_src[] = {
1465 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1466};
1467
1468static SOC_ENUM_SINGLE_DECL(
1469 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1470 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1471
1472static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1473 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1474
1475static const struct snd_kcontrol_new spk_l_vol_control =
1476 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1477 RT5645_L_MUTE_SFT, 1, 1);
1478
1479static const struct snd_kcontrol_new spk_r_vol_control =
1480 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1481 RT5645_R_MUTE_SFT, 1, 1);
1482
1483static const struct snd_kcontrol_new hp_l_vol_control =
1484 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1485 RT5645_L_MUTE_SFT, 1, 1);
1486
1487static const struct snd_kcontrol_new hp_r_vol_control =
1488 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1489 RT5645_R_MUTE_SFT, 1, 1);
1490
1491static const struct snd_kcontrol_new pdm1_l_vol_control =
1492 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1493 RT5645_M_PDM1_L, 1, 1);
1494
1495static const struct snd_kcontrol_new pdm1_r_vol_control =
1496 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1497 RT5645_M_PDM1_R, 1, 1);
1498
1499static void hp_amp_power(struct snd_soc_codec *codec, int on)
1500{
1501 static int hp_amp_power_count;
1502 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1503
1504 if (on) {
1505 if (hp_amp_power_count <= 0) {
d12d6c4e 1506 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
588cd850 1507 snd_soc_write(codec, RT5645_DEPOP_M2, 0x3100);
d12d6c4e
JL		 1508 snd_soc_write(codec, RT5645_CHARGE_PUMP,
1509 0x0e06);
588cd850
OC		 1510 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1511 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1512 RT5645_HP_DCC_INT1, 0x9f01);
1513 msleep(20);
1514 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1515 RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
d12d6c4e
JL		 1516 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1517 0x3e, 0x7400);
1518 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1519 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1520 RT5645_MAMP_INT_REG2, 0xfc00);
1521 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
91ed37e4 1522 msleep(70);
588cd850 1523 rt5645->hp_on = true;
d12d6c4e
JL		 1524 } else {
1525 /* depop parameters */
1526 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1527 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1528 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1529 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1530 RT5645_HP_DCC_INT1, 0x9f01);
1531 mdelay(150);
1532 /* headphone amp power on */
1533 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1534 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1535 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1536 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1537 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1538 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1539 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1540 RT5645_PWR_HA,
1541 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1542 RT5645_PWR_HA);
1543 mdelay(5);
1544 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1545 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1546 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1547
1548 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1549 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1550 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1551 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1552 0x14, 0x1aaa);
1553 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1554 0x24, 0x0430);
1555 }
1319b2f6
OC		 1556 }
1557 hp_amp_power_count++;
1558 } else {
1559 hp_amp_power_count--;
1560 if (hp_amp_power_count <= 0) {
d12d6c4e
JL		 1561 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1562 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1563 0x3e, 0x7400);
1564 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1565 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1566 RT5645_MAMP_INT_REG2, 0xfc00);
1567 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1568 msleep(100);
1569 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1570
1571 } else {
1572 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1573 RT5645_HP_SG_MASK |
1574 RT5645_HP_L_SMT_MASK |
1575 RT5645_HP_R_SMT_MASK,
1576 RT5645_HP_SG_DIS |
1577 RT5645_HP_L_SMT_DIS |
1578 RT5645_HP_R_SMT_DIS);
1579 /* headphone amp power down */
1580 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1581 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1582 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1583 RT5645_PWR_HA, 0);
1584 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1585 RT5645_DEPOP_MASK, 0);
1586 }
1319b2f6
OC		 1587 }
1588 }
1589}
1590
1591static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1592 struct snd_kcontrol *kcontrol, int event)
1593{
c5f596cb 1594 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1595 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1596
1597 switch (event) {
1598 case SND_SOC_DAPM_POST_PMU:
1599 hp_amp_power(codec, 1);
1600 /* headphone unmute sequence */
d12d6c4e 1601 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1602 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1603 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1604 RT5645_CP_FQ3_MASK,
1605 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1606 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1607 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1608 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1609 RT5645_MAMP_INT_REG2, 0xfc00);
1610 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1611 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1612 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1613 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1614 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1615 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1616 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1617 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1618 msleep(40);
1619 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1620 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1621 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1622 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
5c4ca99d 1623 }
1319b2f6
OC		 1624 break;
1625
1626 case SND_SOC_DAPM_PRE_PMD:
1627 /* headphone mute sequence */
d12d6c4e 1628 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1629 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1630 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1631 RT5645_CP_FQ3_MASK,
1632 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1633 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1634 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1635 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1636 RT5645_MAMP_INT_REG2, 0xfc00);
1637 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1638 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1639 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1640 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1641 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1642 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1643 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1644 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1645 msleep(30);
5c4ca99d 1646 }
1319b2f6
OC		 1647 hp_amp_power(codec, 0);
1648 break;
1649
1650 default:
1651 return 0;
1652 }
1653
1654 return 0;
1655}
1656
1657static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1658 struct snd_kcontrol *kcontrol, int event)
1659{
c5f596cb 1660 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1661
1662 switch (event) {
1663 case SND_SOC_DAPM_POST_PMU:
be77b38a 1664 rt5645_enable_hweq(codec);
1319b2f6
OC		 1665 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1666 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1667 RT5645_PWR_CLS_D_L,
1668 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1669 RT5645_PWR_CLS_D_L);
ca8457bb
BL		 1670 snd_soc_update_bits(codec, RT5645_GEN_CTRL3,
1671 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
1319b2f6
OC		 1672 break;
1673
1674 case SND_SOC_DAPM_PRE_PMD:
ca8457bb
BL		 1675 snd_soc_update_bits(codec, RT5645_GEN_CTRL3,
1676 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
be77b38a 1677 snd_soc_write(codec, RT5645_EQ_CTRL2, 0);
1319b2f6
OC		 1678 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1679 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1680 RT5645_PWR_CLS_D_L, 0);
1681 break;
1682
1683 default:
1684 return 0;
1685 }
1686
1687 return 0;
1688}
1689
1690static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1691 struct snd_kcontrol *kcontrol, int event)
1692{
c5f596cb 1693 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1694
1695 switch (event) {
1696 case SND_SOC_DAPM_POST_PMU:
1697 hp_amp_power(codec, 1);
1698 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1699 RT5645_PWR_LM, RT5645_PWR_LM);
1700 snd_soc_update_bits(codec, RT5645_LOUT1,
1701 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1702 break;
1703
1704 case SND_SOC_DAPM_PRE_PMD:
1705 snd_soc_update_bits(codec, RT5645_LOUT1,
1706 RT5645_L_MUTE | RT5645_R_MUTE,
1707 RT5645_L_MUTE | RT5645_R_MUTE);
1708 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1709 RT5645_PWR_LM, 0);
1710 hp_amp_power(codec, 0);
1711 break;
1712
1713 default:
1714 return 0;
1715 }
1716
1717 return 0;
1718}
1719
1720static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1721 struct snd_kcontrol *kcontrol, int event)
1722{
c5f596cb 1723 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1724
1725 switch (event) {
1726 case SND_SOC_DAPM_POST_PMU:
1727 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1728 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1729 break;
1730
1731 case SND_SOC_DAPM_PRE_PMD:
1732 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1733 RT5645_PWR_BST2_P, 0);
1734 break;
1735
1736 default:
1737 return 0;
1738 }
1739
1740 return 0;
1741}
1742
588cd850
OC		 1743static int rt5650_hp_event(struct snd_soc_dapm_widget *w,
1744 struct snd_kcontrol *k, int event)
1745{
1746 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1747 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1748
1749 switch (event) {
1750 case SND_SOC_DAPM_POST_PMU:
1751 if (rt5645->hp_on) {
1752 msleep(100);
1753 rt5645->hp_on = false;
1754 }
1755 break;
1756
1757 default:
1758 return 0;
1759 }
1760
1761 return 0;
1762}
1763
1319b2f6
OC		 1764static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1765 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1766 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1767 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1768 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1769
1770 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1771 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1772 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1773 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1774
9e268353
BL		 1775 /* ASRC */
1776 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1777 11, 0, NULL, 0),
1778 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1779 12, 0, NULL, 0),
1780 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1781 10, 0, NULL, 0),
1782 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1783 9, 0, NULL, 0),
1784 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1785 8, 0, NULL, 0),
1786 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1787 7, 0, NULL, 0),
1788 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1789 5, 0, NULL, 0),
1790 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1791 4, 0, NULL, 0),
1792 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1793 3, 0, NULL, 0),
1794 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1795 1, 0, NULL, 0),
1796 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1797 0, 0, NULL, 0),
1798
1319b2f6
OC		 1799 /* Input Side */
1800 /* micbias */
1801 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1802 RT5645_PWR_MB1_BIT, 0),
1803 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1804 RT5645_PWR_MB2_BIT, 0),
1805 /* Input Lines */
1806 SND_SOC_DAPM_INPUT("DMIC L1"),
1807 SND_SOC_DAPM_INPUT("DMIC R1"),
1808 SND_SOC_DAPM_INPUT("DMIC L2"),
1809 SND_SOC_DAPM_INPUT("DMIC R2"),
1810
1811 SND_SOC_DAPM_INPUT("IN1P"),
1812 SND_SOC_DAPM_INPUT("IN1N"),
1813 SND_SOC_DAPM_INPUT("IN2P"),
1814 SND_SOC_DAPM_INPUT("IN2N"),
1815
1816 SND_SOC_DAPM_INPUT("Haptic Generator"),
1817
1818 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1819 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1820 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1821 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1822 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1823 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1824 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1825 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1826 /* Boost */
1827 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1828 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1829 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1830 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1831 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1832 /* Input Volume */
1833 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1834 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1835 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1836 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1837 /* REC Mixer */
1838 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1839 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1840 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1841 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1842 /* ADCs */
1843 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1844 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1845
1846 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1847 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1848 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1849 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1850
1851 /* ADC Mux */
1852 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1853 &rt5645_sto1_dmic_mux),
1854 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1855 &rt5645_sto_adc2_mux),
1856 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1857 &rt5645_sto_adc2_mux),
1858 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1859 &rt5645_sto_adc1_mux),
1860 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1861 &rt5645_sto_adc1_mux),
1862 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1863 &rt5645_mono_dmic_l_mux),
1864 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1865 &rt5645_mono_dmic_r_mux),
1866 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1867 &rt5645_mono_adc_l2_mux),
1868 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1869 &rt5645_mono_adc_l1_mux),
1870 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1871 &rt5645_mono_adc_r1_mux),
1872 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1873 &rt5645_mono_adc_r2_mux),
1874 /* ADC Mixer */
1875
1876 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1877 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1319b2f6
OC		 1878 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1879 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1880 NULL, 0),
1881 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1882 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1883 NULL, 0),
1884 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1885 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1886 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1887 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1888 NULL, 0),
1889 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1890 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1891 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1892 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1893 NULL, 0),
1894
1895 /* ADC PGA */
1896 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1897 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1898 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1899 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1900 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1901 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1902 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1903 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1904 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1905 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1906
1907 /* IF1 2 Mux */
1319b2f6
OC		 1908 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1909 0, 0, &rt5645_if2_adc_in_mux),
1910
1911 /* Digital Interface */
1912 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1913 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
786aa09b 1914 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 1915 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1916 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
786aa09b 1917 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 1918 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1919 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1920 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1921 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1922 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1923 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1924 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1925 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1926 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1927
1928 /* Digital Interface Select */
1929 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1930 0, 0, &rt5645_vad_adc_mux),
1931
1932 /* Audio Interface */
1933 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1934 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1935 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1936 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1937
1938 /* Output Side */
1939 /* DAC mixer before sound effect */
1940 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1941 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1942 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1943 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1944
1945 /* DAC2 channel Mux */
1946 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1947 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1948 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1949 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1950 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1951 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1952
1953 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1954 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1955
1956 /* DAC Mixer */
1957 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1958 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1959 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1960 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1961 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1962 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1963 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1964 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1965 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1966 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1967 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1968 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1969 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1970 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1971 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1972 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1973 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1974 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1975
1976 /* DACs */
1977 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1978 0),
1979 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1980 0),
1981 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1982 0),
1983 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1984 0),
1985 /* OUT Mixer */
1986 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1987 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1988 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1989 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1990 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1991 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1992 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1993 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1994 /* Ouput Volume */
1995 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1996 &spk_l_vol_control),
1997 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1998 &spk_r_vol_control),
1999 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2000 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2001 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2002 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2003 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2004 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2005 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2006 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2007 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2008 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2009 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2010 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2011 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2012
2013 /* HPO/LOUT/Mono Mixer */
2014 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2015 ARRAY_SIZE(rt5645_spo_l_mix)),
2016 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2017 ARRAY_SIZE(rt5645_spo_r_mix)),
2018 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2019 ARRAY_SIZE(rt5645_hpo_mix)),
2020 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2021 ARRAY_SIZE(rt5645_lout_mix)),
2022
2023 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2024 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2025 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2026 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2027 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2028 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2029
2030 /* PDM */
2031 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2032 0, NULL, 0),
2033 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2034 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2035
2036 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2037 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2038
2039 /* Output Lines */
2040 SND_SOC_DAPM_OUTPUT("HPOL"),
2041 SND_SOC_DAPM_OUTPUT("HPOR"),
2042 SND_SOC_DAPM_OUTPUT("LOUTL"),
2043 SND_SOC_DAPM_OUTPUT("LOUTR"),
2044 SND_SOC_DAPM_OUTPUT("PDM1L"),
2045 SND_SOC_DAPM_OUTPUT("PDM1R"),
2046 SND_SOC_DAPM_OUTPUT("SPOL"),
2047 SND_SOC_DAPM_OUTPUT("SPOR"),
588cd850 2048 SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event),
1319b2f6
OC		 2049};
2050
83c09290
BL		 2051static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2052 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2053 &rt5645_if1_dac0_tdm_sel_mux),
2054 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2055 &rt5645_if1_dac1_tdm_sel_mux),
2056 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2057 &rt5645_if1_dac2_tdm_sel_mux),
2058 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2059 &rt5645_if1_dac3_tdm_sel_mux),
2060 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2061 0, 0, &rt5645_if1_adc_in_mux),
2062 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2063 0, 0, &rt5645_if1_adc1_in_mux),
2064 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2065 0, 0, &rt5645_if1_adc2_in_mux),
2066 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2067 0, 0, &rt5645_if1_adc3_in_mux),
1319b2f6
OC		 2068};
2069
5c4ca99d
BL		 2070static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2071 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2072 0, 0, &rt5650_a_dac1_l_mux),
2073 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2074 0, 0, &rt5650_a_dac1_r_mux),
2075 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2076 0, 0, &rt5650_a_dac2_l_mux),
2077 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2078 0, 0, &rt5650_a_dac2_r_mux),
851b81e8
MC		 2079
2080 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2081 0, 0, &rt5650_if1_adc1_in_mux),
2082 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2083 0, 0, &rt5650_if1_adc2_in_mux),
2084 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2085 0, 0, &rt5650_if1_adc3_in_mux),
2086 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2087 0, 0, &rt5650_if1_adc_in_mux),
2088
2089 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2090 &rt5650_if1_dac0_tdm_sel_mux),
2091 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2092 &rt5650_if1_dac1_tdm_sel_mux),
2093 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2094 &rt5650_if1_dac2_tdm_sel_mux),
2095 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2096 &rt5650_if1_dac3_tdm_sel_mux),
5c4ca99d
BL		 2097};
2098
1319b2f6 2099static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
9e268353 2100 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
9e268353
BL		 2101 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2102 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2103 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2104 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2105 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2106
2107 { "I2S1", NULL, "I2S1 ASRC" },
2108 { "I2S2", NULL, "I2S2 ASRC" },
2109
1319b2f6
OC		 2110 { "IN1P", NULL, "LDO2" },
2111 { "IN2P", NULL, "LDO2" },
2112
2113 { "DMIC1", NULL, "DMIC L1" },
2114 { "DMIC1", NULL, "DMIC R1" },
2115 { "DMIC2", NULL, "DMIC L2" },
2116 { "DMIC2", NULL, "DMIC R2" },
2117
2118 { "BST1", NULL, "IN1P" },
2119 { "BST1", NULL, "IN1N" },
2120 { "BST1", NULL, "JD Power" },
2121 { "BST1", NULL, "Mic Det Power" },
2122 { "BST2", NULL, "IN2P" },
2123 { "BST2", NULL, "IN2N" },
2124
2125 { "INL VOL", NULL, "IN2P" },
2126 { "INR VOL", NULL, "IN2N" },
2127
2128 { "RECMIXL", "HPOL Switch", "HPOL" },
2129 { "RECMIXL", "INL Switch", "INL VOL" },
2130 { "RECMIXL", "BST2 Switch", "BST2" },
2131 { "RECMIXL", "BST1 Switch", "BST1" },
2132 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2133
2134 { "RECMIXR", "HPOR Switch", "HPOR" },
2135 { "RECMIXR", "INR Switch", "INR VOL" },
2136 { "RECMIXR", "BST2 Switch", "BST2" },
2137 { "RECMIXR", "BST1 Switch", "BST1" },
2138 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2139
2140 { "ADC L", NULL, "RECMIXL" },
2141 { "ADC L", NULL, "ADC L power" },
2142 { "ADC R", NULL, "RECMIXR" },
2143 { "ADC R", NULL, "ADC R power" },
2144
2145 {"DMIC L1", NULL, "DMIC CLK"},
2146 {"DMIC L1", NULL, "DMIC1 Power"},
2147 {"DMIC R1", NULL, "DMIC CLK"},
2148 {"DMIC R1", NULL, "DMIC1 Power"},
2149 {"DMIC L2", NULL, "DMIC CLK"},
2150 {"DMIC L2", NULL, "DMIC2 Power"},
2151 {"DMIC R2", NULL, "DMIC CLK"},
2152 {"DMIC R2", NULL, "DMIC2 Power"},
2153
2154 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2155 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
9e268353 2156 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1319b2f6
OC		 2157
2158 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2159 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
9e268353 2160 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1319b2f6
OC		 2161
2162 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2163 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
9e268353 2164 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1319b2f6
OC		 2165
2166 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2167 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2168 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2169 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2170
2171 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2172 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2173 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2174 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2175
2176 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2177 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2178 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2179 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2180
2181 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2182 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2183 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2184 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2185
2186 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2187 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2188 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2189 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2190
2191 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2192 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2193 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2194
2195 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2196 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2197 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2198
2199 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2200 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2201 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2202 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2203
2204 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2205 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2206 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2207 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2208
2209 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2210 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2211 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2212
2213 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2214 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2215 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2216 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2217 { "VAD_ADC", NULL, "VAD ADC Mux" },
2218
1319b2f6
OC		 2219 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2220 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2221 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2222
2223 { "IF1 ADC", NULL, "I2S1" },
1319b2f6
OC		 2224 { "IF2 ADC", NULL, "I2S2" },
2225 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2226
1319b2f6
OC		 2227 { "AIF2TX", NULL, "IF2 ADC" },
2228
21ab3f2b 2229 { "IF1 DAC0", NULL, "AIF1RX" },
1319b2f6
OC		 2230 { "IF1 DAC1", NULL, "AIF1RX" },
2231 { "IF1 DAC2", NULL, "AIF1RX" },
21ab3f2b 2232 { "IF1 DAC3", NULL, "AIF1RX" },
1319b2f6
OC		 2233 { "IF2 DAC", NULL, "AIF2RX" },
2234
21ab3f2b 2235 { "IF1 DAC0", NULL, "I2S1" },
1319b2f6
OC		 2236 { "IF1 DAC1", NULL, "I2S1" },
2237 { "IF1 DAC2", NULL, "I2S1" },
21ab3f2b 2238 { "IF1 DAC3", NULL, "I2S1" },
1319b2f6
OC		 2239 { "IF2 DAC", NULL, "I2S2" },
2240
1319b2f6
OC		 2241 { "IF2 DAC L", NULL, "IF2 DAC" },
2242 { "IF2 DAC R", NULL, "IF2 DAC" },
2243
1319b2f6 2244 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1319b2f6
OC		 2245 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2246
2247 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2248 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2249 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2250 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2251 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2252 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2253
1319b2f6
OC		 2254 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2255 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2256 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2257 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2258 { "DAC L2 Volume", NULL, "dac mono left filter" },
2259
1319b2f6
OC		 2260 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2261 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2262 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2263 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2264 { "DAC R2 Volume", NULL, "dac mono right filter" },
2265
2266 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2267 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2268 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2269 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2270 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2271 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2272 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2273 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2274
2275 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2276 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2277 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2278 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2279 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2280 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2281 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2282 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2283
2284 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2285 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2286 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2287 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2288 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2289 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2290
1319b2f6 2291 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2292 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2293 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6
OC		 2294 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2295
2296 { "SPK MIXL", "BST1 Switch", "BST1" },
2297 { "SPK MIXL", "INL Switch", "INL VOL" },
2298 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2299 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2300 { "SPK MIXR", "BST2 Switch", "BST2" },
2301 { "SPK MIXR", "INR Switch", "INR VOL" },
2302 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2303 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2304
2305 { "OUT MIXL", "BST1 Switch", "BST1" },
2306 { "OUT MIXL", "INL Switch", "INL VOL" },
2307 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2308 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2309
2310 { "OUT MIXR", "BST2 Switch", "BST2" },
2311 { "OUT MIXR", "INR Switch", "INR VOL" },
2312 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2313 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2314
2315 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2316 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2317 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2318 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2319 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2320 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2321 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2322 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2323 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2324 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2325
2326 { "DAC 2", NULL, "DAC L2" },
2327 { "DAC 2", NULL, "DAC R2" },
2328 { "DAC 1", NULL, "DAC L1" },
2329 { "DAC 1", NULL, "DAC R1" },
2330 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2331 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2332 { "HPOVOL", NULL, "HPOVOL L" },
2333 { "HPOVOL", NULL, "HPOVOL R" },
2334 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2335 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2336
2337 { "SPKVOL L", "Switch", "SPK MIXL" },
2338 { "SPKVOL R", "Switch", "SPK MIXR" },
2339
2340 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2341 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2342 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2343 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2344 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2345 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2346
2347 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2348 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2349 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2350 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2351
2352 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2353 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2354 { "PDM1 L Mux", NULL, "PDM1 Power" },
2355 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2356 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2357 { "PDM1 R Mux", NULL, "PDM1 Power" },
2358
2359 { "HP amp", NULL, "HPO MIX" },
2360 { "HP amp", NULL, "JD Power" },
2361 { "HP amp", NULL, "Mic Det Power" },
2362 { "HP amp", NULL, "LDO2" },
2363 { "HPOL", NULL, "HP amp" },
2364 { "HPOR", NULL, "HP amp" },
2365
2366 { "LOUT amp", NULL, "LOUT MIX" },
2367 { "LOUTL", NULL, "LOUT amp" },
2368 { "LOUTR", NULL, "LOUT amp" },
2369
2370 { "PDM1 L", "Switch", "PDM1 L Mux" },
2371 { "PDM1 R", "Switch", "PDM1 R Mux" },
2372
2373 { "PDM1L", NULL, "PDM1 L" },
2374 { "PDM1R", NULL, "PDM1 R" },
2375
2376 { "SPK amp", NULL, "SPOL MIX" },
2377 { "SPK amp", NULL, "SPOR MIX" },
2378 { "SPOL", NULL, "SPK amp" },
2379 { "SPOR", NULL, "SPK amp" },
2380};
2381
5c4ca99d
BL		 2382static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2383 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2384 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2385 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2386 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2387
2388 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2389 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2390 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2391 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2392
2393 { "DAC L1", NULL, "A DAC1 L Mux" },
2394 { "DAC R1", NULL, "A DAC1 R Mux" },
2395 { "DAC L2", NULL, "A DAC2 L Mux" },
2396 { "DAC R2", NULL, "A DAC2 R Mux" },
21ab3f2b
BL		 2397
2398 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2399 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2400 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2401 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2402
2403 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2404 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2405 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2406 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2407
2408 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2409 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2410 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2411 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2412
2413 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2414 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2415 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2416
2417 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2418 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2419 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2420 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2421 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2422 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2423
2424 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2425 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2426 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2427 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2428 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2429 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2430
2431 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2432 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2433 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2434 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2435 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2436 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2437
2438 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2439 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2440 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2441 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2442 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2443 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2444 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2445
2446 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2447 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2448 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2449 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2450
2451 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2452 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2453 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2454 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2455
2456 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2457 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2458 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2459 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2460
2461 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2462 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2463 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2464 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2465
2466 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2467 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2468
2469 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2470 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2471};
2472
2473static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2474 { "DAC L1", NULL, "Stereo DAC MIXL" },
2475 { "DAC R1", NULL, "Stereo DAC MIXR" },
2476 { "DAC L2", NULL, "Mono DAC MIXL" },
2477 { "DAC R2", NULL, "Mono DAC MIXR" },
21ab3f2b
BL		 2478
2479 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2480 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2481 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2482 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2483
2484 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2485 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2486 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2487 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2488
2489 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2490 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2491 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2492 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2493
2494 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2495 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2496 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2497
2498 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2499 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2500 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2501 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2502 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2503
2504 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2505 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2506 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2507 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2508
2509 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2510 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2511 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2512 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2513
2514 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2515 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2516 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2517 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2518
2519 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2520 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2521 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2522 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2523
2524 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2525 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2526
2527 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2528 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2529};
2530
1319b2f6
OC		 2531static int rt5645_hw_params(struct snd_pcm_substream *substream,
2532 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2533{
2534 struct snd_soc_codec *codec = dai->codec;
2535 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736 2536 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
1319b2f6
OC		 2537 int pre_div, bclk_ms, frame_size;
2538
2539 rt5645->lrck[dai->id] = params_rate(params);
d92950e7 2540 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1319b2f6
OC		 2541 if (pre_div < 0) {
2542 dev_err(codec->dev, "Unsupported clock setting\n");
2543 return -EINVAL;
2544 }
2545 frame_size = snd_soc_params_to_frame_size(params);
2546 if (frame_size < 0) {
2547 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2548 return -EINVAL;
2549 }
57bf2736
BL		 2550
2551 switch (rt5645->codec_type) {
2552 case CODEC_TYPE_RT5650:
2553 dl_sft = 4;
2554 break;
2555 default:
2556 dl_sft = 2;
2557 break;
2558 }
2559
1319b2f6
OC		 2560 bclk_ms = frame_size > 32;
2561 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2562
2563 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2564 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2565 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2566 bclk_ms, pre_div, dai->id);
2567
2568 switch (params_width(params)) {
2569 case 16:
2570 break;
2571 case 20:
57bf2736 2572 val_len = 0x1;
1319b2f6
OC		 2573 break;
2574 case 24:
57bf2736 2575 val_len = 0x2;
1319b2f6
OC		 2576 break;
2577 case 8:
57bf2736 2578 val_len = 0x3;
1319b2f6
OC		 2579 break;
2580 default:
2581 return -EINVAL;
2582 }
2583
2584 switch (dai->id) {
2585 case RT5645_AIF1:
33de3d54
BL		 2586 mask_clk = RT5645_I2S_PD1_MASK;
2587 val_clk = pre_div << RT5645_I2S_PD1_SFT;
1319b2f6 2588 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2589 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2590 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2591 break;
2592 case RT5645_AIF2:
2593 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2594 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2595 pre_div << RT5645_I2S_PD2_SFT;
2596 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2597 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2598 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2599 break;
2600 default:
2601 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2602 return -EINVAL;
2603 }
2604
2605 return 0;
2606}
2607
2608static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2609{
2610 struct snd_soc_codec *codec = dai->codec;
2611 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736
BL		 2612 unsigned int reg_val = 0, pol_sft;
2613
2614 switch (rt5645->codec_type) {
2615 case CODEC_TYPE_RT5650:
2616 pol_sft = 8;
2617 break;
2618 default:
2619 pol_sft = 7;
2620 break;
2621 }
1319b2f6
OC		 2622
2623 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2624 case SND_SOC_DAIFMT_CBM_CFM:
2625 rt5645->master[dai->id] = 1;
2626 break;
2627 case SND_SOC_DAIFMT_CBS_CFS:
2628 reg_val |= RT5645_I2S_MS_S;
2629 rt5645->master[dai->id] = 0;
2630 break;
2631 default:
2632 return -EINVAL;
2633 }
2634
2635 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2636 case SND_SOC_DAIFMT_NB_NF:
2637 break;
2638 case SND_SOC_DAIFMT_IB_NF:
57bf2736 2639 reg_val |= (1 << pol_sft);
1319b2f6
OC		 2640 break;
2641 default:
2642 return -EINVAL;
2643 }
2644
2645 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2646 case SND_SOC_DAIFMT_I2S:
2647 break;
2648 case SND_SOC_DAIFMT_LEFT_J:
2649 reg_val |= RT5645_I2S_DF_LEFT;
2650 break;
2651 case SND_SOC_DAIFMT_DSP_A:
2652 reg_val |= RT5645_I2S_DF_PCM_A;
2653 break;
2654 case SND_SOC_DAIFMT_DSP_B:
2655 reg_val |= RT5645_I2S_DF_PCM_B;
2656 break;
2657 default:
2658 return -EINVAL;
2659 }
2660 switch (dai->id) {
2661 case RT5645_AIF1:
2662 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2663 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2664 RT5645_I2S_DF_MASK, reg_val);
2665 break;
8c325704
AL		 2666 case RT5645_AIF2:
2667 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2668 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2669 RT5645_I2S_DF_MASK, reg_val);
2670 break;
2671 default:
2672 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2673 return -EINVAL;
2674 }
2675 return 0;
2676}
2677
2678static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2679 int clk_id, unsigned int freq, int dir)
2680{
2681 struct snd_soc_codec *codec = dai->codec;
2682 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2683 unsigned int reg_val = 0;
2684
2685 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2686 return 0;
2687
2688 switch (clk_id) {
2689 case RT5645_SCLK_S_MCLK:
2690 reg_val |= RT5645_SCLK_SRC_MCLK;
2691 break;
2692 case RT5645_SCLK_S_PLL1:
2693 reg_val |= RT5645_SCLK_SRC_PLL1;
2694 break;
2695 case RT5645_SCLK_S_RCCLK:
2696 reg_val |= RT5645_SCLK_SRC_RCCLK;
2697 break;
2698 default:
2699 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2700 return -EINVAL;
2701 }
2702 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2703 RT5645_SCLK_SRC_MASK, reg_val);
2704 rt5645->sysclk = freq;
2705 rt5645->sysclk_src = clk_id;
2706
2707 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2708
2709 return 0;
2710}
2711
1319b2f6
OC		 2712static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2713 unsigned int freq_in, unsigned int freq_out)
2714{
2715 struct snd_soc_codec *codec = dai->codec;
2716 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
71c7a2d6 2717 struct rl6231_pll_code pll_code;
1319b2f6
OC		 2718 int ret;
2719
2720 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2721 freq_out == rt5645->pll_out)
2722 return 0;
2723
2724 if (!freq_in || !freq_out) {
2725 dev_dbg(codec->dev, "PLL disabled\n");
2726
2727 rt5645->pll_in = 0;
2728 rt5645->pll_out = 0;
2729 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2730 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2731 return 0;
2732 }
2733
2734 switch (source) {
2735 case RT5645_PLL1_S_MCLK:
2736 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2737 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2738 break;
2739 case RT5645_PLL1_S_BCLK1:
2740 case RT5645_PLL1_S_BCLK2:
2741 switch (dai->id) {
2742 case RT5645_AIF1:
2743 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2744 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2745 break;
2746 case RT5645_AIF2:
2747 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2748 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2749 break;
2750 default:
2751 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2752 return -EINVAL;
2753 }
2754 break;
2755 default:
2756 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2757 return -EINVAL;
2758 }
2759
71c7a2d6 2760 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1319b2f6
OC		 2761 if (ret < 0) {
2762 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2763 return ret;
2764 }
2765
2766 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2767 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2768 pll_code.n_code, pll_code.k_code);
2769
2770 snd_soc_write(codec, RT5645_PLL_CTRL1,
2771 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2772 snd_soc_write(codec, RT5645_PLL_CTRL2,
2773 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2774 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2775
2776 rt5645->pll_in = freq_in;
2777 rt5645->pll_out = freq_out;
2778 rt5645->pll_src = source;
2779
2780 return 0;
2781}
2782
2783static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2784 unsigned int rx_mask, int slots, int slot_width)
2785{
2786 struct snd_soc_codec *codec = dai->codec;
42ce5b8a
BL		 2787 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2788 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2789 unsigned int mask, val = 0;
2790
2791 switch (rt5645->codec_type) {
2792 case CODEC_TYPE_RT5650:
2793 en_sft = 15;
2794 i_slot_sft = 10;
2795 o_slot_sft = 8;
2796 i_width_sht = 6;
2797 o_width_sht = 4;
2798 mask = 0x8ff0;
2799 break;
2800 default:
2801 en_sft = 14;
2802 i_slot_sft = o_slot_sft = 12;
2803 i_width_sht = o_width_sht = 10;
2804 mask = 0x7c00;
2805 break;
2806 }
850577db 2807 if (rx_mask || tx_mask) {
42ce5b8a
BL		 2808 val |= (1 << en_sft);
2809 if (rt5645->codec_type == CODEC_TYPE_RT5645)
2810 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2811 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
850577db 2812 }
1319b2f6
OC		 2813
2814 switch (slots) {
2815 case 4:
42ce5b8a 2816 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
1319b2f6
OC		 2817 break;
2818 case 6:
42ce5b8a 2819 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
1319b2f6
OC		 2820 break;
2821 case 8:
42ce5b8a 2822 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
1319b2f6
OC		 2823 break;
2824 case 2:
2825 default:
2826 break;
2827 }
2828
2829 switch (slot_width) {
2830 case 20:
42ce5b8a 2831 val |= (1 << i_width_sht) | (1 << o_width_sht);
1319b2f6
OC		 2832 break;
2833 case 24:
42ce5b8a 2834 val |= (2 << i_width_sht) | (2 << o_width_sht);
1319b2f6
OC		 2835 break;
2836 case 32:
42ce5b8a 2837 val |= (3 << i_width_sht) | (3 << o_width_sht);
1319b2f6
OC		 2838 break;
2839 case 16:
2840 default:
2841 break;
2842 }
2843
42ce5b8a 2844 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
1319b2f6
OC		 2845
2846 return 0;
2847}
2848
2849static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2850 enum snd_soc_bias_level level)
2851{
6e747d53
BL		 2852 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2853
1319b2f6 2854 switch (level) {
0b2e4959 2855 case SND_SOC_BIAS_PREPARE:
e2ada818 2856 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
1319b2f6
OC		 2857 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2858 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2859 RT5645_PWR_BG | RT5645_PWR_VREF2,
2860 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2861 RT5645_PWR_BG | RT5645_PWR_VREF2);
2862 mdelay(10);
2863 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2864 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2865 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2866 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2867 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2868 }
2869 break;
2870
0b2e4959
BL		 2871 case SND_SOC_BIAS_STANDBY:
2872 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2873 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2874 RT5645_PWR_BG | RT5645_PWR_VREF2,
2875 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2876 RT5645_PWR_BG | RT5645_PWR_VREF2);
2877 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2878 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2879 RT5645_PWR_FV1 | RT5645_PWR_FV2);
c962d03b
OC		 2880 if (rt5645->en_button_func &&
2881 snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
2882 queue_delayed_work(system_power_efficient_wq,
2883 &rt5645->jack_detect_work, msecs_to_jiffies(0));
0b2e4959
BL		 2884 break;
2885
1319b2f6
OC		 2886 case SND_SOC_BIAS_OFF:
2887 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
6e747d53
BL		 2888 if (!rt5645->en_button_func)
2889 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2890 RT5645_DIG_GATE_CTRL, 0);
0b2e4959
BL		 2891 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2892 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2893 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2894 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
1319b2f6
OC		 2895 break;
2896
2897 default:
2898 break;
2899 }
1319b2f6
OC		 2900
2901 return 0;
2902}
2903
6e747d53
BL		 2904static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
2905 bool enable)
f3fa1bbd 2906{
e2ada818 2907 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
f3fa1bbd 2908
6e747d53 2909 if (enable) {
a4e3c5fa
NB		 2910 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
2911 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
2912 snd_soc_dapm_sync(dapm);
22f5d9f8 2913
6e747d53
BL		 2914 snd_soc_update_bits(codec,
2915 RT5645_INT_IRQ_ST, 0x8, 0x8);
2916 snd_soc_update_bits(codec,
2917 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
2918 snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2919 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
2920 snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
2921 } else {
2922 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
2923 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
22f5d9f8 2924
a4e3c5fa
NB		 2925 snd_soc_dapm_disable_pin(dapm, "ADC L power");
2926 snd_soc_dapm_disable_pin(dapm, "ADC R power");
2927 snd_soc_dapm_sync(dapm);
75945896 2928 }
6e747d53 2929}
f3fa1bbd 2930
6e747d53
BL		 2931static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
2932{
e2ada818 2933 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
6e747d53
BL		 2934 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2935 unsigned int val;
f3fa1bbd 2936
6e747d53 2937 if (jack_insert) {
05a9b46a
JL		 2938 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2939
b14c9174
NB		 2940 /* for jack type detect */
2941 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
2942 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
2943 snd_soc_dapm_sync(dapm);
2944 if (!dapm->card->instantiated) {
6e747d53
BL		 2945 /* Power up necessary bits for JD if dapm is
2946 not ready yet */
05a9b46a
JL		 2947 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
2948 RT5645_PWR_MB | RT5645_PWR_VREF2,
2949 RT5645_PWR_MB | RT5645_PWR_VREF2);
2950 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
6e747d53 2951 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
05a9b46a 2952 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
6e747d53
BL		 2953 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
2954 }
f3fa1bbd 2955
05a9b46a 2956 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
f2988afe
OC		 2957 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
2958 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
2959 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
2960 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
05a9b46a 2961 msleep(100);
f2988afe
OC		 2962 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
2963 RT5645_CBJ_MN_JD, 0);
05a9b46a 2964
8db7f56d 2965 msleep(600);
05a9b46a
JL		 2966 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
2967 val &= 0x7;
f3fa1bbd
OC		 2968 dev_dbg(codec->dev, "val = %d\n", val);
2969
6e747d53
BL		 2970 if (val == 1 || val == 2) {
2971 rt5645->jack_type = SND_JACK_HEADSET;
2972 if (rt5645->en_button_func) {
6e747d53
BL		 2973 rt5645_enable_push_button_irq(codec, true);
2974 }
2975 } else {
b14c9174
NB		 2976 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
2977 snd_soc_dapm_sync(dapm);
6e747d53
BL		 2978 rt5645->jack_type = SND_JACK_HEADPHONE;
2979 }
917536ae
JL		 2980 if (rt5645->pdata.jd_invert)
2981 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
2982 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
6e747d53
BL		 2983 } else { /* jack out */
2984 rt5645->jack_type = 0;
a4e3c5fa 2985
fce97b4d
OC		 2986 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
2987 RT5645_L_MUTE | RT5645_R_MUTE,
2988 RT5645_L_MUTE | RT5645_R_MUTE);
f2988afe
OC		 2989 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
2990 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
2991 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
2992 RT5645_CBJ_BST1_EN, 0);
8db7f56d 2993
6e747d53
BL		 2994 if (rt5645->en_button_func)
2995 rt5645_enable_push_button_irq(codec, false);
a4e3c5fa
NB		 2996
2997 if (rt5645->pdata.jd_mode == 0)
2998 snd_soc_dapm_disable_pin(dapm, "LDO2");
2999 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3000 snd_soc_dapm_sync(dapm);
917536ae
JL		 3001 if (rt5645->pdata.jd_invert)
3002 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3003 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
f3fa1bbd
OC		 3004 }
3005
6e747d53 3006 return rt5645->jack_type;
f3fa1bbd
OC		 3007}
3008
f312bc59
NB		 3009static int rt5645_button_detect(struct snd_soc_codec *codec)
3010{
3011 int btn_type, val;
3012
3013 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
3014 pr_debug("val=0x%x\n", val);
3015 btn_type = val & 0xfff0;
3016 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
3017
3018 return btn_type;
3019}
3020
345b0f50 3021static irqreturn_t rt5645_irq(int irq, void *data);
d5660422 3022
f3fa1bbd 3023int rt5645_set_jack_detect(struct snd_soc_codec *codec,
6e747d53
BL		 3024 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3025 struct snd_soc_jack *btn_jack)
f3fa1bbd
OC		 3026{
3027 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3028
471f208a
BL		 3029 rt5645->hp_jack = hp_jack;
3030 rt5645->mic_jack = mic_jack;
6e747d53
BL		 3031 rt5645->btn_jack = btn_jack;
3032 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3033 rt5645->en_button_func = true;
3034 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3035 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
6e747d53
BL		 3036 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3037 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3038 }
345b0f50 3039 rt5645_irq(0, rt5645);
f3fa1bbd
OC		 3040
3041 return 0;
3042}
3043EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3044
cd6e82b8
OC		 3045static void rt5645_jack_detect_work(struct work_struct *work)
3046{
3047 struct rt5645_priv *rt5645 =
3048 container_of(work, struct rt5645_priv, jack_detect_work.work);
6e747d53
BL		 3049 int val, btn_type, gpio_state = 0, report = 0;
3050
f2a5ded3 3051 if (!rt5645->codec)
f136dce4 3052 return;
f2a5ded3 3053
6e747d53
BL		 3054 switch (rt5645->pdata.jd_mode) {
3055 case 0: /* Not using rt5645 JD */
0b0cefc8
OC		 3056 if (rt5645->gpiod_hp_det) {
3057 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3058 dev_dbg(rt5645->codec->dev, "gpio_state = %d\n",
3059 gpio_state);
3060 report = rt5645_jack_detect(rt5645->codec, gpio_state);
6e747d53
BL		 3061 }
3062 snd_soc_jack_report(rt5645->hp_jack,
3063 report, SND_JACK_HEADPHONE);
3064 snd_soc_jack_report(rt5645->mic_jack,
3065 report, SND_JACK_MICROPHONE);
f312bc59 3066 return;
6e747d53
BL		 3067 case 1: /* 2 port */
3068 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070;
3069 break;
3070 default: /* 1 port */
3071 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020;
3072 break;
3073
3074 }
3075
3076 switch (val) {
3077 /* jack in */
3078 case 0x30: /* 2 port */
3079 case 0x0: /* 1 port or 2 port */
3080 if (rt5645->jack_type == 0) {
3081 report = rt5645_jack_detect(rt5645->codec, 1);
3082 /* for push button and jack out */
3083 break;
3084 }
3085 btn_type = 0;
3086 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
3087 /* button pressed */
3088 report = SND_JACK_HEADSET;
3089 btn_type = rt5645_button_detect(rt5645->codec);
3090 /* rt5650 can report three kinds of button behavior,
3091 one click, double click and hold. However,
3092 currently we will report button pressed/released
3093 event. So all the three button behaviors are
3094 treated as button pressed. */
3095 switch (btn_type) {
3096 case 0x8000:
3097 case 0x4000:
3098 case 0x2000:
3099 report |= SND_JACK_BTN_0;
3100 break;
3101 case 0x1000:
3102 case 0x0800:
3103 case 0x0400:
3104 report |= SND_JACK_BTN_1;
3105 break;
3106 case 0x0200:
3107 case 0x0100:
3108 case 0x0080:
3109 report |= SND_JACK_BTN_2;
3110 break;
3111 case 0x0040:
3112 case 0x0020:
3113 case 0x0010:
3114 report |= SND_JACK_BTN_3;
3115 break;
3116 case 0x0000: /* unpressed */
3117 break;
3118 default:
3119 dev_err(rt5645->codec->dev,
3120 "Unexpected button code 0x%04x\n",
3121 btn_type);
3122 break;
3123 }
3124 }
3125 if (btn_type == 0)/* button release */
3126 report = rt5645->jack_type;
3127
3128 break;
3129 /* jack out */
3130 case 0x70: /* 2 port */
3131 case 0x10: /* 2 port */
3132 case 0x20: /* 1 port */
3133 report = 0;
3134 snd_soc_update_bits(rt5645->codec,
3135 RT5645_INT_IRQ_ST, 0x1, 0x0);
3136 rt5645_jack_detect(rt5645->codec, 0);
3137 break;
3138 default:
3139 break;
3140 }
3141
3142 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3143 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3144 if (rt5645->en_button_func)
3145 snd_soc_jack_report(rt5645->btn_jack,
e0b5d906
BL		 3146 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3147 SND_JACK_BTN_2 | SND_JACK_BTN_3);
f312bc59 3148}
6e747d53 3149
7099ee85
OC		 3150static void rt5645_rcclock_work(struct work_struct *work)
3151{
3152 struct rt5645_priv *rt5645 =
3153 container_of(work, struct rt5645_priv, rcclock_work.work);
3154
3155 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3156 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3157}
3158
f312bc59
NB		 3159static irqreturn_t rt5645_irq(int irq, void *data)
3160{
3161 struct rt5645_priv *rt5645 = data;
3162
3163 queue_delayed_work(system_power_efficient_wq,
3164 &rt5645->jack_detect_work, msecs_to_jiffies(250));
6e747d53 3165
f312bc59 3166 return IRQ_HANDLED;
6e747d53
BL		 3167}
3168
1319b2f6
OC		 3169static int rt5645_probe(struct snd_soc_codec *codec)
3170{
e2ada818 3171 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1319b2f6
OC		 3172 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3173
3174 rt5645->codec = codec;
3175
5c4ca99d
BL		 3176 switch (rt5645->codec_type) {
3177 case CODEC_TYPE_RT5645:
f2a76385 3178 snd_soc_dapm_new_controls(dapm,
83c09290
BL		 3179 rt5645_specific_dapm_widgets,
3180 ARRAY_SIZE(rt5645_specific_dapm_widgets));
e2ada818 3181 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3182 rt5645_specific_dapm_routes,
3183 ARRAY_SIZE(rt5645_specific_dapm_routes));
3184 break;
3185 case CODEC_TYPE_RT5650:
e2ada818 3186 snd_soc_dapm_new_controls(dapm,
5c4ca99d
BL		 3187 rt5650_specific_dapm_widgets,
3188 ARRAY_SIZE(rt5650_specific_dapm_widgets));
e2ada818 3189 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3190 rt5650_specific_dapm_routes,
3191 ARRAY_SIZE(rt5650_specific_dapm_routes));
3192 break;
3193 }
3194
bd1204cb 3195 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
1319b2f6 3196
bb656add 3197 /* for JD function */
ac4fc3ee 3198 if (rt5645->pdata.jd_mode) {
e2ada818
LPC		 3199 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3200 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3201 snd_soc_dapm_sync(dapm);
bb656add
BL		 3202 }
3203
be77b38a
OC		 3204 rt5645->eq_param = devm_kzalloc(codec->dev,
3205 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s), GFP_KERNEL);
3206
1319b2f6
OC		 3207 return 0;
3208}
3209
3210static int rt5645_remove(struct snd_soc_codec *codec)
3211{
3212 rt5645_reset(codec);
3213 return 0;
3214}
3215
3216#ifdef CONFIG_PM
3217static int rt5645_suspend(struct snd_soc_codec *codec)
3218{
3219 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3220
3221 regcache_cache_only(rt5645->regmap, true);
3222 regcache_mark_dirty(rt5645->regmap);
3223
3224 return 0;
3225}
3226
3227static int rt5645_resume(struct snd_soc_codec *codec)
3228{
3229 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3230
3231 regcache_cache_only(rt5645->regmap, false);
0f776efd 3232 regcache_sync(rt5645->regmap);
1319b2f6
OC		 3233
3234 return 0;
3235}
3236#else
3237#define rt5645_suspend NULL
3238#define rt5645_resume NULL
3239#endif
3240
3241#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3242#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3243 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3244
64793047 3245static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
1319b2f6
OC		 3246 .hw_params = rt5645_hw_params,
3247 .set_fmt = rt5645_set_dai_fmt,
3248 .set_sysclk = rt5645_set_dai_sysclk,
3249 .set_tdm_slot = rt5645_set_tdm_slot,
3250 .set_pll = rt5645_set_dai_pll,
3251};
3252
9e22f782 3253static struct snd_soc_dai_driver rt5645_dai[] = {
1319b2f6
OC		 3254 {
3255 .name = "rt5645-aif1",
3256 .id = RT5645_AIF1,
3257 .playback = {
3258 .stream_name = "AIF1 Playback",
3259 .channels_min = 1,
3260 .channels_max = 2,
3261 .rates = RT5645_STEREO_RATES,
3262 .formats = RT5645_FORMATS,
3263 },
3264 .capture = {
3265 .stream_name = "AIF1 Capture",
3266 .channels_min = 1,
fbe039bb 3267 .channels_max = 4,
1319b2f6
OC		 3268 .rates = RT5645_STEREO_RATES,
3269 .formats = RT5645_FORMATS,
3270 },
3271 .ops = &rt5645_aif_dai_ops,
3272 },
3273 {
3274 .name = "rt5645-aif2",
3275 .id = RT5645_AIF2,
3276 .playback = {
3277 .stream_name = "AIF2 Playback",
3278 .channels_min = 1,
3279 .channels_max = 2,
3280 .rates = RT5645_STEREO_RATES,
3281 .formats = RT5645_FORMATS,
3282 },
3283 .capture = {
3284 .stream_name = "AIF2 Capture",
3285 .channels_min = 1,
3286 .channels_max = 2,
3287 .rates = RT5645_STEREO_RATES,
3288 .formats = RT5645_FORMATS,
3289 },
3290 .ops = &rt5645_aif_dai_ops,
3291 },
3292};
3293
3294static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
3295 .probe = rt5645_probe,
3296 .remove = rt5645_remove,
3297 .suspend = rt5645_suspend,
3298 .resume = rt5645_resume,
3299 .set_bias_level = rt5645_set_bias_level,
3300 .idle_bias_off = true,
3301 .controls = rt5645_snd_controls,
3302 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3303 .dapm_widgets = rt5645_dapm_widgets,
3304 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3305 .dapm_routes = rt5645_dapm_routes,
3306 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3307};
3308
3309static const struct regmap_config rt5645_regmap = {
3310 .reg_bits = 8,
3311 .val_bits = 16,
afefc128 3312 .use_single_rw = true,
1319b2f6
OC		 3313 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3314 RT5645_PR_SPACING),
3315 .volatile_reg = rt5645_volatile_register,
3316 .readable_reg = rt5645_readable_register,
3317
3318 .cache_type = REGCACHE_RBTREE,
3319 .reg_defaults = rt5645_reg,
3320 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3321 .ranges = rt5645_ranges,
3322 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3323};
3324
3325static const struct i2c_device_id rt5645_i2c_id[] = {
3326 { "rt5645", 0 },
5c4ca99d 3327 { "rt5650", 0 },
1319b2f6
OC		 3328 { }
3329};
3330MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3331
3168c201
FY		 3332#ifdef CONFIG_ACPI
3333static struct acpi_device_id rt5645_acpi_match[] = {
3334 { "10EC5645", 0 },
3335 { "10EC5650", 0 },
3336 {},
3337};
3338MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3339#endif
3340
78c34fd4
FY		 3341static struct rt5645_platform_data *rt5645_pdata;
3342
3343static struct rt5645_platform_data strago_platform_data = {
ac4fc3ee 3344 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
78c34fd4 3345 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
78c34fd4
FY		 3346 .jd_mode = 3,
3347};
3348
3349static int strago_quirk_cb(const struct dmi_system_id *id)
3350{
3351 rt5645_pdata = &strago_platform_data;
3352
3353 return 1;
3354}
3355
0bc7d10c 3356static const struct dmi_system_id dmi_platform_intel_braswell[] = {
78c34fd4
FY		 3357 {
3358 .ident = "Intel Strago",
3359 .callback = strago_quirk_cb,
3360 .matches = {
3361 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3362 },
3363 },
c1713485
OC		 3364 {
3365 .ident = "Google Celes",
3366 .callback = strago_quirk_cb,
3367 .matches = {
3368 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
3369 },
3370 },
721b51fc
JL		 3371 {
3372 .ident = "Google Ultima",
3373 .callback = strago_quirk_cb,
3374 .matches = {
3375 DMI_MATCH(DMI_PRODUCT_NAME, "Ultima"),
3376 },
3377 },
942e4a30
JL		 3378 {
3379 .ident = "Google Reks",
3380 .callback = strago_quirk_cb,
3381 .matches = {
3382 DMI_MATCH(DMI_PRODUCT_NAME, "Reks"),
3383 },
3384 },
0580bcc9
JL		 3385 {
3386 .ident = "Google Edgar",
3387 .callback = strago_quirk_cb,
3388 .matches = {
3389 DMI_MATCH(DMI_PRODUCT_NAME, "Edgar"),
3390 },
3391 },
3f58b703
BL		 3392 {
3393 .ident = "Google Wizpig",
3394 .callback = strago_quirk_cb,
3395 .matches = {
3396 DMI_MATCH(DMI_PRODUCT_NAME, "Wizpig"),
3397 },
3398 },
6b3cecd1
BL		 3399 {
3400 .ident = "Google Terra",
3401 .callback = strago_quirk_cb,
3402 .matches = {
3403 DMI_MATCH(DMI_PRODUCT_NAME, "Terra"),
3404 },
3405 },
78c34fd4
FY		 3406 { }
3407};
3408
e9159e75
JL		 3409static struct rt5645_platform_data buddy_platform_data = {
3410 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3411 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3412 .jd_mode = 3,
917536ae 3413 .jd_invert = true,
e9159e75
JL		 3414};
3415
3416static int buddy_quirk_cb(const struct dmi_system_id *id)
3417{
3418 rt5645_pdata = &buddy_platform_data;
3419
3420 return 1;
3421}
3422
dc542fb4 3423static struct dmi_system_id dmi_platform_intel_broadwell[] = {
e9159e75
JL		 3424 {
3425 .ident = "Chrome Buddy",
3426 .callback = buddy_quirk_cb,
3427 .matches = {
3428 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3429 },
3430 },
3431 { }
3432};
3433
3434
48edaa4b
OC		 3435static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3436{
3437 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3438 "realtek,in2-differential");
3439 device_property_read_u32(dev,
3440 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3441 device_property_read_u32(dev,
3442 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3443 device_property_read_u32(dev,
3444 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3445
3446 return 0;
3447}
3448
1319b2f6
OC		 3449static int rt5645_i2c_probe(struct i2c_client *i2c,
3450 const struct i2c_device_id *id)
3451{
3452 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3453 struct rt5645_priv *rt5645;
9fc114c5 3454 int ret, i;
1319b2f6
OC		 3455 unsigned int val;
3456
3457 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3458 GFP_KERNEL);
3459 if (rt5645 == NULL)
3460 return -ENOMEM;
3461
f3fa1bbd 3462 rt5645->i2c = i2c;
1319b2f6
OC		 3463 i2c_set_clientdata(i2c, rt5645);
3464
48edaa4b 3465 if (pdata)
1319b2f6 3466 rt5645->pdata = *pdata;
e9159e75
JL		 3467 else if (dmi_check_system(dmi_platform_intel_braswell) ||
3468 dmi_check_system(dmi_platform_intel_broadwell))
48edaa4b
OC		 3469 rt5645->pdata = *rt5645_pdata;
3470 else
3471 rt5645_parse_dt(rt5645, &i2c->dev);
1319b2f6 3472
25c8888a
AL		 3473 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3474 GPIOD_IN);
0b0cefc8
OC		 3475
3476 if (IS_ERR(rt5645->gpiod_hp_det)) {
0b0cefc8 3477 dev_err(&i2c->dev, "failed to initialize gpiod\n");
25c8888a 3478 return PTR_ERR(rt5645->gpiod_hp_det);
0b0cefc8
OC		 3479 }
3480
1319b2f6
OC		 3481 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3482 if (IS_ERR(rt5645->regmap)) {
3483 ret = PTR_ERR(rt5645->regmap);
3484 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3485 ret);
3486 return ret;
3487 }
3488
9fc114c5
KC		 3489 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3490 rt5645->supplies[i].supply = rt5645_supply_names[i];
3491
3492 ret = devm_regulator_bulk_get(&i2c->dev,
3493 ARRAY_SIZE(rt5645->supplies),
3494 rt5645->supplies);
3495 if (ret) {
3496 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3497 return ret;
3498 }
3499
3500 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3501 rt5645->supplies);
3502 if (ret) {
3503 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3504 return ret;
3505 }
3506
1319b2f6 3507 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
5c4ca99d
BL		 3508
3509 switch (val) {
3510 case RT5645_DEVICE_ID:
3511 rt5645->codec_type = CODEC_TYPE_RT5645;
3512 break;
3513 case RT5650_DEVICE_ID:
3514 rt5645->codec_type = CODEC_TYPE_RT5650;
3515 break;
3516 default:
1319b2f6 3517 dev_err(&i2c->dev,
8f68e80f 3518 "Device with ID register %#x is not rt5645 or rt5650\n",
5c4ca99d 3519 val);
9fc114c5
KC		 3520 ret = -ENODEV;
3521 goto err_enable;
d12d6c4e
JL		 3522 }
3523
1319b2f6
OC		 3524 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3525
3526 ret = regmap_register_patch(rt5645->regmap, init_list,
3527 ARRAY_SIZE(init_list));
3528 if (ret != 0)
3529 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3530
5c4ca99d
BL		 3531 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3532 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3533 ARRAY_SIZE(rt5650_init_list));
3534 if (ret != 0)
3535 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3536 ret);
3537 }
3538
1319b2f6
OC		 3539 if (rt5645->pdata.in2_diff)
3540 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3541 RT5645_IN_DF2, RT5645_IN_DF2);
3542
ac4fc3ee 3543 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
1319b2f6
OC		 3544 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3545 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
ac4fc3ee
BL		 3546 }
3547 switch (rt5645->pdata.dmic1_data_pin) {
3548 case RT5645_DMIC_DATA_IN2N:
3549 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3550 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3551 break;
1319b2f6 3552
ac4fc3ee 3553 case RT5645_DMIC_DATA_GPIO5:
a094935e
BL		 3554 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3555 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
ac4fc3ee
BL		 3556 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3557 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3558 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3559 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3560 break;
1319b2f6 3561
ac4fc3ee
BL		 3562 case RT5645_DMIC_DATA_GPIO11:
3563 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3564 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3565 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3566 RT5645_GP11_PIN_MASK,
3567 RT5645_GP11_PIN_DMIC1_SDA);
3568 break;
1319b2f6 3569
ac4fc3ee
BL		 3570 default:
3571 break;
3572 }
1319b2f6 3573
ac4fc3ee
BL		 3574 switch (rt5645->pdata.dmic2_data_pin) {
3575 case RT5645_DMIC_DATA_IN2P:
3576 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3577 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3578 break;
1319b2f6 3579
ac4fc3ee
BL		 3580 case RT5645_DMIC_DATA_GPIO6:
3581 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3582 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3583 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3584 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3585 break;
1319b2f6 3586
ac4fc3ee
BL		 3587 case RT5645_DMIC_DATA_GPIO10:
3588 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3589 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3590 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3591 RT5645_GP10_PIN_MASK,
3592 RT5645_GP10_PIN_DMIC2_SDA);
3593 break;
1319b2f6 3594
ac4fc3ee
BL		 3595 case RT5645_DMIC_DATA_GPIO12:
3596 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3597 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3598 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3599 RT5645_GP12_PIN_MASK,
3600 RT5645_GP12_PIN_DMIC2_SDA);
3601 break;
1319b2f6 3602
ac4fc3ee
BL		 3603 default:
3604 break;
1319b2f6
OC		 3605 }
3606
ac4fc3ee 3607 if (rt5645->pdata.jd_mode) {
bb656add 3608 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
ac4fc3ee
BL		 3609 RT5645_IRQ_CLK_GATE_CTRL,
3610 RT5645_IRQ_CLK_GATE_CTRL);
bb656add 3611 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
ac4fc3ee 3612 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2d4e2d02
BL		 3613 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3614 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3615 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3616 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3617 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3618 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3619 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3620 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
3621 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3622 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3623 switch (rt5645->pdata.jd_mode) {
3624 case 1:
3625 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3626 RT5645_JD1_MODE_MASK,
3627 RT5645_JD1_MODE_0);
3628 break;
3629 case 2:
3630 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3631 RT5645_JD1_MODE_MASK,
3632 RT5645_JD1_MODE_1);
3633 break;
3634 case 3:
3635 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3636 RT5645_JD1_MODE_MASK,
3637 RT5645_JD1_MODE_2);
3638 break;
3639 default:
3640 break;
3641 }
3642 }
3643
7ea3470a 3644 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
7099ee85 3645 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
7ea3470a 3646
f3fa1bbd
OC		 3647 if (rt5645->i2c->irq) {
3648 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
3649 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3650 | IRQF_ONESHOT, "rt5645", rt5645);
5168c547 3651 if (ret) {
f3fa1bbd 3652 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
9fc114c5 3653 goto err_enable;
5168c547 3654 }
f3fa1bbd
OC		 3655 }
3656
5168c547
KC		 3657 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
3658 rt5645_dai, ARRAY_SIZE(rt5645_dai));
3659 if (ret)
3660 goto err_irq;
3661
3662 return 0;
3663
3664err_irq:
3665 if (rt5645->i2c->irq)
3666 free_irq(rt5645->i2c->irq, rt5645);
9fc114c5
KC		 3667err_enable:
3668 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
5168c547 3669 return ret;
1319b2f6
OC		 3670}
3671
3672static int rt5645_i2c_remove(struct i2c_client *i2c)
3673{
f3fa1bbd
OC		 3674 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3675
3676 if (i2c->irq)
3677 free_irq(i2c->irq, rt5645);
3678
cd6e82b8 3679 cancel_delayed_work_sync(&rt5645->jack_detect_work);
7099ee85 3680 cancel_delayed_work_sync(&rt5645->rcclock_work);
cd6e82b8 3681
1319b2f6 3682 snd_soc_unregister_codec(&i2c->dev);
9fc114c5 3683 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
1319b2f6
OC		 3684
3685 return 0;
3686}
3687
f2988afe
OC		 3688static void rt5645_i2c_shutdown(struct i2c_client *i2c)
3689{
3690 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3691
3692 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3693 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
3694 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
3695 RT5645_CBJ_MN_JD);
3696 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
3697 0);
a2c026cf
OC		 3698 msleep(20);
3699 regmap_write(rt5645->regmap, RT5645_RESET, 0);
f2988afe
OC		 3700}
3701
9e22f782 3702static struct i2c_driver rt5645_i2c_driver = {
1319b2f6
OC		 3703 .driver = {
3704 .name = "rt5645",
3168c201 3705 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
1319b2f6
OC		 3706 },
3707 .probe = rt5645_i2c_probe,
f2988afe
OC		 3708 .remove = rt5645_i2c_remove,
3709 .shutdown = rt5645_i2c_shutdown,
1319b2f6
OC		 3710 .id_table = rt5645_i2c_id,
3711};
3712module_i2c_driver(rt5645_i2c_driver);
3713
3714MODULE_DESCRIPTION("ASoC RT5645 driver");
3715MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3716MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.439347 seconds and 5 git commands to generate.