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ASoC: rt5645: Update dapm pins when the card is not instantiated yet
[deliverable/linux.git] / sound / soc / codecs / rt5645.c
CommitLineData
1319b2f6
OC		 1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
f3fa1bbd 20#include <linux/gpio.h>
baf2a0e1 21#include <linux/gpio/consumer.h>
3168c201 22#include <linux/acpi.h>
78c34fd4 23#include <linux/dmi.h>
1319b2f6
OC		 24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/jack.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
49ef7925 33#include "rl6231.h"
1319b2f6
OC		 34#include "rt5645.h"
35
36#define RT5645_DEVICE_ID 0x6308
5c4ca99d 37#define RT5650_DEVICE_ID 0x6419
1319b2f6
OC		 38
39#define RT5645_PR_RANGE_BASE (0xff + 1)
40#define RT5645_PR_SPACING 0x100
41
42#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
43
44static const struct regmap_range_cfg rt5645_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5645_PR_BASE,
48 .range_max = RT5645_PR_BASE + 0xf8,
49 .selector_reg = RT5645_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5645_PRIV_DATA,
53 .window_len = 0x1,
54 },
55};
56
57static const struct reg_default init_list[] = {
58 {RT5645_PR_BASE + 0x3d, 0x3600},
4809b96e
OC		 59 {RT5645_PR_BASE + 0x1c, 0xfd20},
60 {RT5645_PR_BASE + 0x20, 0x611f},
61 {RT5645_PR_BASE + 0x21, 0x4040},
62 {RT5645_PR_BASE + 0x23, 0x0004},
1319b2f6
OC		 63};
64#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
65
5c4ca99d
BL		 66static const struct reg_default rt5650_init_list[] = {
67 {0xf6, 0x0100},
68};
69
1319b2f6
OC		 70static const struct reg_default rt5645_reg[] = {
71 { 0x00, 0x0000 },
72 { 0x01, 0xc8c8 },
73 { 0x02, 0xc8c8 },
74 { 0x03, 0xc8c8 },
75 { 0x0a, 0x0002 },
76 { 0x0b, 0x2827 },
77 { 0x0c, 0xe000 },
78 { 0x0d, 0x0000 },
79 { 0x0e, 0x0000 },
80 { 0x0f, 0x0808 },
81 { 0x14, 0x3333 },
82 { 0x16, 0x4b00 },
83 { 0x18, 0x018b },
84 { 0x19, 0xafaf },
85 { 0x1a, 0xafaf },
86 { 0x1b, 0x0001 },
87 { 0x1c, 0x2f2f },
88 { 0x1d, 0x2f2f },
89 { 0x1e, 0x0000 },
90 { 0x20, 0x0000 },
91 { 0x27, 0x7060 },
92 { 0x28, 0x7070 },
93 { 0x29, 0x8080 },
94 { 0x2a, 0x5656 },
95 { 0x2b, 0x5454 },
96 { 0x2c, 0xaaa0 },
5c4ca99d 97 { 0x2d, 0x0000 },
1319b2f6
OC		 98 { 0x2f, 0x1002 },
99 { 0x31, 0x5000 },
100 { 0x32, 0x0000 },
101 { 0x33, 0x0000 },
102 { 0x34, 0x0000 },
103 { 0x35, 0x0000 },
104 { 0x3b, 0x0000 },
105 { 0x3c, 0x007f },
106 { 0x3d, 0x0000 },
107 { 0x3e, 0x007f },
108 { 0x3f, 0x0000 },
109 { 0x40, 0x001f },
110 { 0x41, 0x0000 },
111 { 0x42, 0x001f },
112 { 0x45, 0x6000 },
113 { 0x46, 0x003e },
114 { 0x47, 0x003e },
115 { 0x48, 0xf807 },
116 { 0x4a, 0x0004 },
117 { 0x4d, 0x0000 },
118 { 0x4e, 0x0000 },
119 { 0x4f, 0x01ff },
120 { 0x50, 0x0000 },
121 { 0x51, 0x0000 },
122 { 0x52, 0x01ff },
123 { 0x53, 0xf000 },
124 { 0x56, 0x0111 },
125 { 0x57, 0x0064 },
126 { 0x58, 0xef0e },
127 { 0x59, 0xf0f0 },
128 { 0x5a, 0xef0e },
129 { 0x5b, 0xf0f0 },
130 { 0x5c, 0xef0e },
131 { 0x5d, 0xf0f0 },
132 { 0x5e, 0xf000 },
133 { 0x5f, 0x0000 },
134 { 0x61, 0x0300 },
135 { 0x62, 0x0000 },
136 { 0x63, 0x00c2 },
137 { 0x64, 0x0000 },
138 { 0x65, 0x0000 },
139 { 0x66, 0x0000 },
140 { 0x6a, 0x0000 },
141 { 0x6c, 0x0aaa },
142 { 0x70, 0x8000 },
143 { 0x71, 0x8000 },
144 { 0x72, 0x8000 },
145 { 0x73, 0x7770 },
146 { 0x74, 0x3e00 },
147 { 0x75, 0x2409 },
148 { 0x76, 0x000a },
149 { 0x77, 0x0c00 },
150 { 0x78, 0x0000 },
df078d29 151 { 0x79, 0x0123 },
1319b2f6
OC		 152 { 0x80, 0x0000 },
153 { 0x81, 0x0000 },
154 { 0x82, 0x0000 },
155 { 0x83, 0x0000 },
156 { 0x84, 0x0000 },
157 { 0x85, 0x0000 },
158 { 0x8a, 0x0000 },
159 { 0x8e, 0x0004 },
160 { 0x8f, 0x1100 },
161 { 0x90, 0x0646 },
162 { 0x91, 0x0c06 },
163 { 0x93, 0x0000 },
164 { 0x94, 0x0200 },
165 { 0x95, 0x0000 },
166 { 0x9a, 0x2184 },
167 { 0x9b, 0x010a },
168 { 0x9c, 0x0aea },
169 { 0x9d, 0x000c },
170 { 0x9e, 0x0400 },
171 { 0xa0, 0xa0a8 },
172 { 0xa1, 0x0059 },
173 { 0xa2, 0x0001 },
174 { 0xae, 0x6000 },
175 { 0xaf, 0x0000 },
176 { 0xb0, 0x6000 },
177 { 0xb1, 0x0000 },
178 { 0xb2, 0x0000 },
179 { 0xb3, 0x001f },
180 { 0xb4, 0x020c },
181 { 0xb5, 0x1f00 },
182 { 0xb6, 0x0000 },
183 { 0xbb, 0x0000 },
184 { 0xbc, 0x0000 },
185 { 0xbd, 0x0000 },
186 { 0xbe, 0x0000 },
187 { 0xbf, 0x3100 },
188 { 0xc0, 0x0000 },
189 { 0xc1, 0x0000 },
190 { 0xc2, 0x0000 },
191 { 0xc3, 0x2000 },
192 { 0xcd, 0x0000 },
193 { 0xce, 0x0000 },
194 { 0xcf, 0x1813 },
195 { 0xd0, 0x0690 },
196 { 0xd1, 0x1c17 },
197 { 0xd3, 0xb320 },
198 { 0xd4, 0x0000 },
199 { 0xd6, 0x0400 },
200 { 0xd9, 0x0809 },
201 { 0xda, 0x0000 },
202 { 0xdb, 0x0003 },
203 { 0xdc, 0x0049 },
204 { 0xdd, 0x001b },
5c4ca99d
BL		 205 { 0xdf, 0x0008 },
206 { 0xe0, 0x4000 },
1319b2f6
OC		 207 { 0xe6, 0x8000 },
208 { 0xe7, 0x0200 },
209 { 0xec, 0xb300 },
210 { 0xed, 0x0000 },
211 { 0xf0, 0x001f },
212 { 0xf1, 0x020c },
213 { 0xf2, 0x1f00 },
214 { 0xf3, 0x0000 },
215 { 0xf4, 0x4000 },
216 { 0xf8, 0x0000 },
217 { 0xf9, 0x0000 },
218 { 0xfa, 0x2060 },
219 { 0xfb, 0x4040 },
220 { 0xfc, 0x0000 },
221 { 0xfd, 0x0002 },
222 { 0xfe, 0x10ec },
223 { 0xff, 0x6308 },
224};
225
226static int rt5645_reset(struct snd_soc_codec *codec)
227{
228 return snd_soc_write(codec, RT5645_RESET, 0);
229}
230
231static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
232{
233 int i;
234
235 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
236 if (reg >= rt5645_ranges[i].range_min &&
237 reg <= rt5645_ranges[i].range_max) {
238 return true;
239 }
240 }
241
242 switch (reg) {
243 case RT5645_RESET:
244 case RT5645_PRIV_DATA:
245 case RT5645_IN1_CTRL1:
246 case RT5645_IN1_CTRL2:
247 case RT5645_IN1_CTRL3:
248 case RT5645_A_JD_CTRL1:
249 case RT5645_ADC_EQ_CTRL1:
250 case RT5645_EQ_CTRL1:
251 case RT5645_ALC_CTRL_1:
252 case RT5645_IRQ_CTRL2:
253 case RT5645_IRQ_CTRL3:
254 case RT5645_INT_IRQ_ST:
255 case RT5645_IL_CMD:
5c4ca99d 256 case RT5650_4BTN_IL_CMD1:
1319b2f6
OC		 257 case RT5645_VENDOR_ID:
258 case RT5645_VENDOR_ID1:
259 case RT5645_VENDOR_ID2:
71bfa9b4 260 return true;
1319b2f6 261 default:
71bfa9b4 262 return false;
1319b2f6
OC		 263 }
264}
265
266static bool rt5645_readable_register(struct device *dev, unsigned int reg)
267{
268 int i;
269
270 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
271 if (reg >= rt5645_ranges[i].range_min &&
272 reg <= rt5645_ranges[i].range_max) {
273 return true;
274 }
275 }
276
277 switch (reg) {
278 case RT5645_RESET:
279 case RT5645_SPK_VOL:
280 case RT5645_HP_VOL:
281 case RT5645_LOUT1:
282 case RT5645_IN1_CTRL1:
283 case RT5645_IN1_CTRL2:
284 case RT5645_IN1_CTRL3:
285 case RT5645_IN2_CTRL:
286 case RT5645_INL1_INR1_VOL:
287 case RT5645_SPK_FUNC_LIM:
288 case RT5645_ADJ_HPF_CTRL:
289 case RT5645_DAC1_DIG_VOL:
290 case RT5645_DAC2_DIG_VOL:
291 case RT5645_DAC_CTRL:
292 case RT5645_STO1_ADC_DIG_VOL:
293 case RT5645_MONO_ADC_DIG_VOL:
294 case RT5645_ADC_BST_VOL1:
295 case RT5645_ADC_BST_VOL2:
296 case RT5645_STO1_ADC_MIXER:
297 case RT5645_MONO_ADC_MIXER:
298 case RT5645_AD_DA_MIXER:
299 case RT5645_STO_DAC_MIXER:
300 case RT5645_MONO_DAC_MIXER:
301 case RT5645_DIG_MIXER:
5c4ca99d 302 case RT5650_A_DAC_SOUR:
1319b2f6
OC		 303 case RT5645_DIG_INF1_DATA:
304 case RT5645_PDM_OUT_CTRL:
305 case RT5645_REC_L1_MIXER:
306 case RT5645_REC_L2_MIXER:
307 case RT5645_REC_R1_MIXER:
308 case RT5645_REC_R2_MIXER:
309 case RT5645_HPMIXL_CTRL:
310 case RT5645_HPOMIXL_CTRL:
311 case RT5645_HPMIXR_CTRL:
312 case RT5645_HPOMIXR_CTRL:
313 case RT5645_HPO_MIXER:
314 case RT5645_SPK_L_MIXER:
315 case RT5645_SPK_R_MIXER:
316 case RT5645_SPO_MIXER:
317 case RT5645_SPO_CLSD_RATIO:
318 case RT5645_OUT_L1_MIXER:
319 case RT5645_OUT_R1_MIXER:
320 case RT5645_OUT_L_GAIN1:
321 case RT5645_OUT_L_GAIN2:
322 case RT5645_OUT_R_GAIN1:
323 case RT5645_OUT_R_GAIN2:
324 case RT5645_LOUT_MIXER:
325 case RT5645_HAPTIC_CTRL1:
326 case RT5645_HAPTIC_CTRL2:
327 case RT5645_HAPTIC_CTRL3:
328 case RT5645_HAPTIC_CTRL4:
329 case RT5645_HAPTIC_CTRL5:
330 case RT5645_HAPTIC_CTRL6:
331 case RT5645_HAPTIC_CTRL7:
332 case RT5645_HAPTIC_CTRL8:
333 case RT5645_HAPTIC_CTRL9:
334 case RT5645_HAPTIC_CTRL10:
335 case RT5645_PWR_DIG1:
336 case RT5645_PWR_DIG2:
337 case RT5645_PWR_ANLG1:
338 case RT5645_PWR_ANLG2:
339 case RT5645_PWR_MIXER:
340 case RT5645_PWR_VOL:
341 case RT5645_PRIV_INDEX:
342 case RT5645_PRIV_DATA:
343 case RT5645_I2S1_SDP:
344 case RT5645_I2S2_SDP:
345 case RT5645_ADDA_CLK1:
346 case RT5645_ADDA_CLK2:
347 case RT5645_DMIC_CTRL1:
348 case RT5645_DMIC_CTRL2:
349 case RT5645_TDM_CTRL_1:
350 case RT5645_TDM_CTRL_2:
df078d29 351 case RT5645_TDM_CTRL_3:
1fcb76db 352 case RT5650_TDM_CTRL_4:
1319b2f6
OC		 353 case RT5645_GLB_CLK:
354 case RT5645_PLL_CTRL1:
355 case RT5645_PLL_CTRL2:
356 case RT5645_ASRC_1:
357 case RT5645_ASRC_2:
358 case RT5645_ASRC_3:
359 case RT5645_ASRC_4:
360 case RT5645_DEPOP_M1:
361 case RT5645_DEPOP_M2:
362 case RT5645_DEPOP_M3:
363 case RT5645_MICBIAS:
364 case RT5645_A_JD_CTRL1:
365 case RT5645_VAD_CTRL4:
366 case RT5645_CLSD_OUT_CTRL:
367 case RT5645_ADC_EQ_CTRL1:
368 case RT5645_ADC_EQ_CTRL2:
369 case RT5645_EQ_CTRL1:
370 case RT5645_EQ_CTRL2:
371 case RT5645_ALC_CTRL_1:
372 case RT5645_ALC_CTRL_2:
373 case RT5645_ALC_CTRL_3:
374 case RT5645_ALC_CTRL_4:
375 case RT5645_ALC_CTRL_5:
376 case RT5645_JD_CTRL:
377 case RT5645_IRQ_CTRL1:
378 case RT5645_IRQ_CTRL2:
379 case RT5645_IRQ_CTRL3:
380 case RT5645_INT_IRQ_ST:
381 case RT5645_GPIO_CTRL1:
382 case RT5645_GPIO_CTRL2:
383 case RT5645_GPIO_CTRL3:
384 case RT5645_BASS_BACK:
385 case RT5645_MP3_PLUS1:
386 case RT5645_MP3_PLUS2:
387 case RT5645_ADJ_HPF1:
388 case RT5645_ADJ_HPF2:
389 case RT5645_HP_CALIB_AMP_DET:
390 case RT5645_SV_ZCD1:
391 case RT5645_SV_ZCD2:
392 case RT5645_IL_CMD:
393 case RT5645_IL_CMD2:
394 case RT5645_IL_CMD3:
5c4ca99d
BL		 395 case RT5650_4BTN_IL_CMD1:
396 case RT5650_4BTN_IL_CMD2:
1319b2f6
OC		 397 case RT5645_DRC1_HL_CTRL1:
398 case RT5645_DRC2_HL_CTRL1:
399 case RT5645_ADC_MONO_HP_CTRL1:
400 case RT5645_ADC_MONO_HP_CTRL2:
401 case RT5645_DRC2_CTRL1:
402 case RT5645_DRC2_CTRL2:
403 case RT5645_DRC2_CTRL3:
404 case RT5645_DRC2_CTRL4:
405 case RT5645_DRC2_CTRL5:
406 case RT5645_JD_CTRL3:
407 case RT5645_JD_CTRL4:
408 case RT5645_GEN_CTRL1:
409 case RT5645_GEN_CTRL2:
410 case RT5645_GEN_CTRL3:
411 case RT5645_VENDOR_ID:
412 case RT5645_VENDOR_ID1:
413 case RT5645_VENDOR_ID2:
71bfa9b4 414 return true;
1319b2f6 415 default:
71bfa9b4 416 return false;
1319b2f6
OC		 417 }
418}
419
420static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
177e1e1f 421static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1319b2f6 422static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
177e1e1f 423static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1319b2f6
OC		 424static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
425
426/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
427static unsigned int bst_tlv[] = {
428 TLV_DB_RANGE_HEAD(7),
429 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
430 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
431 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
432 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
433 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
434 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
435 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
436};
437
1319b2f6
OC		 438static const struct snd_kcontrol_new rt5645_snd_controls[] = {
439 /* Speaker Output Volume */
440 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
441 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
442 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
443 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
444
445 /* Headphone Output Volume */
692768c4 446 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
1319b2f6 447 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
692768c4 448 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
1319b2f6
OC		 449 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
450
451 /* OUTPUT Control */
452 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
453 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
454 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
455 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
456 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
457 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
458
459 /* DAC Digital Volume */
460 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
461 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
462 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
177e1e1f 463 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6 464 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
177e1e1f 465 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6
OC		 466
467 /* IN1/IN2 Control */
468 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
469 RT5645_BST_SFT1, 8, 0, bst_tlv),
470 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
471 RT5645_BST_SFT2, 8, 0, bst_tlv),
472
473 /* INL/INR Volume Control */
474 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
475 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
476
477 /* ADC Digital Volume Control */
478 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
479 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
480 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
177e1e1f 481 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 482 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
483 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
484 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
177e1e1f 485 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 486
487 /* ADC Boost Volume Control */
488 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
489 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
490 adc_bst_tlv),
491 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
492 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
493 adc_bst_tlv),
494
495 /* I2S2 function select */
496 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
497 1, 1),
1319b2f6
OC		 498};
499
500/**
501 * set_dmic_clk - Set parameter of dmic.
502 *
503 * @w: DAPM widget.
504 * @kcontrol: The kcontrol of this widget.
505 * @event: Event id.
506 *
1319b2f6
OC		 507 */
508static int set_dmic_clk(struct snd_soc_dapm_widget *w,
509 struct snd_kcontrol *kcontrol, int event)
510{
c5f596cb 511 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6 512 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
49ef7925
OC		 513 int idx = -EINVAL;
514
515 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
1319b2f6
OC		 516
517 if (idx < 0)
518 dev_err(codec->dev, "Failed to set DMIC clock\n");
519 else
520 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
521 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
522 return idx;
523}
524
525static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
526 struct snd_soc_dapm_widget *sink)
527{
c5f596cb 528 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1319b2f6
OC		 529 unsigned int val;
530
c5f596cb 531 val = snd_soc_read(codec, RT5645_GLB_CLK);
1319b2f6
OC		 532 val &= RT5645_SCLK_SRC_MASK;
533 if (val == RT5645_SCLK_SRC_PLL1)
534 return 1;
535 else
536 return 0;
537}
538
9e268353
BL		 539static int is_using_asrc(struct snd_soc_dapm_widget *source,
540 struct snd_soc_dapm_widget *sink)
541{
c5f596cb 542 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
9e268353
BL		 543 unsigned int reg, shift, val;
544
545 switch (source->shift) {
546 case 0:
547 reg = RT5645_ASRC_3;
548 shift = 0;
549 break;
550 case 1:
551 reg = RT5645_ASRC_3;
552 shift = 4;
553 break;
554 case 3:
555 reg = RT5645_ASRC_2;
556 shift = 0;
557 break;
558 case 8:
559 reg = RT5645_ASRC_2;
560 shift = 4;
561 break;
562 case 9:
563 reg = RT5645_ASRC_2;
564 shift = 8;
565 break;
566 case 10:
567 reg = RT5645_ASRC_2;
568 shift = 12;
569 break;
570 default:
571 return 0;
572 }
573
c5f596cb 574 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
9e268353
BL		 575 switch (val) {
576 case 1:
577 case 2:
578 case 3:
579 case 4:
580 return 1;
581 default:
582 return 0;
583 }
584
585}
586
79080a8b
FY		 587/**
588 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
589 * @codec: SoC audio codec device.
590 * @filter_mask: mask of filters.
591 * @clk_src: clock source
592 *
593 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
594 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
595 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
596 * ASRC function will track i2s clock and generate a corresponding system clock
597 * for codec. This function provides an API to select the clock source for a
598 * set of filters specified by the mask. And the codec driver will turn on ASRC
599 * for these filters if ASRC is selected as their clock source.
600 */
601int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
602 unsigned int filter_mask, unsigned int clk_src)
603{
604 unsigned int asrc2_mask = 0;
605 unsigned int asrc2_value = 0;
606 unsigned int asrc3_mask = 0;
607 unsigned int asrc3_value = 0;
608
609 switch (clk_src) {
610 case RT5645_CLK_SEL_SYS:
611 case RT5645_CLK_SEL_I2S1_ASRC:
612 case RT5645_CLK_SEL_I2S2_ASRC:
613 case RT5645_CLK_SEL_SYS2:
614 break;
615
616 default:
617 return -EINVAL;
618 }
619
620 if (filter_mask & RT5645_DA_STEREO_FILTER) {
621 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
622 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
623 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
624 }
625
626 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
627 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
628 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
629 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
630 }
631
632 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
633 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
634 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
635 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
636 }
637
638 if (filter_mask & RT5645_AD_STEREO_FILTER) {
639 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
640 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
641 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
642 }
643
644 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
645 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
646 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
647 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
648 }
649
650 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
651 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
652 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
653 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
654 }
655
656 if (asrc2_mask)
657 snd_soc_update_bits(codec, RT5645_ASRC_2,
658 asrc2_mask, asrc2_value);
659
660 if (asrc3_mask)
661 snd_soc_update_bits(codec, RT5645_ASRC_3,
662 asrc3_mask, asrc3_value);
663
664 return 0;
665}
666EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
667
1319b2f6
OC		 668/* Digital Mixer */
669static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
670 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
671 RT5645_M_ADC_L1_SFT, 1, 1),
672 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
673 RT5645_M_ADC_L2_SFT, 1, 1),
674};
675
676static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
677 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
678 RT5645_M_ADC_R1_SFT, 1, 1),
679 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
680 RT5645_M_ADC_R2_SFT, 1, 1),
681};
682
683static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
684 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
685 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
686 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
687 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
688};
689
690static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
691 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
692 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
693 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
694 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
695};
696
697static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
698 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
699 RT5645_M_ADCMIX_L_SFT, 1, 1),
700 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
701 RT5645_M_DAC1_L_SFT, 1, 1),
702};
703
704static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
705 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
706 RT5645_M_ADCMIX_R_SFT, 1, 1),
707 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
708 RT5645_M_DAC1_R_SFT, 1, 1),
709};
710
711static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
712 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
713 RT5645_M_DAC_L1_SFT, 1, 1),
714 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
715 RT5645_M_DAC_L2_SFT, 1, 1),
716 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
717 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
718};
719
720static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
721 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
722 RT5645_M_DAC_R1_SFT, 1, 1),
723 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
724 RT5645_M_DAC_R2_SFT, 1, 1),
725 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
726 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
727};
728
729static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
730 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
731 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
732 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
733 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
734 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
735 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
736};
737
738static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
739 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
740 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
741 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
742 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
743 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
744 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
745};
746
747static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
748 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
749 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
750 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
751 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
752 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
753 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
754};
755
756static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
757 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
758 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
759 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
760 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
761 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
762 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
763};
764
765/* Analog Input Mixer */
766static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
767 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
768 RT5645_M_HP_L_RM_L_SFT, 1, 1),
769 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
770 RT5645_M_IN_L_RM_L_SFT, 1, 1),
771 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
772 RT5645_M_BST2_RM_L_SFT, 1, 1),
773 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
774 RT5645_M_BST1_RM_L_SFT, 1, 1),
775 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
776 RT5645_M_OM_L_RM_L_SFT, 1, 1),
777};
778
779static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
780 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
781 RT5645_M_HP_R_RM_R_SFT, 1, 1),
782 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
783 RT5645_M_IN_R_RM_R_SFT, 1, 1),
784 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
785 RT5645_M_BST2_RM_R_SFT, 1, 1),
786 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
787 RT5645_M_BST1_RM_R_SFT, 1, 1),
788 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
789 RT5645_M_OM_R_RM_R_SFT, 1, 1),
790};
791
792static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
793 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
794 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
795 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
796 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
797 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
798 RT5645_M_IN_L_SM_L_SFT, 1, 1),
799 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
800 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
801};
802
803static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
804 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
805 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
806 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
807 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
808 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
809 RT5645_M_IN_R_SM_R_SFT, 1, 1),
810 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
811 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
812};
813
814static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
815 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
816 RT5645_M_BST1_OM_L_SFT, 1, 1),
817 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
818 RT5645_M_IN_L_OM_L_SFT, 1, 1),
819 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
820 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
821 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
822 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
823};
824
825static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
826 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
827 RT5645_M_BST2_OM_R_SFT, 1, 1),
828 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
829 RT5645_M_IN_R_OM_R_SFT, 1, 1),
830 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
831 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
832 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
833 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
834};
835
836static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
837 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
838 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
839 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
840 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
841 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
842 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
843 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
844 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
845};
846
847static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
848 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
849 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
850 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
851 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
852};
853
854static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
855 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
856 RT5645_M_DAC1_HM_SFT, 1, 1),
857 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
858 RT5645_M_HPVOL_HM_SFT, 1, 1),
859};
860
861static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
862 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
863 RT5645_M_DAC1_HV_SFT, 1, 1),
864 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
865 RT5645_M_DAC2_HV_SFT, 1, 1),
866 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
867 RT5645_M_IN_HV_SFT, 1, 1),
868 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
869 RT5645_M_BST1_HV_SFT, 1, 1),
870};
871
872static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
873 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
874 RT5645_M_DAC1_HV_SFT, 1, 1),
875 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
876 RT5645_M_DAC2_HV_SFT, 1, 1),
877 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
878 RT5645_M_IN_HV_SFT, 1, 1),
879 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
880 RT5645_M_BST2_HV_SFT, 1, 1),
881};
882
883static const struct snd_kcontrol_new rt5645_lout_mix[] = {
884 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
885 RT5645_M_DAC_L1_LM_SFT, 1, 1),
886 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
887 RT5645_M_DAC_R1_LM_SFT, 1, 1),
888 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
889 RT5645_M_OV_L_LM_SFT, 1, 1),
890 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
891 RT5645_M_OV_R_LM_SFT, 1, 1),
892};
893
894/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
895static const char * const rt5645_dac1_src[] = {
896 "IF1 DAC", "IF2 DAC", "IF3 DAC"
897};
898
899static SOC_ENUM_SINGLE_DECL(
900 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
901 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
902
903static const struct snd_kcontrol_new rt5645_dac1l_mux =
904 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
905
906static SOC_ENUM_SINGLE_DECL(
907 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
908 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
909
910static const struct snd_kcontrol_new rt5645_dac1r_mux =
911 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
912
913/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
914static const char * const rt5645_dac12_src[] = {
915 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
916};
917
918static SOC_ENUM_SINGLE_DECL(
919 rt5645_dac2l_enum, RT5645_DAC_CTRL,
920 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
921
922static const struct snd_kcontrol_new rt5645_dac_l2_mux =
923 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
924
925static const char * const rt5645_dacr2_src[] = {
926 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
927};
928
929static SOC_ENUM_SINGLE_DECL(
930 rt5645_dac2r_enum, RT5645_DAC_CTRL,
931 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
932
933static const struct snd_kcontrol_new rt5645_dac_r2_mux =
934 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
935
936
937/* INL/R source */
938static const char * const rt5645_inl_src[] = {
939 "IN2P", "MonoP"
940};
941
942static SOC_ENUM_SINGLE_DECL(
943 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
944 RT5645_INL_SEL_SFT, rt5645_inl_src);
945
946static const struct snd_kcontrol_new rt5645_inl_mux =
947 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
948
949static const char * const rt5645_inr_src[] = {
950 "IN2N", "MonoN"
951};
952
953static SOC_ENUM_SINGLE_DECL(
954 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
955 RT5645_INR_SEL_SFT, rt5645_inr_src);
956
957static const struct snd_kcontrol_new rt5645_inr_mux =
958 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
959
960/* Stereo1 ADC source */
961/* MX-27 [12] */
962static const char * const rt5645_stereo_adc1_src[] = {
963 "DAC MIX", "ADC"
964};
965
966static SOC_ENUM_SINGLE_DECL(
967 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
968 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
969
970static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
971 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
972
973/* MX-27 [11] */
974static const char * const rt5645_stereo_adc2_src[] = {
975 "DAC MIX", "DMIC"
976};
977
978static SOC_ENUM_SINGLE_DECL(
979 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
980 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
981
982static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
983 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
984
985/* MX-27 [8] */
986static const char * const rt5645_stereo_dmic_src[] = {
987 "DMIC1", "DMIC2"
988};
989
990static SOC_ENUM_SINGLE_DECL(
991 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
992 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
993
994static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
995 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
996
997/* Mono ADC source */
998/* MX-28 [12] */
999static const char * const rt5645_mono_adc_l1_src[] = {
1000 "Mono DAC MIXL", "ADC"
1001};
1002
1003static SOC_ENUM_SINGLE_DECL(
1004 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1005 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1006
1007static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1008 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1009/* MX-28 [11] */
1010static const char * const rt5645_mono_adc_l2_src[] = {
1011 "Mono DAC MIXL", "DMIC"
1012};
1013
1014static SOC_ENUM_SINGLE_DECL(
1015 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1016 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1017
1018static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1019 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1020
1021/* MX-28 [8] */
1022static const char * const rt5645_mono_dmic_src[] = {
1023 "DMIC1", "DMIC2"
1024};
1025
1026static SOC_ENUM_SINGLE_DECL(
1027 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1028 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1029
1030static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1031 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1032/* MX-28 [1:0] */
1033static SOC_ENUM_SINGLE_DECL(
1034 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1035 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1036
1037static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1038 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1039/* MX-28 [4] */
1040static const char * const rt5645_mono_adc_r1_src[] = {
1041 "Mono DAC MIXR", "ADC"
1042};
1043
1044static SOC_ENUM_SINGLE_DECL(
1045 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1046 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1047
1048static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1049 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1050/* MX-28 [3] */
1051static const char * const rt5645_mono_adc_r2_src[] = {
1052 "Mono DAC MIXR", "DMIC"
1053};
1054
1055static SOC_ENUM_SINGLE_DECL(
1056 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1057 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1058
1059static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1060 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1061
1062/* MX-77 [9:8] */
1063static const char * const rt5645_if1_adc_in_src[] = {
21ab3f2b
BL		 1064 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1065 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1319b2f6
OC		 1066};
1067
1068static SOC_ENUM_SINGLE_DECL(
1069 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1070 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1071
1072static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1073 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1074
21ab3f2b
BL		 1075/* MX-78 [4:0] */
1076static const char * const rt5650_if1_adc_in_src[] = {
1077 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1078 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1079 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1080 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1081 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1082 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1083
1084 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1085 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1086 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1087 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1088 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1089 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1090
1091 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1092 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1093 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1094 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1095 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1096 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1097
1098 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1099 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1100 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1101 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1102 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1103 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1104};
1105
1106static SOC_ENUM_SINGLE_DECL(
1107 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1108 0, rt5650_if1_adc_in_src);
1109
1110static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1111 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1112
1113/* MX-78 [15:14][13:12][11:10] */
1114static const char * const rt5645_tdm_adc_swap_select[] = {
1115 "L/R", "R/L", "L/L", "R/R"
1116};
1117
1118static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1119 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1120
1121static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1122 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1123
1124static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1125 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1126
1127static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1128 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1129
1130static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1131 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1132
1133static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1134 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1135
1136/* MX-77 [7:6][5:4][3:2] */
1137static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1138 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1139
1140static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1141 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1142
1143static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1144 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1145
1146static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1147 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1148
1149static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1150 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1151
1152static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1153 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1154
1155/* MX-79 [14:12][10:8][6:4][2:0] */
1156static const char * const rt5645_tdm_dac_swap_select[] = {
1157 "Slot0", "Slot1", "Slot2", "Slot3"
1158};
1159
1160static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1161 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1162
1163static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1164 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1165
1166static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1167 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1168
1169static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1170 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1171
1172static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1173 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1174
1175static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1176 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1177
1178static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1179 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1180
1181static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1182 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1183
1184/* MX-7a [14:12][10:8][6:4][2:0] */
1185static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1186 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1187
1188static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1189 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1190
1191static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1192 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1193
1194static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1195 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1196
1197static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1198 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1199
1200static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1201 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1202
1203static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1204 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1205
1206static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1207 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1208
5c4ca99d
BL		 1209/* MX-2d [3] [2] */
1210static const char * const rt5650_a_dac1_src[] = {
1211 "DAC1", "Stereo DAC Mixer"
1212};
1213
1214static SOC_ENUM_SINGLE_DECL(
1215 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1216 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1217
1218static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1219 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1220
1221static SOC_ENUM_SINGLE_DECL(
1222 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1223 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1224
1225static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1226 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1227
1228/* MX-2d [1] [0] */
1229static const char * const rt5650_a_dac2_src[] = {
1230 "Stereo DAC Mixer", "Mono DAC Mixer"
1231};
1232
1233static SOC_ENUM_SINGLE_DECL(
1234 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1235 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1236
1237static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1238 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1239
1240static SOC_ENUM_SINGLE_DECL(
1241 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1242 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1243
1244static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1245 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1246
1319b2f6
OC		 1247/* MX-2F [13:12] */
1248static const char * const rt5645_if2_adc_in_src[] = {
1249 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1250};
1251
1252static SOC_ENUM_SINGLE_DECL(
1253 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1254 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1255
1256static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1257 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1258
1259/* MX-2F [1:0] */
1260static const char * const rt5645_if3_adc_in_src[] = {
1261 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1262};
1263
1264static SOC_ENUM_SINGLE_DECL(
1265 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1266 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1267
1268static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1269 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1270
1271/* MX-31 [15] [13] [11] [9] */
1272static const char * const rt5645_pdm_src[] = {
1273 "Mono DAC", "Stereo DAC"
1274};
1275
1276static SOC_ENUM_SINGLE_DECL(
1277 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1278 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1279
1280static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1281 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1282
1283static SOC_ENUM_SINGLE_DECL(
1284 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1285 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1286
1287static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1288 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1289
1290/* MX-9D [9:8] */
1291static const char * const rt5645_vad_adc_src[] = {
1292 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1293};
1294
1295static SOC_ENUM_SINGLE_DECL(
1296 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1297 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1298
1299static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1300 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1301
1302static const struct snd_kcontrol_new spk_l_vol_control =
1303 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1304 RT5645_L_MUTE_SFT, 1, 1);
1305
1306static const struct snd_kcontrol_new spk_r_vol_control =
1307 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1308 RT5645_R_MUTE_SFT, 1, 1);
1309
1310static const struct snd_kcontrol_new hp_l_vol_control =
1311 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1312 RT5645_L_MUTE_SFT, 1, 1);
1313
1314static const struct snd_kcontrol_new hp_r_vol_control =
1315 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1316 RT5645_R_MUTE_SFT, 1, 1);
1317
1318static const struct snd_kcontrol_new pdm1_l_vol_control =
1319 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1320 RT5645_M_PDM1_L, 1, 1);
1321
1322static const struct snd_kcontrol_new pdm1_r_vol_control =
1323 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1324 RT5645_M_PDM1_R, 1, 1);
1325
1326static void hp_amp_power(struct snd_soc_codec *codec, int on)
1327{
1328 static int hp_amp_power_count;
1329 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1330
1331 if (on) {
1332 if (hp_amp_power_count <= 0) {
d12d6c4e
JL		 1333 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1334 snd_soc_write(codec, RT5645_CHARGE_PUMP,
1335 0x0e06);
1336 snd_soc_write(codec, RT5645_DEPOP_M1, 0x001d);
1337 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1338 0x3e, 0x7400);
1339 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1340 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1341 RT5645_MAMP_INT_REG2, 0xfc00);
1342 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1343 } else {
1344 /* depop parameters */
1345 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1346 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1347 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1348 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1349 RT5645_HP_DCC_INT1, 0x9f01);
1350 mdelay(150);
1351 /* headphone amp power on */
1352 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1353 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1354 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1355 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1356 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1357 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1358 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1359 RT5645_PWR_HA,
1360 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1361 RT5645_PWR_HA);
1362 mdelay(5);
1363 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1364 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1365 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1366
1367 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1368 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1369 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1370 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1371 0x14, 0x1aaa);
1372 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1373 0x24, 0x0430);
1374 }
1319b2f6
OC		 1375 }
1376 hp_amp_power_count++;
1377 } else {
1378 hp_amp_power_count--;
1379 if (hp_amp_power_count <= 0) {
d12d6c4e
JL		 1380 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1381 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1382 0x3e, 0x7400);
1383 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1384 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1385 RT5645_MAMP_INT_REG2, 0xfc00);
1386 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1387 msleep(100);
1388 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1389
1390 } else {
1391 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1392 RT5645_HP_SG_MASK |
1393 RT5645_HP_L_SMT_MASK |
1394 RT5645_HP_R_SMT_MASK,
1395 RT5645_HP_SG_DIS |
1396 RT5645_HP_L_SMT_DIS |
1397 RT5645_HP_R_SMT_DIS);
1398 /* headphone amp power down */
1399 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1400 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1401 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1402 RT5645_PWR_HA, 0);
1403 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1404 RT5645_DEPOP_MASK, 0);
1405 }
1319b2f6
OC		 1406 }
1407 }
1408}
1409
1410static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1411 struct snd_kcontrol *kcontrol, int event)
1412{
c5f596cb 1413 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1414 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1415
1416 switch (event) {
1417 case SND_SOC_DAPM_POST_PMU:
1418 hp_amp_power(codec, 1);
1419 /* headphone unmute sequence */
d12d6c4e 1420 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1421 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1422 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1423 RT5645_CP_FQ3_MASK,
1424 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1425 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1426 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1427 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1428 RT5645_MAMP_INT_REG2, 0xfc00);
1429 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1430 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1431 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1432 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1433 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1434 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1435 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1436 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1437 msleep(40);
1438 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1439 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1440 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1441 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
5c4ca99d 1442 }
1319b2f6
OC		 1443 break;
1444
1445 case SND_SOC_DAPM_PRE_PMD:
1446 /* headphone mute sequence */
d12d6c4e 1447 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1448 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1449 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1450 RT5645_CP_FQ3_MASK,
1451 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1452 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1453 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1454 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1455 RT5645_MAMP_INT_REG2, 0xfc00);
1456 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1457 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1458 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1459 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1460 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1461 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1462 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1463 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1464 msleep(30);
5c4ca99d 1465 }
1319b2f6
OC		 1466 hp_amp_power(codec, 0);
1467 break;
1468
1469 default:
1470 return 0;
1471 }
1472
1473 return 0;
1474}
1475
1476static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1477 struct snd_kcontrol *kcontrol, int event)
1478{
c5f596cb 1479 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1480
1481 switch (event) {
1482 case SND_SOC_DAPM_POST_PMU:
1483 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1484 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1485 RT5645_PWR_CLS_D_L,
1486 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1487 RT5645_PWR_CLS_D_L);
1488 break;
1489
1490 case SND_SOC_DAPM_PRE_PMD:
1491 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1492 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1493 RT5645_PWR_CLS_D_L, 0);
1494 break;
1495
1496 default:
1497 return 0;
1498 }
1499
1500 return 0;
1501}
1502
1503static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1504 struct snd_kcontrol *kcontrol, int event)
1505{
c5f596cb 1506 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1507
1508 switch (event) {
1509 case SND_SOC_DAPM_POST_PMU:
1510 hp_amp_power(codec, 1);
1511 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1512 RT5645_PWR_LM, RT5645_PWR_LM);
1513 snd_soc_update_bits(codec, RT5645_LOUT1,
1514 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1515 break;
1516
1517 case SND_SOC_DAPM_PRE_PMD:
1518 snd_soc_update_bits(codec, RT5645_LOUT1,
1519 RT5645_L_MUTE | RT5645_R_MUTE,
1520 RT5645_L_MUTE | RT5645_R_MUTE);
1521 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1522 RT5645_PWR_LM, 0);
1523 hp_amp_power(codec, 0);
1524 break;
1525
1526 default:
1527 return 0;
1528 }
1529
1530 return 0;
1531}
1532
1533static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1534 struct snd_kcontrol *kcontrol, int event)
1535{
c5f596cb 1536 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1537
1538 switch (event) {
1539 case SND_SOC_DAPM_POST_PMU:
1540 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1541 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1542 break;
1543
1544 case SND_SOC_DAPM_PRE_PMD:
1545 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1546 RT5645_PWR_BST2_P, 0);
1547 break;
1548
1549 default:
1550 return 0;
1551 }
1552
1553 return 0;
1554}
1555
1556static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1557 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1558 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1559 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1560 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1561
1562 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1563 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1564 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1565 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1566
9e268353
BL		 1567 /* ASRC */
1568 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1569 11, 0, NULL, 0),
1570 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1571 12, 0, NULL, 0),
1572 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1573 10, 0, NULL, 0),
1574 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1575 9, 0, NULL, 0),
1576 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1577 8, 0, NULL, 0),
1578 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1579 7, 0, NULL, 0),
1580 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1581 5, 0, NULL, 0),
1582 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1583 4, 0, NULL, 0),
1584 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1585 3, 0, NULL, 0),
1586 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1587 1, 0, NULL, 0),
1588 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1589 0, 0, NULL, 0),
1590
1319b2f6
OC		 1591 /* Input Side */
1592 /* micbias */
1593 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1594 RT5645_PWR_MB1_BIT, 0),
1595 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1596 RT5645_PWR_MB2_BIT, 0),
1597 /* Input Lines */
1598 SND_SOC_DAPM_INPUT("DMIC L1"),
1599 SND_SOC_DAPM_INPUT("DMIC R1"),
1600 SND_SOC_DAPM_INPUT("DMIC L2"),
1601 SND_SOC_DAPM_INPUT("DMIC R2"),
1602
1603 SND_SOC_DAPM_INPUT("IN1P"),
1604 SND_SOC_DAPM_INPUT("IN1N"),
1605 SND_SOC_DAPM_INPUT("IN2P"),
1606 SND_SOC_DAPM_INPUT("IN2N"),
1607
1608 SND_SOC_DAPM_INPUT("Haptic Generator"),
1609
1610 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1611 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1612 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1613 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1614 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1615 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1616 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1617 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1618 /* Boost */
1619 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1620 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1621 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1622 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1623 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1624 /* Input Volume */
1625 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1626 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1627 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1628 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1629 /* REC Mixer */
1630 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1631 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1632 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1633 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1634 /* ADCs */
1635 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1636 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1637
1638 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1639 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1640 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1641 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1642
1643 /* ADC Mux */
1644 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1645 &rt5645_sto1_dmic_mux),
1646 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1647 &rt5645_sto_adc2_mux),
1648 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1649 &rt5645_sto_adc2_mux),
1650 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1651 &rt5645_sto_adc1_mux),
1652 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1653 &rt5645_sto_adc1_mux),
1654 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1655 &rt5645_mono_dmic_l_mux),
1656 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1657 &rt5645_mono_dmic_r_mux),
1658 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1659 &rt5645_mono_adc_l2_mux),
1660 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1661 &rt5645_mono_adc_l1_mux),
1662 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1663 &rt5645_mono_adc_r1_mux),
1664 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1665 &rt5645_mono_adc_r2_mux),
1666 /* ADC Mixer */
1667
1668 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1669 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1319b2f6
OC		 1670 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1671 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1672 NULL, 0),
1673 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1674 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1675 NULL, 0),
1676 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1677 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1678 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1679 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1680 NULL, 0),
1681 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1682 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1683 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1684 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1685 NULL, 0),
1686
1687 /* ADC PGA */
1688 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1689 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1690 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1691 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1692 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1693 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1694 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1695 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1696 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1697 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1698
1699 /* IF1 2 Mux */
1319b2f6
OC		 1700 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1701 0, 0, &rt5645_if2_adc_in_mux),
1702
1703 /* Digital Interface */
1704 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1705 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
786aa09b 1706 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 1707 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1708 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
786aa09b 1709 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 1710 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1711 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1712 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1713 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1714 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1715 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1716 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1717 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1718 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1719
1720 /* Digital Interface Select */
1721 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1722 0, 0, &rt5645_vad_adc_mux),
1723
1724 /* Audio Interface */
1725 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1726 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1727 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1728 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1729
1730 /* Output Side */
1731 /* DAC mixer before sound effect */
1732 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1733 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1734 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1735 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1736
1737 /* DAC2 channel Mux */
1738 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1739 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1740 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1741 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1742 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1743 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1744
1745 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1746 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1747
1748 /* DAC Mixer */
1749 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1750 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1751 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1752 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1753 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1754 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1755 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1756 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1757 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1758 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1759 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1760 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1761 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1762 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1763 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1764 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1765 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1766 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1767
1768 /* DACs */
1769 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1770 0),
1771 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1772 0),
1773 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1774 0),
1775 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1776 0),
1777 /* OUT Mixer */
1778 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1779 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1780 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1781 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1782 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1783 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1784 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1785 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1786 /* Ouput Volume */
1787 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1788 &spk_l_vol_control),
1789 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1790 &spk_r_vol_control),
1791 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1792 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1793 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1794 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1795 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1796 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1797 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1798 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1799 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1800 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1801 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1802 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1803 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1804
1805 /* HPO/LOUT/Mono Mixer */
1806 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1807 ARRAY_SIZE(rt5645_spo_l_mix)),
1808 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1809 ARRAY_SIZE(rt5645_spo_r_mix)),
1810 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1811 ARRAY_SIZE(rt5645_hpo_mix)),
1812 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1813 ARRAY_SIZE(rt5645_lout_mix)),
1814
1815 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1816 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1817 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1818 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1819 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1820 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1821
1822 /* PDM */
1823 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1824 0, NULL, 0),
1825 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1826 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1827
1828 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1829 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1830
1831 /* Output Lines */
1832 SND_SOC_DAPM_OUTPUT("HPOL"),
1833 SND_SOC_DAPM_OUTPUT("HPOR"),
1834 SND_SOC_DAPM_OUTPUT("LOUTL"),
1835 SND_SOC_DAPM_OUTPUT("LOUTR"),
1836 SND_SOC_DAPM_OUTPUT("PDM1L"),
1837 SND_SOC_DAPM_OUTPUT("PDM1R"),
1838 SND_SOC_DAPM_OUTPUT("SPOL"),
1839 SND_SOC_DAPM_OUTPUT("SPOR"),
1840};
1841
83c09290
BL		 1842static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
1843 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1844 &rt5645_if1_dac0_tdm_sel_mux),
1845 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1846 &rt5645_if1_dac1_tdm_sel_mux),
1847 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1848 &rt5645_if1_dac2_tdm_sel_mux),
1849 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1850 &rt5645_if1_dac3_tdm_sel_mux),
1851 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
1852 0, 0, &rt5645_if1_adc_in_mux),
1853 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1854 0, 0, &rt5645_if1_adc1_in_mux),
1855 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1856 0, 0, &rt5645_if1_adc2_in_mux),
1857 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1858 0, 0, &rt5645_if1_adc3_in_mux),
1859};
1860
5c4ca99d
BL		 1861static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
1862 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
1863 0, 0, &rt5650_a_dac1_l_mux),
1864 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
1865 0, 0, &rt5650_a_dac1_r_mux),
1866 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
1867 0, 0, &rt5650_a_dac2_l_mux),
1868 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
1869 0, 0, &rt5650_a_dac2_r_mux),
851b81e8
MC		 1870
1871 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1872 0, 0, &rt5650_if1_adc1_in_mux),
1873 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1874 0, 0, &rt5650_if1_adc2_in_mux),
1875 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1876 0, 0, &rt5650_if1_adc3_in_mux),
1877 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
1878 0, 0, &rt5650_if1_adc_in_mux),
1879
1880 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1881 &rt5650_if1_dac0_tdm_sel_mux),
1882 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1883 &rt5650_if1_dac1_tdm_sel_mux),
1884 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1885 &rt5650_if1_dac2_tdm_sel_mux),
1886 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1887 &rt5650_if1_dac3_tdm_sel_mux),
5c4ca99d
BL		 1888};
1889
1319b2f6 1890static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
9e268353 1891 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
9e268353
BL		 1892 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1893 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1894 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1895 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1896 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1897
1898 { "I2S1", NULL, "I2S1 ASRC" },
1899 { "I2S2", NULL, "I2S2 ASRC" },
1900
1319b2f6
OC		 1901 { "IN1P", NULL, "LDO2" },
1902 { "IN2P", NULL, "LDO2" },
1903
1904 { "DMIC1", NULL, "DMIC L1" },
1905 { "DMIC1", NULL, "DMIC R1" },
1906 { "DMIC2", NULL, "DMIC L2" },
1907 { "DMIC2", NULL, "DMIC R2" },
1908
1909 { "BST1", NULL, "IN1P" },
1910 { "BST1", NULL, "IN1N" },
1911 { "BST1", NULL, "JD Power" },
1912 { "BST1", NULL, "Mic Det Power" },
1913 { "BST2", NULL, "IN2P" },
1914 { "BST2", NULL, "IN2N" },
1915
1916 { "INL VOL", NULL, "IN2P" },
1917 { "INR VOL", NULL, "IN2N" },
1918
1919 { "RECMIXL", "HPOL Switch", "HPOL" },
1920 { "RECMIXL", "INL Switch", "INL VOL" },
1921 { "RECMIXL", "BST2 Switch", "BST2" },
1922 { "RECMIXL", "BST1 Switch", "BST1" },
1923 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1924
1925 { "RECMIXR", "HPOR Switch", "HPOR" },
1926 { "RECMIXR", "INR Switch", "INR VOL" },
1927 { "RECMIXR", "BST2 Switch", "BST2" },
1928 { "RECMIXR", "BST1 Switch", "BST1" },
1929 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1930
1931 { "ADC L", NULL, "RECMIXL" },
1932 { "ADC L", NULL, "ADC L power" },
1933 { "ADC R", NULL, "RECMIXR" },
1934 { "ADC R", NULL, "ADC R power" },
1935
1936 {"DMIC L1", NULL, "DMIC CLK"},
1937 {"DMIC L1", NULL, "DMIC1 Power"},
1938 {"DMIC R1", NULL, "DMIC CLK"},
1939 {"DMIC R1", NULL, "DMIC1 Power"},
1940 {"DMIC L2", NULL, "DMIC CLK"},
1941 {"DMIC L2", NULL, "DMIC2 Power"},
1942 {"DMIC R2", NULL, "DMIC CLK"},
1943 {"DMIC R2", NULL, "DMIC2 Power"},
1944
1945 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1946 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
9e268353 1947 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1319b2f6
OC		 1948
1949 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1950 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
9e268353 1951 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1319b2f6
OC		 1952
1953 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1954 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
9e268353 1955 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1319b2f6
OC		 1956
1957 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1958 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1959 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1960 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1961
1962 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1963 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1964 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1965 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1966
1967 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1968 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1969 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1970 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1971
1972 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1973 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1974 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1975 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1976
1977 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1978 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1979 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1980 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1981
1982 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1983 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1984 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1985
1986 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1987 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1988 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1989
1990 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1991 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1992 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1993 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1994
1995 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1996 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1997 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1998 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1999
2000 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2001 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2002 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2003
2004 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2005 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2006 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2007 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2008 { "VAD_ADC", NULL, "VAD ADC Mux" },
2009
1319b2f6
OC		 2010 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2011 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2012 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2013
2014 { "IF1 ADC", NULL, "I2S1" },
1319b2f6
OC		 2015 { "IF2 ADC", NULL, "I2S2" },
2016 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2017
1319b2f6
OC		 2018 { "AIF2TX", NULL, "IF2 ADC" },
2019
21ab3f2b 2020 { "IF1 DAC0", NULL, "AIF1RX" },
1319b2f6
OC		 2021 { "IF1 DAC1", NULL, "AIF1RX" },
2022 { "IF1 DAC2", NULL, "AIF1RX" },
21ab3f2b 2023 { "IF1 DAC3", NULL, "AIF1RX" },
1319b2f6
OC		 2024 { "IF2 DAC", NULL, "AIF2RX" },
2025
21ab3f2b 2026 { "IF1 DAC0", NULL, "I2S1" },
1319b2f6
OC		 2027 { "IF1 DAC1", NULL, "I2S1" },
2028 { "IF1 DAC2", NULL, "I2S1" },
21ab3f2b 2029 { "IF1 DAC3", NULL, "I2S1" },
1319b2f6
OC		 2030 { "IF2 DAC", NULL, "I2S2" },
2031
1319b2f6
OC		 2032 { "IF2 DAC L", NULL, "IF2 DAC" },
2033 { "IF2 DAC R", NULL, "IF2 DAC" },
2034
1319b2f6 2035 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1319b2f6
OC		 2036 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2037
2038 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2039 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2040 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2041 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2042 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2043 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2044
1319b2f6
OC		 2045 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2046 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2047 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2048 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2049 { "DAC L2 Volume", NULL, "dac mono left filter" },
2050
1319b2f6
OC		 2051 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2052 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2053 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2054 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2055 { "DAC R2 Volume", NULL, "dac mono right filter" },
2056
2057 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2058 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2059 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2060 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2061 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2062 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2063 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2064 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2065
2066 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2067 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2068 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2069 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2070 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2071 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2072 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2073 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2074
2075 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2076 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2077 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2078 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2079 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2080 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2081
1319b2f6 2082 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2083 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2084 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6
OC		 2085 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2086
2087 { "SPK MIXL", "BST1 Switch", "BST1" },
2088 { "SPK MIXL", "INL Switch", "INL VOL" },
2089 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2090 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2091 { "SPK MIXR", "BST2 Switch", "BST2" },
2092 { "SPK MIXR", "INR Switch", "INR VOL" },
2093 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2094 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2095
2096 { "OUT MIXL", "BST1 Switch", "BST1" },
2097 { "OUT MIXL", "INL Switch", "INL VOL" },
2098 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2099 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2100
2101 { "OUT MIXR", "BST2 Switch", "BST2" },
2102 { "OUT MIXR", "INR Switch", "INR VOL" },
2103 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2104 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2105
2106 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2107 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2108 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2109 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2110 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2111 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2112 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2113 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2114 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2115 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2116
2117 { "DAC 2", NULL, "DAC L2" },
2118 { "DAC 2", NULL, "DAC R2" },
2119 { "DAC 1", NULL, "DAC L1" },
2120 { "DAC 1", NULL, "DAC R1" },
2121 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2122 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2123 { "HPOVOL", NULL, "HPOVOL L" },
2124 { "HPOVOL", NULL, "HPOVOL R" },
2125 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2126 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2127
2128 { "SPKVOL L", "Switch", "SPK MIXL" },
2129 { "SPKVOL R", "Switch", "SPK MIXR" },
2130
2131 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2132 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2133 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2134 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2135 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2136 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2137
2138 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2139 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2140 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2141 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2142
2143 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2144 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2145 { "PDM1 L Mux", NULL, "PDM1 Power" },
2146 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2147 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2148 { "PDM1 R Mux", NULL, "PDM1 Power" },
2149
2150 { "HP amp", NULL, "HPO MIX" },
2151 { "HP amp", NULL, "JD Power" },
2152 { "HP amp", NULL, "Mic Det Power" },
2153 { "HP amp", NULL, "LDO2" },
2154 { "HPOL", NULL, "HP amp" },
2155 { "HPOR", NULL, "HP amp" },
2156
2157 { "LOUT amp", NULL, "LOUT MIX" },
2158 { "LOUTL", NULL, "LOUT amp" },
2159 { "LOUTR", NULL, "LOUT amp" },
2160
2161 { "PDM1 L", "Switch", "PDM1 L Mux" },
2162 { "PDM1 R", "Switch", "PDM1 R Mux" },
2163
2164 { "PDM1L", NULL, "PDM1 L" },
2165 { "PDM1R", NULL, "PDM1 R" },
2166
2167 { "SPK amp", NULL, "SPOL MIX" },
2168 { "SPK amp", NULL, "SPOR MIX" },
2169 { "SPOL", NULL, "SPK amp" },
2170 { "SPOR", NULL, "SPK amp" },
2171};
2172
5c4ca99d
BL		 2173static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2174 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2175 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2176 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2177 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2178
2179 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2180 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2181 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2182 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2183
2184 { "DAC L1", NULL, "A DAC1 L Mux" },
2185 { "DAC R1", NULL, "A DAC1 R Mux" },
2186 { "DAC L2", NULL, "A DAC2 L Mux" },
2187 { "DAC R2", NULL, "A DAC2 R Mux" },
21ab3f2b
BL		 2188
2189 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2190 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2191 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2192 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2193
2194 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2195 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2196 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2197 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2198
2199 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2200 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2201 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2202 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2203
2204 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2205 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2206 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2207
2208 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2209 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2210 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2211 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2212 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2213 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2214
2215 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2216 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2217 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2218 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2219 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2220 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2221
2222 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2223 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2224 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2225 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2226 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2227 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2228
2229 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2230 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2231 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2232 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2233 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2234 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2235 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2236
2237 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2238 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2239 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2240 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2241
2242 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2243 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2244 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2245 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2246
2247 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2248 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2249 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2250 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2251
2252 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2253 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2254 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2255 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2256
2257 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2258 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2259
2260 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2261 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2262};
2263
2264static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2265 { "DAC L1", NULL, "Stereo DAC MIXL" },
2266 { "DAC R1", NULL, "Stereo DAC MIXR" },
2267 { "DAC L2", NULL, "Mono DAC MIXL" },
2268 { "DAC R2", NULL, "Mono DAC MIXR" },
21ab3f2b
BL		 2269
2270 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2271 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2272 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2273 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2274
2275 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2276 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2277 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2278 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2279
2280 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2281 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2282 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2283 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2284
2285 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2286 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2287 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2288
2289 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2290 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2291 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2292 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2293 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2294
2295 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2296 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2297 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2298 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2299
2300 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2301 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2302 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2303 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2304
2305 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2306 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2307 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2308 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2309
2310 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2311 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2312 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2313 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2314
2315 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2316 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2317
2318 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2319 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2320};
2321
1319b2f6
OC		 2322static int rt5645_hw_params(struct snd_pcm_substream *substream,
2323 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2324{
2325 struct snd_soc_codec *codec = dai->codec;
2326 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736 2327 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
1319b2f6
OC		 2328 int pre_div, bclk_ms, frame_size;
2329
2330 rt5645->lrck[dai->id] = params_rate(params);
d92950e7 2331 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1319b2f6
OC		 2332 if (pre_div < 0) {
2333 dev_err(codec->dev, "Unsupported clock setting\n");
2334 return -EINVAL;
2335 }
2336 frame_size = snd_soc_params_to_frame_size(params);
2337 if (frame_size < 0) {
2338 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2339 return -EINVAL;
2340 }
57bf2736
BL		 2341
2342 switch (rt5645->codec_type) {
2343 case CODEC_TYPE_RT5650:
2344 dl_sft = 4;
2345 break;
2346 default:
2347 dl_sft = 2;
2348 break;
2349 }
2350
1319b2f6
OC		 2351 bclk_ms = frame_size > 32;
2352 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2353
2354 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2355 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2356 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2357 bclk_ms, pre_div, dai->id);
2358
2359 switch (params_width(params)) {
2360 case 16:
2361 break;
2362 case 20:
57bf2736 2363 val_len = 0x1;
1319b2f6
OC		 2364 break;
2365 case 24:
57bf2736 2366 val_len = 0x2;
1319b2f6
OC		 2367 break;
2368 case 8:
57bf2736 2369 val_len = 0x3;
1319b2f6
OC		 2370 break;
2371 default:
2372 return -EINVAL;
2373 }
2374
2375 switch (dai->id) {
2376 case RT5645_AIF1:
33de3d54
BL		 2377 mask_clk = RT5645_I2S_PD1_MASK;
2378 val_clk = pre_div << RT5645_I2S_PD1_SFT;
1319b2f6 2379 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2380 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2381 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2382 break;
2383 case RT5645_AIF2:
2384 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2385 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2386 pre_div << RT5645_I2S_PD2_SFT;
2387 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2388 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2389 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2390 break;
2391 default:
2392 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2393 return -EINVAL;
2394 }
2395
2396 return 0;
2397}
2398
2399static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2400{
2401 struct snd_soc_codec *codec = dai->codec;
2402 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736
BL		 2403 unsigned int reg_val = 0, pol_sft;
2404
2405 switch (rt5645->codec_type) {
2406 case CODEC_TYPE_RT5650:
2407 pol_sft = 8;
2408 break;
2409 default:
2410 pol_sft = 7;
2411 break;
2412 }
1319b2f6
OC		 2413
2414 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2415 case SND_SOC_DAIFMT_CBM_CFM:
2416 rt5645->master[dai->id] = 1;
2417 break;
2418 case SND_SOC_DAIFMT_CBS_CFS:
2419 reg_val |= RT5645_I2S_MS_S;
2420 rt5645->master[dai->id] = 0;
2421 break;
2422 default:
2423 return -EINVAL;
2424 }
2425
2426 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2427 case SND_SOC_DAIFMT_NB_NF:
2428 break;
2429 case SND_SOC_DAIFMT_IB_NF:
57bf2736 2430 reg_val |= (1 << pol_sft);
1319b2f6
OC		 2431 break;
2432 default:
2433 return -EINVAL;
2434 }
2435
2436 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2437 case SND_SOC_DAIFMT_I2S:
2438 break;
2439 case SND_SOC_DAIFMT_LEFT_J:
2440 reg_val |= RT5645_I2S_DF_LEFT;
2441 break;
2442 case SND_SOC_DAIFMT_DSP_A:
2443 reg_val |= RT5645_I2S_DF_PCM_A;
2444 break;
2445 case SND_SOC_DAIFMT_DSP_B:
2446 reg_val |= RT5645_I2S_DF_PCM_B;
2447 break;
2448 default:
2449 return -EINVAL;
2450 }
2451 switch (dai->id) {
2452 case RT5645_AIF1:
2453 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2454 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2455 RT5645_I2S_DF_MASK, reg_val);
2456 break;
8c325704
AL		 2457 case RT5645_AIF2:
2458 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2459 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2460 RT5645_I2S_DF_MASK, reg_val);
2461 break;
2462 default:
2463 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2464 return -EINVAL;
2465 }
2466 return 0;
2467}
2468
2469static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2470 int clk_id, unsigned int freq, int dir)
2471{
2472 struct snd_soc_codec *codec = dai->codec;
2473 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2474 unsigned int reg_val = 0;
2475
2476 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2477 return 0;
2478
2479 switch (clk_id) {
2480 case RT5645_SCLK_S_MCLK:
2481 reg_val |= RT5645_SCLK_SRC_MCLK;
2482 break;
2483 case RT5645_SCLK_S_PLL1:
2484 reg_val |= RT5645_SCLK_SRC_PLL1;
2485 break;
2486 case RT5645_SCLK_S_RCCLK:
2487 reg_val |= RT5645_SCLK_SRC_RCCLK;
2488 break;
2489 default:
2490 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2491 return -EINVAL;
2492 }
2493 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2494 RT5645_SCLK_SRC_MASK, reg_val);
2495 rt5645->sysclk = freq;
2496 rt5645->sysclk_src = clk_id;
2497
2498 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2499
2500 return 0;
2501}
2502
1319b2f6
OC		 2503static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2504 unsigned int freq_in, unsigned int freq_out)
2505{
2506 struct snd_soc_codec *codec = dai->codec;
2507 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
71c7a2d6 2508 struct rl6231_pll_code pll_code;
1319b2f6
OC		 2509 int ret;
2510
2511 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2512 freq_out == rt5645->pll_out)
2513 return 0;
2514
2515 if (!freq_in || !freq_out) {
2516 dev_dbg(codec->dev, "PLL disabled\n");
2517
2518 rt5645->pll_in = 0;
2519 rt5645->pll_out = 0;
2520 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2521 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2522 return 0;
2523 }
2524
2525 switch (source) {
2526 case RT5645_PLL1_S_MCLK:
2527 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2528 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2529 break;
2530 case RT5645_PLL1_S_BCLK1:
2531 case RT5645_PLL1_S_BCLK2:
2532 switch (dai->id) {
2533 case RT5645_AIF1:
2534 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2535 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2536 break;
2537 case RT5645_AIF2:
2538 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2539 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2540 break;
2541 default:
2542 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2543 return -EINVAL;
2544 }
2545 break;
2546 default:
2547 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2548 return -EINVAL;
2549 }
2550
71c7a2d6 2551 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1319b2f6
OC		 2552 if (ret < 0) {
2553 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2554 return ret;
2555 }
2556
2557 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2558 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2559 pll_code.n_code, pll_code.k_code);
2560
2561 snd_soc_write(codec, RT5645_PLL_CTRL1,
2562 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2563 snd_soc_write(codec, RT5645_PLL_CTRL2,
2564 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2565 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2566
2567 rt5645->pll_in = freq_in;
2568 rt5645->pll_out = freq_out;
2569 rt5645->pll_src = source;
2570
2571 return 0;
2572}
2573
2574static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2575 unsigned int rx_mask, int slots, int slot_width)
2576{
2577 struct snd_soc_codec *codec = dai->codec;
42ce5b8a
BL		 2578 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2579 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2580 unsigned int mask, val = 0;
2581
2582 switch (rt5645->codec_type) {
2583 case CODEC_TYPE_RT5650:
2584 en_sft = 15;
2585 i_slot_sft = 10;
2586 o_slot_sft = 8;
2587 i_width_sht = 6;
2588 o_width_sht = 4;
2589 mask = 0x8ff0;
2590 break;
2591 default:
2592 en_sft = 14;
2593 i_slot_sft = o_slot_sft = 12;
2594 i_width_sht = o_width_sht = 10;
2595 mask = 0x7c00;
2596 break;
2597 }
850577db 2598 if (rx_mask || tx_mask) {
42ce5b8a
BL		 2599 val |= (1 << en_sft);
2600 if (rt5645->codec_type == CODEC_TYPE_RT5645)
2601 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2602 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
850577db 2603 }
1319b2f6
OC		 2604
2605 switch (slots) {
2606 case 4:
42ce5b8a 2607 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
1319b2f6
OC		 2608 break;
2609 case 6:
42ce5b8a 2610 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
1319b2f6
OC		 2611 break;
2612 case 8:
42ce5b8a 2613 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
1319b2f6
OC		 2614 break;
2615 case 2:
2616 default:
2617 break;
2618 }
2619
2620 switch (slot_width) {
2621 case 20:
42ce5b8a 2622 val |= (1 << i_width_sht) | (1 << o_width_sht);
1319b2f6
OC		 2623 break;
2624 case 24:
42ce5b8a 2625 val |= (2 << i_width_sht) | (2 << o_width_sht);
1319b2f6
OC		 2626 break;
2627 case 32:
42ce5b8a 2628 val |= (3 << i_width_sht) | (3 << o_width_sht);
1319b2f6
OC		 2629 break;
2630 case 16:
2631 default:
2632 break;
2633 }
2634
42ce5b8a 2635 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
1319b2f6
OC		 2636
2637 return 0;
2638}
2639
2640static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2641 enum snd_soc_bias_level level)
2642{
6e747d53
BL		 2643 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2644
1319b2f6 2645 switch (level) {
0b2e4959 2646 case SND_SOC_BIAS_PREPARE:
e2ada818 2647 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
1319b2f6
OC		 2648 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2649 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2650 RT5645_PWR_BG | RT5645_PWR_VREF2,
2651 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2652 RT5645_PWR_BG | RT5645_PWR_VREF2);
2653 mdelay(10);
2654 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2655 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2656 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2657 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2658 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2659 }
2660 break;
2661
0b2e4959
BL		 2662 case SND_SOC_BIAS_STANDBY:
2663 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2664 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2665 RT5645_PWR_BG | RT5645_PWR_VREF2,
2666 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2667 RT5645_PWR_BG | RT5645_PWR_VREF2);
2668 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2669 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2670 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2671 break;
2672
1319b2f6
OC		 2673 case SND_SOC_BIAS_OFF:
2674 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
6e747d53
BL		 2675 if (!rt5645->en_button_func)
2676 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2677 RT5645_DIG_GATE_CTRL, 0);
0b2e4959
BL		 2678 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2679 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2680 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2681 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
1319b2f6
OC		 2682 break;
2683
2684 default:
2685 break;
2686 }
1319b2f6
OC		 2687
2688 return 0;
2689}
2690
d12d6c4e
JL		 2691static int rt5650_calibration(struct rt5645_priv *rt5645)
2692{
2693 int val, i;
2694 int ret = -1;
2695
2696 regcache_cache_bypass(rt5645->regmap, true);
2697 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2698 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0800);
2699 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_CHOP_DAC_ADC,
2700 0x3600);
2701 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x25, 0x7000);
2702 regmap_write(rt5645->regmap, RT5645_I2S1_SDP, 0x8008);
2703 /* headset type */
2704 regmap_write(rt5645->regmap, RT5645_GEN_CTRL1, 0x2061);
2705 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2706 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0x2012);
2707 regmap_write(rt5645->regmap, RT5645_PWR_MIXER, 0x0002);
2708 regmap_write(rt5645->regmap, RT5645_PWR_VOL, 0x0020);
2709 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2710 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2711 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x1827);
2712 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x0827);
2713 msleep(400);
2714 /* Inline command */
2715 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0001);
2716 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2717 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2718 /* Calbration */
2719 regmap_write(rt5645->regmap, RT5645_GLB_CLK, 0x8000);
2720 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2721 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2722 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2723 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x8800);
2724 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0xe8fa);
2725 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x8c04);
2726 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x3100);
2727 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
2728 regmap_write(rt5645->regmap, RT5645_BASS_BACK, 0x8a13);
2729 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0820);
2730 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x000d);
2731 /* Power on and Calbration */
2732 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_HP_DCC_INT1,
2733 0x9f01);
2734 msleep(200);
2735 for (i = 0; i < 5; i++) {
2736 regmap_read(rt5645->regmap, RT5645_PR_BASE + 0x7a, &val);
2737 if (val != 0 && val != 0x3f3f) {
2738 ret = 0;
2739 break;
2740 }
2741 msleep(50);
2742 }
2743 pr_debug("%s: PR-7A = 0x%x\n", __func__, val);
2744
2745 /* mute */
2746 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x3e, 0x7400);
2747 regmap_write(rt5645->regmap, RT5645_DEPOP_M3, 0x0737);
2748 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_MAMP_INT_REG2,
2749 0xfc00);
2750 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x1140);
2751 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2752 regmap_write(rt5645->regmap, RT5645_GEN_CTRL2, 0x4020);
2753 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x0006);
2754 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x0000);
2755 msleep(350);
2756
2757 regcache_cache_bypass(rt5645->regmap, false);
2758
2759 return ret;
2760}
2761
6e747d53
BL		 2762static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
2763 bool enable)
f3fa1bbd 2764{
e2ada818 2765 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
f3fa1bbd 2766 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
f3fa1bbd 2767
6e747d53 2768 if (enable) {
e2ada818
LPC		 2769 snd_soc_dapm_mutex_lock(dapm);
2770 snd_soc_dapm_force_enable_pin_unlocked(dapm, "ADC L power");
2771 snd_soc_dapm_force_enable_pin_unlocked(dapm, "ADC R power");
2772 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
2773 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Mic Det Power");
2774 snd_soc_dapm_sync_unlocked(dapm);
2775 snd_soc_dapm_mutex_unlock(dapm);
22f5d9f8 2776
6e747d53
BL		 2777 snd_soc_update_bits(codec,
2778 RT5645_INT_IRQ_ST, 0x8, 0x8);
2779 snd_soc_update_bits(codec,
2780 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
2781 snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2782 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
2783 snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
2784 } else {
2785 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
2786 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
22f5d9f8 2787
e2ada818
LPC		 2788 snd_soc_dapm_mutex_lock(dapm);
2789 snd_soc_dapm_disable_pin_unlocked(dapm, "ADC L power");
2790 snd_soc_dapm_disable_pin_unlocked(dapm, "ADC R power");
6e747d53 2791 if (rt5645->pdata.jd_mode == 0)
e2ada818
LPC		 2792 snd_soc_dapm_disable_pin_unlocked(dapm, "LDO2");
2793 snd_soc_dapm_disable_pin_unlocked(dapm, "Mic Det Power");
2794 snd_soc_dapm_sync_unlocked(dapm);
2795 snd_soc_dapm_mutex_unlock(dapm);
75945896 2796 }
6e747d53 2797}
f3fa1bbd 2798
6e747d53
BL		 2799static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
2800{
e2ada818 2801 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
6e747d53
BL		 2802 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2803 unsigned int val;
f3fa1bbd 2804
6e747d53 2805 if (jack_insert) {
05a9b46a
JL		 2806 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2807
b14c9174
NB		 2808 /* for jack type detect */
2809 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
2810 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
2811 snd_soc_dapm_sync(dapm);
2812 if (!dapm->card->instantiated) {
6e747d53
BL		 2813 /* Power up necessary bits for JD if dapm is
2814 not ready yet */
05a9b46a
JL		 2815 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
2816 RT5645_PWR_MB | RT5645_PWR_VREF2,
2817 RT5645_PWR_MB | RT5645_PWR_VREF2);
2818 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
6e747d53 2819 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
05a9b46a 2820 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
6e747d53
BL		 2821 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
2822 }
f3fa1bbd 2823
05a9b46a
JL		 2824 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2825 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2826 regmap_update_bits(rt5645->regmap,
2827 RT5645_IN1_CTRL2, 0x1000, 0x1000);
2828 msleep(100);
2829 regmap_update_bits(rt5645->regmap,
2830 RT5645_IN1_CTRL2, 0x1000, 0x0000);
2831
2832 msleep(450);
2833 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
2834 val &= 0x7;
f3fa1bbd
OC		 2835 dev_dbg(codec->dev, "val = %d\n", val);
2836
6e747d53
BL		 2837 if (val == 1 || val == 2) {
2838 rt5645->jack_type = SND_JACK_HEADSET;
2839 if (rt5645->en_button_func) {
6e747d53
BL		 2840 rt5645_enable_push_button_irq(codec, true);
2841 }
2842 } else {
b14c9174
NB		 2843 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
2844 snd_soc_dapm_sync(dapm);
6e747d53
BL		 2845 rt5645->jack_type = SND_JACK_HEADPHONE;
2846 }
2847
2848 } else { /* jack out */
2849 rt5645->jack_type = 0;
2850 if (rt5645->en_button_func)
2851 rt5645_enable_push_button_irq(codec, false);
b7f22478 2852 else {
b14c9174
NB		 2853 if (rt5645->pdata.jd_mode == 0)
2854 snd_soc_dapm_disable_pin(dapm, "LDO2");
2855 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
2856 snd_soc_dapm_sync(dapm);
b7f22478 2857 }
f3fa1bbd
OC		 2858 }
2859
6e747d53 2860 return rt5645->jack_type;
f3fa1bbd
OC		 2861}
2862
f312bc59
NB		 2863static int rt5645_button_detect(struct snd_soc_codec *codec)
2864{
2865 int btn_type, val;
2866
2867 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2868 pr_debug("val=0x%x\n", val);
2869 btn_type = val & 0xfff0;
2870 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
2871
2872 return btn_type;
2873}
2874
345b0f50 2875static irqreturn_t rt5645_irq(int irq, void *data);
d5660422 2876
f3fa1bbd 2877int rt5645_set_jack_detect(struct snd_soc_codec *codec,
6e747d53
BL		 2878 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
2879 struct snd_soc_jack *btn_jack)
f3fa1bbd
OC		 2880{
2881 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2882
471f208a
BL		 2883 rt5645->hp_jack = hp_jack;
2884 rt5645->mic_jack = mic_jack;
6e747d53
BL		 2885 rt5645->btn_jack = btn_jack;
2886 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
2887 rt5645->en_button_func = true;
2888 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2889 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2890 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
2891 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
2892 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
2893 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2894 }
345b0f50 2895 rt5645_irq(0, rt5645);
f3fa1bbd
OC		 2896
2897 return 0;
2898}
2899EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2900
cd6e82b8
OC		 2901static void rt5645_jack_detect_work(struct work_struct *work)
2902{
2903 struct rt5645_priv *rt5645 =
2904 container_of(work, struct rt5645_priv, jack_detect_work.work);
6e747d53
BL		 2905 int val, btn_type, gpio_state = 0, report = 0;
2906
2907 switch (rt5645->pdata.jd_mode) {
2908 case 0: /* Not using rt5645 JD */
0b0cefc8
OC		 2909 if (rt5645->gpiod_hp_det) {
2910 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
2911 dev_dbg(rt5645->codec->dev, "gpio_state = %d\n",
2912 gpio_state);
2913 report = rt5645_jack_detect(rt5645->codec, gpio_state);
6e747d53
BL		 2914 }
2915 snd_soc_jack_report(rt5645->hp_jack,
2916 report, SND_JACK_HEADPHONE);
2917 snd_soc_jack_report(rt5645->mic_jack,
2918 report, SND_JACK_MICROPHONE);
f312bc59 2919 return;
6e747d53
BL		 2920 case 1: /* 2 port */
2921 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070;
2922 break;
2923 default: /* 1 port */
2924 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020;
2925 break;
2926
2927 }
2928
2929 switch (val) {
2930 /* jack in */
2931 case 0x30: /* 2 port */
2932 case 0x0: /* 1 port or 2 port */
2933 if (rt5645->jack_type == 0) {
2934 report = rt5645_jack_detect(rt5645->codec, 1);
2935 /* for push button and jack out */
2936 break;
2937 }
2938 btn_type = 0;
2939 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
2940 /* button pressed */
2941 report = SND_JACK_HEADSET;
2942 btn_type = rt5645_button_detect(rt5645->codec);
2943 /* rt5650 can report three kinds of button behavior,
2944 one click, double click and hold. However,
2945 currently we will report button pressed/released
2946 event. So all the three button behaviors are
2947 treated as button pressed. */
2948 switch (btn_type) {
2949 case 0x8000:
2950 case 0x4000:
2951 case 0x2000:
2952 report |= SND_JACK_BTN_0;
2953 break;
2954 case 0x1000:
2955 case 0x0800:
2956 case 0x0400:
2957 report |= SND_JACK_BTN_1;
2958 break;
2959 case 0x0200:
2960 case 0x0100:
2961 case 0x0080:
2962 report |= SND_JACK_BTN_2;
2963 break;
2964 case 0x0040:
2965 case 0x0020:
2966 case 0x0010:
2967 report |= SND_JACK_BTN_3;
2968 break;
2969 case 0x0000: /* unpressed */
2970 break;
2971 default:
2972 dev_err(rt5645->codec->dev,
2973 "Unexpected button code 0x%04x\n",
2974 btn_type);
2975 break;
2976 }
2977 }
2978 if (btn_type == 0)/* button release */
2979 report = rt5645->jack_type;
2980
2981 break;
2982 /* jack out */
2983 case 0x70: /* 2 port */
2984 case 0x10: /* 2 port */
2985 case 0x20: /* 1 port */
2986 report = 0;
2987 snd_soc_update_bits(rt5645->codec,
2988 RT5645_INT_IRQ_ST, 0x1, 0x0);
2989 rt5645_jack_detect(rt5645->codec, 0);
2990 break;
2991 default:
2992 break;
2993 }
2994
2995 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
2996 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
2997 if (rt5645->en_button_func)
2998 snd_soc_jack_report(rt5645->btn_jack,
e0b5d906
BL		 2999 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3000 SND_JACK_BTN_2 | SND_JACK_BTN_3);
f312bc59 3001}
6e747d53 3002
f312bc59
NB		 3003static irqreturn_t rt5645_irq(int irq, void *data)
3004{
3005 struct rt5645_priv *rt5645 = data;
3006
3007 queue_delayed_work(system_power_efficient_wq,
3008 &rt5645->jack_detect_work, msecs_to_jiffies(250));
3009
3010 return IRQ_HANDLED;
6e747d53
BL		 3011}
3012
1319b2f6
OC		 3013static int rt5645_probe(struct snd_soc_codec *codec)
3014{
e2ada818 3015 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1319b2f6
OC		 3016 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3017
3018 rt5645->codec = codec;
3019
5c4ca99d
BL		 3020 switch (rt5645->codec_type) {
3021 case CODEC_TYPE_RT5645:
f2a76385 3022 snd_soc_dapm_new_controls(dapm,
83c09290
BL		 3023 rt5645_specific_dapm_widgets,
3024 ARRAY_SIZE(rt5645_specific_dapm_widgets));
e2ada818 3025 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3026 rt5645_specific_dapm_routes,
3027 ARRAY_SIZE(rt5645_specific_dapm_routes));
3028 break;
3029 case CODEC_TYPE_RT5650:
e2ada818 3030 snd_soc_dapm_new_controls(dapm,
5c4ca99d
BL		 3031 rt5650_specific_dapm_widgets,
3032 ARRAY_SIZE(rt5650_specific_dapm_widgets));
e2ada818 3033 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3034 rt5650_specific_dapm_routes,
3035 ARRAY_SIZE(rt5650_specific_dapm_routes));
3036 break;
3037 }
3038
bd1204cb 3039 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
1319b2f6 3040
bb656add 3041 /* for JD function */
ac4fc3ee 3042 if (rt5645->pdata.jd_mode) {
e2ada818
LPC		 3043 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3044 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3045 snd_soc_dapm_sync(dapm);
bb656add
BL		 3046 }
3047
1319b2f6
OC		 3048 return 0;
3049}
3050
3051static int rt5645_remove(struct snd_soc_codec *codec)
3052{
3053 rt5645_reset(codec);
3054 return 0;
3055}
3056
3057#ifdef CONFIG_PM
3058static int rt5645_suspend(struct snd_soc_codec *codec)
3059{
3060 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3061
3062 regcache_cache_only(rt5645->regmap, true);
3063 regcache_mark_dirty(rt5645->regmap);
3064
3065 return 0;
3066}
3067
3068static int rt5645_resume(struct snd_soc_codec *codec)
3069{
3070 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3071
3072 regcache_cache_only(rt5645->regmap, false);
0f776efd 3073 regcache_sync(rt5645->regmap);
1319b2f6
OC		 3074
3075 return 0;
3076}
3077#else
3078#define rt5645_suspend NULL
3079#define rt5645_resume NULL
3080#endif
3081
3082#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3083#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3084 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3085
9e22f782 3086static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
1319b2f6
OC		 3087 .hw_params = rt5645_hw_params,
3088 .set_fmt = rt5645_set_dai_fmt,
3089 .set_sysclk = rt5645_set_dai_sysclk,
3090 .set_tdm_slot = rt5645_set_tdm_slot,
3091 .set_pll = rt5645_set_dai_pll,
3092};
3093
9e22f782 3094static struct snd_soc_dai_driver rt5645_dai[] = {
1319b2f6
OC		 3095 {
3096 .name = "rt5645-aif1",
3097 .id = RT5645_AIF1,
3098 .playback = {
3099 .stream_name = "AIF1 Playback",
3100 .channels_min = 1,
3101 .channels_max = 2,
3102 .rates = RT5645_STEREO_RATES,
3103 .formats = RT5645_FORMATS,
3104 },
3105 .capture = {
3106 .stream_name = "AIF1 Capture",
3107 .channels_min = 1,
3108 .channels_max = 2,
3109 .rates = RT5645_STEREO_RATES,
3110 .formats = RT5645_FORMATS,
3111 },
3112 .ops = &rt5645_aif_dai_ops,
3113 },
3114 {
3115 .name = "rt5645-aif2",
3116 .id = RT5645_AIF2,
3117 .playback = {
3118 .stream_name = "AIF2 Playback",
3119 .channels_min = 1,
3120 .channels_max = 2,
3121 .rates = RT5645_STEREO_RATES,
3122 .formats = RT5645_FORMATS,
3123 },
3124 .capture = {
3125 .stream_name = "AIF2 Capture",
3126 .channels_min = 1,
3127 .channels_max = 2,
3128 .rates = RT5645_STEREO_RATES,
3129 .formats = RT5645_FORMATS,
3130 },
3131 .ops = &rt5645_aif_dai_ops,
3132 },
3133};
3134
3135static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
3136 .probe = rt5645_probe,
3137 .remove = rt5645_remove,
3138 .suspend = rt5645_suspend,
3139 .resume = rt5645_resume,
3140 .set_bias_level = rt5645_set_bias_level,
3141 .idle_bias_off = true,
3142 .controls = rt5645_snd_controls,
3143 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3144 .dapm_widgets = rt5645_dapm_widgets,
3145 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3146 .dapm_routes = rt5645_dapm_routes,
3147 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3148};
3149
3150static const struct regmap_config rt5645_regmap = {
3151 .reg_bits = 8,
3152 .val_bits = 16,
afefc128 3153 .use_single_rw = true,
1319b2f6
OC		 3154 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3155 RT5645_PR_SPACING),
3156 .volatile_reg = rt5645_volatile_register,
3157 .readable_reg = rt5645_readable_register,
3158
3159 .cache_type = REGCACHE_RBTREE,
3160 .reg_defaults = rt5645_reg,
3161 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3162 .ranges = rt5645_ranges,
3163 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3164};
3165
3166static const struct i2c_device_id rt5645_i2c_id[] = {
3167 { "rt5645", 0 },
5c4ca99d 3168 { "rt5650", 0 },
1319b2f6
OC		 3169 { }
3170};
3171MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3172
3168c201
FY		 3173#ifdef CONFIG_ACPI
3174static struct acpi_device_id rt5645_acpi_match[] = {
3175 { "10EC5645", 0 },
3176 { "10EC5650", 0 },
3177 {},
3178};
3179MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3180#endif
3181
78c34fd4
FY		 3182static struct rt5645_platform_data *rt5645_pdata;
3183
3184static struct rt5645_platform_data strago_platform_data = {
ac4fc3ee 3185 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
78c34fd4 3186 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
78c34fd4
FY		 3187 .jd_mode = 3,
3188};
3189
3190static int strago_quirk_cb(const struct dmi_system_id *id)
3191{
3192 rt5645_pdata = &strago_platform_data;
3193
3194 return 1;
3195}
3196
0bc7d10c 3197static const struct dmi_system_id dmi_platform_intel_braswell[] = {
78c34fd4
FY		 3198 {
3199 .ident = "Intel Strago",
3200 .callback = strago_quirk_cb,
3201 .matches = {
3202 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3203 },
3204 },
3205 { }
3206};
3207
48edaa4b
OC		 3208static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3209{
3210 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3211 "realtek,in2-differential");
3212 device_property_read_u32(dev,
3213 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3214 device_property_read_u32(dev,
3215 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3216 device_property_read_u32(dev,
3217 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3218
3219 return 0;
3220}
3221
1319b2f6
OC		 3222static int rt5645_i2c_probe(struct i2c_client *i2c,
3223 const struct i2c_device_id *id)
3224{
3225 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3226 struct rt5645_priv *rt5645;
3227 int ret;
3228 unsigned int val;
3229
3230 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3231 GFP_KERNEL);
3232 if (rt5645 == NULL)
3233 return -ENOMEM;
3234
f3fa1bbd 3235 rt5645->i2c = i2c;
1319b2f6
OC		 3236 i2c_set_clientdata(i2c, rt5645);
3237
48edaa4b 3238 if (pdata)
1319b2f6 3239 rt5645->pdata = *pdata;
48edaa4b
OC		 3240 else if (dmi_check_system(dmi_platform_intel_braswell))
3241 rt5645->pdata = *rt5645_pdata;
3242 else
3243 rt5645_parse_dt(rt5645, &i2c->dev);
1319b2f6 3244
25c8888a
AL		 3245 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3246 GPIOD_IN);
0b0cefc8
OC		 3247
3248 if (IS_ERR(rt5645->gpiod_hp_det)) {
0b0cefc8 3249 dev_err(&i2c->dev, "failed to initialize gpiod\n");
25c8888a 3250 return PTR_ERR(rt5645->gpiod_hp_det);
0b0cefc8
OC		 3251 }
3252
1319b2f6
OC		 3253 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3254 if (IS_ERR(rt5645->regmap)) {
3255 ret = PTR_ERR(rt5645->regmap);
3256 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3257 ret);
3258 return ret;
3259 }
3260
3261 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
5c4ca99d
BL		 3262
3263 switch (val) {
3264 case RT5645_DEVICE_ID:
3265 rt5645->codec_type = CODEC_TYPE_RT5645;
3266 break;
3267 case RT5650_DEVICE_ID:
3268 rt5645->codec_type = CODEC_TYPE_RT5650;
3269 break;
3270 default:
1319b2f6 3271 dev_err(&i2c->dev,
8f68e80f 3272 "Device with ID register %#x is not rt5645 or rt5650\n",
5c4ca99d 3273 val);
1319b2f6
OC		 3274 return -ENODEV;
3275 }
3276
d12d6c4e
JL		 3277 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3278 ret = rt5650_calibration(rt5645);
3279
3280 if (ret < 0)
3281 pr_err("calibration failed!\n");
3282 }
3283
1319b2f6
OC		 3284 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3285
3286 ret = regmap_register_patch(rt5645->regmap, init_list,
3287 ARRAY_SIZE(init_list));
3288 if (ret != 0)
3289 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3290
5c4ca99d
BL		 3291 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3292 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3293 ARRAY_SIZE(rt5650_init_list));
3294 if (ret != 0)
3295 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3296 ret);
3297 }
3298
1319b2f6
OC		 3299 if (rt5645->pdata.in2_diff)
3300 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3301 RT5645_IN_DF2, RT5645_IN_DF2);
3302
ac4fc3ee 3303 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
1319b2f6
OC		 3304 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3305 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
ac4fc3ee
BL		 3306 }
3307 switch (rt5645->pdata.dmic1_data_pin) {
3308 case RT5645_DMIC_DATA_IN2N:
3309 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3310 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3311 break;
1319b2f6 3312
ac4fc3ee
BL		 3313 case RT5645_DMIC_DATA_GPIO5:
3314 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3315 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3316 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3317 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3318 break;
1319b2f6 3319
ac4fc3ee
BL		 3320 case RT5645_DMIC_DATA_GPIO11:
3321 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3322 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3323 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3324 RT5645_GP11_PIN_MASK,
3325 RT5645_GP11_PIN_DMIC1_SDA);
3326 break;
1319b2f6 3327
ac4fc3ee
BL		 3328 default:
3329 break;
3330 }
1319b2f6 3331
ac4fc3ee
BL		 3332 switch (rt5645->pdata.dmic2_data_pin) {
3333 case RT5645_DMIC_DATA_IN2P:
3334 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3335 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3336 break;
1319b2f6 3337
ac4fc3ee
BL		 3338 case RT5645_DMIC_DATA_GPIO6:
3339 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3340 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3341 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3342 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3343 break;
1319b2f6 3344
ac4fc3ee
BL		 3345 case RT5645_DMIC_DATA_GPIO10:
3346 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3347 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3348 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3349 RT5645_GP10_PIN_MASK,
3350 RT5645_GP10_PIN_DMIC2_SDA);
3351 break;
1319b2f6 3352
ac4fc3ee
BL		 3353 case RT5645_DMIC_DATA_GPIO12:
3354 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3355 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3356 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3357 RT5645_GP12_PIN_MASK,
3358 RT5645_GP12_PIN_DMIC2_SDA);
3359 break;
1319b2f6 3360
ac4fc3ee
BL		 3361 default:
3362 break;
1319b2f6
OC		 3363 }
3364
ac4fc3ee 3365 if (rt5645->pdata.jd_mode) {
bb656add 3366 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
ac4fc3ee
BL		 3367 RT5645_IRQ_CLK_GATE_CTRL,
3368 RT5645_IRQ_CLK_GATE_CTRL);
bb656add 3369 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
ac4fc3ee 3370 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
bb656add 3371 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
ac4fc3ee 3372 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2d4e2d02
BL		 3373 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3374 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3375 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3376 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3377 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3378 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3379 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3380 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
3381 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3382 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3383 switch (rt5645->pdata.jd_mode) {
3384 case 1:
3385 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3386 RT5645_JD1_MODE_MASK,
3387 RT5645_JD1_MODE_0);
3388 break;
3389 case 2:
3390 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3391 RT5645_JD1_MODE_MASK,
3392 RT5645_JD1_MODE_1);
3393 break;
3394 case 3:
3395 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3396 RT5645_JD1_MODE_MASK,
3397 RT5645_JD1_MODE_2);
3398 break;
3399 default:
3400 break;
3401 }
3402 }
3403
7ea3470a
NB		 3404 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
3405
f3fa1bbd
OC		 3406 if (rt5645->i2c->irq) {
3407 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
3408 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3409 | IRQF_ONESHOT, "rt5645", rt5645);
3410 if (ret)
3411 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3412 }
3413
dd56ebad
AL		 3414 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
3415 rt5645_dai, ARRAY_SIZE(rt5645_dai));
1319b2f6
OC		 3416}
3417
3418static int rt5645_i2c_remove(struct i2c_client *i2c)
3419{
f3fa1bbd
OC		 3420 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3421
3422 if (i2c->irq)
3423 free_irq(i2c->irq, rt5645);
3424
cd6e82b8
OC		 3425 cancel_delayed_work_sync(&rt5645->jack_detect_work);
3426
1319b2f6
OC		 3427 snd_soc_unregister_codec(&i2c->dev);
3428
3429 return 0;
3430}
3431
9e22f782 3432static struct i2c_driver rt5645_i2c_driver = {
1319b2f6
OC		 3433 .driver = {
3434 .name = "rt5645",
3435 .owner = THIS_MODULE,
3168c201 3436 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
1319b2f6
OC		 3437 },
3438 .probe = rt5645_i2c_probe,
3439 .remove = rt5645_i2c_remove,
3440 .id_table = rt5645_i2c_id,
3441};
3442module_i2c_driver(rt5645_i2c_driver);
3443
3444MODULE_DESCRIPTION("ASoC RT5645 driver");
3445MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3446MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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