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1319b2f6 OC |
1 | /* |
2 | * rt5645.h -- RT5645 ALSA SoC audio driver | |
3 | * | |
4 | * Copyright 2013 Realtek Microelectronics | |
5 | * Author: Bard Liao <bardliao@realtek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef __RT5645_H__ | |
13 | #define __RT5645_H__ | |
14 | ||
15 | #include <sound/rt5645.h> | |
16 | ||
17 | /* Info */ | |
18 | #define RT5645_RESET 0x00 | |
19 | #define RT5645_VENDOR_ID 0xfd | |
20 | #define RT5645_VENDOR_ID1 0xfe | |
21 | #define RT5645_VENDOR_ID2 0xff | |
22 | /* I/O - Output */ | |
23 | #define RT5645_SPK_VOL 0x01 | |
24 | #define RT5645_HP_VOL 0x02 | |
25 | #define RT5645_LOUT1 0x03 | |
26 | #define RT5645_LOUT_CTRL 0x05 | |
27 | /* I/O - Input */ | |
28 | #define RT5645_IN1_CTRL1 0x0a | |
29 | #define RT5645_IN1_CTRL2 0x0b | |
30 | #define RT5645_IN1_CTRL3 0x0c | |
31 | #define RT5645_IN2_CTRL 0x0d | |
32 | #define RT5645_INL1_INR1_VOL 0x0f | |
33 | #define RT5645_SPK_FUNC_LIM 0x14 | |
34 | #define RT5645_ADJ_HPF_CTRL 0x16 | |
35 | /* I/O - ADC/DAC/DMIC */ | |
36 | #define RT5645_DAC1_DIG_VOL 0x19 | |
37 | #define RT5645_DAC2_DIG_VOL 0x1a | |
38 | #define RT5645_DAC_CTRL 0x1b | |
39 | #define RT5645_STO1_ADC_DIG_VOL 0x1c | |
40 | #define RT5645_MONO_ADC_DIG_VOL 0x1d | |
41 | #define RT5645_ADC_BST_VOL1 0x1e | |
1319b2f6 | 42 | #define RT5645_ADC_BST_VOL2 0x20 |
8c1a9d63 | 43 | /* Mixer - D-D */ |
1319b2f6 OC |
44 | #define RT5645_STO1_ADC_MIXER 0x27 |
45 | #define RT5645_MONO_ADC_MIXER 0x28 | |
46 | #define RT5645_AD_DA_MIXER 0x29 | |
47 | #define RT5645_STO_DAC_MIXER 0x2a | |
48 | #define RT5645_MONO_DAC_MIXER 0x2b | |
49 | #define RT5645_DIG_MIXER 0x2c | |
5c4ca99d | 50 | #define RT5650_A_DAC_SOUR 0x2d |
1319b2f6 OC |
51 | #define RT5645_DIG_INF1_DATA 0x2f |
52 | /* Mixer - PDM */ | |
53 | #define RT5645_PDM_OUT_CTRL 0x31 | |
54 | /* Mixer - ADC */ | |
55 | #define RT5645_REC_L1_MIXER 0x3b | |
56 | #define RT5645_REC_L2_MIXER 0x3c | |
57 | #define RT5645_REC_R1_MIXER 0x3d | |
58 | #define RT5645_REC_R2_MIXER 0x3e | |
59 | /* Mixer - DAC */ | |
60 | #define RT5645_HPMIXL_CTRL 0x3f | |
61 | #define RT5645_HPOMIXL_CTRL 0x40 | |
62 | #define RT5645_HPMIXR_CTRL 0x41 | |
63 | #define RT5645_HPOMIXR_CTRL 0x42 | |
64 | #define RT5645_HPO_MIXER 0x45 | |
65 | #define RT5645_SPK_L_MIXER 0x46 | |
66 | #define RT5645_SPK_R_MIXER 0x47 | |
67 | #define RT5645_SPO_MIXER 0x48 | |
68 | #define RT5645_SPO_CLSD_RATIO 0x4a | |
69 | #define RT5645_OUT_L_GAIN1 0x4d | |
70 | #define RT5645_OUT_L_GAIN2 0x4e | |
71 | #define RT5645_OUT_L1_MIXER 0x4f | |
72 | #define RT5645_OUT_R_GAIN1 0x50 | |
73 | #define RT5645_OUT_R_GAIN2 0x51 | |
74 | #define RT5645_OUT_R1_MIXER 0x52 | |
75 | #define RT5645_LOUT_MIXER 0x53 | |
76 | /* Haptic */ | |
77 | #define RT5645_HAPTIC_CTRL1 0x56 | |
78 | #define RT5645_HAPTIC_CTRL2 0x57 | |
79 | #define RT5645_HAPTIC_CTRL3 0x58 | |
80 | #define RT5645_HAPTIC_CTRL4 0x59 | |
81 | #define RT5645_HAPTIC_CTRL5 0x5a | |
82 | #define RT5645_HAPTIC_CTRL6 0x5b | |
83 | #define RT5645_HAPTIC_CTRL7 0x5c | |
84 | #define RT5645_HAPTIC_CTRL8 0x5d | |
85 | #define RT5645_HAPTIC_CTRL9 0x5e | |
86 | #define RT5645_HAPTIC_CTRL10 0x5f | |
87 | /* Power */ | |
88 | #define RT5645_PWR_DIG1 0x61 | |
89 | #define RT5645_PWR_DIG2 0x62 | |
90 | #define RT5645_PWR_ANLG1 0x63 | |
91 | #define RT5645_PWR_ANLG2 0x64 | |
92 | #define RT5645_PWR_MIXER 0x65 | |
93 | #define RT5645_PWR_VOL 0x66 | |
94 | /* Private Register Control */ | |
95 | #define RT5645_PRIV_INDEX 0x6a | |
96 | #define RT5645_PRIV_DATA 0x6c | |
97 | /* Format - ADC/DAC */ | |
98 | #define RT5645_I2S1_SDP 0x70 | |
99 | #define RT5645_I2S2_SDP 0x71 | |
100 | #define RT5645_ADDA_CLK1 0x73 | |
101 | #define RT5645_ADDA_CLK2 0x74 | |
102 | #define RT5645_DMIC_CTRL1 0x75 | |
103 | #define RT5645_DMIC_CTRL2 0x76 | |
104 | /* Format - TDM Control */ | |
105 | #define RT5645_TDM_CTRL_1 0x77 | |
106 | #define RT5645_TDM_CTRL_2 0x78 | |
107 | #define RT5645_TDM_CTRL_3 0x79 | |
21ab3f2b | 108 | #define RT5650_TDM_CTRL_4 0x7a |
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109 | |
110 | /* Function - Analog */ | |
111 | #define RT5645_GLB_CLK 0x80 | |
112 | #define RT5645_PLL_CTRL1 0x81 | |
113 | #define RT5645_PLL_CTRL2 0x82 | |
114 | #define RT5645_ASRC_1 0x83 | |
115 | #define RT5645_ASRC_2 0x84 | |
116 | #define RT5645_ASRC_3 0x85 | |
117 | #define RT5645_ASRC_4 0x8a | |
118 | #define RT5645_DEPOP_M1 0x8e | |
119 | #define RT5645_DEPOP_M2 0x8f | |
120 | #define RT5645_DEPOP_M3 0x90 | |
121 | #define RT5645_CHARGE_PUMP 0x91 | |
122 | #define RT5645_MICBIAS 0x93 | |
123 | #define RT5645_A_JD_CTRL1 0x94 | |
124 | #define RT5645_VAD_CTRL4 0x9d | |
125 | #define RT5645_CLSD_OUT_CTRL 0xa0 | |
126 | /* Function - Digital */ | |
127 | #define RT5645_ADC_EQ_CTRL1 0xae | |
128 | #define RT5645_ADC_EQ_CTRL2 0xaf | |
129 | #define RT5645_EQ_CTRL1 0xb0 | |
130 | #define RT5645_EQ_CTRL2 0xb1 | |
131 | #define RT5645_ALC_CTRL_1 0xb3 | |
132 | #define RT5645_ALC_CTRL_2 0xb4 | |
133 | #define RT5645_ALC_CTRL_3 0xb5 | |
134 | #define RT5645_ALC_CTRL_4 0xb6 | |
135 | #define RT5645_ALC_CTRL_5 0xb7 | |
136 | #define RT5645_JD_CTRL 0xbb | |
137 | #define RT5645_IRQ_CTRL1 0xbc | |
138 | #define RT5645_IRQ_CTRL2 0xbd | |
139 | #define RT5645_IRQ_CTRL3 0xbe | |
140 | #define RT5645_INT_IRQ_ST 0xbf | |
141 | #define RT5645_GPIO_CTRL1 0xc0 | |
142 | #define RT5645_GPIO_CTRL2 0xc1 | |
143 | #define RT5645_GPIO_CTRL3 0xc2 | |
144 | #define RT5645_BASS_BACK 0xcf | |
145 | #define RT5645_MP3_PLUS1 0xd0 | |
146 | #define RT5645_MP3_PLUS2 0xd1 | |
147 | #define RT5645_ADJ_HPF1 0xd3 | |
148 | #define RT5645_ADJ_HPF2 0xd4 | |
149 | #define RT5645_HP_CALIB_AMP_DET 0xd6 | |
150 | #define RT5645_SV_ZCD1 0xd9 | |
151 | #define RT5645_SV_ZCD2 0xda | |
152 | #define RT5645_IL_CMD 0xdb | |
153 | #define RT5645_IL_CMD2 0xdc | |
154 | #define RT5645_IL_CMD3 0xdd | |
5c4ca99d BL |
155 | #define RT5650_4BTN_IL_CMD1 0xdf |
156 | #define RT5650_4BTN_IL_CMD2 0xe0 | |
1319b2f6 OC |
157 | #define RT5645_DRC1_HL_CTRL1 0xe7 |
158 | #define RT5645_DRC2_HL_CTRL1 0xe9 | |
159 | #define RT5645_MUTI_DRC_CTRL1 0xea | |
160 | #define RT5645_ADC_MONO_HP_CTRL1 0xec | |
161 | #define RT5645_ADC_MONO_HP_CTRL2 0xed | |
162 | #define RT5645_DRC2_CTRL1 0xf0 | |
163 | #define RT5645_DRC2_CTRL2 0xf1 | |
164 | #define RT5645_DRC2_CTRL3 0xf2 | |
165 | #define RT5645_DRC2_CTRL4 0xf3 | |
166 | #define RT5645_DRC2_CTRL5 0xf4 | |
167 | #define RT5645_JD_CTRL3 0xf8 | |
168 | #define RT5645_JD_CTRL4 0xf9 | |
169 | /* General Control */ | |
170 | #define RT5645_GEN_CTRL1 0xfa | |
171 | #define RT5645_GEN_CTRL2 0xfb | |
172 | #define RT5645_GEN_CTRL3 0xfc | |
173 | ||
174 | ||
175 | /* Index of Codec Private Register definition */ | |
176 | #define RT5645_DIG_VOL 0x00 | |
177 | #define RT5645_PR_ALC_CTRL_1 0x01 | |
178 | #define RT5645_PR_ALC_CTRL_2 0x02 | |
179 | #define RT5645_PR_ALC_CTRL_3 0x03 | |
180 | #define RT5645_PR_ALC_CTRL_4 0x04 | |
181 | #define RT5645_PR_ALC_CTRL_5 0x05 | |
182 | #define RT5645_PR_ALC_CTRL_6 0x06 | |
183 | #define RT5645_BIAS_CUR1 0x12 | |
184 | #define RT5645_BIAS_CUR3 0x14 | |
185 | #define RT5645_CLSD_INT_REG1 0x1c | |
186 | #define RT5645_MAMP_INT_REG2 0x37 | |
187 | #define RT5645_CHOP_DAC_ADC 0x3d | |
188 | #define RT5645_MIXER_INT_REG 0x3f | |
189 | #define RT5645_3D_SPK 0x63 | |
190 | #define RT5645_WND_1 0x6c | |
191 | #define RT5645_WND_2 0x6d | |
192 | #define RT5645_WND_3 0x6e | |
193 | #define RT5645_WND_4 0x6f | |
194 | #define RT5645_WND_5 0x70 | |
195 | #define RT5645_WND_8 0x73 | |
196 | #define RT5645_DIP_SPK_INF 0x75 | |
197 | #define RT5645_HP_DCC_INT1 0x77 | |
198 | #define RT5645_EQ_BW_LOP 0xa0 | |
199 | #define RT5645_EQ_GN_LOP 0xa1 | |
200 | #define RT5645_EQ_FC_BP1 0xa2 | |
201 | #define RT5645_EQ_BW_BP1 0xa3 | |
202 | #define RT5645_EQ_GN_BP1 0xa4 | |
203 | #define RT5645_EQ_FC_BP2 0xa5 | |
204 | #define RT5645_EQ_BW_BP2 0xa6 | |
205 | #define RT5645_EQ_GN_BP2 0xa7 | |
206 | #define RT5645_EQ_FC_BP3 0xa8 | |
207 | #define RT5645_EQ_BW_BP3 0xa9 | |
208 | #define RT5645_EQ_GN_BP3 0xaa | |
209 | #define RT5645_EQ_FC_BP4 0xab | |
210 | #define RT5645_EQ_BW_BP4 0xac | |
211 | #define RT5645_EQ_GN_BP4 0xad | |
212 | #define RT5645_EQ_FC_HIP1 0xae | |
213 | #define RT5645_EQ_GN_HIP1 0xaf | |
214 | #define RT5645_EQ_FC_HIP2 0xb0 | |
215 | #define RT5645_EQ_BW_HIP2 0xb1 | |
216 | #define RT5645_EQ_GN_HIP2 0xb2 | |
217 | #define RT5645_EQ_PRE_VOL 0xb3 | |
218 | #define RT5645_EQ_PST_VOL 0xb4 | |
219 | ||
220 | ||
221 | /* global definition */ | |
222 | #define RT5645_L_MUTE (0x1 << 15) | |
223 | #define RT5645_L_MUTE_SFT 15 | |
224 | #define RT5645_VOL_L_MUTE (0x1 << 14) | |
225 | #define RT5645_VOL_L_SFT 14 | |
226 | #define RT5645_R_MUTE (0x1 << 7) | |
227 | #define RT5645_R_MUTE_SFT 7 | |
228 | #define RT5645_VOL_R_MUTE (0x1 << 6) | |
229 | #define RT5645_VOL_R_SFT 6 | |
230 | #define RT5645_L_VOL_MASK (0x3f << 8) | |
231 | #define RT5645_L_VOL_SFT 8 | |
232 | #define RT5645_R_VOL_MASK (0x3f) | |
233 | #define RT5645_R_VOL_SFT 0 | |
234 | ||
235 | /* IN1 Control 1 (0x0a) */ | |
236 | #define RT5645_CBJ_BST1_MASK (0xf << 12) | |
237 | #define RT5645_CBJ_BST1_SFT (12) | |
238 | #define RT5645_CBJ_JD_HP_EN (0x1 << 9) | |
239 | #define RT5645_CBJ_JD_MIC_EN (0x1 << 8) | |
240 | #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7) | |
241 | #define RT5645_CBJ_MIC_SEL_R (0x1 << 6) | |
242 | #define RT5645_CBJ_MIC_SEL_L (0x1 << 5) | |
243 | #define RT5645_CBJ_MIC_SW (0x1 << 4) | |
244 | #define RT5645_CBJ_BST1_EN (0x1 << 2) | |
245 | ||
246 | /* IN1 Control 2 (0x0b) */ | |
247 | #define RT5645_CBJ_MN_JD (0x1 << 12) | |
248 | #define RT5645_CAPLESS_EN (0x1 << 11) | |
249 | #define RT5645_CBJ_DET_MODE (0x1 << 7) | |
250 | ||
251 | /* IN1 Control 3 (0x0c) */ | |
252 | #define RT5645_CBJ_TIE_G_L (0x1 << 15) | |
253 | #define RT5645_CBJ_TIE_G_R (0x1 << 14) | |
254 | ||
255 | /* IN2 Control (0x0d) */ | |
256 | #define RT5645_BST_MASK1 (0xf<<12) | |
257 | #define RT5645_BST_SFT1 12 | |
258 | #define RT5645_BST_MASK2 (0xf<<8) | |
259 | #define RT5645_BST_SFT2 8 | |
260 | #define RT5645_IN_DF2 (0x1 << 6) | |
261 | #define RT5645_IN_SFT2 6 | |
262 | ||
263 | /* INL and INR Volume Control (0x0f) */ | |
264 | #define RT5645_INL_SEL_MASK (0x1 << 15) | |
265 | #define RT5645_INL_SEL_SFT 15 | |
266 | #define RT5645_INL_SEL_IN4P (0x0 << 15) | |
267 | #define RT5645_INL_SEL_MONOP (0x1 << 15) | |
268 | #define RT5645_INL_VOL_MASK (0x1f << 8) | |
269 | #define RT5645_INL_VOL_SFT 8 | |
270 | #define RT5645_INR_SEL_MASK (0x1 << 7) | |
271 | #define RT5645_INR_SEL_SFT 7 | |
272 | #define RT5645_INR_SEL_IN4N (0x0 << 7) | |
273 | #define RT5645_INR_SEL_MONON (0x1 << 7) | |
274 | #define RT5645_INR_VOL_MASK (0x1f) | |
275 | #define RT5645_INR_VOL_SFT 0 | |
276 | ||
277 | /* DAC1 Digital Volume (0x19) */ | |
278 | #define RT5645_DAC_L1_VOL_MASK (0xff << 8) | |
279 | #define RT5645_DAC_L1_VOL_SFT 8 | |
280 | #define RT5645_DAC_R1_VOL_MASK (0xff) | |
281 | #define RT5645_DAC_R1_VOL_SFT 0 | |
282 | ||
283 | /* DAC2 Digital Volume (0x1a) */ | |
284 | #define RT5645_DAC_L2_VOL_MASK (0xff << 8) | |
285 | #define RT5645_DAC_L2_VOL_SFT 8 | |
286 | #define RT5645_DAC_R2_VOL_MASK (0xff) | |
287 | #define RT5645_DAC_R2_VOL_SFT 0 | |
288 | ||
289 | /* DAC2 Control (0x1b) */ | |
290 | #define RT5645_M_DAC_L2_VOL (0x1 << 13) | |
291 | #define RT5645_M_DAC_L2_VOL_SFT 13 | |
292 | #define RT5645_M_DAC_R2_VOL (0x1 << 12) | |
293 | #define RT5645_M_DAC_R2_VOL_SFT 12 | |
294 | #define RT5645_DAC2_L_SEL_MASK (0x7 << 4) | |
295 | #define RT5645_DAC2_L_SEL_SFT 4 | |
296 | #define RT5645_DAC2_R_SEL_MASK (0x7 << 0) | |
297 | #define RT5645_DAC2_R_SEL_SFT 0 | |
298 | ||
299 | /* ADC Digital Volume Control (0x1c) */ | |
300 | #define RT5645_ADC_L_VOL_MASK (0x7f << 8) | |
301 | #define RT5645_ADC_L_VOL_SFT 8 | |
302 | #define RT5645_ADC_R_VOL_MASK (0x7f) | |
303 | #define RT5645_ADC_R_VOL_SFT 0 | |
304 | ||
305 | /* Mono ADC Digital Volume Control (0x1d) */ | |
306 | #define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8) | |
307 | #define RT5645_MONO_ADC_L_VOL_SFT 8 | |
308 | #define RT5645_MONO_ADC_R_VOL_MASK (0x7f) | |
309 | #define RT5645_MONO_ADC_R_VOL_SFT 0 | |
310 | ||
311 | /* ADC Boost Volume Control (0x1e) */ | |
312 | #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14) | |
313 | #define RT5645_STO1_ADC_L_BST_SFT 14 | |
314 | #define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12) | |
315 | #define RT5645_STO1_ADC_R_BST_SFT 12 | |
316 | #define RT5645_STO1_ADC_COMP_MASK (0x3 << 10) | |
317 | #define RT5645_STO1_ADC_COMP_SFT 10 | |
8c1a9d63 OC |
318 | |
319 | /* ADC Boost Volume Control (0x20) */ | |
320 | #define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14) | |
321 | #define RT5645_MONO_ADC_L_BST_SFT 14 | |
322 | #define RT5645_MONO_ADC_R_BST_MASK (0x3 << 12) | |
323 | #define RT5645_MONO_ADC_R_BST_SFT 12 | |
324 | #define RT5645_MONO_ADC_COMP_MASK (0x3 << 10) | |
325 | #define RT5645_MONO_ADC_COMP_SFT 10 | |
1319b2f6 OC |
326 | |
327 | /* Stereo2 ADC Mixer Control (0x26) */ | |
328 | #define RT5645_STO2_ADC_SRC_MASK (0x1 << 15) | |
329 | #define RT5645_STO2_ADC_SRC_SFT 15 | |
330 | ||
331 | /* Stereo ADC Mixer Control (0x27) */ | |
332 | #define RT5645_M_ADC_L1 (0x1 << 14) | |
333 | #define RT5645_M_ADC_L1_SFT 14 | |
334 | #define RT5645_M_ADC_L2 (0x1 << 13) | |
335 | #define RT5645_M_ADC_L2_SFT 13 | |
336 | #define RT5645_ADC_1_SRC_MASK (0x1 << 12) | |
337 | #define RT5645_ADC_1_SRC_SFT 12 | |
338 | #define RT5645_ADC_1_SRC_ADC (0x1 << 12) | |
339 | #define RT5645_ADC_1_SRC_DACMIX (0x0 << 12) | |
340 | #define RT5645_ADC_2_SRC_MASK (0x1 << 11) | |
341 | #define RT5645_ADC_2_SRC_SFT 11 | |
342 | #define RT5645_DMIC_SRC_MASK (0x1 << 8) | |
343 | #define RT5645_DMIC_SRC_SFT 8 | |
344 | #define RT5645_M_ADC_R1 (0x1 << 6) | |
345 | #define RT5645_M_ADC_R1_SFT 6 | |
346 | #define RT5645_M_ADC_R2 (0x1 << 5) | |
347 | #define RT5645_M_ADC_R2_SFT 5 | |
348 | #define RT5645_DMIC3_SRC_MASK (0x1 << 1) | |
349 | #define RT5645_DMIC3_SRC_SFT 0 | |
350 | ||
351 | /* Mono ADC Mixer Control (0x28) */ | |
352 | #define RT5645_M_MONO_ADC_L1 (0x1 << 14) | |
353 | #define RT5645_M_MONO_ADC_L1_SFT 14 | |
354 | #define RT5645_M_MONO_ADC_L2 (0x1 << 13) | |
355 | #define RT5645_M_MONO_ADC_L2_SFT 13 | |
356 | #define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12) | |
357 | #define RT5645_MONO_ADC_L1_SRC_SFT 12 | |
358 | #define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12) | |
359 | #define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12) | |
360 | #define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11) | |
361 | #define RT5645_MONO_ADC_L2_SRC_SFT 11 | |
362 | #define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8) | |
363 | #define RT5645_MONO_DMIC_L_SRC_SFT 8 | |
364 | #define RT5645_M_MONO_ADC_R1 (0x1 << 6) | |
365 | #define RT5645_M_MONO_ADC_R1_SFT 6 | |
366 | #define RT5645_M_MONO_ADC_R2 (0x1 << 5) | |
367 | #define RT5645_M_MONO_ADC_R2_SFT 5 | |
368 | #define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4) | |
369 | #define RT5645_MONO_ADC_R1_SRC_SFT 4 | |
370 | #define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4) | |
371 | #define RT5645_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4) | |
372 | #define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3) | |
373 | #define RT5645_MONO_ADC_R2_SRC_SFT 3 | |
374 | #define RT5645_MONO_DMIC_R_SRC_MASK (0x3) | |
375 | #define RT5645_MONO_DMIC_R_SRC_SFT 0 | |
376 | ||
377 | /* ADC Mixer to DAC Mixer Control (0x29) */ | |
378 | #define RT5645_M_ADCMIX_L (0x1 << 15) | |
379 | #define RT5645_M_ADCMIX_L_SFT 15 | |
380 | #define RT5645_M_DAC1_L (0x1 << 14) | |
381 | #define RT5645_M_DAC1_L_SFT 14 | |
382 | #define RT5645_DAC1_R_SEL_MASK (0x3 << 10) | |
383 | #define RT5645_DAC1_R_SEL_SFT 10 | |
384 | #define RT5645_DAC1_R_SEL_IF1 (0x0 << 10) | |
385 | #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10) | |
386 | #define RT5645_DAC1_R_SEL_IF3 (0x2 << 10) | |
387 | #define RT5645_DAC1_R_SEL_IF4 (0x3 << 10) | |
388 | #define RT5645_DAC1_L_SEL_MASK (0x3 << 8) | |
389 | #define RT5645_DAC1_L_SEL_SFT 8 | |
390 | #define RT5645_DAC1_L_SEL_IF1 (0x0 << 8) | |
391 | #define RT5645_DAC1_L_SEL_IF2 (0x1 << 8) | |
392 | #define RT5645_DAC1_L_SEL_IF3 (0x2 << 8) | |
393 | #define RT5645_DAC1_L_SEL_IF4 (0x3 << 8) | |
394 | #define RT5645_M_ADCMIX_R (0x1 << 7) | |
395 | #define RT5645_M_ADCMIX_R_SFT 7 | |
396 | #define RT5645_M_DAC1_R (0x1 << 6) | |
397 | #define RT5645_M_DAC1_R_SFT 6 | |
398 | ||
399 | /* Stereo DAC Mixer Control (0x2a) */ | |
400 | #define RT5645_M_DAC_L1 (0x1 << 14) | |
401 | #define RT5645_M_DAC_L1_SFT 14 | |
402 | #define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13) | |
403 | #define RT5645_DAC_L1_STO_L_VOL_SFT 13 | |
404 | #define RT5645_M_DAC_L2 (0x1 << 12) | |
405 | #define RT5645_M_DAC_L2_SFT 12 | |
406 | #define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11) | |
407 | #define RT5645_DAC_L2_STO_L_VOL_SFT 11 | |
408 | #define RT5645_M_ANC_DAC_L (0x1 << 10) | |
409 | #define RT5645_M_ANC_DAC_L_SFT 10 | |
410 | #define RT5645_M_DAC_R1_STO_L (0x1 << 9) | |
411 | #define RT5645_M_DAC_R1_STO_L_SFT 9 | |
412 | #define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8) | |
413 | #define RT5645_DAC_R1_STO_L_VOL_SFT 8 | |
414 | #define RT5645_M_DAC_R1 (0x1 << 6) | |
415 | #define RT5645_M_DAC_R1_SFT 6 | |
416 | #define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5) | |
417 | #define RT5645_DAC_R1_STO_R_VOL_SFT 5 | |
418 | #define RT5645_M_DAC_R2 (0x1 << 4) | |
419 | #define RT5645_M_DAC_R2_SFT 4 | |
420 | #define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3) | |
421 | #define RT5645_DAC_R2_STO_R_VOL_SFT 3 | |
422 | #define RT5645_M_ANC_DAC_R (0x1 << 2) | |
423 | #define RT5645_M_ANC_DAC_R_SFT 2 | |
424 | #define RT5645_M_DAC_L1_STO_R (0x1 << 1) | |
425 | #define RT5645_M_DAC_L1_STO_R_SFT 1 | |
426 | #define RT5645_DAC_L1_STO_R_VOL_MASK (0x1) | |
427 | #define RT5645_DAC_L1_STO_R_VOL_SFT 0 | |
428 | ||
429 | /* Mono DAC Mixer Control (0x2b) */ | |
430 | #define RT5645_M_DAC_L1_MONO_L (0x1 << 14) | |
431 | #define RT5645_M_DAC_L1_MONO_L_SFT 14 | |
432 | #define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13) | |
433 | #define RT5645_DAC_L1_MONO_L_VOL_SFT 13 | |
434 | #define RT5645_M_DAC_L2_MONO_L (0x1 << 12) | |
435 | #define RT5645_M_DAC_L2_MONO_L_SFT 12 | |
436 | #define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11) | |
437 | #define RT5645_DAC_L2_MONO_L_VOL_SFT 11 | |
438 | #define RT5645_M_DAC_R2_MONO_L (0x1 << 10) | |
439 | #define RT5645_M_DAC_R2_MONO_L_SFT 10 | |
440 | #define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9) | |
441 | #define RT5645_DAC_R2_MONO_L_VOL_SFT 9 | |
442 | #define RT5645_M_DAC_R1_MONO_R (0x1 << 6) | |
443 | #define RT5645_M_DAC_R1_MONO_R_SFT 6 | |
444 | #define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5) | |
445 | #define RT5645_DAC_R1_MONO_R_VOL_SFT 5 | |
446 | #define RT5645_M_DAC_R2_MONO_R (0x1 << 4) | |
447 | #define RT5645_M_DAC_R2_MONO_R_SFT 4 | |
448 | #define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3) | |
449 | #define RT5645_DAC_R2_MONO_R_VOL_SFT 3 | |
450 | #define RT5645_M_DAC_L2_MONO_R (0x1 << 2) | |
451 | #define RT5645_M_DAC_L2_MONO_R_SFT 2 | |
452 | #define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1) | |
453 | #define RT5645_DAC_L2_MONO_R_VOL_SFT 1 | |
454 | ||
455 | /* Digital Mixer Control (0x2c) */ | |
456 | #define RT5645_M_STO_L_DAC_L (0x1 << 15) | |
457 | #define RT5645_M_STO_L_DAC_L_SFT 15 | |
458 | #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14) | |
459 | #define RT5645_STO_L_DAC_L_VOL_SFT 14 | |
460 | #define RT5645_M_DAC_L2_DAC_L (0x1 << 13) | |
461 | #define RT5645_M_DAC_L2_DAC_L_SFT 13 | |
462 | #define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12) | |
463 | #define RT5645_DAC_L2_DAC_L_VOL_SFT 12 | |
464 | #define RT5645_M_STO_R_DAC_R (0x1 << 11) | |
465 | #define RT5645_M_STO_R_DAC_R_SFT 11 | |
466 | #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10) | |
467 | #define RT5645_STO_R_DAC_R_VOL_SFT 10 | |
468 | #define RT5645_M_DAC_R2_DAC_R (0x1 << 9) | |
469 | #define RT5645_M_DAC_R2_DAC_R_SFT 9 | |
470 | #define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8) | |
471 | #define RT5645_DAC_R2_DAC_R_VOL_SFT 8 | |
472 | #define RT5645_M_DAC_R2_DAC_L (0x1 << 7) | |
473 | #define RT5645_M_DAC_R2_DAC_L_SFT 7 | |
474 | #define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6) | |
475 | #define RT5645_DAC_R2_DAC_L_VOL_SFT 6 | |
476 | #define RT5645_M_DAC_L2_DAC_R (0x1 << 5) | |
477 | #define RT5645_M_DAC_L2_DAC_R_SFT 5 | |
478 | #define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4) | |
479 | #define RT5645_DAC_L2_DAC_R_VOL_SFT 4 | |
480 | ||
5c4ca99d BL |
481 | /* Analog DAC1/2 Input Source Control (0x2d) */ |
482 | #define RT5650_A_DAC1_L_IN_SFT 3 | |
483 | #define RT5650_A_DAC1_R_IN_SFT 2 | |
484 | #define RT5650_A_DAC2_L_IN_SFT 1 | |
485 | #define RT5650_A_DAC2_R_IN_SFT 0 | |
486 | ||
1319b2f6 OC |
487 | /* Digital Interface Data Control (0x2f) */ |
488 | #define RT5645_IF1_ADC2_IN_SEL (0x1 << 15) | |
489 | #define RT5645_IF1_ADC2_IN_SFT 15 | |
490 | #define RT5645_IF2_ADC_IN_MASK (0x7 << 12) | |
491 | #define RT5645_IF2_ADC_IN_SFT 12 | |
492 | #define RT5645_IF2_DAC_SEL_MASK (0x3 << 10) | |
493 | #define RT5645_IF2_DAC_SEL_SFT 10 | |
494 | #define RT5645_IF2_ADC_SEL_MASK (0x3 << 8) | |
495 | #define RT5645_IF2_ADC_SEL_SFT 8 | |
496 | #define RT5645_IF3_DAC_SEL_MASK (0x3 << 6) | |
497 | #define RT5645_IF3_DAC_SEL_SFT 6 | |
498 | #define RT5645_IF3_ADC_SEL_MASK (0x3 << 4) | |
499 | #define RT5645_IF3_ADC_SEL_SFT 4 | |
500 | #define RT5645_IF3_ADC_IN_MASK (0x7) | |
501 | #define RT5645_IF3_ADC_IN_SFT 0 | |
502 | ||
503 | /* PDM Output Control (0x31) */ | |
504 | #define RT5645_PDM1_L_MASK (0x1 << 15) | |
505 | #define RT5645_PDM1_L_SFT 15 | |
506 | #define RT5645_M_PDM1_L (0x1 << 14) | |
507 | #define RT5645_M_PDM1_L_SFT 14 | |
508 | #define RT5645_PDM1_R_MASK (0x1 << 13) | |
509 | #define RT5645_PDM1_R_SFT 13 | |
510 | #define RT5645_M_PDM1_R (0x1 << 12) | |
511 | #define RT5645_M_PDM1_R_SFT 12 | |
512 | #define RT5645_PDM2_L_MASK (0x1 << 11) | |
513 | #define RT5645_PDM2_L_SFT 11 | |
514 | #define RT5645_M_PDM2_L (0x1 << 10) | |
515 | #define RT5645_M_PDM2_L_SFT 10 | |
516 | #define RT5645_PDM2_R_MASK (0x1 << 9) | |
517 | #define RT5645_PDM2_R_SFT 9 | |
518 | #define RT5645_M_PDM2_R (0x1 << 8) | |
519 | #define RT5645_M_PDM2_R_SFT 8 | |
520 | #define RT5645_PDM2_BUSY (0x1 << 7) | |
521 | #define RT5645_PDM1_BUSY (0x1 << 6) | |
522 | #define RT5645_PDM_PATTERN (0x1 << 5) | |
523 | #define RT5645_PDM_GAIN (0x1 << 4) | |
524 | #define RT5645_PDM_DIV_MASK (0x3) | |
525 | ||
526 | /* REC Left Mixer Control 1 (0x3b) */ | |
527 | #define RT5645_G_HP_L_RM_L_MASK (0x7 << 13) | |
528 | #define RT5645_G_HP_L_RM_L_SFT 13 | |
529 | #define RT5645_G_IN_L_RM_L_MASK (0x7 << 10) | |
530 | #define RT5645_G_IN_L_RM_L_SFT 10 | |
531 | #define RT5645_G_BST4_RM_L_MASK (0x7 << 7) | |
532 | #define RT5645_G_BST4_RM_L_SFT 7 | |
533 | #define RT5645_G_BST3_RM_L_MASK (0x7 << 4) | |
534 | #define RT5645_G_BST3_RM_L_SFT 4 | |
535 | #define RT5645_G_BST2_RM_L_MASK (0x7 << 1) | |
536 | #define RT5645_G_BST2_RM_L_SFT 1 | |
537 | ||
538 | /* REC Left Mixer Control 2 (0x3c) */ | |
539 | #define RT5645_G_BST1_RM_L_MASK (0x7 << 13) | |
540 | #define RT5645_G_BST1_RM_L_SFT 13 | |
541 | #define RT5645_G_OM_L_RM_L_MASK (0x7 << 10) | |
542 | #define RT5645_G_OM_L_RM_L_SFT 10 | |
543 | #define RT5645_M_MM_L_RM_L (0x1 << 6) | |
544 | #define RT5645_M_MM_L_RM_L_SFT 6 | |
545 | #define RT5645_M_IN_L_RM_L (0x1 << 5) | |
546 | #define RT5645_M_IN_L_RM_L_SFT 5 | |
547 | #define RT5645_M_HP_L_RM_L (0x1 << 4) | |
548 | #define RT5645_M_HP_L_RM_L_SFT 4 | |
549 | #define RT5645_M_BST3_RM_L (0x1 << 3) | |
550 | #define RT5645_M_BST3_RM_L_SFT 3 | |
551 | #define RT5645_M_BST2_RM_L (0x1 << 2) | |
552 | #define RT5645_M_BST2_RM_L_SFT 2 | |
553 | #define RT5645_M_BST1_RM_L (0x1 << 1) | |
554 | #define RT5645_M_BST1_RM_L_SFT 1 | |
555 | #define RT5645_M_OM_L_RM_L (0x1) | |
556 | #define RT5645_M_OM_L_RM_L_SFT 0 | |
557 | ||
558 | /* REC Right Mixer Control 1 (0x3d) */ | |
559 | #define RT5645_G_HP_R_RM_R_MASK (0x7 << 13) | |
560 | #define RT5645_G_HP_R_RM_R_SFT 13 | |
561 | #define RT5645_G_IN_R_RM_R_MASK (0x7 << 10) | |
562 | #define RT5645_G_IN_R_RM_R_SFT 10 | |
563 | #define RT5645_G_BST4_RM_R_MASK (0x7 << 7) | |
564 | #define RT5645_G_BST4_RM_R_SFT 7 | |
565 | #define RT5645_G_BST3_RM_R_MASK (0x7 << 4) | |
566 | #define RT5645_G_BST3_RM_R_SFT 4 | |
567 | #define RT5645_G_BST2_RM_R_MASK (0x7 << 1) | |
568 | #define RT5645_G_BST2_RM_R_SFT 1 | |
569 | ||
570 | /* REC Right Mixer Control 2 (0x3e) */ | |
571 | #define RT5645_G_BST1_RM_R_MASK (0x7 << 13) | |
572 | #define RT5645_G_BST1_RM_R_SFT 13 | |
573 | #define RT5645_G_OM_R_RM_R_MASK (0x7 << 10) | |
574 | #define RT5645_G_OM_R_RM_R_SFT 10 | |
575 | #define RT5645_M_MM_R_RM_R (0x1 << 6) | |
576 | #define RT5645_M_MM_R_RM_R_SFT 6 | |
577 | #define RT5645_M_IN_R_RM_R (0x1 << 5) | |
578 | #define RT5645_M_IN_R_RM_R_SFT 5 | |
579 | #define RT5645_M_HP_R_RM_R (0x1 << 4) | |
580 | #define RT5645_M_HP_R_RM_R_SFT 4 | |
581 | #define RT5645_M_BST3_RM_R (0x1 << 3) | |
582 | #define RT5645_M_BST3_RM_R_SFT 3 | |
583 | #define RT5645_M_BST2_RM_R (0x1 << 2) | |
584 | #define RT5645_M_BST2_RM_R_SFT 2 | |
585 | #define RT5645_M_BST1_RM_R (0x1 << 1) | |
586 | #define RT5645_M_BST1_RM_R_SFT 1 | |
587 | #define RT5645_M_OM_R_RM_R (0x1) | |
588 | #define RT5645_M_OM_R_RM_R_SFT 0 | |
589 | ||
590 | /* HPOMIX Control (0x40) (0x42) */ | |
591 | #define RT5645_M_BST1_HV (0x1 << 4) | |
592 | #define RT5645_M_BST1_HV_SFT 4 | |
593 | #define RT5645_M_BST2_HV (0x1 << 4) | |
594 | #define RT5645_M_BST2_HV_SFT 4 | |
595 | #define RT5645_M_BST3_HV (0x1 << 3) | |
596 | #define RT5645_M_BST3_HV_SFT 3 | |
597 | #define RT5645_M_IN_HV (0x1 << 2) | |
598 | #define RT5645_M_IN_HV_SFT 2 | |
599 | #define RT5645_M_DAC2_HV (0x1 << 1) | |
600 | #define RT5645_M_DAC2_HV_SFT 1 | |
601 | #define RT5645_M_DAC1_HV (0x1 << 0) | |
602 | #define RT5645_M_DAC1_HV_SFT 0 | |
603 | ||
604 | /* HPMIX Control (0x45) */ | |
605 | #define RT5645_M_DAC1_HM (0x1 << 14) | |
606 | #define RT5645_M_DAC1_HM_SFT 14 | |
607 | #define RT5645_M_HPVOL_HM (0x1 << 13) | |
608 | #define RT5645_M_HPVOL_HM_SFT 13 | |
2d4e2d02 | 609 | #define RT5645_IRQ_PSV_MODE (0x1 << 12) |
1319b2f6 OC |
610 | |
611 | /* SPK Left Mixer Control (0x46) */ | |
612 | #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14) | |
613 | #define RT5645_G_RM_L_SM_L_SFT 14 | |
614 | #define RT5645_G_IN_L_SM_L_MASK (0x3 << 12) | |
615 | #define RT5645_G_IN_L_SM_L_SFT 12 | |
616 | #define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10) | |
617 | #define RT5645_G_DAC_L1_SM_L_SFT 10 | |
618 | #define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8) | |
619 | #define RT5645_G_DAC_L2_SM_L_SFT 8 | |
620 | #define RT5645_G_OM_L_SM_L_MASK (0x3 << 6) | |
621 | #define RT5645_G_OM_L_SM_L_SFT 6 | |
622 | #define RT5645_M_BST1_L_SM_L (0x1 << 5) | |
623 | #define RT5645_M_BST1_L_SM_L_SFT 5 | |
bc86e53a AL |
624 | #define RT5645_M_BST3_L_SM_L (0x1 << 4) |
625 | #define RT5645_M_BST3_L_SM_L_SFT 4 | |
1319b2f6 OC |
626 | #define RT5645_M_IN_L_SM_L (0x1 << 3) |
627 | #define RT5645_M_IN_L_SM_L_SFT 3 | |
1319b2f6 OC |
628 | #define RT5645_M_DAC_L2_SM_L (0x1 << 2) |
629 | #define RT5645_M_DAC_L2_SM_L_SFT 2 | |
bc86e53a AL |
630 | #define RT5645_M_DAC_L1_SM_L (0x1 << 1) |
631 | #define RT5645_M_DAC_L1_SM_L_SFT 1 | |
1319b2f6 OC |
632 | |
633 | /* SPK Right Mixer Control (0x47) */ | |
634 | #define RT5645_G_RM_R_SM_R_MASK (0x3 << 14) | |
635 | #define RT5645_G_RM_R_SM_R_SFT 14 | |
636 | #define RT5645_G_IN_R_SM_R_MASK (0x3 << 12) | |
637 | #define RT5645_G_IN_R_SM_R_SFT 12 | |
638 | #define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10) | |
639 | #define RT5645_G_DAC_R1_SM_R_SFT 10 | |
640 | #define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8) | |
641 | #define RT5645_G_DAC_R2_SM_R_SFT 8 | |
642 | #define RT5645_G_OM_R_SM_R_MASK (0x3 << 6) | |
643 | #define RT5645_G_OM_R_SM_R_SFT 6 | |
644 | #define RT5645_M_BST2_R_SM_R (0x1 << 5) | |
645 | #define RT5645_M_BST2_R_SM_R_SFT 5 | |
bc86e53a AL |
646 | #define RT5645_M_BST3_R_SM_R (0x1 << 4) |
647 | #define RT5645_M_BST3_R_SM_R_SFT 4 | |
1319b2f6 OC |
648 | #define RT5645_M_IN_R_SM_R (0x1 << 3) |
649 | #define RT5645_M_IN_R_SM_R_SFT 3 | |
1319b2f6 OC |
650 | #define RT5645_M_DAC_R2_SM_R (0x1 << 2) |
651 | #define RT5645_M_DAC_R2_SM_R_SFT 2 | |
bc86e53a AL |
652 | #define RT5645_M_DAC_R1_SM_R (0x1 << 1) |
653 | #define RT5645_M_DAC_R1_SM_R_SFT 1 | |
1319b2f6 OC |
654 | |
655 | /* SPOLMIX Control (0x48) */ | |
656 | #define RT5645_M_DAC_L1_SPM_L (0x1 << 15) | |
657 | #define RT5645_M_DAC_L1_SPM_L_SFT 15 | |
658 | #define RT5645_M_DAC_R1_SPM_L (0x1 << 14) | |
659 | #define RT5645_M_DAC_R1_SPM_L_SFT 14 | |
660 | #define RT5645_M_SV_L_SPM_L (0x1 << 13) | |
661 | #define RT5645_M_SV_L_SPM_L_SFT 13 | |
662 | #define RT5645_M_SV_R_SPM_L (0x1 << 12) | |
663 | #define RT5645_M_SV_R_SPM_L_SFT 12 | |
664 | #define RT5645_M_BST3_SPM_L (0x1 << 11) | |
665 | #define RT5645_M_BST3_SPM_L_SFT 11 | |
666 | #define RT5645_M_DAC_R1_SPM_R (0x1 << 2) | |
667 | #define RT5645_M_DAC_R1_SPM_R_SFT 2 | |
668 | #define RT5645_M_BST3_SPM_R (0x1 << 1) | |
669 | #define RT5645_M_BST3_SPM_R_SFT 1 | |
670 | #define RT5645_M_SV_R_SPM_R (0x1 << 0) | |
671 | #define RT5645_M_SV_R_SPM_R_SFT 0 | |
672 | ||
e29fd55d OC |
673 | /* SPOMIX Ratio Control (0x4a) */ |
674 | #define RT5645_SPK_G_CLSD_MASK (0x7 << 0) | |
675 | #define RT5645_SPK_G_CLSD_SFT 0 | |
676 | ||
1319b2f6 | 677 | /* Mono Output Mixer Control (0x4c) */ |
bc86e53a AL |
678 | #define RT5645_G_MONOMIX_MASK (0x1 << 10) |
679 | #define RT5645_G_MONOMIX_SFT 10 | |
1319b2f6 OC |
680 | #define RT5645_M_OV_L_MM (0x1 << 9) |
681 | #define RT5645_M_OV_L_MM_SFT 9 | |
682 | #define RT5645_M_DAC_L2_MA (0x1 << 8) | |
683 | #define RT5645_M_DAC_L2_MA_SFT 8 | |
1319b2f6 OC |
684 | #define RT5645_M_BST2_MM (0x1 << 4) |
685 | #define RT5645_M_BST2_MM_SFT 4 | |
686 | #define RT5645_M_DAC_R1_MM (0x1 << 3) | |
687 | #define RT5645_M_DAC_R1_MM_SFT 3 | |
688 | #define RT5645_M_DAC_R2_MM (0x1 << 2) | |
689 | #define RT5645_M_DAC_R2_MM_SFT 2 | |
690 | #define RT5645_M_DAC_L2_MM (0x1 << 1) | |
691 | #define RT5645_M_DAC_L2_MM_SFT 1 | |
692 | #define RT5645_M_BST3_MM (0x1 << 0) | |
693 | #define RT5645_M_BST3_MM_SFT 0 | |
694 | ||
695 | /* Output Left Mixer Control 1 (0x4d) */ | |
696 | #define RT5645_G_BST3_OM_L_MASK (0x7 << 13) | |
697 | #define RT5645_G_BST3_OM_L_SFT 13 | |
698 | #define RT5645_G_BST2_OM_L_MASK (0x7 << 10) | |
699 | #define RT5645_G_BST2_OM_L_SFT 10 | |
700 | #define RT5645_G_BST1_OM_L_MASK (0x7 << 7) | |
701 | #define RT5645_G_BST1_OM_L_SFT 7 | |
702 | #define RT5645_G_IN_L_OM_L_MASK (0x7 << 4) | |
703 | #define RT5645_G_IN_L_OM_L_SFT 4 | |
704 | #define RT5645_G_RM_L_OM_L_MASK (0x7 << 1) | |
705 | #define RT5645_G_RM_L_OM_L_SFT 1 | |
706 | ||
707 | /* Output Left Mixer Control 2 (0x4e) */ | |
708 | #define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13) | |
709 | #define RT5645_G_DAC_R2_OM_L_SFT 13 | |
710 | #define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10) | |
711 | #define RT5645_G_DAC_L2_OM_L_SFT 10 | |
712 | #define RT5645_G_DAC_L1_OM_L_MASK (0x7 << 7) | |
713 | #define RT5645_G_DAC_L1_OM_L_SFT 7 | |
714 | ||
715 | /* Output Left Mixer Control 3 (0x4f) */ | |
716 | #define RT5645_M_BST3_OM_L (0x1 << 4) | |
717 | #define RT5645_M_BST3_OM_L_SFT 4 | |
718 | #define RT5645_M_BST1_OM_L (0x1 << 3) | |
719 | #define RT5645_M_BST1_OM_L_SFT 3 | |
720 | #define RT5645_M_IN_L_OM_L (0x1 << 2) | |
721 | #define RT5645_M_IN_L_OM_L_SFT 2 | |
722 | #define RT5645_M_DAC_L2_OM_L (0x1 << 1) | |
723 | #define RT5645_M_DAC_L2_OM_L_SFT 1 | |
724 | #define RT5645_M_DAC_L1_OM_L (0x1) | |
725 | #define RT5645_M_DAC_L1_OM_L_SFT 0 | |
726 | ||
727 | /* Output Right Mixer Control 1 (0x50) */ | |
728 | #define RT5645_G_BST4_OM_R_MASK (0x7 << 13) | |
729 | #define RT5645_G_BST4_OM_R_SFT 13 | |
730 | #define RT5645_G_BST2_OM_R_MASK (0x7 << 10) | |
731 | #define RT5645_G_BST2_OM_R_SFT 10 | |
732 | #define RT5645_G_BST1_OM_R_MASK (0x7 << 7) | |
733 | #define RT5645_G_BST1_OM_R_SFT 7 | |
734 | #define RT5645_G_IN_R_OM_R_MASK (0x7 << 4) | |
735 | #define RT5645_G_IN_R_OM_R_SFT 4 | |
736 | #define RT5645_G_RM_R_OM_R_MASK (0x7 << 1) | |
737 | #define RT5645_G_RM_R_OM_R_SFT 1 | |
738 | ||
739 | /* Output Right Mixer Control 2 (0x51) */ | |
740 | #define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13) | |
741 | #define RT5645_G_DAC_L2_OM_R_SFT 13 | |
742 | #define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10) | |
743 | #define RT5645_G_DAC_R2_OM_R_SFT 10 | |
744 | #define RT5645_G_DAC_R1_OM_R_MASK (0x7 << 7) | |
745 | #define RT5645_G_DAC_R1_OM_R_SFT 7 | |
746 | ||
747 | /* Output Right Mixer Control 3 (0x52) */ | |
748 | #define RT5645_M_BST3_OM_R (0x1 << 4) | |
749 | #define RT5645_M_BST3_OM_R_SFT 4 | |
750 | #define RT5645_M_BST2_OM_R (0x1 << 3) | |
751 | #define RT5645_M_BST2_OM_R_SFT 3 | |
752 | #define RT5645_M_IN_R_OM_R (0x1 << 2) | |
753 | #define RT5645_M_IN_R_OM_R_SFT 2 | |
754 | #define RT5645_M_DAC_R2_OM_R (0x1 << 1) | |
755 | #define RT5645_M_DAC_R2_OM_R_SFT 1 | |
756 | #define RT5645_M_DAC_R1_OM_R (0x1) | |
757 | #define RT5645_M_DAC_R1_OM_R_SFT 0 | |
758 | ||
759 | /* LOUT Mixer Control (0x53) */ | |
760 | #define RT5645_M_DAC_L1_LM (0x1 << 15) | |
761 | #define RT5645_M_DAC_L1_LM_SFT 15 | |
762 | #define RT5645_M_DAC_R1_LM (0x1 << 14) | |
763 | #define RT5645_M_DAC_R1_LM_SFT 14 | |
764 | #define RT5645_M_OV_L_LM (0x1 << 13) | |
765 | #define RT5645_M_OV_L_LM_SFT 13 | |
766 | #define RT5645_M_OV_R_LM (0x1 << 12) | |
767 | #define RT5645_M_OV_R_LM_SFT 12 | |
768 | #define RT5645_G_LOUTMIX_MASK (0x1 << 11) | |
769 | #define RT5645_G_LOUTMIX_SFT 11 | |
770 | ||
771 | /* Power Management for Digital 1 (0x61) */ | |
772 | #define RT5645_PWR_I2S1 (0x1 << 15) | |
773 | #define RT5645_PWR_I2S1_BIT 15 | |
774 | #define RT5645_PWR_I2S2 (0x1 << 14) | |
775 | #define RT5645_PWR_I2S2_BIT 14 | |
776 | #define RT5645_PWR_I2S3 (0x1 << 13) | |
777 | #define RT5645_PWR_I2S3_BIT 13 | |
778 | #define RT5645_PWR_DAC_L1 (0x1 << 12) | |
779 | #define RT5645_PWR_DAC_L1_BIT 12 | |
780 | #define RT5645_PWR_DAC_R1 (0x1 << 11) | |
781 | #define RT5645_PWR_DAC_R1_BIT 11 | |
782 | #define RT5645_PWR_CLS_D_R (0x1 << 9) | |
783 | #define RT5645_PWR_CLS_D_R_BIT 9 | |
784 | #define RT5645_PWR_CLS_D_L (0x1 << 8) | |
785 | #define RT5645_PWR_CLS_D_L_BIT 8 | |
1319b2f6 OC |
786 | #define RT5645_PWR_DAC_L2 (0x1 << 7) |
787 | #define RT5645_PWR_DAC_L2_BIT 7 | |
788 | #define RT5645_PWR_DAC_R2 (0x1 << 6) | |
789 | #define RT5645_PWR_DAC_R2_BIT 6 | |
790 | #define RT5645_PWR_ADC_L (0x1 << 2) | |
791 | #define RT5645_PWR_ADC_L_BIT 2 | |
792 | #define RT5645_PWR_ADC_R (0x1 << 1) | |
793 | #define RT5645_PWR_ADC_R_BIT 1 | |
794 | #define RT5645_PWR_CLS_D (0x1) | |
795 | #define RT5645_PWR_CLS_D_BIT 0 | |
796 | ||
797 | /* Power Management for Digital 2 (0x62) */ | |
798 | #define RT5645_PWR_ADC_S1F (0x1 << 15) | |
799 | #define RT5645_PWR_ADC_S1F_BIT 15 | |
800 | #define RT5645_PWR_ADC_MF_L (0x1 << 14) | |
801 | #define RT5645_PWR_ADC_MF_L_BIT 14 | |
802 | #define RT5645_PWR_ADC_MF_R (0x1 << 13) | |
803 | #define RT5645_PWR_ADC_MF_R_BIT 13 | |
804 | #define RT5645_PWR_I2S_DSP (0x1 << 12) | |
805 | #define RT5645_PWR_I2S_DSP_BIT 12 | |
806 | #define RT5645_PWR_DAC_S1F (0x1 << 11) | |
807 | #define RT5645_PWR_DAC_S1F_BIT 11 | |
808 | #define RT5645_PWR_DAC_MF_L (0x1 << 10) | |
809 | #define RT5645_PWR_DAC_MF_L_BIT 10 | |
810 | #define RT5645_PWR_DAC_MF_R (0x1 << 9) | |
811 | #define RT5645_PWR_DAC_MF_R_BIT 9 | |
1319b2f6 OC |
812 | #define RT5645_PWR_PDM1 (0x1 << 7) |
813 | #define RT5645_PWR_PDM1_BIT 7 | |
814 | #define RT5645_PWR_PDM2 (0x1 << 6) | |
815 | #define RT5645_PWR_PDM2_BIT 6 | |
816 | #define RT5645_PWR_IPTV (0x1 << 1) | |
817 | #define RT5645_PWR_IPTV_BIT 1 | |
818 | #define RT5645_PWR_PAD (0x1) | |
819 | #define RT5645_PWR_PAD_BIT 0 | |
820 | ||
821 | /* Power Management for Analog 1 (0x63) */ | |
822 | #define RT5645_PWR_VREF1 (0x1 << 15) | |
823 | #define RT5645_PWR_VREF1_BIT 15 | |
824 | #define RT5645_PWR_FV1 (0x1 << 14) | |
825 | #define RT5645_PWR_FV1_BIT 14 | |
826 | #define RT5645_PWR_MB (0x1 << 13) | |
827 | #define RT5645_PWR_MB_BIT 13 | |
828 | #define RT5645_PWR_LM (0x1 << 12) | |
829 | #define RT5645_PWR_LM_BIT 12 | |
830 | #define RT5645_PWR_BG (0x1 << 11) | |
831 | #define RT5645_PWR_BG_BIT 11 | |
832 | #define RT5645_PWR_MA (0x1 << 10) | |
833 | #define RT5645_PWR_MA_BIT 10 | |
834 | #define RT5645_PWR_HP_L (0x1 << 7) | |
835 | #define RT5645_PWR_HP_L_BIT 7 | |
836 | #define RT5645_PWR_HP_R (0x1 << 6) | |
837 | #define RT5645_PWR_HP_R_BIT 6 | |
838 | #define RT5645_PWR_HA (0x1 << 5) | |
839 | #define RT5645_PWR_HA_BIT 5 | |
840 | #define RT5645_PWR_VREF2 (0x1 << 4) | |
841 | #define RT5645_PWR_VREF2_BIT 4 | |
842 | #define RT5645_PWR_FV2 (0x1 << 3) | |
843 | #define RT5645_PWR_FV2_BIT 3 | |
844 | #define RT5645_LDO_SEL_MASK (0x3) | |
845 | #define RT5645_LDO_SEL_SFT 0 | |
846 | ||
847 | /* Power Management for Analog 2 (0x64) */ | |
848 | #define RT5645_PWR_BST1 (0x1 << 15) | |
849 | #define RT5645_PWR_BST1_BIT 15 | |
850 | #define RT5645_PWR_BST2 (0x1 << 14) | |
851 | #define RT5645_PWR_BST2_BIT 14 | |
852 | #define RT5645_PWR_BST3 (0x1 << 13) | |
853 | #define RT5645_PWR_BST3_BIT 13 | |
854 | #define RT5645_PWR_BST4 (0x1 << 12) | |
855 | #define RT5645_PWR_BST4_BIT 12 | |
856 | #define RT5645_PWR_MB1 (0x1 << 11) | |
857 | #define RT5645_PWR_MB1_BIT 11 | |
858 | #define RT5645_PWR_MB2 (0x1 << 10) | |
859 | #define RT5645_PWR_MB2_BIT 10 | |
860 | #define RT5645_PWR_PLL (0x1 << 9) | |
861 | #define RT5645_PWR_PLL_BIT 9 | |
862 | #define RT5645_PWR_BST2_P (0x1 << 5) | |
863 | #define RT5645_PWR_BST2_P_BIT 5 | |
864 | #define RT5645_PWR_BST3_P (0x1 << 4) | |
865 | #define RT5645_PWR_BST3_P_BIT 4 | |
866 | #define RT5645_PWR_BST4_P (0x1 << 3) | |
867 | #define RT5645_PWR_BST4_P_BIT 3 | |
868 | #define RT5645_PWR_JD1 (0x1 << 2) | |
869 | #define RT5645_PWR_JD1_BIT 2 | |
870 | #define RT5645_PWR_JD (0x1 << 1) | |
871 | #define RT5645_PWR_JD_BIT 1 | |
872 | ||
873 | /* Power Management for Mixer (0x65) */ | |
874 | #define RT5645_PWR_OM_L (0x1 << 15) | |
875 | #define RT5645_PWR_OM_L_BIT 15 | |
876 | #define RT5645_PWR_OM_R (0x1 << 14) | |
877 | #define RT5645_PWR_OM_R_BIT 14 | |
878 | #define RT5645_PWR_SM_L (0x1 << 13) | |
879 | #define RT5645_PWR_SM_L_BIT 13 | |
880 | #define RT5645_PWR_SM_R (0x1 << 12) | |
881 | #define RT5645_PWR_SM_R_BIT 12 | |
882 | #define RT5645_PWR_RM_L (0x1 << 11) | |
883 | #define RT5645_PWR_RM_L_BIT 11 | |
884 | #define RT5645_PWR_RM_R (0x1 << 10) | |
885 | #define RT5645_PWR_RM_R_BIT 10 | |
886 | #define RT5645_PWR_MM (0x1 << 8) | |
887 | #define RT5645_PWR_MM_BIT 8 | |
888 | #define RT5645_PWR_HM_L (0x1 << 7) | |
889 | #define RT5645_PWR_HM_L_BIT 7 | |
890 | #define RT5645_PWR_HM_R (0x1 << 6) | |
891 | #define RT5645_PWR_HM_R_BIT 6 | |
892 | #define RT5645_PWR_LDO2 (0x1 << 1) | |
893 | #define RT5645_PWR_LDO2_BIT 1 | |
894 | ||
895 | /* Power Management for Volume (0x66) */ | |
896 | #define RT5645_PWR_SV_L (0x1 << 15) | |
897 | #define RT5645_PWR_SV_L_BIT 15 | |
898 | #define RT5645_PWR_SV_R (0x1 << 14) | |
899 | #define RT5645_PWR_SV_R_BIT 14 | |
900 | #define RT5645_PWR_HV_L (0x1 << 11) | |
901 | #define RT5645_PWR_HV_L_BIT 11 | |
902 | #define RT5645_PWR_HV_R (0x1 << 10) | |
903 | #define RT5645_PWR_HV_R_BIT 10 | |
904 | #define RT5645_PWR_IN_L (0x1 << 9) | |
905 | #define RT5645_PWR_IN_L_BIT 9 | |
906 | #define RT5645_PWR_IN_R (0x1 << 8) | |
907 | #define RT5645_PWR_IN_R_BIT 8 | |
908 | #define RT5645_PWR_MIC_DET (0x1 << 5) | |
909 | #define RT5645_PWR_MIC_DET_BIT 5 | |
910 | ||
911 | /* I2S1/2 Audio Serial Data Port Control (0x70 0x71) */ | |
912 | #define RT5645_I2S_MS_MASK (0x1 << 15) | |
913 | #define RT5645_I2S_MS_SFT 15 | |
914 | #define RT5645_I2S_MS_M (0x0 << 15) | |
915 | #define RT5645_I2S_MS_S (0x1 << 15) | |
916 | #define RT5645_I2S_O_CP_MASK (0x3 << 10) | |
917 | #define RT5645_I2S_O_CP_SFT 10 | |
918 | #define RT5645_I2S_O_CP_OFF (0x0 << 10) | |
919 | #define RT5645_I2S_O_CP_U_LAW (0x1 << 10) | |
920 | #define RT5645_I2S_O_CP_A_LAW (0x2 << 10) | |
921 | #define RT5645_I2S_I_CP_MASK (0x3 << 8) | |
922 | #define RT5645_I2S_I_CP_SFT 8 | |
923 | #define RT5645_I2S_I_CP_OFF (0x0 << 8) | |
924 | #define RT5645_I2S_I_CP_U_LAW (0x1 << 8) | |
925 | #define RT5645_I2S_I_CP_A_LAW (0x2 << 8) | |
926 | #define RT5645_I2S_BP_MASK (0x1 << 7) | |
927 | #define RT5645_I2S_BP_SFT 7 | |
928 | #define RT5645_I2S_BP_NOR (0x0 << 7) | |
929 | #define RT5645_I2S_BP_INV (0x1 << 7) | |
930 | #define RT5645_I2S_DL_MASK (0x3 << 2) | |
931 | #define RT5645_I2S_DL_SFT 2 | |
932 | #define RT5645_I2S_DL_16 (0x0 << 2) | |
933 | #define RT5645_I2S_DL_20 (0x1 << 2) | |
934 | #define RT5645_I2S_DL_24 (0x2 << 2) | |
935 | #define RT5645_I2S_DL_8 (0x3 << 2) | |
936 | #define RT5645_I2S_DF_MASK (0x3) | |
937 | #define RT5645_I2S_DF_SFT 0 | |
938 | #define RT5645_I2S_DF_I2S (0x0) | |
939 | #define RT5645_I2S_DF_LEFT (0x1) | |
940 | #define RT5645_I2S_DF_PCM_A (0x2) | |
941 | #define RT5645_I2S_DF_PCM_B (0x3) | |
942 | ||
943 | /* I2S2 Audio Serial Data Port Control (0x71) */ | |
944 | #define RT5645_I2S2_SDI_MASK (0x1 << 6) | |
945 | #define RT5645_I2S2_SDI_SFT 6 | |
946 | #define RT5645_I2S2_SDI_I2S1 (0x0 << 6) | |
947 | #define RT5645_I2S2_SDI_I2S2 (0x1 << 6) | |
948 | ||
949 | /* ADC/DAC Clock Control 1 (0x73) */ | |
1319b2f6 OC |
950 | #define RT5645_I2S_PD1_MASK (0x7 << 12) |
951 | #define RT5645_I2S_PD1_SFT 12 | |
952 | #define RT5645_I2S_PD1_1 (0x0 << 12) | |
953 | #define RT5645_I2S_PD1_2 (0x1 << 12) | |
954 | #define RT5645_I2S_PD1_3 (0x2 << 12) | |
955 | #define RT5645_I2S_PD1_4 (0x3 << 12) | |
956 | #define RT5645_I2S_PD1_6 (0x4 << 12) | |
957 | #define RT5645_I2S_PD1_8 (0x5 << 12) | |
958 | #define RT5645_I2S_PD1_12 (0x6 << 12) | |
959 | #define RT5645_I2S_PD1_16 (0x7 << 12) | |
960 | #define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11) | |
961 | #define RT5645_I2S_BCLK_MS2_SFT 11 | |
962 | #define RT5645_I2S_BCLK_MS2_32 (0x0 << 11) | |
963 | #define RT5645_I2S_BCLK_MS2_64 (0x1 << 11) | |
964 | #define RT5645_I2S_PD2_MASK (0x7 << 8) | |
965 | #define RT5645_I2S_PD2_SFT 8 | |
966 | #define RT5645_I2S_PD2_1 (0x0 << 8) | |
967 | #define RT5645_I2S_PD2_2 (0x1 << 8) | |
968 | #define RT5645_I2S_PD2_3 (0x2 << 8) | |
969 | #define RT5645_I2S_PD2_4 (0x3 << 8) | |
970 | #define RT5645_I2S_PD2_6 (0x4 << 8) | |
971 | #define RT5645_I2S_PD2_8 (0x5 << 8) | |
972 | #define RT5645_I2S_PD2_12 (0x6 << 8) | |
973 | #define RT5645_I2S_PD2_16 (0x7 << 8) | |
974 | #define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7) | |
975 | #define RT5645_I2S_BCLK_MS3_SFT 7 | |
976 | #define RT5645_I2S_BCLK_MS3_32 (0x0 << 7) | |
977 | #define RT5645_I2S_BCLK_MS3_64 (0x1 << 7) | |
978 | #define RT5645_I2S_PD3_MASK (0x7 << 4) | |
979 | #define RT5645_I2S_PD3_SFT 4 | |
980 | #define RT5645_I2S_PD3_1 (0x0 << 4) | |
981 | #define RT5645_I2S_PD3_2 (0x1 << 4) | |
982 | #define RT5645_I2S_PD3_3 (0x2 << 4) | |
983 | #define RT5645_I2S_PD3_4 (0x3 << 4) | |
984 | #define RT5645_I2S_PD3_6 (0x4 << 4) | |
985 | #define RT5645_I2S_PD3_8 (0x5 << 4) | |
986 | #define RT5645_I2S_PD3_12 (0x6 << 4) | |
987 | #define RT5645_I2S_PD3_16 (0x7 << 4) | |
988 | #define RT5645_DAC_OSR_MASK (0x3 << 2) | |
989 | #define RT5645_DAC_OSR_SFT 2 | |
990 | #define RT5645_DAC_OSR_128 (0x0 << 2) | |
991 | #define RT5645_DAC_OSR_64 (0x1 << 2) | |
992 | #define RT5645_DAC_OSR_32 (0x2 << 2) | |
993 | #define RT5645_DAC_OSR_16 (0x3 << 2) | |
994 | #define RT5645_ADC_OSR_MASK (0x3) | |
995 | #define RT5645_ADC_OSR_SFT 0 | |
996 | #define RT5645_ADC_OSR_128 (0x0) | |
997 | #define RT5645_ADC_OSR_64 (0x1) | |
998 | #define RT5645_ADC_OSR_32 (0x2) | |
999 | #define RT5645_ADC_OSR_16 (0x3) | |
1000 | ||
1001 | /* ADC/DAC Clock Control 2 (0x74) */ | |
1002 | #define RT5645_DAC_L_OSR_MASK (0x3 << 14) | |
1003 | #define RT5645_DAC_L_OSR_SFT 14 | |
1004 | #define RT5645_DAC_L_OSR_128 (0x0 << 14) | |
1005 | #define RT5645_DAC_L_OSR_64 (0x1 << 14) | |
1006 | #define RT5645_DAC_L_OSR_32 (0x2 << 14) | |
1007 | #define RT5645_DAC_L_OSR_16 (0x3 << 14) | |
1008 | #define RT5645_ADC_R_OSR_MASK (0x3 << 12) | |
1009 | #define RT5645_ADC_R_OSR_SFT 12 | |
1010 | #define RT5645_ADC_R_OSR_128 (0x0 << 12) | |
1011 | #define RT5645_ADC_R_OSR_64 (0x1 << 12) | |
1012 | #define RT5645_ADC_R_OSR_32 (0x2 << 12) | |
1013 | #define RT5645_ADC_R_OSR_16 (0x3 << 12) | |
1014 | #define RT5645_DAHPF_EN (0x1 << 11) | |
1015 | #define RT5645_DAHPF_EN_SFT 11 | |
1016 | #define RT5645_ADHPF_EN (0x1 << 10) | |
1017 | #define RT5645_ADHPF_EN_SFT 10 | |
1018 | ||
1019 | /* Digital Microphone Control (0x75) */ | |
1020 | #define RT5645_DMIC_1_EN_MASK (0x1 << 15) | |
1021 | #define RT5645_DMIC_1_EN_SFT 15 | |
1022 | #define RT5645_DMIC_1_DIS (0x0 << 15) | |
1023 | #define RT5645_DMIC_1_EN (0x1 << 15) | |
1024 | #define RT5645_DMIC_2_EN_MASK (0x1 << 14) | |
1025 | #define RT5645_DMIC_2_EN_SFT 14 | |
1026 | #define RT5645_DMIC_2_DIS (0x0 << 14) | |
1027 | #define RT5645_DMIC_2_EN (0x1 << 14) | |
1028 | #define RT5645_DMIC_1L_LH_MASK (0x1 << 13) | |
1029 | #define RT5645_DMIC_1L_LH_SFT 13 | |
1030 | #define RT5645_DMIC_1L_LH_FALLING (0x0 << 13) | |
1031 | #define RT5645_DMIC_1L_LH_RISING (0x1 << 13) | |
1032 | #define RT5645_DMIC_1R_LH_MASK (0x1 << 12) | |
1033 | #define RT5645_DMIC_1R_LH_SFT 12 | |
1034 | #define RT5645_DMIC_1R_LH_FALLING (0x0 << 12) | |
1035 | #define RT5645_DMIC_1R_LH_RISING (0x1 << 12) | |
1036 | #define RT5645_DMIC_2_DP_MASK (0x3 << 10) | |
1037 | #define RT5645_DMIC_2_DP_SFT 10 | |
1038 | #define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10) | |
1039 | #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10) | |
1040 | #define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10) | |
1041 | #define RT5645_DMIC_2_DP_IN2P (0x3 << 10) | |
1042 | #define RT5645_DMIC_2L_LH_MASK (0x1 << 9) | |
1043 | #define RT5645_DMIC_2L_LH_SFT 9 | |
1044 | #define RT5645_DMIC_2L_LH_FALLING (0x0 << 9) | |
1045 | #define RT5645_DMIC_2L_LH_RISING (0x1 << 9) | |
1046 | #define RT5645_DMIC_2R_LH_MASK (0x1 << 8) | |
1047 | #define RT5645_DMIC_2R_LH_SFT 8 | |
1048 | #define RT5645_DMIC_2R_LH_FALLING (0x0 << 8) | |
1049 | #define RT5645_DMIC_2R_LH_RISING (0x1 << 8) | |
1050 | #define RT5645_DMIC_CLK_MASK (0x7 << 5) | |
1051 | #define RT5645_DMIC_CLK_SFT 5 | |
1052 | #define RT5645_DMIC_3_EN_MASK (0x1 << 4) | |
1053 | #define RT5645_DMIC_3_EN_SFT 4 | |
1054 | #define RT5645_DMIC_3_DIS (0x0 << 4) | |
1055 | #define RT5645_DMIC_3_EN (0x1 << 4) | |
1056 | #define RT5645_DMIC_1_DP_MASK (0x3 << 0) | |
1057 | #define RT5645_DMIC_1_DP_SFT 0 | |
1058 | #define RT5645_DMIC_1_DP_GPIO5 (0x0 << 0) | |
1059 | #define RT5645_DMIC_1_DP_IN2N (0x1 << 0) | |
1060 | #define RT5645_DMIC_1_DP_GPIO11 (0x2 << 0) | |
1061 | ||
1062 | /* TDM Control 1 (0x77) */ | |
1063 | #define RT5645_IF1_ADC_IN_MASK (0x3 << 8) | |
1064 | #define RT5645_IF1_ADC_IN_SFT 8 | |
1065 | ||
1066 | /* Global Clock Control (0x80) */ | |
1067 | #define RT5645_SCLK_SRC_MASK (0x3 << 14) | |
1068 | #define RT5645_SCLK_SRC_SFT 14 | |
1069 | #define RT5645_SCLK_SRC_MCLK (0x0 << 14) | |
1070 | #define RT5645_SCLK_SRC_PLL1 (0x1 << 14) | |
de97c15b BL |
1071 | #define RT5645_SCLK_SRC_RCCLK (0x2 << 14) |
1072 | #define RT5645_PLL1_SRC_MASK (0x7 << 11) | |
1073 | #define RT5645_PLL1_SRC_SFT 11 | |
1074 | #define RT5645_PLL1_SRC_MCLK (0x0 << 11) | |
1075 | #define RT5645_PLL1_SRC_BCLK1 (0x1 << 11) | |
1076 | #define RT5645_PLL1_SRC_BCLK2 (0x2 << 11) | |
1077 | #define RT5645_PLL1_SRC_BCLK3 (0x3 << 11) | |
1078 | #define RT5645_PLL1_SRC_RCCLK (0x4 << 11) | |
1319b2f6 OC |
1079 | #define RT5645_PLL1_PD_MASK (0x1 << 3) |
1080 | #define RT5645_PLL1_PD_SFT 3 | |
1081 | #define RT5645_PLL1_PD_1 (0x0 << 3) | |
1082 | #define RT5645_PLL1_PD_2 (0x1 << 3) | |
1083 | ||
1084 | #define RT5645_PLL_INP_MAX 40000000 | |
1085 | #define RT5645_PLL_INP_MIN 256000 | |
1086 | /* PLL M/N/K Code Control 1 (0x81) */ | |
1087 | #define RT5645_PLL_N_MAX 0x1ff | |
1088 | #define RT5645_PLL_N_MASK (RT5645_PLL_N_MAX << 7) | |
1089 | #define RT5645_PLL_N_SFT 7 | |
1090 | #define RT5645_PLL_K_MAX 0x1f | |
1091 | #define RT5645_PLL_K_MASK (RT5645_PLL_K_MAX) | |
1092 | #define RT5645_PLL_K_SFT 0 | |
1093 | ||
1094 | /* PLL M/N/K Code Control 2 (0x82) */ | |
1095 | #define RT5645_PLL_M_MAX 0xf | |
1096 | #define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12) | |
1097 | #define RT5645_PLL_M_SFT 12 | |
1098 | #define RT5645_PLL_M_BP (0x1 << 11) | |
1099 | #define RT5645_PLL_M_BP_SFT 11 | |
1100 | ||
1101 | /* ASRC Control 1 (0x83) */ | |
1102 | #define RT5645_STO_T_MASK (0x1 << 15) | |
1103 | #define RT5645_STO_T_SFT 15 | |
1104 | #define RT5645_STO_T_SCLK (0x0 << 15) | |
1105 | #define RT5645_STO_T_LRCK1 (0x1 << 15) | |
1106 | #define RT5645_M1_T_MASK (0x1 << 14) | |
1107 | #define RT5645_M1_T_SFT 14 | |
1108 | #define RT5645_M1_T_I2S2 (0x0 << 14) | |
1109 | #define RT5645_M1_T_I2S2_D3 (0x1 << 14) | |
1110 | #define RT5645_I2S2_F_MASK (0x1 << 12) | |
1111 | #define RT5645_I2S2_F_SFT 12 | |
1112 | #define RT5645_I2S2_F_I2S2_D2 (0x0 << 12) | |
1113 | #define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12) | |
1114 | #define RT5645_DMIC_1_M_MASK (0x1 << 9) | |
1115 | #define RT5645_DMIC_1_M_SFT 9 | |
1116 | #define RT5645_DMIC_1_M_NOR (0x0 << 9) | |
1117 | #define RT5645_DMIC_1_M_ASYN (0x1 << 9) | |
1118 | #define RT5645_DMIC_2_M_MASK (0x1 << 8) | |
1119 | #define RT5645_DMIC_2_M_SFT 8 | |
1120 | #define RT5645_DMIC_2_M_NOR (0x0 << 8) | |
1121 | #define RT5645_DMIC_2_M_ASYN (0x1 << 8) | |
1122 | ||
79080a8b FY |
1123 | /* ASRC clock source selection (0x84, 0x85) */ |
1124 | #define RT5645_CLK_SEL_SYS (0x0) | |
1125 | #define RT5645_CLK_SEL_I2S1_ASRC (0x1) | |
1126 | #define RT5645_CLK_SEL_I2S2_ASRC (0x2) | |
1127 | #define RT5645_CLK_SEL_SYS2 (0x5) | |
1128 | ||
1319b2f6 | 1129 | /* ASRC Control 2 (0x84) */ |
79080a8b FY |
1130 | #define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12) |
1131 | #define RT5645_DA_STO_CLK_SEL_SFT 12 | |
1132 | #define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8) | |
1133 | #define RT5645_DA_MONOL_CLK_SEL_SFT 8 | |
1134 | #define RT5645_DA_MONOR_CLK_SEL_MASK (0xf << 4) | |
1135 | #define RT5645_DA_MONOR_CLK_SEL_SFT 4 | |
1136 | #define RT5645_AD_STO1_CLK_SEL_MASK (0xf << 0) | |
1137 | #define RT5645_AD_STO1_CLK_SEL_SFT 0 | |
1319b2f6 OC |
1138 | |
1139 | /* ASRC Control 3 (0x85) */ | |
79080a8b FY |
1140 | #define RT5645_AD_MONOL_CLK_SEL_MASK (0xf << 4) |
1141 | #define RT5645_AD_MONOL_CLK_SEL_SFT 4 | |
1142 | #define RT5645_AD_MONOR_CLK_SEL_MASK (0xf << 0) | |
1143 | #define RT5645_AD_MONOR_CLK_SEL_SFT 0 | |
1319b2f6 OC |
1144 | |
1145 | /* ASRC Control 4 (0x89) */ | |
1146 | #define RT5645_I2S1_PD_MASK (0x7 << 12) | |
1147 | #define RT5645_I2S1_PD_SFT 12 | |
1148 | #define RT5645_I2S2_PD_MASK (0x7 << 8) | |
1149 | #define RT5645_I2S2_PD_SFT 8 | |
1150 | ||
1151 | /* HPOUT Over Current Detection (0x8b) */ | |
1152 | #define RT5645_HP_OVCD_MASK (0x1 << 10) | |
1153 | #define RT5645_HP_OVCD_SFT 10 | |
1154 | #define RT5645_HP_OVCD_DIS (0x0 << 10) | |
1155 | #define RT5645_HP_OVCD_EN (0x1 << 10) | |
1156 | #define RT5645_HP_OC_TH_MASK (0x3 << 8) | |
1157 | #define RT5645_HP_OC_TH_SFT 8 | |
1158 | #define RT5645_HP_OC_TH_90 (0x0 << 8) | |
1159 | #define RT5645_HP_OC_TH_105 (0x1 << 8) | |
1160 | #define RT5645_HP_OC_TH_120 (0x2 << 8) | |
1161 | #define RT5645_HP_OC_TH_135 (0x3 << 8) | |
1162 | ||
1163 | /* Class D Over Current Control (0x8c) */ | |
1164 | #define RT5645_CLSD_OC_MASK (0x1 << 9) | |
1165 | #define RT5645_CLSD_OC_SFT 9 | |
1166 | #define RT5645_CLSD_OC_PU (0x0 << 9) | |
1167 | #define RT5645_CLSD_OC_PD (0x1 << 9) | |
1168 | #define RT5645_AUTO_PD_MASK (0x1 << 8) | |
1169 | #define RT5645_AUTO_PD_SFT 8 | |
1170 | #define RT5645_AUTO_PD_DIS (0x0 << 8) | |
1171 | #define RT5645_AUTO_PD_EN (0x1 << 8) | |
1172 | #define RT5645_CLSD_OC_TH_MASK (0x3f) | |
1173 | #define RT5645_CLSD_OC_TH_SFT 0 | |
1174 | ||
1175 | /* Class D Output Control (0x8d) */ | |
1176 | #define RT5645_CLSD_RATIO_MASK (0xf << 12) | |
1177 | #define RT5645_CLSD_RATIO_SFT 12 | |
1178 | #define RT5645_CLSD_OM_MASK (0x1 << 11) | |
1179 | #define RT5645_CLSD_OM_SFT 11 | |
1180 | #define RT5645_CLSD_OM_MONO (0x0 << 11) | |
1181 | #define RT5645_CLSD_OM_STO (0x1 << 11) | |
1182 | #define RT5645_CLSD_SCH_MASK (0x1 << 10) | |
1183 | #define RT5645_CLSD_SCH_SFT 10 | |
1184 | #define RT5645_CLSD_SCH_L (0x0 << 10) | |
1185 | #define RT5645_CLSD_SCH_S (0x1 << 10) | |
1186 | ||
1187 | /* Depop Mode Control 1 (0x8e) */ | |
1188 | #define RT5645_SMT_TRIG_MASK (0x1 << 15) | |
1189 | #define RT5645_SMT_TRIG_SFT 15 | |
1190 | #define RT5645_SMT_TRIG_DIS (0x0 << 15) | |
1191 | #define RT5645_SMT_TRIG_EN (0x1 << 15) | |
1192 | #define RT5645_HP_L_SMT_MASK (0x1 << 9) | |
1193 | #define RT5645_HP_L_SMT_SFT 9 | |
1194 | #define RT5645_HP_L_SMT_DIS (0x0 << 9) | |
1195 | #define RT5645_HP_L_SMT_EN (0x1 << 9) | |
1196 | #define RT5645_HP_R_SMT_MASK (0x1 << 8) | |
1197 | #define RT5645_HP_R_SMT_SFT 8 | |
1198 | #define RT5645_HP_R_SMT_DIS (0x0 << 8) | |
1199 | #define RT5645_HP_R_SMT_EN (0x1 << 8) | |
1200 | #define RT5645_HP_CD_PD_MASK (0x1 << 7) | |
1201 | #define RT5645_HP_CD_PD_SFT 7 | |
1202 | #define RT5645_HP_CD_PD_DIS (0x0 << 7) | |
1203 | #define RT5645_HP_CD_PD_EN (0x1 << 7) | |
1204 | #define RT5645_RSTN_MASK (0x1 << 6) | |
1205 | #define RT5645_RSTN_SFT 6 | |
1206 | #define RT5645_RSTN_DIS (0x0 << 6) | |
1207 | #define RT5645_RSTN_EN (0x1 << 6) | |
1208 | #define RT5645_RSTP_MASK (0x1 << 5) | |
1209 | #define RT5645_RSTP_SFT 5 | |
1210 | #define RT5645_RSTP_DIS (0x0 << 5) | |
1211 | #define RT5645_RSTP_EN (0x1 << 5) | |
1212 | #define RT5645_HP_CO_MASK (0x1 << 4) | |
1213 | #define RT5645_HP_CO_SFT 4 | |
1214 | #define RT5645_HP_CO_DIS (0x0 << 4) | |
1215 | #define RT5645_HP_CO_EN (0x1 << 4) | |
1216 | #define RT5645_HP_CP_MASK (0x1 << 3) | |
1217 | #define RT5645_HP_CP_SFT 3 | |
1218 | #define RT5645_HP_CP_PD (0x0 << 3) | |
1219 | #define RT5645_HP_CP_PU (0x1 << 3) | |
1220 | #define RT5645_HP_SG_MASK (0x1 << 2) | |
1221 | #define RT5645_HP_SG_SFT 2 | |
1222 | #define RT5645_HP_SG_DIS (0x0 << 2) | |
1223 | #define RT5645_HP_SG_EN (0x1 << 2) | |
1224 | #define RT5645_HP_DP_MASK (0x1 << 1) | |
1225 | #define RT5645_HP_DP_SFT 1 | |
1226 | #define RT5645_HP_DP_PD (0x0 << 1) | |
1227 | #define RT5645_HP_DP_PU (0x1 << 1) | |
1228 | #define RT5645_HP_CB_MASK (0x1) | |
1229 | #define RT5645_HP_CB_SFT 0 | |
1230 | #define RT5645_HP_CB_PD (0x0) | |
1231 | #define RT5645_HP_CB_PU (0x1) | |
1232 | ||
1233 | /* Depop Mode Control 2 (0x8f) */ | |
1234 | #define RT5645_DEPOP_MASK (0x1 << 13) | |
1235 | #define RT5645_DEPOP_SFT 13 | |
1236 | #define RT5645_DEPOP_AUTO (0x0 << 13) | |
1237 | #define RT5645_DEPOP_MAN (0x1 << 13) | |
1238 | #define RT5645_RAMP_MASK (0x1 << 12) | |
1239 | #define RT5645_RAMP_SFT 12 | |
1240 | #define RT5645_RAMP_DIS (0x0 << 12) | |
1241 | #define RT5645_RAMP_EN (0x1 << 12) | |
1242 | #define RT5645_BPS_MASK (0x1 << 11) | |
1243 | #define RT5645_BPS_SFT 11 | |
1244 | #define RT5645_BPS_DIS (0x0 << 11) | |
1245 | #define RT5645_BPS_EN (0x1 << 11) | |
1246 | #define RT5645_FAST_UPDN_MASK (0x1 << 10) | |
1247 | #define RT5645_FAST_UPDN_SFT 10 | |
1248 | #define RT5645_FAST_UPDN_DIS (0x0 << 10) | |
1249 | #define RT5645_FAST_UPDN_EN (0x1 << 10) | |
1250 | #define RT5645_MRES_MASK (0x3 << 8) | |
1251 | #define RT5645_MRES_SFT 8 | |
1252 | #define RT5645_MRES_15MO (0x0 << 8) | |
1253 | #define RT5645_MRES_25MO (0x1 << 8) | |
1254 | #define RT5645_MRES_35MO (0x2 << 8) | |
1255 | #define RT5645_MRES_45MO (0x3 << 8) | |
1256 | #define RT5645_VLO_MASK (0x1 << 7) | |
1257 | #define RT5645_VLO_SFT 7 | |
1258 | #define RT5645_VLO_3V (0x0 << 7) | |
1259 | #define RT5645_VLO_32V (0x1 << 7) | |
1260 | #define RT5645_DIG_DP_MASK (0x1 << 6) | |
1261 | #define RT5645_DIG_DP_SFT 6 | |
1262 | #define RT5645_DIG_DP_DIS (0x0 << 6) | |
1263 | #define RT5645_DIG_DP_EN (0x1 << 6) | |
1264 | #define RT5645_DP_TH_MASK (0x3 << 4) | |
1265 | #define RT5645_DP_TH_SFT 4 | |
1266 | ||
1267 | /* Depop Mode Control 3 (0x90) */ | |
1268 | #define RT5645_CP_SYS_MASK (0x7 << 12) | |
1269 | #define RT5645_CP_SYS_SFT 12 | |
1270 | #define RT5645_CP_FQ1_MASK (0x7 << 8) | |
1271 | #define RT5645_CP_FQ1_SFT 8 | |
1272 | #define RT5645_CP_FQ2_MASK (0x7 << 4) | |
1273 | #define RT5645_CP_FQ2_SFT 4 | |
1274 | #define RT5645_CP_FQ3_MASK (0x7) | |
1275 | #define RT5645_CP_FQ3_SFT 0 | |
1276 | #define RT5645_CP_FQ_1_5_KHZ 0 | |
1277 | #define RT5645_CP_FQ_3_KHZ 1 | |
1278 | #define RT5645_CP_FQ_6_KHZ 2 | |
1279 | #define RT5645_CP_FQ_12_KHZ 3 | |
1280 | #define RT5645_CP_FQ_24_KHZ 4 | |
1281 | #define RT5645_CP_FQ_48_KHZ 5 | |
1282 | #define RT5645_CP_FQ_96_KHZ 6 | |
1283 | #define RT5645_CP_FQ_192_KHZ 7 | |
1284 | ||
1285 | /* PV detection and SPK gain control (0x92) */ | |
1286 | #define RT5645_PVDD_DET_MASK (0x1 << 15) | |
1287 | #define RT5645_PVDD_DET_SFT 15 | |
1288 | #define RT5645_PVDD_DET_DIS (0x0 << 15) | |
1289 | #define RT5645_PVDD_DET_EN (0x1 << 15) | |
1290 | #define RT5645_SPK_AG_MASK (0x1 << 14) | |
1291 | #define RT5645_SPK_AG_SFT 14 | |
1292 | #define RT5645_SPK_AG_DIS (0x0 << 14) | |
1293 | #define RT5645_SPK_AG_EN (0x1 << 14) | |
1294 | ||
1295 | /* Micbias Control (0x93) */ | |
1296 | #define RT5645_MIC1_BS_MASK (0x1 << 15) | |
1297 | #define RT5645_MIC1_BS_SFT 15 | |
1298 | #define RT5645_MIC1_BS_9AV (0x0 << 15) | |
1299 | #define RT5645_MIC1_BS_75AV (0x1 << 15) | |
1300 | #define RT5645_MIC2_BS_MASK (0x1 << 14) | |
1301 | #define RT5645_MIC2_BS_SFT 14 | |
1302 | #define RT5645_MIC2_BS_9AV (0x0 << 14) | |
1303 | #define RT5645_MIC2_BS_75AV (0x1 << 14) | |
1304 | #define RT5645_MIC1_CLK_MASK (0x1 << 13) | |
1305 | #define RT5645_MIC1_CLK_SFT 13 | |
1306 | #define RT5645_MIC1_CLK_DIS (0x0 << 13) | |
1307 | #define RT5645_MIC1_CLK_EN (0x1 << 13) | |
1308 | #define RT5645_MIC2_CLK_MASK (0x1 << 12) | |
1309 | #define RT5645_MIC2_CLK_SFT 12 | |
1310 | #define RT5645_MIC2_CLK_DIS (0x0 << 12) | |
1311 | #define RT5645_MIC2_CLK_EN (0x1 << 12) | |
1312 | #define RT5645_MIC1_OVCD_MASK (0x1 << 11) | |
1313 | #define RT5645_MIC1_OVCD_SFT 11 | |
1314 | #define RT5645_MIC1_OVCD_DIS (0x0 << 11) | |
1315 | #define RT5645_MIC1_OVCD_EN (0x1 << 11) | |
1316 | #define RT5645_MIC1_OVTH_MASK (0x3 << 9) | |
1317 | #define RT5645_MIC1_OVTH_SFT 9 | |
1318 | #define RT5645_MIC1_OVTH_600UA (0x0 << 9) | |
1319 | #define RT5645_MIC1_OVTH_1500UA (0x1 << 9) | |
1320 | #define RT5645_MIC1_OVTH_2000UA (0x2 << 9) | |
1321 | #define RT5645_MIC2_OVCD_MASK (0x1 << 8) | |
1322 | #define RT5645_MIC2_OVCD_SFT 8 | |
1323 | #define RT5645_MIC2_OVCD_DIS (0x0 << 8) | |
1324 | #define RT5645_MIC2_OVCD_EN (0x1 << 8) | |
1325 | #define RT5645_MIC2_OVTH_MASK (0x3 << 6) | |
1326 | #define RT5645_MIC2_OVTH_SFT 6 | |
1327 | #define RT5645_MIC2_OVTH_600UA (0x0 << 6) | |
1328 | #define RT5645_MIC2_OVTH_1500UA (0x1 << 6) | |
1329 | #define RT5645_MIC2_OVTH_2000UA (0x2 << 6) | |
1330 | #define RT5645_PWR_MB_MASK (0x1 << 5) | |
1331 | #define RT5645_PWR_MB_SFT 5 | |
1332 | #define RT5645_PWR_MB_PD (0x0 << 5) | |
1333 | #define RT5645_PWR_MB_PU (0x1 << 5) | |
1334 | #define RT5645_PWR_CLK25M_MASK (0x1 << 4) | |
1335 | #define RT5645_PWR_CLK25M_SFT 4 | |
1336 | #define RT5645_PWR_CLK25M_PD (0x0 << 4) | |
1337 | #define RT5645_PWR_CLK25M_PU (0x1 << 4) | |
bb656add BL |
1338 | #define RT5645_IRQ_CLK_MCLK (0x0 << 3) |
1339 | #define RT5645_IRQ_CLK_INT (0x1 << 3) | |
2d4e2d02 BL |
1340 | #define RT5645_JD1_MODE_MASK (0x3 << 0) |
1341 | #define RT5645_JD1_MODE_0 (0x0 << 0) | |
1342 | #define RT5645_JD1_MODE_1 (0x1 << 0) | |
1343 | #define RT5645_JD1_MODE_2 (0x2 << 0) | |
1319b2f6 OC |
1344 | |
1345 | /* VAD Control 4 (0x9d) */ | |
1346 | #define RT5645_VAD_SEL_MASK (0x3 << 8) | |
1347 | #define RT5645_VAD_SEL_SFT 8 | |
1348 | ||
1349 | /* EQ Control 1 (0xb0) */ | |
1350 | #define RT5645_EQ_SRC_MASK (0x1 << 15) | |
1351 | #define RT5645_EQ_SRC_SFT 15 | |
1352 | #define RT5645_EQ_SRC_DAC (0x0 << 15) | |
1353 | #define RT5645_EQ_SRC_ADC (0x1 << 15) | |
1354 | #define RT5645_EQ_UPD (0x1 << 14) | |
1355 | #define RT5645_EQ_UPD_BIT 14 | |
1356 | #define RT5645_EQ_CD_MASK (0x1 << 13) | |
1357 | #define RT5645_EQ_CD_SFT 13 | |
1358 | #define RT5645_EQ_CD_DIS (0x0 << 13) | |
1359 | #define RT5645_EQ_CD_EN (0x1 << 13) | |
1360 | #define RT5645_EQ_DITH_MASK (0x3 << 8) | |
1361 | #define RT5645_EQ_DITH_SFT 8 | |
1362 | #define RT5645_EQ_DITH_NOR (0x0 << 8) | |
1363 | #define RT5645_EQ_DITH_LSB (0x1 << 8) | |
1364 | #define RT5645_EQ_DITH_LSB_1 (0x2 << 8) | |
1365 | #define RT5645_EQ_DITH_LSB_2 (0x3 << 8) | |
1366 | ||
1367 | /* EQ Control 2 (0xb1) */ | |
1368 | #define RT5645_EQ_HPF1_M_MASK (0x1 << 8) | |
1369 | #define RT5645_EQ_HPF1_M_SFT 8 | |
1370 | #define RT5645_EQ_HPF1_M_HI (0x0 << 8) | |
1371 | #define RT5645_EQ_HPF1_M_1ST (0x1 << 8) | |
1372 | #define RT5645_EQ_LPF1_M_MASK (0x1 << 7) | |
1373 | #define RT5645_EQ_LPF1_M_SFT 7 | |
1374 | #define RT5645_EQ_LPF1_M_LO (0x0 << 7) | |
1375 | #define RT5645_EQ_LPF1_M_1ST (0x1 << 7) | |
1376 | #define RT5645_EQ_HPF2_MASK (0x1 << 6) | |
1377 | #define RT5645_EQ_HPF2_SFT 6 | |
1378 | #define RT5645_EQ_HPF2_DIS (0x0 << 6) | |
1379 | #define RT5645_EQ_HPF2_EN (0x1 << 6) | |
1380 | #define RT5645_EQ_HPF1_MASK (0x1 << 5) | |
1381 | #define RT5645_EQ_HPF1_SFT 5 | |
1382 | #define RT5645_EQ_HPF1_DIS (0x0 << 5) | |
1383 | #define RT5645_EQ_HPF1_EN (0x1 << 5) | |
1384 | #define RT5645_EQ_BPF4_MASK (0x1 << 4) | |
1385 | #define RT5645_EQ_BPF4_SFT 4 | |
1386 | #define RT5645_EQ_BPF4_DIS (0x0 << 4) | |
1387 | #define RT5645_EQ_BPF4_EN (0x1 << 4) | |
1388 | #define RT5645_EQ_BPF3_MASK (0x1 << 3) | |
1389 | #define RT5645_EQ_BPF3_SFT 3 | |
1390 | #define RT5645_EQ_BPF3_DIS (0x0 << 3) | |
1391 | #define RT5645_EQ_BPF3_EN (0x1 << 3) | |
1392 | #define RT5645_EQ_BPF2_MASK (0x1 << 2) | |
1393 | #define RT5645_EQ_BPF2_SFT 2 | |
1394 | #define RT5645_EQ_BPF2_DIS (0x0 << 2) | |
1395 | #define RT5645_EQ_BPF2_EN (0x1 << 2) | |
1396 | #define RT5645_EQ_BPF1_MASK (0x1 << 1) | |
1397 | #define RT5645_EQ_BPF1_SFT 1 | |
1398 | #define RT5645_EQ_BPF1_DIS (0x0 << 1) | |
1399 | #define RT5645_EQ_BPF1_EN (0x1 << 1) | |
1400 | #define RT5645_EQ_LPF_MASK (0x1) | |
1401 | #define RT5645_EQ_LPF_SFT 0 | |
1402 | #define RT5645_EQ_LPF_DIS (0x0) | |
1403 | #define RT5645_EQ_LPF_EN (0x1) | |
1404 | #define RT5645_EQ_CTRL_MASK (0x7f) | |
1405 | ||
1406 | /* Memory Test (0xb2) */ | |
1407 | #define RT5645_MT_MASK (0x1 << 15) | |
1408 | #define RT5645_MT_SFT 15 | |
1409 | #define RT5645_MT_DIS (0x0 << 15) | |
1410 | #define RT5645_MT_EN (0x1 << 15) | |
1411 | ||
1412 | /* DRC/AGC Control 1 (0xb4) */ | |
1413 | #define RT5645_DRC_AGC_P_MASK (0x1 << 15) | |
1414 | #define RT5645_DRC_AGC_P_SFT 15 | |
1415 | #define RT5645_DRC_AGC_P_DAC (0x0 << 15) | |
1416 | #define RT5645_DRC_AGC_P_ADC (0x1 << 15) | |
1417 | #define RT5645_DRC_AGC_MASK (0x1 << 14) | |
1418 | #define RT5645_DRC_AGC_SFT 14 | |
1419 | #define RT5645_DRC_AGC_DIS (0x0 << 14) | |
1420 | #define RT5645_DRC_AGC_EN (0x1 << 14) | |
1421 | #define RT5645_DRC_AGC_UPD (0x1 << 13) | |
1422 | #define RT5645_DRC_AGC_UPD_BIT 13 | |
1423 | #define RT5645_DRC_AGC_AR_MASK (0x1f << 8) | |
1424 | #define RT5645_DRC_AGC_AR_SFT 8 | |
1425 | #define RT5645_DRC_AGC_R_MASK (0x7 << 5) | |
1426 | #define RT5645_DRC_AGC_R_SFT 5 | |
1427 | #define RT5645_DRC_AGC_R_48K (0x1 << 5) | |
1428 | #define RT5645_DRC_AGC_R_96K (0x2 << 5) | |
1429 | #define RT5645_DRC_AGC_R_192K (0x3 << 5) | |
1430 | #define RT5645_DRC_AGC_R_441K (0x5 << 5) | |
1431 | #define RT5645_DRC_AGC_R_882K (0x6 << 5) | |
1432 | #define RT5645_DRC_AGC_R_1764K (0x7 << 5) | |
1433 | #define RT5645_DRC_AGC_RC_MASK (0x1f) | |
1434 | #define RT5645_DRC_AGC_RC_SFT 0 | |
1435 | ||
1436 | /* DRC/AGC Control 2 (0xb5) */ | |
1437 | #define RT5645_DRC_AGC_POB_MASK (0x3f << 8) | |
1438 | #define RT5645_DRC_AGC_POB_SFT 8 | |
1439 | #define RT5645_DRC_AGC_CP_MASK (0x1 << 7) | |
1440 | #define RT5645_DRC_AGC_CP_SFT 7 | |
1441 | #define RT5645_DRC_AGC_CP_DIS (0x0 << 7) | |
1442 | #define RT5645_DRC_AGC_CP_EN (0x1 << 7) | |
1443 | #define RT5645_DRC_AGC_CPR_MASK (0x3 << 5) | |
1444 | #define RT5645_DRC_AGC_CPR_SFT 5 | |
1445 | #define RT5645_DRC_AGC_CPR_1_1 (0x0 << 5) | |
1446 | #define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5) | |
1447 | #define RT5645_DRC_AGC_CPR_1_3 (0x2 << 5) | |
1448 | #define RT5645_DRC_AGC_CPR_1_4 (0x3 << 5) | |
1449 | #define RT5645_DRC_AGC_PRB_MASK (0x1f) | |
1450 | #define RT5645_DRC_AGC_PRB_SFT 0 | |
1451 | ||
1452 | /* DRC/AGC Control 3 (0xb6) */ | |
1453 | #define RT5645_DRC_AGC_NGB_MASK (0xf << 12) | |
1454 | #define RT5645_DRC_AGC_NGB_SFT 12 | |
1455 | #define RT5645_DRC_AGC_TAR_MASK (0x1f << 7) | |
1456 | #define RT5645_DRC_AGC_TAR_SFT 7 | |
1457 | #define RT5645_DRC_AGC_NG_MASK (0x1 << 6) | |
1458 | #define RT5645_DRC_AGC_NG_SFT 6 | |
1459 | #define RT5645_DRC_AGC_NG_DIS (0x0 << 6) | |
1460 | #define RT5645_DRC_AGC_NG_EN (0x1 << 6) | |
1461 | #define RT5645_DRC_AGC_NGH_MASK (0x1 << 5) | |
1462 | #define RT5645_DRC_AGC_NGH_SFT 5 | |
1463 | #define RT5645_DRC_AGC_NGH_DIS (0x0 << 5) | |
1464 | #define RT5645_DRC_AGC_NGH_EN (0x1 << 5) | |
1465 | #define RT5645_DRC_AGC_NGT_MASK (0x1f) | |
1466 | #define RT5645_DRC_AGC_NGT_SFT 0 | |
1467 | ||
1468 | /* ANC Control 1 (0xb8) */ | |
1469 | #define RT5645_ANC_M_MASK (0x1 << 15) | |
1470 | #define RT5645_ANC_M_SFT 15 | |
1471 | #define RT5645_ANC_M_NOR (0x0 << 15) | |
1472 | #define RT5645_ANC_M_REV (0x1 << 15) | |
1473 | #define RT5645_ANC_MASK (0x1 << 14) | |
1474 | #define RT5645_ANC_SFT 14 | |
1475 | #define RT5645_ANC_DIS (0x0 << 14) | |
1476 | #define RT5645_ANC_EN (0x1 << 14) | |
1477 | #define RT5645_ANC_MD_MASK (0x3 << 12) | |
1478 | #define RT5645_ANC_MD_SFT 12 | |
1479 | #define RT5645_ANC_MD_DIS (0x0 << 12) | |
1480 | #define RT5645_ANC_MD_67MS (0x1 << 12) | |
1481 | #define RT5645_ANC_MD_267MS (0x2 << 12) | |
1482 | #define RT5645_ANC_MD_1067MS (0x3 << 12) | |
1483 | #define RT5645_ANC_SN_MASK (0x1 << 11) | |
1484 | #define RT5645_ANC_SN_SFT 11 | |
1485 | #define RT5645_ANC_SN_DIS (0x0 << 11) | |
1486 | #define RT5645_ANC_SN_EN (0x1 << 11) | |
1487 | #define RT5645_ANC_CLK_MASK (0x1 << 10) | |
1488 | #define RT5645_ANC_CLK_SFT 10 | |
1489 | #define RT5645_ANC_CLK_ANC (0x0 << 10) | |
1490 | #define RT5645_ANC_CLK_REG (0x1 << 10) | |
1491 | #define RT5645_ANC_ZCD_MASK (0x3 << 8) | |
1492 | #define RT5645_ANC_ZCD_SFT 8 | |
1493 | #define RT5645_ANC_ZCD_DIS (0x0 << 8) | |
1494 | #define RT5645_ANC_ZCD_T1 (0x1 << 8) | |
1495 | #define RT5645_ANC_ZCD_T2 (0x2 << 8) | |
1496 | #define RT5645_ANC_ZCD_WT (0x3 << 8) | |
1497 | #define RT5645_ANC_CS_MASK (0x1 << 7) | |
1498 | #define RT5645_ANC_CS_SFT 7 | |
1499 | #define RT5645_ANC_CS_DIS (0x0 << 7) | |
1500 | #define RT5645_ANC_CS_EN (0x1 << 7) | |
1501 | #define RT5645_ANC_SW_MASK (0x1 << 6) | |
1502 | #define RT5645_ANC_SW_SFT 6 | |
1503 | #define RT5645_ANC_SW_NOR (0x0 << 6) | |
1504 | #define RT5645_ANC_SW_AUTO (0x1 << 6) | |
1505 | #define RT5645_ANC_CO_L_MASK (0x3f) | |
1506 | #define RT5645_ANC_CO_L_SFT 0 | |
1507 | ||
1508 | /* ANC Control 2 (0xb6) */ | |
1509 | #define RT5645_ANC_FG_R_MASK (0xf << 12) | |
1510 | #define RT5645_ANC_FG_R_SFT 12 | |
1511 | #define RT5645_ANC_FG_L_MASK (0xf << 8) | |
1512 | #define RT5645_ANC_FG_L_SFT 8 | |
1513 | #define RT5645_ANC_CG_R_MASK (0xf << 4) | |
1514 | #define RT5645_ANC_CG_R_SFT 4 | |
1515 | #define RT5645_ANC_CG_L_MASK (0xf) | |
1516 | #define RT5645_ANC_CG_L_SFT 0 | |
1517 | ||
1518 | /* ANC Control 3 (0xb6) */ | |
1519 | #define RT5645_ANC_CD_MASK (0x1 << 6) | |
1520 | #define RT5645_ANC_CD_SFT 6 | |
1521 | #define RT5645_ANC_CD_BOTH (0x0 << 6) | |
1522 | #define RT5645_ANC_CD_IND (0x1 << 6) | |
1523 | #define RT5645_ANC_CO_R_MASK (0x3f) | |
1524 | #define RT5645_ANC_CO_R_SFT 0 | |
1525 | ||
1526 | /* Jack Detect Control (0xbb) */ | |
1527 | #define RT5645_JD_MASK (0x7 << 13) | |
1528 | #define RT5645_JD_SFT 13 | |
1529 | #define RT5645_JD_DIS (0x0 << 13) | |
1530 | #define RT5645_JD_GPIO1 (0x1 << 13) | |
1531 | #define RT5645_JD_JD1_IN4P (0x2 << 13) | |
1532 | #define RT5645_JD_JD2_IN4N (0x3 << 13) | |
1533 | #define RT5645_JD_GPIO2 (0x4 << 13) | |
1534 | #define RT5645_JD_GPIO3 (0x5 << 13) | |
1535 | #define RT5645_JD_GPIO4 (0x6 << 13) | |
1536 | #define RT5645_JD_HP_MASK (0x1 << 11) | |
1537 | #define RT5645_JD_HP_SFT 11 | |
1538 | #define RT5645_JD_HP_DIS (0x0 << 11) | |
1539 | #define RT5645_JD_HP_EN (0x1 << 11) | |
1540 | #define RT5645_JD_HP_TRG_MASK (0x1 << 10) | |
1541 | #define RT5645_JD_HP_TRG_SFT 10 | |
1542 | #define RT5645_JD_HP_TRG_LO (0x0 << 10) | |
1543 | #define RT5645_JD_HP_TRG_HI (0x1 << 10) | |
1544 | #define RT5645_JD_SPL_MASK (0x1 << 9) | |
1545 | #define RT5645_JD_SPL_SFT 9 | |
1546 | #define RT5645_JD_SPL_DIS (0x0 << 9) | |
1547 | #define RT5645_JD_SPL_EN (0x1 << 9) | |
1548 | #define RT5645_JD_SPL_TRG_MASK (0x1 << 8) | |
1549 | #define RT5645_JD_SPL_TRG_SFT 8 | |
1550 | #define RT5645_JD_SPL_TRG_LO (0x0 << 8) | |
1551 | #define RT5645_JD_SPL_TRG_HI (0x1 << 8) | |
1552 | #define RT5645_JD_SPR_MASK (0x1 << 7) | |
1553 | #define RT5645_JD_SPR_SFT 7 | |
1554 | #define RT5645_JD_SPR_DIS (0x0 << 7) | |
1555 | #define RT5645_JD_SPR_EN (0x1 << 7) | |
1556 | #define RT5645_JD_SPR_TRG_MASK (0x1 << 6) | |
1557 | #define RT5645_JD_SPR_TRG_SFT 6 | |
1558 | #define RT5645_JD_SPR_TRG_LO (0x0 << 6) | |
1559 | #define RT5645_JD_SPR_TRG_HI (0x1 << 6) | |
1560 | #define RT5645_JD_MO_MASK (0x1 << 5) | |
1561 | #define RT5645_JD_MO_SFT 5 | |
1562 | #define RT5645_JD_MO_DIS (0x0 << 5) | |
1563 | #define RT5645_JD_MO_EN (0x1 << 5) | |
1564 | #define RT5645_JD_MO_TRG_MASK (0x1 << 4) | |
1565 | #define RT5645_JD_MO_TRG_SFT 4 | |
1566 | #define RT5645_JD_MO_TRG_LO (0x0 << 4) | |
1567 | #define RT5645_JD_MO_TRG_HI (0x1 << 4) | |
1568 | #define RT5645_JD_LO_MASK (0x1 << 3) | |
1569 | #define RT5645_JD_LO_SFT 3 | |
1570 | #define RT5645_JD_LO_DIS (0x0 << 3) | |
1571 | #define RT5645_JD_LO_EN (0x1 << 3) | |
1572 | #define RT5645_JD_LO_TRG_MASK (0x1 << 2) | |
1573 | #define RT5645_JD_LO_TRG_SFT 2 | |
1574 | #define RT5645_JD_LO_TRG_LO (0x0 << 2) | |
1575 | #define RT5645_JD_LO_TRG_HI (0x1 << 2) | |
1576 | #define RT5645_JD1_IN4P_MASK (0x1 << 1) | |
1577 | #define RT5645_JD1_IN4P_SFT 1 | |
1578 | #define RT5645_JD1_IN4P_DIS (0x0 << 1) | |
1579 | #define RT5645_JD1_IN4P_EN (0x1 << 1) | |
1580 | #define RT5645_JD2_IN4N_MASK (0x1) | |
1581 | #define RT5645_JD2_IN4N_SFT 0 | |
1582 | #define RT5645_JD2_IN4N_DIS (0x0) | |
1583 | #define RT5645_JD2_IN4N_EN (0x1) | |
1584 | ||
1585 | /* Jack detect for ANC (0xbc) */ | |
1586 | #define RT5645_ANC_DET_MASK (0x3 << 4) | |
1587 | #define RT5645_ANC_DET_SFT 4 | |
1588 | #define RT5645_ANC_DET_DIS (0x0 << 4) | |
1589 | #define RT5645_ANC_DET_MB1 (0x1 << 4) | |
1590 | #define RT5645_ANC_DET_MB2 (0x2 << 4) | |
1591 | #define RT5645_ANC_DET_JD (0x3 << 4) | |
1592 | #define RT5645_AD_TRG_MASK (0x1 << 3) | |
1593 | #define RT5645_AD_TRG_SFT 3 | |
1594 | #define RT5645_AD_TRG_LO (0x0 << 3) | |
1595 | #define RT5645_AD_TRG_HI (0x1 << 3) | |
1596 | #define RT5645_ANCM_DET_MASK (0x3 << 4) | |
1597 | #define RT5645_ANCM_DET_SFT 4 | |
1598 | #define RT5645_ANCM_DET_DIS (0x0 << 4) | |
1599 | #define RT5645_ANCM_DET_MB1 (0x1 << 4) | |
1600 | #define RT5645_ANCM_DET_MB2 (0x2 << 4) | |
1601 | #define RT5645_ANCM_DET_JD (0x3 << 4) | |
1602 | #define RT5645_AMD_TRG_MASK (0x1 << 3) | |
1603 | #define RT5645_AMD_TRG_SFT 3 | |
1604 | #define RT5645_AMD_TRG_LO (0x0 << 3) | |
1605 | #define RT5645_AMD_TRG_HI (0x1 << 3) | |
1606 | ||
1607 | /* IRQ Control 1 (0xbd) */ | |
1608 | #define RT5645_IRQ_JD_MASK (0x1 << 15) | |
1609 | #define RT5645_IRQ_JD_SFT 15 | |
1610 | #define RT5645_IRQ_JD_BP (0x0 << 15) | |
1611 | #define RT5645_IRQ_JD_NOR (0x1 << 15) | |
1612 | #define RT5645_IRQ_OT_MASK (0x1 << 14) | |
1613 | #define RT5645_IRQ_OT_SFT 14 | |
1614 | #define RT5645_IRQ_OT_BP (0x0 << 14) | |
1615 | #define RT5645_IRQ_OT_NOR (0x1 << 14) | |
1616 | #define RT5645_JD_STKY_MASK (0x1 << 13) | |
1617 | #define RT5645_JD_STKY_SFT 13 | |
1618 | #define RT5645_JD_STKY_DIS (0x0 << 13) | |
1619 | #define RT5645_JD_STKY_EN (0x1 << 13) | |
1620 | #define RT5645_OT_STKY_MASK (0x1 << 12) | |
1621 | #define RT5645_OT_STKY_SFT 12 | |
1622 | #define RT5645_OT_STKY_DIS (0x0 << 12) | |
1623 | #define RT5645_OT_STKY_EN (0x1 << 12) | |
1624 | #define RT5645_JD_P_MASK (0x1 << 11) | |
1625 | #define RT5645_JD_P_SFT 11 | |
1626 | #define RT5645_JD_P_NOR (0x0 << 11) | |
1627 | #define RT5645_JD_P_INV (0x1 << 11) | |
1628 | #define RT5645_OT_P_MASK (0x1 << 10) | |
1629 | #define RT5645_OT_P_SFT 10 | |
1630 | #define RT5645_OT_P_NOR (0x0 << 10) | |
1631 | #define RT5645_OT_P_INV (0x1 << 10) | |
2d4e2d02 | 1632 | #define RT5645_IRQ_JD_1_1_EN (0x1 << 9) |
917536ae JL |
1633 | #define RT5645_JD_1_1_MASK (0x1 << 7) |
1634 | #define RT5645_JD_1_1_SFT 7 | |
1635 | #define RT5645_JD_1_1_NOR (0x0 << 7) | |
1636 | #define RT5645_JD_1_1_INV (0x1 << 7) | |
1319b2f6 OC |
1637 | |
1638 | /* IRQ Control 2 (0xbe) */ | |
1639 | #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15) | |
1640 | #define RT5645_IRQ_MB1_OC_SFT 15 | |
1641 | #define RT5645_IRQ_MB1_OC_BP (0x0 << 15) | |
1642 | #define RT5645_IRQ_MB1_OC_NOR (0x1 << 15) | |
1643 | #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14) | |
1644 | #define RT5645_IRQ_MB2_OC_SFT 14 | |
1645 | #define RT5645_IRQ_MB2_OC_BP (0x0 << 14) | |
1646 | #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14) | |
1647 | #define RT5645_MB1_OC_STKY_MASK (0x1 << 13) | |
1648 | #define RT5645_MB1_OC_STKY_SFT 13 | |
1649 | #define RT5645_MB1_OC_STKY_DIS (0x0 << 13) | |
1650 | #define RT5645_MB1_OC_STKY_EN (0x1 << 13) | |
1651 | #define RT5645_MB2_OC_STKY_MASK (0x1 << 12) | |
1652 | #define RT5645_MB2_OC_STKY_SFT 12 | |
1653 | #define RT5645_MB2_OC_STKY_DIS (0x0 << 12) | |
1654 | #define RT5645_MB2_OC_STKY_EN (0x1 << 12) | |
1655 | #define RT5645_MB1_OC_P_MASK (0x1 << 7) | |
1656 | #define RT5645_MB1_OC_P_SFT 7 | |
1657 | #define RT5645_MB1_OC_P_NOR (0x0 << 7) | |
1658 | #define RT5645_MB1_OC_P_INV (0x1 << 7) | |
1659 | #define RT5645_MB2_OC_P_MASK (0x1 << 6) | |
1660 | #define RT5645_MB2_OC_P_SFT 6 | |
1661 | #define RT5645_MB2_OC_P_NOR (0x0 << 6) | |
1662 | #define RT5645_MB2_OC_P_INV (0x1 << 6) | |
1663 | #define RT5645_MB1_OC_CLR (0x1 << 3) | |
1664 | #define RT5645_MB1_OC_CLR_SFT 3 | |
1665 | #define RT5645_MB2_OC_CLR (0x1 << 2) | |
1666 | #define RT5645_MB2_OC_CLR_SFT 2 | |
1667 | ||
1668 | /* GPIO Control 1 (0xc0) */ | |
1669 | #define RT5645_GP1_PIN_MASK (0x1 << 15) | |
1670 | #define RT5645_GP1_PIN_SFT 15 | |
1671 | #define RT5645_GP1_PIN_GPIO1 (0x0 << 15) | |
1672 | #define RT5645_GP1_PIN_IRQ (0x1 << 15) | |
1673 | #define RT5645_GP2_PIN_MASK (0x1 << 14) | |
1674 | #define RT5645_GP2_PIN_SFT 14 | |
1675 | #define RT5645_GP2_PIN_GPIO2 (0x0 << 14) | |
1676 | #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14) | |
1677 | #define RT5645_GP3_PIN_MASK (0x3 << 12) | |
1678 | #define RT5645_GP3_PIN_SFT 12 | |
1679 | #define RT5645_GP3_PIN_GPIO3 (0x0 << 12) | |
1680 | #define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12) | |
1681 | #define RT5645_GP3_PIN_IRQ (0x2 << 12) | |
1682 | #define RT5645_GP4_PIN_MASK (0x1 << 11) | |
1683 | #define RT5645_GP4_PIN_SFT 11 | |
1684 | #define RT5645_GP4_PIN_GPIO4 (0x0 << 11) | |
1685 | #define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11) | |
1686 | #define RT5645_DP_SIG_MASK (0x1 << 10) | |
1687 | #define RT5645_DP_SIG_SFT 10 | |
1688 | #define RT5645_DP_SIG_TEST (0x0 << 10) | |
1689 | #define RT5645_DP_SIG_AP (0x1 << 10) | |
1690 | #define RT5645_GPIO_M_MASK (0x1 << 9) | |
1691 | #define RT5645_GPIO_M_SFT 9 | |
1692 | #define RT5645_GPIO_M_FLT (0x0 << 9) | |
1693 | #define RT5645_GPIO_M_PH (0x1 << 9) | |
1694 | #define RT5645_I2S2_SEL (0x1 << 8) | |
1695 | #define RT5645_I2S2_SEL_SFT 8 | |
1696 | #define RT5645_GP5_PIN_MASK (0x1 << 7) | |
1697 | #define RT5645_GP5_PIN_SFT 7 | |
1698 | #define RT5645_GP5_PIN_GPIO5 (0x0 << 7) | |
1699 | #define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7) | |
1700 | #define RT5645_GP6_PIN_MASK (0x1 << 6) | |
1701 | #define RT5645_GP6_PIN_SFT 6 | |
1702 | #define RT5645_GP6_PIN_GPIO6 (0x0 << 6) | |
1703 | #define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6) | |
a094935e BL |
1704 | #define RT5645_I2S2_DAC_PIN_MASK (0x1 << 4) |
1705 | #define RT5645_I2S2_DAC_PIN_SFT 4 | |
1706 | #define RT5645_I2S2_DAC_PIN_I2S (0x0 << 4) | |
1707 | #define RT5645_I2S2_DAC_PIN_GPIO (0x1 << 4) | |
1319b2f6 OC |
1708 | #define RT5645_GP8_PIN_MASK (0x1 << 3) |
1709 | #define RT5645_GP8_PIN_SFT 3 | |
1710 | #define RT5645_GP8_PIN_GPIO8 (0x0 << 3) | |
1711 | #define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3) | |
1712 | #define RT5645_GP12_PIN_MASK (0x1 << 2) | |
1713 | #define RT5645_GP12_PIN_SFT 2 | |
1714 | #define RT5645_GP12_PIN_GPIO12 (0x0 << 2) | |
1715 | #define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2) | |
1716 | #define RT5645_GP11_PIN_MASK (0x1 << 1) | |
1717 | #define RT5645_GP11_PIN_SFT 1 | |
1718 | #define RT5645_GP11_PIN_GPIO11 (0x0 << 1) | |
1719 | #define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1) | |
1720 | #define RT5645_GP10_PIN_MASK (0x1) | |
1721 | #define RT5645_GP10_PIN_SFT 0 | |
1722 | #define RT5645_GP10_PIN_GPIO10 (0x0) | |
1723 | #define RT5645_GP10_PIN_DMIC2_SDA (0x1) | |
1724 | ||
1725 | /* GPIO Control 3 (0xc2) */ | |
1726 | #define RT5645_GP4_PF_MASK (0x1 << 11) | |
1727 | #define RT5645_GP4_PF_SFT 11 | |
1728 | #define RT5645_GP4_PF_IN (0x0 << 11) | |
1729 | #define RT5645_GP4_PF_OUT (0x1 << 11) | |
1730 | #define RT5645_GP4_OUT_MASK (0x1 << 10) | |
1731 | #define RT5645_GP4_OUT_SFT 10 | |
1732 | #define RT5645_GP4_OUT_LO (0x0 << 10) | |
1733 | #define RT5645_GP4_OUT_HI (0x1 << 10) | |
1734 | #define RT5645_GP4_P_MASK (0x1 << 9) | |
1735 | #define RT5645_GP4_P_SFT 9 | |
1736 | #define RT5645_GP4_P_NOR (0x0 << 9) | |
1737 | #define RT5645_GP4_P_INV (0x1 << 9) | |
1738 | #define RT5645_GP3_PF_MASK (0x1 << 8) | |
1739 | #define RT5645_GP3_PF_SFT 8 | |
1740 | #define RT5645_GP3_PF_IN (0x0 << 8) | |
1741 | #define RT5645_GP3_PF_OUT (0x1 << 8) | |
1742 | #define RT5645_GP3_OUT_MASK (0x1 << 7) | |
1743 | #define RT5645_GP3_OUT_SFT 7 | |
1744 | #define RT5645_GP3_OUT_LO (0x0 << 7) | |
1745 | #define RT5645_GP3_OUT_HI (0x1 << 7) | |
1746 | #define RT5645_GP3_P_MASK (0x1 << 6) | |
1747 | #define RT5645_GP3_P_SFT 6 | |
1748 | #define RT5645_GP3_P_NOR (0x0 << 6) | |
1749 | #define RT5645_GP3_P_INV (0x1 << 6) | |
1750 | #define RT5645_GP2_PF_MASK (0x1 << 5) | |
1751 | #define RT5645_GP2_PF_SFT 5 | |
1752 | #define RT5645_GP2_PF_IN (0x0 << 5) | |
1753 | #define RT5645_GP2_PF_OUT (0x1 << 5) | |
1754 | #define RT5645_GP2_OUT_MASK (0x1 << 4) | |
1755 | #define RT5645_GP2_OUT_SFT 4 | |
1756 | #define RT5645_GP2_OUT_LO (0x0 << 4) | |
1757 | #define RT5645_GP2_OUT_HI (0x1 << 4) | |
1758 | #define RT5645_GP2_P_MASK (0x1 << 3) | |
1759 | #define RT5645_GP2_P_SFT 3 | |
1760 | #define RT5645_GP2_P_NOR (0x0 << 3) | |
1761 | #define RT5645_GP2_P_INV (0x1 << 3) | |
1762 | #define RT5645_GP1_PF_MASK (0x1 << 2) | |
1763 | #define RT5645_GP1_PF_SFT 2 | |
1764 | #define RT5645_GP1_PF_IN (0x0 << 2) | |
1765 | #define RT5645_GP1_PF_OUT (0x1 << 2) | |
1766 | #define RT5645_GP1_OUT_MASK (0x1 << 1) | |
1767 | #define RT5645_GP1_OUT_SFT 1 | |
1768 | #define RT5645_GP1_OUT_LO (0x0 << 1) | |
1769 | #define RT5645_GP1_OUT_HI (0x1 << 1) | |
1770 | #define RT5645_GP1_P_MASK (0x1) | |
1771 | #define RT5645_GP1_P_SFT 0 | |
1772 | #define RT5645_GP1_P_NOR (0x0) | |
1773 | #define RT5645_GP1_P_INV (0x1) | |
1774 | ||
1775 | /* Programmable Register Array Control 1 (0xc8) */ | |
1776 | #define RT5645_REG_SEQ_MASK (0xf << 12) | |
1777 | #define RT5645_REG_SEQ_SFT 12 | |
1778 | #define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/ | |
1779 | #define RT5645_SEQ1_ST_SFT 11 | |
1780 | #define RT5645_SEQ1_ST_RUN (0x0 << 11) | |
1781 | #define RT5645_SEQ1_ST_FIN (0x1 << 11) | |
1782 | #define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/ | |
1783 | #define RT5645_SEQ2_ST_SFT 10 | |
1784 | #define RT5645_SEQ2_ST_RUN (0x0 << 10) | |
1785 | #define RT5645_SEQ2_ST_FIN (0x1 << 10) | |
1786 | #define RT5645_REG_LV_MASK (0x1 << 9) | |
1787 | #define RT5645_REG_LV_SFT 9 | |
1788 | #define RT5645_REG_LV_MX (0x0 << 9) | |
1789 | #define RT5645_REG_LV_PR (0x1 << 9) | |
1790 | #define RT5645_SEQ_2_PT_MASK (0x1 << 8) | |
1791 | #define RT5645_SEQ_2_PT_BIT 8 | |
1792 | #define RT5645_REG_IDX_MASK (0xff) | |
1793 | #define RT5645_REG_IDX_SFT 0 | |
1794 | ||
1795 | /* Programmable Register Array Control 2 (0xc9) */ | |
1796 | #define RT5645_REG_DAT_MASK (0xffff) | |
1797 | #define RT5645_REG_DAT_SFT 0 | |
1798 | ||
1799 | /* Programmable Register Array Control 3 (0xca) */ | |
1800 | #define RT5645_SEQ_DLY_MASK (0xff << 8) | |
1801 | #define RT5645_SEQ_DLY_SFT 8 | |
1802 | #define RT5645_PROG_MASK (0x1 << 7) | |
1803 | #define RT5645_PROG_SFT 7 | |
1804 | #define RT5645_PROG_DIS (0x0 << 7) | |
1805 | #define RT5645_PROG_EN (0x1 << 7) | |
1806 | #define RT5645_SEQ1_PT_RUN (0x1 << 6) | |
1807 | #define RT5645_SEQ1_PT_RUN_BIT 6 | |
1808 | #define RT5645_SEQ2_PT_RUN (0x1 << 5) | |
1809 | #define RT5645_SEQ2_PT_RUN_BIT 5 | |
1810 | ||
1811 | /* Programmable Register Array Control 4 (0xcb) */ | |
1812 | #define RT5645_SEQ1_START_MASK (0xf << 8) | |
1813 | #define RT5645_SEQ1_START_SFT 8 | |
1814 | #define RT5645_SEQ1_END_MASK (0xf) | |
1815 | #define RT5645_SEQ1_END_SFT 0 | |
1816 | ||
1817 | /* Programmable Register Array Control 5 (0xcc) */ | |
1818 | #define RT5645_SEQ2_START_MASK (0xf << 8) | |
1819 | #define RT5645_SEQ2_START_SFT 8 | |
1820 | #define RT5645_SEQ2_END_MASK (0xf) | |
1821 | #define RT5645_SEQ2_END_SFT 0 | |
1822 | ||
1823 | /* Scramble Function (0xcd) */ | |
1824 | #define RT5645_SCB_KEY_MASK (0xff) | |
1825 | #define RT5645_SCB_KEY_SFT 0 | |
1826 | ||
1827 | /* Scramble Control (0xce) */ | |
1828 | #define RT5645_SCB_SWAP_MASK (0x1 << 15) | |
1829 | #define RT5645_SCB_SWAP_SFT 15 | |
1830 | #define RT5645_SCB_SWAP_DIS (0x0 << 15) | |
1831 | #define RT5645_SCB_SWAP_EN (0x1 << 15) | |
1832 | #define RT5645_SCB_MASK (0x1 << 14) | |
1833 | #define RT5645_SCB_SFT 14 | |
1834 | #define RT5645_SCB_DIS (0x0 << 14) | |
1835 | #define RT5645_SCB_EN (0x1 << 14) | |
1836 | ||
1837 | /* Baseback Control (0xcf) */ | |
1838 | #define RT5645_BB_MASK (0x1 << 15) | |
1839 | #define RT5645_BB_SFT 15 | |
1840 | #define RT5645_BB_DIS (0x0 << 15) | |
1841 | #define RT5645_BB_EN (0x1 << 15) | |
1842 | #define RT5645_BB_CT_MASK (0x7 << 12) | |
1843 | #define RT5645_BB_CT_SFT 12 | |
1844 | #define RT5645_BB_CT_A (0x0 << 12) | |
1845 | #define RT5645_BB_CT_B (0x1 << 12) | |
1846 | #define RT5645_BB_CT_C (0x2 << 12) | |
1847 | #define RT5645_BB_CT_D (0x3 << 12) | |
1848 | #define RT5645_M_BB_L_MASK (0x1 << 9) | |
1849 | #define RT5645_M_BB_L_SFT 9 | |
1850 | #define RT5645_M_BB_R_MASK (0x1 << 8) | |
1851 | #define RT5645_M_BB_R_SFT 8 | |
1852 | #define RT5645_M_BB_HPF_L_MASK (0x1 << 7) | |
1853 | #define RT5645_M_BB_HPF_L_SFT 7 | |
1854 | #define RT5645_M_BB_HPF_R_MASK (0x1 << 6) | |
1855 | #define RT5645_M_BB_HPF_R_SFT 6 | |
1856 | #define RT5645_G_BB_BST_MASK (0x3f) | |
1857 | #define RT5645_G_BB_BST_SFT 0 | |
850577db | 1858 | #define RT5645_G_BB_BST_25DB 0x14 |
1319b2f6 OC |
1859 | |
1860 | /* MP3 Plus Control 1 (0xd0) */ | |
1861 | #define RT5645_M_MP3_L_MASK (0x1 << 15) | |
1862 | #define RT5645_M_MP3_L_SFT 15 | |
1863 | #define RT5645_M_MP3_R_MASK (0x1 << 14) | |
1864 | #define RT5645_M_MP3_R_SFT 14 | |
1865 | #define RT5645_M_MP3_MASK (0x1 << 13) | |
1866 | #define RT5645_M_MP3_SFT 13 | |
1867 | #define RT5645_M_MP3_DIS (0x0 << 13) | |
1868 | #define RT5645_M_MP3_EN (0x1 << 13) | |
1869 | #define RT5645_EG_MP3_MASK (0x1f << 8) | |
1870 | #define RT5645_EG_MP3_SFT 8 | |
1871 | #define RT5645_MP3_HLP_MASK (0x1 << 7) | |
1872 | #define RT5645_MP3_HLP_SFT 7 | |
1873 | #define RT5645_MP3_HLP_DIS (0x0 << 7) | |
1874 | #define RT5645_MP3_HLP_EN (0x1 << 7) | |
1875 | #define RT5645_M_MP3_ORG_L_MASK (0x1 << 6) | |
1876 | #define RT5645_M_MP3_ORG_L_SFT 6 | |
1877 | #define RT5645_M_MP3_ORG_R_MASK (0x1 << 5) | |
1878 | #define RT5645_M_MP3_ORG_R_SFT 5 | |
1879 | ||
1880 | /* MP3 Plus Control 2 (0xd1) */ | |
1881 | #define RT5645_MP3_WT_MASK (0x1 << 13) | |
1882 | #define RT5645_MP3_WT_SFT 13 | |
1883 | #define RT5645_MP3_WT_1_4 (0x0 << 13) | |
1884 | #define RT5645_MP3_WT_1_2 (0x1 << 13) | |
1885 | #define RT5645_OG_MP3_MASK (0x1f << 8) | |
1886 | #define RT5645_OG_MP3_SFT 8 | |
1887 | #define RT5645_HG_MP3_MASK (0x3f) | |
1888 | #define RT5645_HG_MP3_SFT 0 | |
1889 | ||
1890 | /* 3D HP Control 1 (0xd2) */ | |
1891 | #define RT5645_3D_CF_MASK (0x1 << 15) | |
1892 | #define RT5645_3D_CF_SFT 15 | |
1893 | #define RT5645_3D_CF_DIS (0x0 << 15) | |
1894 | #define RT5645_3D_CF_EN (0x1 << 15) | |
1895 | #define RT5645_3D_HP_MASK (0x1 << 14) | |
1896 | #define RT5645_3D_HP_SFT 14 | |
1897 | #define RT5645_3D_HP_DIS (0x0 << 14) | |
1898 | #define RT5645_3D_HP_EN (0x1 << 14) | |
1899 | #define RT5645_3D_BT_MASK (0x1 << 13) | |
1900 | #define RT5645_3D_BT_SFT 13 | |
1901 | #define RT5645_3D_BT_DIS (0x0 << 13) | |
1902 | #define RT5645_3D_BT_EN (0x1 << 13) | |
1903 | #define RT5645_3D_1F_MIX_MASK (0x3 << 11) | |
1904 | #define RT5645_3D_1F_MIX_SFT 11 | |
1905 | #define RT5645_3D_HP_M_MASK (0x1 << 10) | |
1906 | #define RT5645_3D_HP_M_SFT 10 | |
1907 | #define RT5645_3D_HP_M_SUR (0x0 << 10) | |
1908 | #define RT5645_3D_HP_M_FRO (0x1 << 10) | |
1909 | #define RT5645_M_3D_HRTF_MASK (0x1 << 9) | |
1910 | #define RT5645_M_3D_HRTF_SFT 9 | |
1911 | #define RT5645_M_3D_D2H_MASK (0x1 << 8) | |
1912 | #define RT5645_M_3D_D2H_SFT 8 | |
1913 | #define RT5645_M_3D_D2R_MASK (0x1 << 7) | |
1914 | #define RT5645_M_3D_D2R_SFT 7 | |
1915 | #define RT5645_M_3D_REVB_MASK (0x1 << 6) | |
1916 | #define RT5645_M_3D_REVB_SFT 6 | |
1917 | ||
1918 | /* Adjustable high pass filter control 1 (0xd3) */ | |
1919 | #define RT5645_2ND_HPF_MASK (0x1 << 15) | |
1920 | #define RT5645_2ND_HPF_SFT 15 | |
1921 | #define RT5645_2ND_HPF_DIS (0x0 << 15) | |
1922 | #define RT5645_2ND_HPF_EN (0x1 << 15) | |
1923 | #define RT5645_HPF_CF_L_MASK (0x7 << 12) | |
1924 | #define RT5645_HPF_CF_L_SFT 12 | |
1925 | #define RT5645_1ST_HPF_MASK (0x1 << 11) | |
1926 | #define RT5645_1ST_HPF_SFT 11 | |
1927 | #define RT5645_1ST_HPF_DIS (0x0 << 11) | |
1928 | #define RT5645_1ST_HPF_EN (0x1 << 11) | |
1929 | #define RT5645_HPF_CF_R_MASK (0x7 << 8) | |
1930 | #define RT5645_HPF_CF_R_SFT 8 | |
1931 | #define RT5645_ZD_T_MASK (0x3 << 6) | |
1932 | #define RT5645_ZD_T_SFT 6 | |
1933 | #define RT5645_ZD_F_MASK (0x3 << 4) | |
1934 | #define RT5645_ZD_F_SFT 4 | |
1935 | #define RT5645_ZD_F_IM (0x0 << 4) | |
1936 | #define RT5645_ZD_F_ZC_IM (0x1 << 4) | |
1937 | #define RT5645_ZD_F_ZC_IOD (0x2 << 4) | |
1938 | #define RT5645_ZD_F_UN (0x3 << 4) | |
1939 | ||
1940 | /* HP calibration control and Amp detection (0xd6) */ | |
1941 | #define RT5645_SI_DAC_MASK (0x1 << 11) | |
1942 | #define RT5645_SI_DAC_SFT 11 | |
1943 | #define RT5645_SI_DAC_AUTO (0x0 << 11) | |
1944 | #define RT5645_SI_DAC_TEST (0x1 << 11) | |
1945 | #define RT5645_DC_CAL_M_MASK (0x1 << 10) | |
1946 | #define RT5645_DC_CAL_M_SFT 10 | |
1947 | #define RT5645_DC_CAL_M_CAL (0x0 << 10) | |
1948 | #define RT5645_DC_CAL_M_NOR (0x1 << 10) | |
1949 | #define RT5645_DC_CAL_MASK (0x1 << 9) | |
1950 | #define RT5645_DC_CAL_SFT 9 | |
1951 | #define RT5645_DC_CAL_DIS (0x0 << 9) | |
1952 | #define RT5645_DC_CAL_EN (0x1 << 9) | |
1953 | #define RT5645_HPD_RCV_MASK (0x7 << 6) | |
1954 | #define RT5645_HPD_RCV_SFT 6 | |
1955 | #define RT5645_HPD_PS_MASK (0x1 << 5) | |
1956 | #define RT5645_HPD_PS_SFT 5 | |
1957 | #define RT5645_HPD_PS_DIS (0x0 << 5) | |
1958 | #define RT5645_HPD_PS_EN (0x1 << 5) | |
1959 | #define RT5645_CAL_M_MASK (0x1 << 4) | |
1960 | #define RT5645_CAL_M_SFT 4 | |
1961 | #define RT5645_CAL_M_DEP (0x0 << 4) | |
1962 | #define RT5645_CAL_M_CAL (0x1 << 4) | |
1963 | #define RT5645_CAL_MASK (0x1 << 3) | |
1964 | #define RT5645_CAL_SFT 3 | |
1965 | #define RT5645_CAL_DIS (0x0 << 3) | |
1966 | #define RT5645_CAL_EN (0x1 << 3) | |
1967 | #define RT5645_CAL_TEST_MASK (0x1 << 2) | |
1968 | #define RT5645_CAL_TEST_SFT 2 | |
1969 | #define RT5645_CAL_TEST_DIS (0x0 << 2) | |
1970 | #define RT5645_CAL_TEST_EN (0x1 << 2) | |
1971 | #define RT5645_CAL_P_MASK (0x3) | |
1972 | #define RT5645_CAL_P_SFT 0 | |
1973 | #define RT5645_CAL_P_NONE (0x0) | |
1974 | #define RT5645_CAL_P_CAL (0x1) | |
1975 | #define RT5645_CAL_P_DAC_CAL (0x2) | |
1976 | ||
1977 | /* Soft volume and zero cross control 1 (0xd9) */ | |
1978 | #define RT5645_SV_MASK (0x1 << 15) | |
1979 | #define RT5645_SV_SFT 15 | |
1980 | #define RT5645_SV_DIS (0x0 << 15) | |
1981 | #define RT5645_SV_EN (0x1 << 15) | |
1982 | #define RT5645_SPO_SV_MASK (0x1 << 14) | |
1983 | #define RT5645_SPO_SV_SFT 14 | |
1984 | #define RT5645_SPO_SV_DIS (0x0 << 14) | |
1985 | #define RT5645_SPO_SV_EN (0x1 << 14) | |
1986 | #define RT5645_OUT_SV_MASK (0x1 << 13) | |
1987 | #define RT5645_OUT_SV_SFT 13 | |
1988 | #define RT5645_OUT_SV_DIS (0x0 << 13) | |
1989 | #define RT5645_OUT_SV_EN (0x1 << 13) | |
1990 | #define RT5645_HP_SV_MASK (0x1 << 12) | |
1991 | #define RT5645_HP_SV_SFT 12 | |
1992 | #define RT5645_HP_SV_DIS (0x0 << 12) | |
1993 | #define RT5645_HP_SV_EN (0x1 << 12) | |
1994 | #define RT5645_ZCD_DIG_MASK (0x1 << 11) | |
1995 | #define RT5645_ZCD_DIG_SFT 11 | |
1996 | #define RT5645_ZCD_DIG_DIS (0x0 << 11) | |
1997 | #define RT5645_ZCD_DIG_EN (0x1 << 11) | |
1998 | #define RT5645_ZCD_MASK (0x1 << 10) | |
1999 | #define RT5645_ZCD_SFT 10 | |
2000 | #define RT5645_ZCD_PD (0x0 << 10) | |
2001 | #define RT5645_ZCD_PU (0x1 << 10) | |
2002 | #define RT5645_M_ZCD_MASK (0x3f << 4) | |
2003 | #define RT5645_M_ZCD_SFT 4 | |
2004 | #define RT5645_M_ZCD_RM_L (0x1 << 9) | |
2005 | #define RT5645_M_ZCD_RM_R (0x1 << 8) | |
2006 | #define RT5645_M_ZCD_SM_L (0x1 << 7) | |
2007 | #define RT5645_M_ZCD_SM_R (0x1 << 6) | |
2008 | #define RT5645_M_ZCD_OM_L (0x1 << 5) | |
2009 | #define RT5645_M_ZCD_OM_R (0x1 << 4) | |
2010 | #define RT5645_SV_DLY_MASK (0xf) | |
2011 | #define RT5645_SV_DLY_SFT 0 | |
2012 | ||
2013 | /* Soft volume and zero cross control 2 (0xda) */ | |
2014 | #define RT5645_ZCD_HP_MASK (0x1 << 15) | |
2015 | #define RT5645_ZCD_HP_SFT 15 | |
2016 | #define RT5645_ZCD_HP_DIS (0x0 << 15) | |
2017 | #define RT5645_ZCD_HP_EN (0x1 << 15) | |
2018 | ||
2019 | ||
2020 | /* Codec Private Register definition */ | |
2021 | /* 3D Speaker Control (0x63) */ | |
2022 | #define RT5645_3D_SPK_MASK (0x1 << 15) | |
2023 | #define RT5645_3D_SPK_SFT 15 | |
2024 | #define RT5645_3D_SPK_DIS (0x0 << 15) | |
2025 | #define RT5645_3D_SPK_EN (0x1 << 15) | |
2026 | #define RT5645_3D_SPK_M_MASK (0x3 << 13) | |
2027 | #define RT5645_3D_SPK_M_SFT 13 | |
2028 | #define RT5645_3D_SPK_CG_MASK (0x1f << 8) | |
2029 | #define RT5645_3D_SPK_CG_SFT 8 | |
2030 | #define RT5645_3D_SPK_SG_MASK (0x1f) | |
2031 | #define RT5645_3D_SPK_SG_SFT 0 | |
2032 | ||
2033 | /* Wind Noise Detection Control 1 (0x6c) */ | |
2034 | #define RT5645_WND_MASK (0x1 << 15) | |
2035 | #define RT5645_WND_SFT 15 | |
2036 | #define RT5645_WND_DIS (0x0 << 15) | |
2037 | #define RT5645_WND_EN (0x1 << 15) | |
2038 | ||
2039 | /* Wind Noise Detection Control 2 (0x6d) */ | |
2040 | #define RT5645_WND_FC_NW_MASK (0x3f << 10) | |
2041 | #define RT5645_WND_FC_NW_SFT 10 | |
2042 | #define RT5645_WND_FC_WK_MASK (0x3f << 4) | |
2043 | #define RT5645_WND_FC_WK_SFT 4 | |
2044 | ||
2045 | /* Wind Noise Detection Control 3 (0x6e) */ | |
2046 | #define RT5645_HPF_FC_MASK (0x3f << 6) | |
2047 | #define RT5645_HPF_FC_SFT 6 | |
2048 | #define RT5645_WND_FC_ST_MASK (0x3f) | |
2049 | #define RT5645_WND_FC_ST_SFT 0 | |
2050 | ||
2051 | /* Wind Noise Detection Control 4 (0x6f) */ | |
2052 | #define RT5645_WND_TH_LO_MASK (0x3ff) | |
2053 | #define RT5645_WND_TH_LO_SFT 0 | |
2054 | ||
2055 | /* Wind Noise Detection Control 5 (0x70) */ | |
2056 | #define RT5645_WND_TH_HI_MASK (0x3ff) | |
2057 | #define RT5645_WND_TH_HI_SFT 0 | |
2058 | ||
2059 | /* Wind Noise Detection Control 8 (0x73) */ | |
2060 | #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */ | |
2061 | #define RT5645_WND_WIND_SFT 13 | |
2062 | #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */ | |
2063 | #define RT5645_WND_STRONG_SFT 12 | |
2064 | enum { | |
2065 | RT5645_NO_WIND, | |
2066 | RT5645_BREEZE, | |
2067 | RT5645_STORM, | |
2068 | }; | |
2069 | ||
2070 | /* Dipole Speaker Interface (0x75) */ | |
2071 | #define RT5645_DP_ATT_MASK (0x3 << 14) | |
2072 | #define RT5645_DP_ATT_SFT 14 | |
2073 | #define RT5645_DP_SPK_MASK (0x1 << 10) | |
2074 | #define RT5645_DP_SPK_SFT 10 | |
2075 | #define RT5645_DP_SPK_DIS (0x0 << 10) | |
2076 | #define RT5645_DP_SPK_EN (0x1 << 10) | |
2077 | ||
2078 | /* EQ Pre Volume Control (0xb3) */ | |
2079 | #define RT5645_EQ_PRE_VOL_MASK (0xffff) | |
2080 | #define RT5645_EQ_PRE_VOL_SFT 0 | |
2081 | ||
2082 | /* EQ Post Volume Control (0xb4) */ | |
2083 | #define RT5645_EQ_PST_VOL_MASK (0xffff) | |
2084 | #define RT5645_EQ_PST_VOL_SFT 0 | |
2085 | ||
2086 | /* Jack Detect Control 3 (0xf8) */ | |
2087 | #define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12) | |
2088 | #define RT5645_JD_CBJ_EN (0x1 << 7) | |
2089 | #define RT5645_JD_CBJ_POL (0x1 << 6) | |
2090 | #define RT5645_JD_TRI_CBJ_SEL_MASK (0x7 << 3) | |
2091 | #define RT5645_JD_TRI_CBJ_SEL_SFT (3) | |
2092 | #define RT5645_JD_TRI_HPO_SEL_MASK (0x7) | |
2093 | #define RT5645_JD_TRI_HPO_SEL_SFT (0) | |
2094 | #define RT5645_JD_F_GPIO_JD1 (0x0) | |
2095 | #define RT5645_JD_F_JD1_1 (0x1) | |
2096 | #define RT5645_JD_F_JD1_2 (0x2) | |
2097 | #define RT5645_JD_F_JD2 (0x3) | |
2098 | #define RT5645_JD_F_JD3 (0x4) | |
2099 | #define RT5645_JD_F_GPIO_JD2 (0x5) | |
2100 | #define RT5645_JD_F_MX0B_12 (0x6) | |
2101 | ||
2102 | /* Digital Misc Control (0xfa) */ | |
2103 | #define RT5645_RST_DSP (0x1 << 13) | |
2104 | #define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12) | |
2105 | #define RT5645_IF1_ADC1_IN1_SFT 12 | |
2106 | #define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11) | |
2107 | #define RT5645_IF1_ADC1_IN2_SFT 11 | |
2108 | #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10) | |
2109 | #define RT5645_IF1_ADC2_IN1_SFT 10 | |
2110 | #define RT5645_DIG_GATE_CTRL 0x1 | |
2111 | ||
2112 | /* General Control2 (0xfb) */ | |
2113 | #define RT5645_RXDC_SRC_MASK (0x1 << 7) | |
2114 | #define RT5645_RXDC_SRC_STO (0x0 << 7) | |
2115 | #define RT5645_RXDC_SRC_MONO (0x1 << 7) | |
2116 | #define RT5645_RXDC_SRC_SFT (7) | |
2117 | #define RT5645_RXDP2_SEL_MASK (0x1 << 3) | |
2118 | #define RT5645_RXDP2_SEL_IF2 (0x0 << 3) | |
2119 | #define RT5645_RXDP2_SEL_ADC (0x1 << 3) | |
2120 | #define RT5645_RXDP2_SEL_SFT (3) | |
2121 | ||
bb656add | 2122 | /* General Control3 (0xfc) */ |
2d4e2d02 | 2123 | #define RT5645_JD_PSV_MODE (0x1 << 12) |
bb656add | 2124 | #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11) |
ca8457bb BL |
2125 | #define RT5645_DET_CLK_MASK (0x3 << 9) |
2126 | #define RT5645_DET_CLK_DIS (0x0 << 9) | |
2127 | #define RT5645_DET_CLK_MODE1 (0x1 << 9) | |
2128 | #define RT5645_DET_CLK_MODE2 (0x2 << 9) | |
bb656add | 2129 | #define RT5645_MICINDET_MANU (0x1 << 7) |
f2988afe | 2130 | #define RT5645_RING2_SLEEVE_GND (0x1 << 5) |
1319b2f6 OC |
2131 | |
2132 | /* Vendor ID (0xfd) */ | |
2133 | #define RT5645_VER_C 0x2 | |
2134 | #define RT5645_VER_D 0x3 | |
2135 | ||
2136 | ||
2137 | /* Volume Rescale */ | |
2138 | #define RT5645_VOL_RSCL_MAX 0x27 | |
2139 | #define RT5645_VOL_RSCL_RANGE 0x1F | |
2140 | /* Debug String Length */ | |
2141 | #define RT5645_REG_DISP_LEN 23 | |
2142 | ||
2143 | ||
2144 | /* System Clock Source */ | |
2145 | enum { | |
2146 | RT5645_SCLK_S_MCLK, | |
2147 | RT5645_SCLK_S_PLL1, | |
2148 | RT5645_SCLK_S_RCCLK, | |
2149 | }; | |
2150 | ||
2151 | /* PLL1 Source */ | |
2152 | enum { | |
2153 | RT5645_PLL1_S_MCLK, | |
2154 | RT5645_PLL1_S_BCLK1, | |
2155 | RT5645_PLL1_S_BCLK2, | |
2156 | }; | |
2157 | ||
2158 | enum { | |
2159 | RT5645_AIF1, | |
2160 | RT5645_AIF2, | |
2161 | RT5645_AIFS, | |
2162 | }; | |
2163 | ||
2164 | enum { | |
ac4fc3ee | 2165 | RT5645_DMIC1_DISABLE, |
1319b2f6 OC |
2166 | RT5645_DMIC_DATA_IN2P, |
2167 | RT5645_DMIC_DATA_GPIO6, | |
2168 | RT5645_DMIC_DATA_GPIO10, | |
2169 | RT5645_DMIC_DATA_GPIO12, | |
2170 | }; | |
2171 | ||
2172 | enum { | |
ac4fc3ee | 2173 | RT5645_DMIC2_DISABLE, |
1319b2f6 OC |
2174 | RT5645_DMIC_DATA_IN2N, |
2175 | RT5645_DMIC_DATA_GPIO5, | |
2176 | RT5645_DMIC_DATA_GPIO11, | |
2177 | }; | |
2178 | ||
5c4ca99d BL |
2179 | enum { |
2180 | CODEC_TYPE_RT5645, | |
2181 | CODEC_TYPE_RT5650, | |
2182 | }; | |
2183 | ||
79080a8b FY |
2184 | /* filter mask */ |
2185 | enum { | |
2186 | RT5645_DA_STEREO_FILTER = 0x1, | |
2187 | RT5645_DA_MONO_L_FILTER = (0x1 << 1), | |
2188 | RT5645_DA_MONO_R_FILTER = (0x1 << 2), | |
2189 | RT5645_AD_STEREO_FILTER = (0x1 << 3), | |
2190 | RT5645_AD_MONO_L_FILTER = (0x1 << 4), | |
2191 | RT5645_AD_MONO_R_FILTER = (0x1 << 5), | |
2192 | }; | |
2193 | ||
2194 | int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec, | |
2195 | unsigned int filter_mask, unsigned int clk_src); | |
2196 | ||
f3fa1bbd | 2197 | int rt5645_set_jack_detect(struct snd_soc_codec *codec, |
6e747d53 BL |
2198 | struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, |
2199 | struct snd_soc_jack *btn_jack); | |
1319b2f6 | 2200 | #endif /* __RT5645_H__ */ |