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Merge tag 'hwmon-for-linus-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / sound / soc / codecs / rt5677.c
CommitLineData
0e826e86
OC		 1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/spi/spi.h>
af48f1d0 22#include <linux/firmware.h>
9bfde721 23#include <linux/property.h>
0e826e86
OC		 24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
30f14b43 32#include "rl6231.h"
0e826e86 33#include "rt5677.h"
af48f1d0 34#include "rt5677-spi.h"
0e826e86
OC		 35
36#define RT5677_DEVICE_ID 0x6327
37
38#define RT5677_PR_RANGE_BASE (0xff + 1)
39#define RT5677_PR_SPACING 0x100
40
41#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
42
43static const struct regmap_range_cfg rt5677_ranges[] = {
44 {
45 .name = "PR",
46 .range_min = RT5677_PR_BASE,
47 .range_max = RT5677_PR_BASE + 0xfd,
48 .selector_reg = RT5677_PRIV_INDEX,
49 .selector_mask = 0xff,
50 .selector_shift = 0x0,
51 .window_start = RT5677_PRIV_DATA,
52 .window_len = 0x1,
53 },
54};
55
8019ff6c 56static const struct reg_sequence init_list[] = {
2dfe2b08
OC		 57 {RT5677_ASRC_12, 0x0018},
58 {RT5677_PR_BASE + 0x3d, 0x364d},
59 {RT5677_PR_BASE + 0x17, 0x4fc0},
60 {RT5677_PR_BASE + 0x13, 0x0312},
61 {RT5677_PR_BASE + 0x1e, 0x0000},
62 {RT5677_PR_BASE + 0x12, 0x0eaa},
63 {RT5677_PR_BASE + 0x14, 0x018a},
74d6ea52
BL		 64 {RT5677_PR_BASE + 0x15, 0x0490},
65 {RT5677_PR_BASE + 0x38, 0x0f71},
66 {RT5677_PR_BASE + 0x39, 0x0f71},
0e826e86
OC		 67};
68#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
69
70static const struct reg_default rt5677_reg[] = {
71 {RT5677_RESET , 0x0000},
72 {RT5677_LOUT1 , 0xa800},
73 {RT5677_IN1 , 0x0000},
74 {RT5677_MICBIAS , 0x0000},
75 {RT5677_SLIMBUS_PARAM , 0x0000},
76 {RT5677_SLIMBUS_RX , 0x0000},
77 {RT5677_SLIMBUS_CTRL , 0x0000},
78 {RT5677_SIDETONE_CTRL , 0x000b},
79 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
80 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
81 {RT5677_DAC4_DIG_VOL , 0xafaf},
82 {RT5677_DAC3_DIG_VOL , 0xafaf},
83 {RT5677_DAC1_DIG_VOL , 0xafaf},
84 {RT5677_DAC2_DIG_VOL , 0xafaf},
85 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
86 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_STO1_2_ADC_BST , 0x0000},
89 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_ADC_BST_CTRL2 , 0x0000},
91 {RT5677_STO3_4_ADC_BST , 0x0000},
92 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
93 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
94 {RT5677_STO4_ADC_MIXER , 0xd4c0},
95 {RT5677_STO3_ADC_MIXER , 0xd4c0},
96 {RT5677_STO2_ADC_MIXER , 0xd4c0},
97 {RT5677_STO1_ADC_MIXER , 0xd4c0},
98 {RT5677_MONO_ADC_MIXER , 0xd4d1},
99 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
100 {RT5677_STO1_DAC_MIXER , 0xaaaa},
101 {RT5677_MONO_DAC_MIXER , 0xaaaa},
102 {RT5677_DD1_MIXER , 0xaaaa},
103 {RT5677_DD2_MIXER , 0xaaaa},
104 {RT5677_IF3_DATA , 0x0000},
105 {RT5677_IF4_DATA , 0x0000},
106 {RT5677_PDM_OUT_CTRL , 0x8888},
107 {RT5677_PDM_DATA_CTRL1 , 0x0000},
108 {RT5677_PDM_DATA_CTRL2 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
111 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
113 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
114 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
115 {RT5677_TDM1_CTRL1 , 0x0300},
116 {RT5677_TDM1_CTRL2 , 0x0000},
117 {RT5677_TDM1_CTRL3 , 0x4000},
118 {RT5677_TDM1_CTRL4 , 0x0123},
119 {RT5677_TDM1_CTRL5 , 0x4567},
120 {RT5677_TDM2_CTRL1 , 0x0300},
121 {RT5677_TDM2_CTRL2 , 0x0000},
122 {RT5677_TDM2_CTRL3 , 0x4000},
123 {RT5677_TDM2_CTRL4 , 0x0123},
124 {RT5677_TDM2_CTRL5 , 0x4567},
125 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
126 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
132 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
133 {RT5677_DMIC_CTRL1 , 0x1505},
134 {RT5677_DMIC_CTRL2 , 0x0055},
135 {RT5677_HAP_GENE_CTRL1 , 0x0111},
136 {RT5677_HAP_GENE_CTRL2 , 0x0064},
137 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
142 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
143 {RT5677_HAP_GENE_CTRL9 , 0xf000},
144 {RT5677_HAP_GENE_CTRL10 , 0x0000},
145 {RT5677_PWR_DIG1 , 0x0000},
146 {RT5677_PWR_DIG2 , 0x0000},
147 {RT5677_PWR_ANLG1 , 0x0055},
148 {RT5677_PWR_ANLG2 , 0x0000},
149 {RT5677_PWR_DSP1 , 0x0001},
150 {RT5677_PWR_DSP_ST , 0x0000},
151 {RT5677_PWR_DSP2 , 0x0000},
152 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
153 {RT5677_PRIV_INDEX , 0x0000},
154 {RT5677_PRIV_DATA , 0x0000},
155 {RT5677_I2S4_SDP , 0x8000},
156 {RT5677_I2S1_SDP , 0x8000},
157 {RT5677_I2S2_SDP , 0x8000},
158 {RT5677_I2S3_SDP , 0x8000},
159 {RT5677_CLK_TREE_CTRL1 , 0x1111},
160 {RT5677_CLK_TREE_CTRL2 , 0x1111},
161 {RT5677_CLK_TREE_CTRL3 , 0x0000},
162 {RT5677_PLL1_CTRL1 , 0x0000},
163 {RT5677_PLL1_CTRL2 , 0x0000},
164 {RT5677_PLL2_CTRL1 , 0x0c60},
165 {RT5677_PLL2_CTRL2 , 0x2000},
166 {RT5677_GLB_CLK1 , 0x0000},
167 {RT5677_GLB_CLK2 , 0x0000},
168 {RT5677_ASRC_1 , 0x0000},
169 {RT5677_ASRC_2 , 0x0000},
170 {RT5677_ASRC_3 , 0x0000},
171 {RT5677_ASRC_4 , 0x0000},
172 {RT5677_ASRC_5 , 0x0000},
173 {RT5677_ASRC_6 , 0x0000},
174 {RT5677_ASRC_7 , 0x0000},
175 {RT5677_ASRC_8 , 0x0000},
176 {RT5677_ASRC_9 , 0x0000},
177 {RT5677_ASRC_10 , 0x0000},
178 {RT5677_ASRC_11 , 0x0000},
86ae04b1 179 {RT5677_ASRC_12 , 0x0018},
0e826e86
OC		 180 {RT5677_ASRC_13 , 0x0000},
181 {RT5677_ASRC_14 , 0x0000},
182 {RT5677_ASRC_15 , 0x0000},
183 {RT5677_ASRC_16 , 0x0000},
184 {RT5677_ASRC_17 , 0x0000},
185 {RT5677_ASRC_18 , 0x0000},
186 {RT5677_ASRC_19 , 0x0000},
187 {RT5677_ASRC_20 , 0x0000},
188 {RT5677_ASRC_21 , 0x000c},
189 {RT5677_ASRC_22 , 0x0000},
190 {RT5677_ASRC_23 , 0x0000},
191 {RT5677_VAD_CTRL1 , 0x2184},
192 {RT5677_VAD_CTRL2 , 0x010a},
193 {RT5677_VAD_CTRL3 , 0x0aea},
194 {RT5677_VAD_CTRL4 , 0x000c},
195 {RT5677_VAD_CTRL5 , 0x0000},
196 {RT5677_DSP_INB_CTRL1 , 0x0000},
197 {RT5677_DSP_INB_CTRL2 , 0x0000},
198 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
199 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
201 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
202 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
203 {RT5677_ADC_EQ_CTRL1 , 0x6000},
204 {RT5677_ADC_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL1 , 0xc000},
206 {RT5677_EQ_CTRL2 , 0x0000},
207 {RT5677_EQ_CTRL3 , 0x0000},
208 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
209 {RT5677_JD_CTRL1 , 0x0000},
210 {RT5677_JD_CTRL2 , 0x0000},
211 {RT5677_JD_CTRL3 , 0x0000},
212 {RT5677_IRQ_CTRL1 , 0x0000},
213 {RT5677_IRQ_CTRL2 , 0x0000},
214 {RT5677_GPIO_ST , 0x0000},
215 {RT5677_GPIO_CTRL1 , 0x0000},
216 {RT5677_GPIO_CTRL2 , 0x0000},
217 {RT5677_GPIO_CTRL3 , 0x0000},
218 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
219 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
227 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
228 {RT5677_MB_DRC_CTRL1 , 0x0f20},
229 {RT5677_DRC1_CTRL1 , 0x001f},
230 {RT5677_DRC1_CTRL2 , 0x020c},
231 {RT5677_DRC1_CTRL3 , 0x1f00},
232 {RT5677_DRC1_CTRL4 , 0x0000},
233 {RT5677_DRC1_CTRL5 , 0x0000},
234 {RT5677_DRC1_CTRL6 , 0x0029},
235 {RT5677_DRC2_CTRL1 , 0x001f},
236 {RT5677_DRC2_CTRL2 , 0x020c},
237 {RT5677_DRC2_CTRL3 , 0x1f00},
238 {RT5677_DRC2_CTRL4 , 0x0000},
239 {RT5677_DRC2_CTRL5 , 0x0000},
240 {RT5677_DRC2_CTRL6 , 0x0029},
241 {RT5677_DRC1_HL_CTRL1 , 0x8000},
242 {RT5677_DRC1_HL_CTRL2 , 0x0200},
243 {RT5677_DRC2_HL_CTRL1 , 0x8000},
244 {RT5677_DRC2_HL_CTRL2 , 0x0200},
245 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
246 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
247 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
248 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
249 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
250 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
251 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
252 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
253 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
254 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
255 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
256 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
257 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
258 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
259 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
260 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
261 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
262 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
263 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
264 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
265 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
266 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
267 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
268 {RT5677_DIG_MISC , 0x0000},
269 {RT5677_GEN_CTRL1 , 0x0000},
270 {RT5677_GEN_CTRL2 , 0x0000},
271 {RT5677_VENDOR_ID , 0x0000},
272 {RT5677_VENDOR_ID1 , 0x10ec},
273 {RT5677_VENDOR_ID2 , 0x6327},
274};
275
276static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
277{
278 int i;
279
280 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
281 if (reg >= rt5677_ranges[i].range_min &&
282 reg <= rt5677_ranges[i].range_max) {
283 return true;
284 }
285 }
286
287 switch (reg) {
288 case RT5677_RESET:
289 case RT5677_SLIMBUS_PARAM:
290 case RT5677_PDM_DATA_CTRL1:
291 case RT5677_PDM_DATA_CTRL2:
292 case RT5677_PDM1_DATA_CTRL4:
293 case RT5677_PDM2_DATA_CTRL4:
294 case RT5677_I2C_MASTER_CTRL1:
295 case RT5677_I2C_MASTER_CTRL7:
296 case RT5677_I2C_MASTER_CTRL8:
297 case RT5677_HAP_GENE_CTRL2:
298 case RT5677_PWR_DSP_ST:
299 case RT5677_PRIV_DATA:
0e826e86
OC		 300 case RT5677_ASRC_22:
301 case RT5677_ASRC_23:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
307 case RT5677_GPIO_ST:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
316 return true;
317 default:
318 return false;
319 }
320}
321
322static bool rt5677_readable_register(struct device *dev, unsigned int reg)
323{
324 int i;
325
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
329 return true;
330 }
331 }
332
333 switch (reg) {
334 case RT5677_RESET:
335 case RT5677_LOUT1:
336 case RT5677_IN1:
337 case RT5677_MICBIAS:
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
431 case RT5677_ASRC_1:
432 case RT5677_ASRC_2:
433 case RT5677_ASRC_3:
434 case RT5677_ASRC_4:
435 case RT5677_ASRC_5:
436 case RT5677_ASRC_6:
437 case RT5677_ASRC_7:
438 case RT5677_ASRC_8:
439 case RT5677_ASRC_9:
440 case RT5677_ASRC_10:
441 case RT5677_ASRC_11:
442 case RT5677_ASRC_12:
443 case RT5677_ASRC_13:
444 case RT5677_ASRC_14:
445 case RT5677_ASRC_15:
446 case RT5677_ASRC_16:
447 case RT5677_ASRC_17:
448 case RT5677_ASRC_18:
449 case RT5677_ASRC_19:
450 case RT5677_ASRC_20:
451 case RT5677_ASRC_21:
452 case RT5677_ASRC_22:
453 case RT5677_ASRC_23:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
477 case RT5677_GPIO_ST:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
537 return true;
538 default:
539 return false;
540 }
541}
542
af48f1d0
OC		 543/**
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
19ba484d 545 * @rt5677: Private Data.
af48f1d0
OC		 546 * @addr: Address index.
547 * @value: Address data.
548 *
549 *
550 * Returns 0 for success or negative error code.
551 */
19ba484d 552static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
af48f1d0
OC		 553 unsigned int addr, unsigned int value, unsigned int opcode)
554{
19ba484d 555 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 556 int ret;
557
558 mutex_lock(&rt5677->dsp_cmd_lock);
559
19ba484d
OC		 560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
561 addr >> 16);
af48f1d0
OC		 562 if (ret < 0) {
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
564 goto err;
565 }
566
19ba484d 567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 568 addr & 0xffff);
569 if (ret < 0) {
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
571 goto err;
572 }
573
19ba484d 574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
af48f1d0
OC		 575 value >> 16);
576 if (ret < 0) {
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
578 goto err;
579 }
580
19ba484d 581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
af48f1d0
OC		 582 value & 0xffff);
583 if (ret < 0) {
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
585 goto err;
586 }
587
19ba484d
OC		 588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
589 opcode);
af48f1d0
OC		 590 if (ret < 0) {
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
592 goto err;
593 }
594
595err:
596 mutex_unlock(&rt5677->dsp_cmd_lock);
597
598 return ret;
599}
600
601/**
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
19ba484d 603 * rt5677: Private Data.
af48f1d0
OC		 604 * @addr: Address index.
605 * @value: Address data.
606 *
19ba484d 607 *
af48f1d0
OC		 608 * Returns 0 for success or negative error code.
609 */
610static int rt5677_dsp_mode_i2c_read_addr(
19ba484d 611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
af48f1d0 612{
19ba484d 613 struct snd_soc_codec *codec = rt5677->codec;
af48f1d0
OC		 614 int ret;
615 unsigned int msb, lsb;
616
617 mutex_lock(&rt5677->dsp_cmd_lock);
618
19ba484d
OC		 619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
620 addr >> 16);
af48f1d0
OC		 621 if (ret < 0) {
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
623 goto err;
624 }
625
19ba484d 626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
af48f1d0
OC		 627 addr & 0xffff);
628 if (ret < 0) {
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
630 goto err;
631 }
632
19ba484d
OC		 633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
634 0x0002);
af48f1d0
OC		 635 if (ret < 0) {
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
637 goto err;
638 }
639
19ba484d
OC		 640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
af48f1d0
OC		 642 *value = (msb << 16) | lsb;
643
644err:
645 mutex_unlock(&rt5677->dsp_cmd_lock);
646
647 return ret;
648}
649
650/**
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
19ba484d 652 * rt5677: Private Data.
af48f1d0
OC		 653 * @reg: Register index.
654 * @value: Register data.
655 *
656 *
657 * Returns 0 for success or negative error code.
658 */
19ba484d 659static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
af48f1d0
OC		 660 unsigned int reg, unsigned int value)
661{
19ba484d 662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
af48f1d0
OC		 663 value, 0x0001);
664}
665
666/**
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
19ba484d 670 * @value: Register data.
af48f1d0
OC		 671 *
672 *
19ba484d 673 * Returns 0 for success or negative error code.
af48f1d0 674 */
19ba484d
OC		 675static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
af48f1d0 677{
19ba484d
OC		 678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
679 value);
af48f1d0 680
19ba484d 681 *value &= 0xffff;
af48f1d0 682
19ba484d 683 return ret;
af48f1d0
OC		 684}
685
19ba484d 686static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
af48f1d0 687{
19ba484d 688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
af48f1d0 689
19ba484d
OC		 690 if (on) {
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
693 } else {
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
af48f1d0 696 }
af48f1d0
OC		 697}
698
699static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
700{
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
703 int ret;
704
4c121129
AB		 705 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
706 return -ENXIO;
707
af48f1d0
OC		 708 if (on && !activity) {
709 activity = true;
710
711 regcache_cache_only(rt5677->regmap, false);
712 regcache_cache_bypass(rt5677->regmap, true);
713
714 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
715 regmap_update_bits(rt5677->regmap,
716 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
717 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
718 RT5677_LDO1_SEL_MASK, 0x0);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
720 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
ab1f7095
OC		 721 switch (rt5677->type) {
722 case RT5677:
723 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
724 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
725 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
726 RT5677_PLL2_PR_SRC_MASK |
727 RT5677_DSP_CLK_SRC_MASK,
728 RT5677_PLL2_PR_SRC_MCLK2 |
729 RT5677_DSP_CLK_SRC_BYPASS);
730 break;
731 case RT5676:
732 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
733 RT5677_DSP_CLK_SRC_MASK,
734 RT5677_DSP_CLK_SRC_BYPASS);
735 break;
736 default:
737 break;
738 }
af48f1d0 739 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
19ba484d
OC		 740 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
741 rt5677_set_dsp_mode(codec, true);
af48f1d0
OC		 742
743 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
744 codec->dev);
745 if (ret == 0) {
7d4d443e 746 rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
af48f1d0
OC		 747 release_firmware(rt5677->fw1);
748 }
749
750 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
751 codec->dev);
752 if (ret == 0) {
7d4d443e 753 rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
af48f1d0
OC		 754 release_firmware(rt5677->fw2);
755 }
756
19ba484d 757 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
af48f1d0
OC		 758
759 regcache_cache_bypass(rt5677->regmap, false);
760 regcache_cache_only(rt5677->regmap, true);
761 } else if (!on && activity) {
762 activity = false;
763
764 regcache_cache_only(rt5677->regmap, false);
765 regcache_cache_bypass(rt5677->regmap, true);
766
19ba484d
OC		 767 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
768 rt5677_set_dsp_mode(codec, false);
769 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
af48f1d0
OC		 770
771 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
772
773 regcache_cache_bypass(rt5677->regmap, false);
774 regcache_mark_dirty(rt5677->regmap);
775 regcache_sync(rt5677->regmap);
776 }
777
778 return 0;
779}
780
0e826e86 781static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
40e3262e 782static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
0e826e86 783static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
40e3262e 784static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
0e826e86 785static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
90bdbb46 786static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
0e826e86
OC		 787
788/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
53f28609 789static const DECLARE_TLV_DB_RANGE(bst_tlv,
0e826e86
OC		 790 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
791 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
792 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
793 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
794 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
795 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
53f28609
LPC		 796 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
797);
0e826e86 798
af48f1d0
OC		 799static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
800 struct snd_ctl_elem_value *ucontrol)
801{
6087fcab
FY		 802 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
803 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
af48f1d0
OC		 804
805 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
806
807 return 0;
808}
809
810static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
811 struct snd_ctl_elem_value *ucontrol)
812{
6087fcab
FY		 813 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
814 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
815 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
af48f1d0
OC		 816
817 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
818
6b43c2eb 819 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
af48f1d0
OC		 820 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
821
822 return 0;
823}
824
0e826e86
OC		 825static const struct snd_kcontrol_new rt5677_snd_controls[] = {
826 /* OUTPUT Control */
827 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
828 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
829 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
830 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
831 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
832 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
833
834 /* DAC Digital Volume */
835 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
40e3262e 836 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 837 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
40e3262e 838 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 839 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
40e3262e 840 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86 841 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
40e3262e 842 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
0e826e86
OC		 843
844 /* IN1/IN2 Control */
845 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
846 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
847
848 /* ADC Digital Volume Control */
849 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
850 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
851 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
852 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
853 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
854 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
856 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
857 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
858 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
859
860 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
40e3262e 861 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 862 adc_vol_tlv),
863 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
40e3262e 864 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 865 adc_vol_tlv),
866 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
40e3262e 867 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 868 adc_vol_tlv),
869 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
40e3262e 870 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 871 adc_vol_tlv),
872 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
40e3262e 873 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
0e826e86
OC		 874 adc_vol_tlv),
875
90bdbb46
OC		 876 /* Sidetone Control */
877 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
878 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
879
0e826e86 880 /* ADC Boost Volume Control */
80220f29 881 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 882 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
883 adc_bst_tlv),
80220f29 884 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 885 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
886 adc_bst_tlv),
80220f29 887 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 888 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
889 adc_bst_tlv),
80220f29 890 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 891 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
892 adc_bst_tlv),
80220f29 893 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
0e826e86
OC		 894 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
895 adc_bst_tlv),
af48f1d0
OC		 896
897 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
898 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
0e826e86
OC		 899};
900
901/**
902 * set_dmic_clk - Set parameter of dmic.
903 *
904 * @w: DAPM widget.
905 * @kcontrol: The kcontrol of this widget.
906 * @event: Event id.
907 *
908 * Choose dmic clock between 1MHz and 3MHz.
909 * It is better for clock to approximate 3MHz.
910 */
911static int set_dmic_clk(struct snd_soc_dapm_widget *w,
912 struct snd_kcontrol *kcontrol, int event)
913{
46f20872 914 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86 915 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
00a6d6e5 916 int idx, rate;
0e826e86 917
00a6d6e5
OC		 918 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
919 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
920 idx = rl6231_calc_dmic_clk(rate);
0e826e86
OC		 921 if (idx < 0)
922 dev_err(codec->dev, "Failed to set DMIC clock\n");
923 else
924 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
925 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
926 return idx;
927}
928
929static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
930 struct snd_soc_dapm_widget *sink)
931{
46f20872
LPC		 932 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
933 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
0e826e86
OC		 934 unsigned int val;
935
936 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
937 val &= RT5677_SCLK_SRC_MASK;
938 if (val == RT5677_SCLK_SRC_PLL1)
939 return 1;
940 else
941 return 0;
942}
943
5a8c7c26
OC		 944static int is_using_asrc(struct snd_soc_dapm_widget *source,
945 struct snd_soc_dapm_widget *sink)
946{
46f20872 947 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
e4b7e6a8 948 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
5a8c7c26
OC		 949 unsigned int reg, shift, val;
950
951 if (source->reg == RT5677_ASRC_1) {
952 switch (source->shift) {
953 case 12:
954 reg = RT5677_ASRC_4;
955 shift = 0;
956 break;
957 case 13:
958 reg = RT5677_ASRC_4;
959 shift = 4;
960 break;
961 case 14:
962 reg = RT5677_ASRC_4;
963 shift = 8;
964 break;
965 case 15:
966 reg = RT5677_ASRC_4;
967 shift = 12;
968 break;
969 default:
970 return 0;
971 }
972 } else {
973 switch (source->shift) {
974 case 0:
975 reg = RT5677_ASRC_6;
976 shift = 8;
977 break;
978 case 1:
979 reg = RT5677_ASRC_6;
980 shift = 12;
981 break;
982 case 2:
983 reg = RT5677_ASRC_5;
984 shift = 0;
985 break;
986 case 3:
987 reg = RT5677_ASRC_5;
988 shift = 4;
989 break;
990 case 4:
991 reg = RT5677_ASRC_5;
992 shift = 8;
993 break;
994 case 5:
995 reg = RT5677_ASRC_5;
996 shift = 12;
997 break;
998 case 12:
999 reg = RT5677_ASRC_3;
1000 shift = 0;
1001 break;
1002 case 13:
1003 reg = RT5677_ASRC_3;
1004 shift = 4;
1005 break;
1006 case 14:
1007 reg = RT5677_ASRC_3;
1008 shift = 12;
1009 break;
1010 default:
1011 return 0;
1012 }
1013 }
1014
e4b7e6a8
OC		 1015 regmap_read(rt5677->regmap, reg, &val);
1016 val = (val >> shift) & 0xf;
1017
5a8c7c26
OC		 1018 switch (val) {
1019 case 1 ... 6:
1020 return 1;
1021 default:
1022 return 0;
1023 }
1024
1025}
1026
1027static int can_use_asrc(struct snd_soc_dapm_widget *source,
1028 struct snd_soc_dapm_widget *sink)
1029{
1030 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1031 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1032
1033 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1034 return 1;
1035
1036 return 0;
1037}
1038
c36aa0a1
OC		 1039/**
1040 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1041 * @codec: SoC audio codec device.
1042 * @filter_mask: mask of filters.
1043 * @clk_src: clock source
1044 *
1045 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1046 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1047 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1048 * ASRC function will track i2s clock and generate a corresponding system clock
1049 * for codec. This function provides an API to select the clock source for a
1050 * set of filters specified by the mask. And the codec driver will turn on ASRC
1051 * for these filters if ASRC is selected as their clock source.
1052 */
1053int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1054 unsigned int filter_mask, unsigned int clk_src)
1055{
1056 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1057 unsigned int asrc3_mask = 0, asrc3_value = 0;
1058 unsigned int asrc4_mask = 0, asrc4_value = 0;
1059 unsigned int asrc5_mask = 0, asrc5_value = 0;
1060 unsigned int asrc6_mask = 0, asrc6_value = 0;
1061 unsigned int asrc7_mask = 0, asrc7_value = 0;
16ab6e18 1062 unsigned int asrc8_mask = 0, asrc8_value = 0;
c36aa0a1
OC		 1063
1064 switch (clk_src) {
1065 case RT5677_CLK_SEL_SYS:
1066 case RT5677_CLK_SEL_I2S1_ASRC:
1067 case RT5677_CLK_SEL_I2S2_ASRC:
1068 case RT5677_CLK_SEL_I2S3_ASRC:
1069 case RT5677_CLK_SEL_I2S4_ASRC:
1070 case RT5677_CLK_SEL_I2S5_ASRC:
1071 case RT5677_CLK_SEL_I2S6_ASRC:
1072 case RT5677_CLK_SEL_SYS2:
1073 case RT5677_CLK_SEL_SYS3:
1074 case RT5677_CLK_SEL_SYS4:
1075 case RT5677_CLK_SEL_SYS5:
1076 case RT5677_CLK_SEL_SYS6:
1077 case RT5677_CLK_SEL_SYS7:
1078 break;
1079
1080 default:
1081 return -EINVAL;
1082 }
1083
1084 /* ASRC 3 */
1085 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1086 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1087 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1088 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1089 }
1090
1091 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1092 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1093 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1094 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1095 }
1096
1097 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1098 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1099 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1100 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1101 }
1102
1103 if (asrc3_mask)
1104 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1105 asrc3_value);
1106
1107 /* ASRC 4 */
1108 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1109 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1110 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1111 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1112 }
1113
1114 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1115 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1116 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1117 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1118 }
1119
1120 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1121 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1122 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1123 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1124 }
1125
1126 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1127 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1128 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1129 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1130 }
1131
1132 if (asrc4_mask)
1133 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1134 asrc4_value);
1135
1136 /* ASRC 5 */
1137 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1138 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1139 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1140 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1141 }
1142
1143 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1144 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1145 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1146 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1147 }
1148
1149 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1150 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1151 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1152 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1153 }
1154
1155 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1156 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1157 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1158 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1159 }
1160
1161 if (asrc5_mask)
1162 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1163 asrc5_value);
1164
1165 /* ASRC 6 */
1166 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1167 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1168 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1169 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1170 }
1171
1172 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1173 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1174 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1175 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1176 }
1177
1178 if (asrc6_mask)
1179 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1180 asrc6_value);
1181
1182 /* ASRC 7 */
1183 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1184 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1185 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1186 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1187 }
1188
1189 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1190 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1191 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1192 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1193 }
1194
1195 if (asrc7_mask)
1196 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1197 asrc7_value);
1198
16ab6e18
BL		 1199 /* ASRC 8 */
1200 if (filter_mask & RT5677_I2S1_SOURCE) {
1201 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1202 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1203 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1204 }
1205
1206 if (filter_mask & RT5677_I2S2_SOURCE) {
1207 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1208 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1209 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1210 }
1211
1212 if (filter_mask & RT5677_I2S3_SOURCE) {
1213 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1214 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1215 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1216 }
1217
1218 if (filter_mask & RT5677_I2S4_SOURCE) {
1219 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1220 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1221 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1222 }
1223
1224 if (asrc8_mask)
1225 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1226 asrc8_value);
1227
c36aa0a1
OC		 1228 return 0;
1229}
1230EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1231
5220f7fb
OC		 1232static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1233 struct snd_soc_dapm_widget *sink)
1234{
1235 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1236 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1237 unsigned int asrc_setting;
1238
1239 switch (source->shift) {
1240 case 11:
1241 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1242 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1243 RT5677_AD_STO1_CLK_SEL_SFT;
1244 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1245 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1246 return 1;
1247 break;
1248
1249 case 10:
1250 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1251 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1252 RT5677_AD_STO2_CLK_SEL_SFT;
1253 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1254 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1255 return 1;
1256 break;
1257
1258 case 9:
1259 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1260 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1261 RT5677_AD_STO3_CLK_SEL_SFT;
1262 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1263 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1264 return 1;
1265 break;
1266
1267 case 8:
1268 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1269 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1270 RT5677_AD_STO4_CLK_SEL_SFT;
1271 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1272 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1273 return 1;
1274 break;
1275
1276 case 7:
1277 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1278 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1279 RT5677_AD_MONOL_CLK_SEL_SFT;
1280 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1281 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1282 return 1;
1283 break;
1284
1285 case 6:
1286 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1287 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1288 RT5677_AD_MONOR_CLK_SEL_SFT;
1289 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1290 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1291 return 1;
1292 break;
1293
1294 default:
1295 break;
1296 }
1297
1298 return 0;
1299}
1300
0e826e86
OC		 1301/* Digital Mixer */
1302static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1303 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1304 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1305 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1306 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1307};
1308
1309static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1310 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1311 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1312 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1313 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1314};
1315
1316static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1317 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1318 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1319 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1320 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1321};
1322
1323static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1324 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1325 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1326 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1327 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1328};
1329
1330static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1331 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1332 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1333 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1334 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1335};
1336
1337static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1338 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1339 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1340 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1341 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1342};
1343
1344static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1345 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1346 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1347 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1348 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1349};
1350
1351static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1352 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1353 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1354 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1355 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1356};
1357
1358static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1359 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1360 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1361 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1362 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1363};
1364
1365static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1366 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1367 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1368 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1369 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1370};
1371
1372static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1373 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1374 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1375 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1376 RT5677_M_DAC1_L_SFT, 1, 1),
1377};
1378
1379static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1380 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1381 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1382 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1383 RT5677_M_DAC1_R_SFT, 1, 1),
1384};
1385
1386static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
c22d7666 1387 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1388 RT5677_M_ST_DAC1_L_SFT, 1, 1),
c22d7666 1389 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1390 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
c22d7666 1391 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1392 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
c22d7666 1393 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
0e826e86
OC		 1394 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1395};
1396
1397static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
c22d7666 1398 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1399 RT5677_M_ST_DAC1_R_SFT, 1, 1),
c22d7666 1400 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1401 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
c22d7666 1402 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
0e826e86 1403 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
c22d7666 1404 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
0e826e86
OC		 1405 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1406};
1407
1408static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
c22d7666 1409 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1410 RT5677_M_ST_DAC2_L_SFT, 1, 1),
c22d7666 1411 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1412 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
c22d7666 1413 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1414 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
c22d7666 1415 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
0e826e86
OC		 1416 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1417};
1418
1419static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
c22d7666 1420 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1421 RT5677_M_ST_DAC2_R_SFT, 1, 1),
c22d7666 1422 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1423 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
c22d7666 1424 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
0e826e86 1425 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
c22d7666 1426 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
0e826e86
OC		 1427 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1428};
1429
1430static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
c22d7666 1431 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
0e826e86 1432 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
c22d7666 1433 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
0e826e86 1434 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
c22d7666 1435 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
0e826e86 1436 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
c22d7666 1437 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
0e826e86
OC		 1438 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1439};
1440
1441static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
c22d7666 1442 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
0e826e86 1443 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
c22d7666 1444 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
0e826e86 1445 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
c22d7666 1446 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
0e826e86 1447 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
c22d7666 1448 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
0e826e86
OC		 1449 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1450};
1451
1452static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
c22d7666 1453 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
0e826e86 1454 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
c22d7666 1455 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
0e826e86 1456 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
c22d7666 1457 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
0e826e86 1458 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
c22d7666 1459 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
0e826e86
OC		 1460 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1461};
1462
1463static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
c22d7666 1464 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
0e826e86 1465 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
c22d7666 1466 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
0e826e86 1467 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
c22d7666 1468 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
0e826e86 1469 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
c22d7666 1470 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
0e826e86
OC		 1471 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1472};
1473
1474static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1475 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1476 RT5677_DSP_IB_01_H_SFT, 1, 1),
1477 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1478 RT5677_DSP_IB_23_H_SFT, 1, 1),
1479 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1480 RT5677_DSP_IB_45_H_SFT, 1, 1),
1481 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1482 RT5677_DSP_IB_6_H_SFT, 1, 1),
1483 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1484 RT5677_DSP_IB_7_H_SFT, 1, 1),
1485 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1486 RT5677_DSP_IB_8_H_SFT, 1, 1),
1487 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1488 RT5677_DSP_IB_9_H_SFT, 1, 1),
1489};
1490
1491static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1492 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1493 RT5677_DSP_IB_01_L_SFT, 1, 1),
1494 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1495 RT5677_DSP_IB_23_L_SFT, 1, 1),
1496 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1497 RT5677_DSP_IB_45_L_SFT, 1, 1),
1498 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1499 RT5677_DSP_IB_6_L_SFT, 1, 1),
1500 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1501 RT5677_DSP_IB_7_L_SFT, 1, 1),
1502 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1503 RT5677_DSP_IB_8_L_SFT, 1, 1),
1504 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1505 RT5677_DSP_IB_9_L_SFT, 1, 1),
1506};
1507
1508static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1509 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1510 RT5677_DSP_IB_01_H_SFT, 1, 1),
1511 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1512 RT5677_DSP_IB_23_H_SFT, 1, 1),
1513 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1514 RT5677_DSP_IB_45_H_SFT, 1, 1),
1515 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1516 RT5677_DSP_IB_6_H_SFT, 1, 1),
1517 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1518 RT5677_DSP_IB_7_H_SFT, 1, 1),
1519 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1520 RT5677_DSP_IB_8_H_SFT, 1, 1),
1521 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1522 RT5677_DSP_IB_9_H_SFT, 1, 1),
1523};
1524
1525static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1526 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1527 RT5677_DSP_IB_01_L_SFT, 1, 1),
1528 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1529 RT5677_DSP_IB_23_L_SFT, 1, 1),
1530 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1531 RT5677_DSP_IB_45_L_SFT, 1, 1),
1532 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1533 RT5677_DSP_IB_6_L_SFT, 1, 1),
1534 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1535 RT5677_DSP_IB_7_L_SFT, 1, 1),
1536 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1537 RT5677_DSP_IB_8_L_SFT, 1, 1),
1538 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1539 RT5677_DSP_IB_9_L_SFT, 1, 1),
1540};
1541
1542static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1543 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1544 RT5677_DSP_IB_01_H_SFT, 1, 1),
1545 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1546 RT5677_DSP_IB_23_H_SFT, 1, 1),
1547 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1548 RT5677_DSP_IB_45_H_SFT, 1, 1),
1549 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1550 RT5677_DSP_IB_6_H_SFT, 1, 1),
1551 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1552 RT5677_DSP_IB_7_H_SFT, 1, 1),
1553 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1554 RT5677_DSP_IB_8_H_SFT, 1, 1),
1555 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1556 RT5677_DSP_IB_9_H_SFT, 1, 1),
1557};
1558
1559static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1560 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1561 RT5677_DSP_IB_01_L_SFT, 1, 1),
1562 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1563 RT5677_DSP_IB_23_L_SFT, 1, 1),
1564 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1565 RT5677_DSP_IB_45_L_SFT, 1, 1),
1566 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1567 RT5677_DSP_IB_6_L_SFT, 1, 1),
1568 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1569 RT5677_DSP_IB_7_L_SFT, 1, 1),
1570 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1571 RT5677_DSP_IB_8_L_SFT, 1, 1),
1572 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1573 RT5677_DSP_IB_9_L_SFT, 1, 1),
1574};
1575
1576
1577/* Mux */
1b7fd76a 1578/* DAC1 L/R Source */ /* MX-29 [10:8] */
0e826e86
OC		 1579static const char * const rt5677_dac1_src[] = {
1580 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1581 "OB 01"
1582};
1583
1584static SOC_ENUM_SINGLE_DECL(
1585 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1586 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1587
1588static const struct snd_kcontrol_new rt5677_dac1_mux =
1b7fd76a 1589 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
0e826e86 1590
1b7fd76a 1591/* ADDA1 L/R Source */ /* MX-29 [1:0] */
0e826e86
OC		 1592static const char * const rt5677_adda1_src[] = {
1593 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1594};
1595
1596static SOC_ENUM_SINGLE_DECL(
1597 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1598 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1599
1600static const struct snd_kcontrol_new rt5677_adda1_mux =
1b7fd76a 1601 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
0e826e86
OC		 1602
1603
1b7fd76a 1604/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
0e826e86
OC		 1605static const char * const rt5677_dac2l_src[] = {
1606 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1607 "OB 2",
1608};
1609
1610static SOC_ENUM_SINGLE_DECL(
1611 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1612 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1613
1614static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1b7fd76a 1615 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
0e826e86
OC		 1616
1617static const char * const rt5677_dac2r_src[] = {
1618 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1619 "OB 3", "Haptic Generator", "VAD ADC"
1620};
1621
1622static SOC_ENUM_SINGLE_DECL(
1623 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1624 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1625
1626static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1b7fd76a 1627 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
0e826e86 1628
1b7fd76a 1629/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
0e826e86
OC		 1630static const char * const rt5677_dac3l_src[] = {
1631 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1632 "SLB DAC 4", "OB 4"
1633};
1634
1635static SOC_ENUM_SINGLE_DECL(
1636 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1637 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1638
1639static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1b7fd76a 1640 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
0e826e86
OC		 1641
1642static const char * const rt5677_dac3r_src[] = {
1643 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1644 "SLB DAC 5", "OB 5"
1645};
1646
1647static SOC_ENUM_SINGLE_DECL(
1648 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1649 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1650
1651static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1b7fd76a 1652 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
0e826e86 1653
1b7fd76a 1654/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
0e826e86
OC		 1655static const char * const rt5677_dac4l_src[] = {
1656 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1657 "SLB DAC 6", "OB 6"
1658};
1659
1660static SOC_ENUM_SINGLE_DECL(
1661 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1662 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1663
1664static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1b7fd76a 1665 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
0e826e86
OC		 1666
1667static const char * const rt5677_dac4r_src[] = {
1668 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1669 "SLB DAC 7", "OB 7"
1670};
1671
1672static SOC_ENUM_SINGLE_DECL(
1673 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1674 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1675
1676static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1b7fd76a 1677 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
0e826e86
OC		 1678
1679/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1680static const char * const rt5677_iob_bypass_src[] = {
1681 "Bypass", "Pass SRC"
1682};
1683
1684static SOC_ENUM_SINGLE_DECL(
1685 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1686 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1687
1688static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1b7fd76a 1689 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
0e826e86
OC		 1690
1691static SOC_ENUM_SINGLE_DECL(
1692 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1693 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1694
1695static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1b7fd76a 1696 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
0e826e86
OC		 1697
1698static SOC_ENUM_SINGLE_DECL(
1699 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1700 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1701
1702static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1b7fd76a 1703 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
0e826e86
OC		 1704
1705static SOC_ENUM_SINGLE_DECL(
1706 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1707 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1708
1709static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1b7fd76a 1710 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
0e826e86
OC		 1711
1712static SOC_ENUM_SINGLE_DECL(
1713 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1714 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1715
1716static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1b7fd76a 1717 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
0e826e86 1718
d65fd3a4 1719/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
0e826e86
OC		 1720static const char * const rt5677_stereo_adc2_src[] = {
1721 "DD MIX1", "DMIC", "Stereo DAC MIX"
1722};
1723
1724static SOC_ENUM_SINGLE_DECL(
1725 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1726 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1727
1728static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1b7fd76a 1729 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
0e826e86
OC		 1730
1731static SOC_ENUM_SINGLE_DECL(
1732 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1733 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1734
1735static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1b7fd76a 1736 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
0e826e86
OC		 1737
1738static SOC_ENUM_SINGLE_DECL(
1739 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1740 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1741
1742static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1b7fd76a 1743 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
0e826e86
OC		 1744
1745/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1746static const char * const rt5677_dmic_src[] = {
1747 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1748};
1749
1750static SOC_ENUM_SINGLE_DECL(
1751 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1752 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1753
1754static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1b7fd76a 1755 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
0e826e86
OC		 1756
1757static SOC_ENUM_SINGLE_DECL(
1758 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1759 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1760
1761static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1b7fd76a 1762 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
0e826e86
OC		 1763
1764static SOC_ENUM_SINGLE_DECL(
1765 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1766 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1767
1768static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1b7fd76a 1769 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
0e826e86
OC		 1770
1771static SOC_ENUM_SINGLE_DECL(
1772 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1773 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1774
1775static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1b7fd76a 1776 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
0e826e86
OC		 1777
1778static SOC_ENUM_SINGLE_DECL(
1779 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1780 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1781
1782static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1b7fd76a 1783 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
0e826e86
OC		 1784
1785static SOC_ENUM_SINGLE_DECL(
1786 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1787 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1788
1789static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1b7fd76a 1790 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
0e826e86 1791
1b7fd76a 1792/* Stereo2 ADC Source */ /* MX-26 [0] */
0e826e86
OC		 1793static const char * const rt5677_stereo2_adc_lr_src[] = {
1794 "L", "LR"
1795};
1796
1797static SOC_ENUM_SINGLE_DECL(
1798 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1799 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1800
1801static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1b7fd76a 1802 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
0e826e86 1803
d65fd3a4 1804/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
0e826e86
OC		 1805static const char * const rt5677_stereo_adc1_src[] = {
1806 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1807};
1808
1809static SOC_ENUM_SINGLE_DECL(
1810 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1811 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1812
1813static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1b7fd76a 1814 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
0e826e86
OC		 1815
1816static SOC_ENUM_SINGLE_DECL(
1817 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1818 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1819
1820static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1b7fd76a 1821 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
0e826e86
OC		 1822
1823static SOC_ENUM_SINGLE_DECL(
1824 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1825 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1826
1827static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1b7fd76a 1828 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
0e826e86 1829
1b7fd76a 1830/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
0e826e86
OC		 1831static const char * const rt5677_mono_adc2_l_src[] = {
1832 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1833};
1834
1835static SOC_ENUM_SINGLE_DECL(
1836 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1837 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1838
1839static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1b7fd76a 1840 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
0e826e86 1841
1b7fd76a 1842/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
0e826e86
OC		 1843static const char * const rt5677_mono_adc1_l_src[] = {
1844 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1845};
1846
1847static SOC_ENUM_SINGLE_DECL(
1848 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1849 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1850
1851static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1b7fd76a 1852 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
0e826e86 1853
1b7fd76a 1854/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
0e826e86
OC		 1855static const char * const rt5677_mono_adc2_r_src[] = {
1856 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1857};
1858
1859static SOC_ENUM_SINGLE_DECL(
1860 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1861 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1862
1863static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1b7fd76a 1864 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
0e826e86 1865
1b7fd76a 1866/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
0e826e86
OC		 1867static const char * const rt5677_mono_adc1_r_src[] = {
1868 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1869};
1870
1871static SOC_ENUM_SINGLE_DECL(
1872 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1873 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1874
1875static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1b7fd76a 1876 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
0e826e86
OC		 1877
1878/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1879static const char * const rt5677_stereo4_adc2_src[] = {
1880 "DD MIX1", "DMIC", "DD MIX2"
1881};
1882
1883static SOC_ENUM_SINGLE_DECL(
1884 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1885 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1886
1887static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1b7fd76a 1888 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
0e826e86
OC		 1889
1890
1891/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1892static const char * const rt5677_stereo4_adc1_src[] = {
1893 "DD MIX1", "ADC1/2", "DD MIX2"
1894};
1895
1896static SOC_ENUM_SINGLE_DECL(
1897 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1898 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1899
1900static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1b7fd76a 1901 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
0e826e86
OC		 1902
1903/* InBound0/1 Source */ /* MX-A3 [14:12] */
1904static const char * const rt5677_inbound01_src[] = {
1905 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1906 "VAD ADC/DAC1 FS"
1907};
1908
1909static SOC_ENUM_SINGLE_DECL(
1910 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1911 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1912
1913static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1914 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1915
1916/* InBound2/3 Source */ /* MX-A3 [10:8] */
1917static const char * const rt5677_inbound23_src[] = {
1918 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1919 "DAC1 FS", "IF4 DAC"
1920};
1921
1922static SOC_ENUM_SINGLE_DECL(
1923 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1924 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1925
1926static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1927 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1928
1929/* InBound4/5 Source */ /* MX-A3 [6:4] */
1930static const char * const rt5677_inbound45_src[] = {
1931 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1932 "IF3 DAC"
1933};
1934
1935static SOC_ENUM_SINGLE_DECL(
1936 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1937 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1938
1939static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1940 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1941
1942/* InBound6 Source */ /* MX-A3 [2:0] */
1943static const char * const rt5677_inbound6_src[] = {
1944 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1945 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1946};
1947
1948static SOC_ENUM_SINGLE_DECL(
1949 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1950 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1951
1952static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1953 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1954
1955/* InBound7 Source */ /* MX-A4 [14:12] */
1956static const char * const rt5677_inbound7_src[] = {
1957 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1958 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1959};
1960
1961static SOC_ENUM_SINGLE_DECL(
1962 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1963 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1964
1965static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1966 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1967
1968/* InBound8 Source */ /* MX-A4 [10:8] */
1969static const char * const rt5677_inbound8_src[] = {
1970 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1971 "MONO ADC MIX L", "DACL1 FS"
1972};
1973
1974static SOC_ENUM_SINGLE_DECL(
1975 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1976 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1977
1978static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1979 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1980
1981/* InBound9 Source */ /* MX-A4 [6:4] */
1982static const char * const rt5677_inbound9_src[] = {
1983 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1984 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1985};
1986
1987static SOC_ENUM_SINGLE_DECL(
1988 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1989 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1990
1991static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1992 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1993
1994/* VAD Source */ /* MX-9F [6:4] */
1995static const char * const rt5677_vad_src[] = {
1996 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1997 "STO3 ADC MIX L"
1998};
1999
2000static SOC_ENUM_SINGLE_DECL(
2001 rt5677_vad_enum, RT5677_VAD_CTRL4,
2002 RT5677_VAD_SRC_SFT, rt5677_vad_src);
2003
2004static const struct snd_kcontrol_new rt5677_vad_src_mux =
2005 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
2006
2007/* Sidetone Source */ /* MX-13 [11:9] */
2008static const char * const rt5677_sidetone_src[] = {
2009 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
2010};
2011
2012static SOC_ENUM_SINGLE_DECL(
2013 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2014 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2015
2016static const struct snd_kcontrol_new rt5677_sidetone_mux =
2017 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2018
2019/* DAC1/2 Source */ /* MX-15 [1:0] */
2020static const char * const rt5677_dac12_src[] = {
2021 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2022};
2023
2024static SOC_ENUM_SINGLE_DECL(
2025 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2026 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2027
2028static const struct snd_kcontrol_new rt5677_dac12_mux =
2029 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2030
2031/* DAC3 Source */ /* MX-15 [5:4] */
2032static const char * const rt5677_dac3_src[] = {
2033 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2034};
2035
2036static SOC_ENUM_SINGLE_DECL(
2037 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2038 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2039
2040static const struct snd_kcontrol_new rt5677_dac3_mux =
2041 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2042
1b7fd76a 2043/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
0e826e86
OC		 2044static const char * const rt5677_pdm_src[] = {
2045 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2046};
2047
2048static SOC_ENUM_SINGLE_DECL(
2049 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2050 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2051
2052static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1b7fd76a 2053 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
0e826e86
OC		 2054
2055static SOC_ENUM_SINGLE_DECL(
2056 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2057 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2058
2059static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1b7fd76a 2060 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
0e826e86
OC		 2061
2062static SOC_ENUM_SINGLE_DECL(
2063 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2064 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2065
2066static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1b7fd76a 2067 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
0e826e86
OC		 2068
2069static SOC_ENUM_SINGLE_DECL(
2070 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2071 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2072
2073static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1b7fd76a 2074 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
0e826e86 2075
d65fd3a4 2076/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
0e826e86
OC		 2077static const char * const rt5677_if12_adc1_src[] = {
2078 "STO1 ADC MIX", "OB01", "VAD ADC"
2079};
2080
2081static SOC_ENUM_SINGLE_DECL(
2082 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2083 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2084
2085static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1b7fd76a 2086 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
0e826e86
OC		 2087
2088static SOC_ENUM_SINGLE_DECL(
2089 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2090 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2091
2092static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1b7fd76a 2093 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
0e826e86
OC		 2094
2095static SOC_ENUM_SINGLE_DECL(
2096 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2097 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2098
2099static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1b7fd76a 2100 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
0e826e86
OC		 2101
2102/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2103static const char * const rt5677_if12_adc2_src[] = {
2104 "STO2 ADC MIX", "OB23"
2105};
2106
2107static SOC_ENUM_SINGLE_DECL(
2108 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2109 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2110
2111static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1b7fd76a 2112 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
0e826e86
OC		 2113
2114static SOC_ENUM_SINGLE_DECL(
2115 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2116 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2117
2118static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1b7fd76a 2119 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
0e826e86
OC		 2120
2121static SOC_ENUM_SINGLE_DECL(
2122 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2123 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2124
2125static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1b7fd76a 2126 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
0e826e86
OC		 2127
2128/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2129static const char * const rt5677_if12_adc3_src[] = {
2130 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2131};
2132
2133static SOC_ENUM_SINGLE_DECL(
2134 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2135 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2136
2137static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1b7fd76a 2138 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
0e826e86
OC		 2139
2140static SOC_ENUM_SINGLE_DECL(
2141 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2142 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2143
2144static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1b7fd76a 2145 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
0e826e86
OC		 2146
2147static SOC_ENUM_SINGLE_DECL(
2148 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2149 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2150
2151static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1b7fd76a 2152 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
0e826e86 2153
d65fd3a4 2154/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
0e826e86
OC		 2155static const char * const rt5677_if12_adc4_src[] = {
2156 "STO4 ADC MIX", "OB67", "OB01"
2157};
2158
2159static SOC_ENUM_SINGLE_DECL(
2160 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2161 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2162
2163static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1b7fd76a 2164 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
0e826e86
OC		 2165
2166static SOC_ENUM_SINGLE_DECL(
2167 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2168 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2169
2170static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1b7fd76a 2171 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
0e826e86
OC		 2172
2173static SOC_ENUM_SINGLE_DECL(
2174 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2175 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2176
2177static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1b7fd76a 2178 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
0e826e86 2179
d65fd3a4 2180/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
0e826e86
OC		 2181static const char * const rt5677_if34_adc_src[] = {
2182 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2183 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2184};
2185
2186static SOC_ENUM_SINGLE_DECL(
2187 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2188 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2189
2190static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1b7fd76a 2191 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
0e826e86
OC		 2192
2193static SOC_ENUM_SINGLE_DECL(
2194 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2195 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2196
2197static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1b7fd76a 2198 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
0e826e86 2199
e6f6ebc1
OC		 2200/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2201static const char * const rt5677_if12_adc_swap_src[] = {
2202 "L/R", "R/L", "L/L", "R/R"
2203};
2204
2205static SOC_ENUM_SINGLE_DECL(
2206 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2207 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2208
2209static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2210 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2211
2212static SOC_ENUM_SINGLE_DECL(
2213 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2214 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2215
2216static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2217 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2218
2219static SOC_ENUM_SINGLE_DECL(
2220 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2221 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2222
2223static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2224 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2225
2226static SOC_ENUM_SINGLE_DECL(
2227 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2228 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2229
2230static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2231 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2232
2233static SOC_ENUM_SINGLE_DECL(
2234 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2235 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2236
2237static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2238 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2239
2240static SOC_ENUM_SINGLE_DECL(
2241 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2242 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2243
2244static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2245 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2246
2247static SOC_ENUM_SINGLE_DECL(
2248 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2249 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2250
2251static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2252 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2253
2254static SOC_ENUM_SINGLE_DECL(
2255 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2256 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2257
2258static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2259 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2260
d65fd3a4 2261/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
e6f6ebc1
OC		 2262static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2263 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2264 "3/1/2/4", "3/4/1/2"
2265};
2266
2267static SOC_ENUM_SINGLE_DECL(
2268 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2269 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2270
2271static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2272 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2273
2274/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2275static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2276 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2277 "2/3/1/4", "3/4/1/2"
2278};
2279
2280static SOC_ENUM_SINGLE_DECL(
2281 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2282 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2283
2284static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2285 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2286
91159eca
OC		 2287/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2288 MX-3F[14:12][10:8][6:4][2:0]
2289 MX-43[14:12][10:8][6:4][2:0]
2290 MX-44[14:12][10:8][6:4][2:0] */
2291static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2292 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2293};
2294
2295static SOC_ENUM_SINGLE_DECL(
2296 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2297 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2298
2299static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2300 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2301
2302static SOC_ENUM_SINGLE_DECL(
2303 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2304 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2305
2306static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2307 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2308
2309static SOC_ENUM_SINGLE_DECL(
2310 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2311 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2312
2313static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2314 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2315
2316static SOC_ENUM_SINGLE_DECL(
2317 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2318 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2319
2320static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2321 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2322
2323static SOC_ENUM_SINGLE_DECL(
2324 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2325 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2326
2327static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2328 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2329
2330static SOC_ENUM_SINGLE_DECL(
2331 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2332 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2333
2334static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2335 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2336
2337static SOC_ENUM_SINGLE_DECL(
2338 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2339 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2340
2341static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2342 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2343
2344static SOC_ENUM_SINGLE_DECL(
2345 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2346 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2347
2348static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2349 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2350
2351static SOC_ENUM_SINGLE_DECL(
2352 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2353 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2354
2355static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2356 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2357
2358static SOC_ENUM_SINGLE_DECL(
2359 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2360 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2361
2362static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2363 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2364
2365static SOC_ENUM_SINGLE_DECL(
2366 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2367 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2368
2369static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2370 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2371
2372static SOC_ENUM_SINGLE_DECL(
2373 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2374 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2375
2376static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2377 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2378
2379static SOC_ENUM_SINGLE_DECL(
2380 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2381 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2382
2383static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2384 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2385
2386static SOC_ENUM_SINGLE_DECL(
2387 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2388 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2389
2390static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2391 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2392
2393static SOC_ENUM_SINGLE_DECL(
2394 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2395 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2396
2397static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2398 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2399
2400static SOC_ENUM_SINGLE_DECL(
2401 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2402 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2403
2404static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2405 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2406
0e826e86
OC		 2407static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2408 struct snd_kcontrol *kcontrol, int event)
2409{
46f20872 2410 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2411 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2412
2413 switch (event) {
2414 case SND_SOC_DAPM_POST_PMU:
2415 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2416 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2417 break;
2418
2419 case SND_SOC_DAPM_PRE_PMD:
2420 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2421 RT5677_PWR_BST1_P, 0);
2422 break;
2423
2424 default:
2425 return 0;
2426 }
2427
2428 return 0;
2429}
2430
2431static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2432 struct snd_kcontrol *kcontrol, int event)
2433{
46f20872 2434 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2435 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2436
2437 switch (event) {
2438 case SND_SOC_DAPM_POST_PMU:
2439 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2440 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2441 break;
2442
2443 case SND_SOC_DAPM_PRE_PMD:
2444 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2445 RT5677_PWR_BST2_P, 0);
2446 break;
2447
2448 default:
2449 return 0;
2450 }
2451
2452 return 0;
2453}
2454
2455static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2456 struct snd_kcontrol *kcontrol, int event)
2457{
46f20872 2458 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2459 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2460
2461 switch (event) {
bdfbf255 2462 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2463 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2464 break;
2465
2466 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2467 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2468 break;
bdfbf255 2469
0e826e86
OC		 2470 default:
2471 return 0;
2472 }
2473
2474 return 0;
2475}
2476
2477static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2478 struct snd_kcontrol *kcontrol, int event)
2479{
46f20872 2480 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2481 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2482
2483 switch (event) {
bdfbf255 2484 case SND_SOC_DAPM_PRE_PMU:
0e826e86 2485 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
bdfbf255
OC		 2486 break;
2487
2488 case SND_SOC_DAPM_POST_PMU:
0e826e86
OC		 2489 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2490 break;
bdfbf255 2491
0e826e86
OC		 2492 default:
2493 return 0;
2494 }
2495
2496 return 0;
2497}
2498
2499static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2500 struct snd_kcontrol *kcontrol, int event)
2501{
46f20872 2502 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
0e826e86
OC		 2503 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2504
2505 switch (event) {
2506 case SND_SOC_DAPM_POST_PMU:
2507 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2508 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2509 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2510 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2511 break;
f58c3b91
OC		 2512
2513 case SND_SOC_DAPM_PRE_PMD:
2514 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2515 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2516 RT5677_PWR_CLK_MB, 0);
2517 break;
2518
0e826e86
OC		 2519 default:
2520 return 0;
2521 }
2522
2523 return 0;
2524}
2525
e6f6ebc1
OC		 2526static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2527 struct snd_kcontrol *kcontrol, int event)
2528{
46f20872 2529 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e6f6ebc1
OC		 2530 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2531 unsigned int value;
2532
2533 switch (event) {
2534 case SND_SOC_DAPM_PRE_PMU:
2535 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2536 if (value & RT5677_IF1_ADC_CTRL_MASK)
2537 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2538 RT5677_IF1_ADC_MODE_MASK,
2539 RT5677_IF1_ADC_MODE_TDM);
2540 break;
2541
2542 default:
2543 return 0;
2544 }
2545
2546 return 0;
2547}
2548
2549static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2550 struct snd_kcontrol *kcontrol, int event)
2551{
46f20872 2552 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e6f6ebc1
OC		 2553 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2554 unsigned int value;
2555
2556 switch (event) {
2557 case SND_SOC_DAPM_PRE_PMU:
2558 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2559 if (value & RT5677_IF2_ADC_CTRL_MASK)
2560 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2561 RT5677_IF2_ADC_MODE_MASK,
2562 RT5677_IF2_ADC_MODE_TDM);
2563 break;
2564
2565 default:
2566 return 0;
2567 }
2568
2569 return 0;
2570}
2571
683996cb
OC		 2572static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2573 struct snd_kcontrol *kcontrol, int event)
2574{
46f20872 2575 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
683996cb
OC		 2576 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2577
2578 switch (event) {
2579 case SND_SOC_DAPM_POST_PMU:
6b43c2eb 2580 if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON &&
683996cb
OC		 2581 !rt5677->is_vref_slow) {
2582 mdelay(20);
2583 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2584 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2585 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2586 rt5677->is_vref_slow = true;
2587 }
2588 break;
2589
2590 default:
2591 return 0;
2592 }
2593
2594 return 0;
2595}
2596
c22d7666
OC		 2597static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
2598 struct snd_kcontrol *kcontrol, int event)
2599{
2600 switch (event) {
2601 case SND_SOC_DAPM_POST_PMU:
2602 msleep(50);
2603 break;
2604
2605 default:
2606 return 0;
2607 }
2608
2609 return 0;
2610}
2611
0e826e86
OC		 2612static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2613 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
bdfbf255
OC		 2614 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2615 SND_SOC_DAPM_POST_PMU),
0e826e86 2616 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
bdfbf255
OC		 2617 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2618 SND_SOC_DAPM_POST_PMU),
0e826e86 2619
5a8c7c26
OC		 2620 /* ASRC */
2621 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2622 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2623 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2624 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2625 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2626 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2627 0),
2628 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2629 0),
2630 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2631 0),
2632 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2633 0),
2634 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2635 0),
2636 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2637 0),
2638 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2639 0),
2640 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2641 0),
2642 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2643 0),
2644 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2645 0),
2646 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2647 0),
2648 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2649 0),
2650 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2651 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2652 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2653 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2654 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2655 0),
2656 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2657 0),
2658
0e826e86
OC		 2659 /* Input Side */
2660 /* micbias */
3d0c03d9 2661 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
f58c3b91
OC		 2662 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2663 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 2664
2665 /* Input Lines */
2666 SND_SOC_DAPM_INPUT("DMIC L1"),
2667 SND_SOC_DAPM_INPUT("DMIC R1"),
2668 SND_SOC_DAPM_INPUT("DMIC L2"),
2669 SND_SOC_DAPM_INPUT("DMIC R2"),
2670 SND_SOC_DAPM_INPUT("DMIC L3"),
2671 SND_SOC_DAPM_INPUT("DMIC R3"),
2672 SND_SOC_DAPM_INPUT("DMIC L4"),
2673 SND_SOC_DAPM_INPUT("DMIC R4"),
2674
2675 SND_SOC_DAPM_INPUT("IN1P"),
2676 SND_SOC_DAPM_INPUT("IN1N"),
2677 SND_SOC_DAPM_INPUT("IN2P"),
2678 SND_SOC_DAPM_INPUT("IN2N"),
2679
2680 SND_SOC_DAPM_INPUT("Haptic Generator"),
2681
2d15d974
BL		 2682 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2683 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2684 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2685 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2686
2687 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2688 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2689 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2690 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2691 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2692 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2693 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2694 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
0e826e86
OC		 2695
2696 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2697 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2698
2699 /* Boost */
2700 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2701 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2702 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2703 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2704 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2705 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2706
2707 /* ADCs */
2708 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2709 0, 0),
2710 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2711 0, 0),
2712 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2713
2714 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2715 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2716 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2717 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2718 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2719 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2720 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2721 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2722
2723 /* ADC Mux */
2724 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2725 &rt5677_sto1_dmic_mux),
2726 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2727 &rt5677_sto1_adc1_mux),
2728 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2729 &rt5677_sto1_adc2_mux),
2730 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2731 &rt5677_sto2_dmic_mux),
2732 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2733 &rt5677_sto2_adc1_mux),
2734 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2735 &rt5677_sto2_adc2_mux),
2736 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2737 &rt5677_sto2_adc_lr_mux),
2738 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2739 &rt5677_sto3_dmic_mux),
2740 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2741 &rt5677_sto3_adc1_mux),
2742 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2743 &rt5677_sto3_adc2_mux),
2744 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2745 &rt5677_sto4_dmic_mux),
2746 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2747 &rt5677_sto4_adc1_mux),
2748 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2749 &rt5677_sto4_adc2_mux),
2750 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2751 &rt5677_mono_dmic_l_mux),
2752 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2753 &rt5677_mono_dmic_r_mux),
2754 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2755 &rt5677_mono_adc2_l_mux),
2756 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2757 &rt5677_mono_adc1_l_mux),
2758 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2759 &rt5677_mono_adc1_r_mux),
2760 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2761 &rt5677_mono_adc2_r_mux),
2762
2763 /* ADC Mixer */
2764 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2765 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2766 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2767 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2768 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2769 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2770 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2771 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2772 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2773 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2774 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2775 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2776 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2777 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2778 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2779 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2780 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2781 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2782 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2783 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2784 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2785 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2786 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2787 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2788 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2789 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2790 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2791 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2792 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2793 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2794 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2795 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2796
2797 /* ADC PGA */
2798 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2800 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2801 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2802 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2803 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2804 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2805 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2806 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2807 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2808 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2809 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2810 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2811 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
e6f6ebc1
OC		 2812 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2813 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
0e826e86
OC		 2814
2815 /* DSP */
2816 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5677_ib9_src_mux),
2818 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5677_ib8_src_mux),
2820 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5677_ib7_src_mux),
2822 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5677_ib6_src_mux),
2824 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5677_ib45_src_mux),
2826 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2827 &rt5677_ib23_src_mux),
2828 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2829 &rt5677_ib01_src_mux),
2830 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2831 &rt5677_ib45_bypass_src_mux),
2832 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2833 &rt5677_ib23_bypass_src_mux),
2834 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2835 &rt5677_ib01_bypass_src_mux),
2836 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2837 &rt5677_ob23_bypass_src_mux),
2838 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2839 &rt5677_ob01_bypass_src_mux),
2840
2841 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2842 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2843
2844 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2850
2851 /* Digital Interface */
2852 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2853 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2856 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2858 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2859 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2860 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2870
2871 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2872 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2886 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2887 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2888 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2889
2890 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2891 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2892 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2893 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2894 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2895 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2896 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2897 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2898
2899 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2900 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2907
2908 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2909 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2912 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2913 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2914 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2915 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2916 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2917 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2918 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2919 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2920 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2921 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2922 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2923 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2924 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2925 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2926
2927 /* Digital Interface Select */
2928 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2929 &rt5677_if1_adc1_mux),
2930 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5677_if1_adc2_mux),
2932 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2933 &rt5677_if1_adc3_mux),
2934 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2935 &rt5677_if1_adc4_mux),
e6f6ebc1
OC		 2936 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2937 &rt5677_if1_adc1_swap_mux),
2938 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2939 &rt5677_if1_adc2_swap_mux),
2940 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5677_if1_adc3_swap_mux),
2942 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5677_if1_adc4_swap_mux),
2944 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2946 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2947 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2948 &rt5677_if2_adc1_mux),
2949 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5677_if2_adc2_mux),
2951 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2952 &rt5677_if2_adc3_mux),
2953 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2954 &rt5677_if2_adc4_mux),
e6f6ebc1
OC		 2955 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2956 &rt5677_if2_adc1_swap_mux),
2957 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2958 &rt5677_if2_adc2_swap_mux),
2959 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5677_if2_adc3_swap_mux),
2961 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5677_if2_adc4_swap_mux),
2963 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2965 SND_SOC_DAPM_PRE_PMU),
0e826e86
OC		 2966 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2967 &rt5677_if3_adc_mux),
2968 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2969 &rt5677_if4_adc_mux),
2970 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2971 &rt5677_slb_adc1_mux),
2972 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2973 &rt5677_slb_adc2_mux),
2974 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2975 &rt5677_slb_adc3_mux),
2976 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2977 &rt5677_slb_adc4_mux),
2978
91159eca
OC		 2979 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5677_if1_dac0_tdm_sel_mux),
2981 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2982 &rt5677_if1_dac1_tdm_sel_mux),
2983 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5677_if1_dac2_tdm_sel_mux),
2985 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5677_if1_dac3_tdm_sel_mux),
2987 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2988 &rt5677_if1_dac4_tdm_sel_mux),
2989 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5677_if1_dac5_tdm_sel_mux),
2991 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5677_if1_dac6_tdm_sel_mux),
2993 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5677_if1_dac7_tdm_sel_mux),
2995
2996 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2997 &rt5677_if2_dac0_tdm_sel_mux),
2998 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2999 &rt5677_if2_dac1_tdm_sel_mux),
3000 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
3001 &rt5677_if2_dac2_tdm_sel_mux),
3002 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
3003 &rt5677_if2_dac3_tdm_sel_mux),
3004 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
3005 &rt5677_if2_dac4_tdm_sel_mux),
3006 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
3007 &rt5677_if2_dac5_tdm_sel_mux),
3008 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
3009 &rt5677_if2_dac6_tdm_sel_mux),
3010 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
3011 &rt5677_if2_dac7_tdm_sel_mux),
3012
0e826e86
OC		 3013 /* Audio Interface */
3014 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3015 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3016 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3017 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3018 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3019 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3020 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3021 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3022 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3023 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3024
3025 /* Sidetone Mux */
3026 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3027 &rt5677_sidetone_mux),
90bdbb46
OC		 3028 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3029 RT5677_ST_EN_SFT, 0, NULL, 0),
3030
0e826e86
OC		 3031 /* VAD Mux*/
3032 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3033 &rt5677_vad_src_mux),
3034
3035 /* Tensilica DSP */
3036 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3037 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3038 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3039 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3040 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3041 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3042 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3043 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3044 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3045 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3046 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3047 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3048 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3049
3050 /* Output Side */
d65fd3a4 3051 /* DAC mixer before sound effect */
0e826e86
OC		 3052 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3053 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3054 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3055 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3056 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3057
3058 /* DAC Mux */
3059 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3060 &rt5677_dac1_mux),
3061 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3062 &rt5677_adda1_mux),
3063 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3064 &rt5677_dac12_mux),
3065 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3066 &rt5677_dac3_mux),
3067
3068 /* DAC2 channel Mux */
3069 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3070 &rt5677_dac2_l_mux),
3071 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3072 &rt5677_dac2_r_mux),
3073
3074 /* DAC3 channel Mux */
3075 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3076 &rt5677_dac3_l_mux),
3077 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3078 &rt5677_dac3_r_mux),
3079
3080 /* DAC4 channel Mux */
3081 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3082 &rt5677_dac4_l_mux),
3083 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3084 &rt5677_dac4_r_mux),
3085
3086 /* DAC Mixer */
3087 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
c22d7666
OC		 3088 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
3089 SND_SOC_DAPM_POST_PMU),
6800b5ba 3090 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
c22d7666
OC		 3091 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
3092 SND_SOC_DAPM_POST_PMU),
6800b5ba 3093 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
c22d7666
OC		 3094 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
3095 SND_SOC_DAPM_POST_PMU),
6800b5ba 3096 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
c22d7666
OC		 3097 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
3098 SND_SOC_DAPM_POST_PMU),
6800b5ba 3099 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
c22d7666
OC		 3100 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
3101 SND_SOC_DAPM_POST_PMU),
6800b5ba 3102 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
c22d7666
OC		 3103 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
3104 SND_SOC_DAPM_POST_PMU),
6800b5ba 3105 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
c22d7666
OC		 3106 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
3107 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 3108
3109 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3110 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3111 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3112 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3113 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3114 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3115 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3116 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3117 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3118 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3119 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3120 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3121 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3122 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3123 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3124 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3125 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3126 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3127 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3128 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3129
3130 /* DACs */
3131 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3132 RT5677_PWR_DAC1_BIT, 0),
3133 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3134 RT5677_PWR_DAC2_BIT, 0),
3135 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3136 RT5677_PWR_DAC3_BIT, 0),
3137
3138 /* PDM */
3139 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3140 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3141 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3142 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3143
3144 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3145 1, &rt5677_pdm1_l_mux),
3146 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3147 1, &rt5677_pdm1_r_mux),
3148 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3149 1, &rt5677_pdm2_l_mux),
3150 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3151 1, &rt5677_pdm2_r_mux),
3152
683996cb 3153 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
0e826e86 3154 0, NULL, 0),
683996cb 3155 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
0e826e86 3156 0, NULL, 0),
683996cb 3157 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
0e826e86
OC		 3158 0, NULL, 0),
3159
683996cb
OC		 3160 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3161 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3162 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3163 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3164 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3165 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3166
0e826e86
OC		 3167 /* Output Lines */
3168 SND_SOC_DAPM_OUTPUT("LOUT1"),
3169 SND_SOC_DAPM_OUTPUT("LOUT2"),
3170 SND_SOC_DAPM_OUTPUT("LOUT3"),
3171 SND_SOC_DAPM_OUTPUT("PDM1L"),
3172 SND_SOC_DAPM_OUTPUT("PDM1R"),
3173 SND_SOC_DAPM_OUTPUT("PDM2L"),
3174 SND_SOC_DAPM_OUTPUT("PDM2R"),
683996cb
OC		 3175
3176 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
0e826e86
OC		 3177};
3178
3179static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
5220f7fb
OC		 3180 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3181 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3182 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3183 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3184 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3185 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
5a8c7c26
OC		 3186 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3187 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3188 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3189 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3190
3191 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3192 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3193 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3194 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3195 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3196 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3197 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3198 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3199 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3200 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3201 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3202 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3203 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3204
0e826e86
OC		 3205 { "DMIC1", NULL, "DMIC L1" },
3206 { "DMIC1", NULL, "DMIC R1" },
3207 { "DMIC2", NULL, "DMIC L2" },
3208 { "DMIC2", NULL, "DMIC R2" },
3209 { "DMIC3", NULL, "DMIC L3" },
3210 { "DMIC3", NULL, "DMIC R3" },
3211 { "DMIC4", NULL, "DMIC L4" },
3212 { "DMIC4", NULL, "DMIC R4" },
3213
3214 { "DMIC L1", NULL, "DMIC CLK" },
3215 { "DMIC R1", NULL, "DMIC CLK" },
3216 { "DMIC L2", NULL, "DMIC CLK" },
3217 { "DMIC R2", NULL, "DMIC CLK" },
3218 { "DMIC L3", NULL, "DMIC CLK" },
3219 { "DMIC R3", NULL, "DMIC CLK" },
3220 { "DMIC L4", NULL, "DMIC CLK" },
3221 { "DMIC R4", NULL, "DMIC CLK" },
3222
2d15d974
BL		 3223 { "DMIC L1", NULL, "DMIC1 power" },
3224 { "DMIC R1", NULL, "DMIC1 power" },
3225 { "DMIC L3", NULL, "DMIC3 power" },
3226 { "DMIC R3", NULL, "DMIC3 power" },
3227 { "DMIC L4", NULL, "DMIC4 power" },
3228 { "DMIC R4", NULL, "DMIC4 power" },
3229
0e826e86
OC		 3230 { "BST1", NULL, "IN1P" },
3231 { "BST1", NULL, "IN1N" },
3232 { "BST2", NULL, "IN2P" },
3233 { "BST2", NULL, "IN2N" },
3234
22e51345
BL		 3235 { "IN1P", NULL, "MICBIAS1" },
3236 { "IN1N", NULL, "MICBIAS1" },
3237 { "IN2P", NULL, "MICBIAS1" },
3238 { "IN2N", NULL, "MICBIAS1" },
0e826e86
OC		 3239
3240 { "ADC 1", NULL, "BST1" },
3241 { "ADC 1", NULL, "ADC 1 power" },
3242 { "ADC 1", NULL, "ADC1 clock" },
3243 { "ADC 2", NULL, "BST2" },
3244 { "ADC 2", NULL, "ADC 2 power" },
3245 { "ADC 2", NULL, "ADC2 clock" },
3246
3247 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3248 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3249 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3250 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3251
3252 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3253 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3254 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3255 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3256
3257 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3258 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3259 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3260 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3261
3262 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3263 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3264 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3265 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3266
3267 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3268 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3269 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3270 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3271
3272 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3273 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3274 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3275 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3276
3277 { "ADC 1_2", NULL, "ADC 1" },
3278 { "ADC 1_2", NULL, "ADC 2" },
3279
3280 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3281 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3282 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3283
3284 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3285 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3286 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3287
3288 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3289 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3290 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3291
3292 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3293 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3294 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3295
3296 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3297 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3298 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3299
3300 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3301 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3302 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3303
3304 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3305 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3306 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3307
3308 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3309 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3310 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3311
3312 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3313 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3314 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3315
3316 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3317 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3318 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3319
3320 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3321 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3322 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3323
3324 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3325 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3326 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3327
3328 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3329 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3330 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3331 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3332
3333 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3334 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
0e826e86
OC		 3335 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3336 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3337 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3338
3339 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3340 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3341
3342 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3343 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3344 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3345 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3346
3347 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3348 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3349
3350 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3351 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3352
3353 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3354 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
0e826e86
OC		 3355 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3356 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3357 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3358
3359 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3360 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3361
3362 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3363 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3364 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3365 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3366
3367 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3368 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
0e826e86
OC		 3369 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3370 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3371 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3372
3373 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3374 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3375
3376 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3377 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3378 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3379 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3380
3381 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3382 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
0e826e86
OC		 3383 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3384 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3385 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3386
3387 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3388 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3389
3390 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3391 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3392 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3393 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3394
3395 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3396 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3397 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3398 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3399
3400 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3401 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3402
3403 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3404 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3405 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3406 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3407 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3408
3409 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3410 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3411 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3412
3413 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3414 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3415
3416 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3417 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3418 { "IF1 ADC3 Mux", "OB45", "OB45" },
3419
3420 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3421 { "IF1 ADC4 Mux", "OB67", "OB67" },
3422 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3423
e6f6ebc1
OC		 3424 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3425 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3426 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3427 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3428
3429 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3430 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3431 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3432 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3433
3434 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3435 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3436 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3437 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3438
3439 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3440 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3441 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3442 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3443
3444 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3445 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3446 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3447 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3448
3449 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3450 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3451 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3452 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3453 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3454 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3455 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3456 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3457
0e826e86 3458 { "AIF1TX", NULL, "I2S1" },
e6f6ebc1 3459 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
0e826e86
OC		 3460
3461 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3462 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3463 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3464
3465 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3466 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3467
3468 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3469 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3470 { "IF2 ADC3 Mux", "OB45", "OB45" },
3471
3472 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3473 { "IF2 ADC4 Mux", "OB67", "OB67" },
3474 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3475
e6f6ebc1
OC		 3476 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3477 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3478 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3479 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3480
3481 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3482 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3483 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3484 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3485
3486 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3487 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3488 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3489 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3490
3491 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3492 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3493 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3494 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3495
3496 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3497 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3498 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3499 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3500
3501 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3502 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3503 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3504 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3505 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3506 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3507 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3508 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3509
0e826e86 3510 { "AIF2TX", NULL, "I2S2" },
e6f6ebc1 3511 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
0e826e86
OC		 3512
3513 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3514 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3515 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3516 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3517 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3518 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3519 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3520 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3521
3522 { "AIF3TX", NULL, "I2S3" },
3523 { "AIF3TX", NULL, "IF3 ADC Mux" },
3524
3525 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3526 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3527 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3528 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3529 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3530 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3531 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3532 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3533
3534 { "AIF4TX", NULL, "I2S4" },
3535 { "AIF4TX", NULL, "IF4 ADC Mux" },
3536
3537 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3538 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3539 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3540
3541 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3542 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3543
3544 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3545 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3546 { "SLB ADC3 Mux", "OB45", "OB45" },
3547
3548 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3549 { "SLB ADC4 Mux", "OB67", "OB67" },
3550 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3551
3552 { "SLBTX", NULL, "SLB" },
3553 { "SLBTX", NULL, "SLB ADC1 Mux" },
3554 { "SLBTX", NULL, "SLB ADC2 Mux" },
3555 { "SLBTX", NULL, "SLB ADC3 Mux" },
3556 { "SLBTX", NULL, "SLB ADC4 Mux" },
3557
3558 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3559 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3560 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3561 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3562 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3563
3564 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3565 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3566
3567 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3568 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3569 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3570 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3571 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3572 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3573
3574 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3575 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3576
3577 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3578 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3579 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3580 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3581 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3582
3583 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3584 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3585
70068776
OC		 3586 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3587 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
0e826e86
OC		 3588 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3589 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3590 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3591 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3592 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3593 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3594
70068776
OC		 3595 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3596 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
0e826e86
OC		 3597 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3598 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3599 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3600 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3601 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3602 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3603
3604 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3605 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3606 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3607 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3608 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3609 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3610
3611 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3612 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3613 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3614 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3615 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3616 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3617 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3618
3619 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3620 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3621 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3622 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3623 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3624 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3625 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3626
3627 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3628 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3629 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3630 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3631 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3632 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3633 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3634
3635 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3636 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3637 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3638 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3639 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3640 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3641 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3642
3643 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3644 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3645 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3646 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3647 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3648 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3649 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3650
3651 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3652 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3653 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3654 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3655 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3656 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3657 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3658
3659 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3660 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3661 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3662 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3663 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3664 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3665 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3666
3667 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3668 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3669 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3670 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3671
3672 { "OutBound2", NULL, "OB23 Bypass Mux" },
3673 { "OutBound3", NULL, "OB23 Bypass Mux" },
3674 { "OutBound4", NULL, "OB4 MIX" },
3675 { "OutBound5", NULL, "OB5 MIX" },
3676 { "OutBound6", NULL, "OB6 MIX" },
3677 { "OutBound7", NULL, "OB7 MIX" },
3678
3679 { "OB45", NULL, "OutBound4" },
3680 { "OB45", NULL, "OutBound5" },
3681 { "OB67", NULL, "OutBound6" },
3682 { "OB67", NULL, "OutBound7" },
3683
3684 { "IF1 DAC0", NULL, "AIF1RX" },
3685 { "IF1 DAC1", NULL, "AIF1RX" },
3686 { "IF1 DAC2", NULL, "AIF1RX" },
3687 { "IF1 DAC3", NULL, "AIF1RX" },
3688 { "IF1 DAC4", NULL, "AIF1RX" },
3689 { "IF1 DAC5", NULL, "AIF1RX" },
3690 { "IF1 DAC6", NULL, "AIF1RX" },
3691 { "IF1 DAC7", NULL, "AIF1RX" },
3692 { "IF1 DAC0", NULL, "I2S1" },
3693 { "IF1 DAC1", NULL, "I2S1" },
3694 { "IF1 DAC2", NULL, "I2S1" },
3695 { "IF1 DAC3", NULL, "I2S1" },
3696 { "IF1 DAC4", NULL, "I2S1" },
3697 { "IF1 DAC5", NULL, "I2S1" },
3698 { "IF1 DAC6", NULL, "I2S1" },
3699 { "IF1 DAC7", NULL, "I2S1" },
3700
91159eca
OC		 3701 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3702 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3703 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3704 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3705 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3706 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3707 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3708 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3709
3710 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3711 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3712 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3713 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3714 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3715 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3716 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3717 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3718
3719 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3720 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3721 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3722 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3723 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3724 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3725 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3726 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3727
3728 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3729 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3730 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3731 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3732 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3733 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3734 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3735 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3736
3737 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3738 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3739 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3740 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3741 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3742 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3743 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3744 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3745
3746 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3747 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3748 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3749 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3750 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3751 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3752 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3753 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3754
3755 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3756 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3757 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3758 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3759 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3760 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3761 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3762 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3763
3764 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3765 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3766 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3767 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3768 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3769 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3770 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3771 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3772
3773 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3774 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3775 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3776 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3777 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3778 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3779 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3780 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
0e826e86
OC		 3781
3782 { "IF2 DAC0", NULL, "AIF2RX" },
3783 { "IF2 DAC1", NULL, "AIF2RX" },
3784 { "IF2 DAC2", NULL, "AIF2RX" },
3785 { "IF2 DAC3", NULL, "AIF2RX" },
3786 { "IF2 DAC4", NULL, "AIF2RX" },
3787 { "IF2 DAC5", NULL, "AIF2RX" },
3788 { "IF2 DAC6", NULL, "AIF2RX" },
3789 { "IF2 DAC7", NULL, "AIF2RX" },
3790 { "IF2 DAC0", NULL, "I2S2" },
3791 { "IF2 DAC1", NULL, "I2S2" },
3792 { "IF2 DAC2", NULL, "I2S2" },
3793 { "IF2 DAC3", NULL, "I2S2" },
3794 { "IF2 DAC4", NULL, "I2S2" },
3795 { "IF2 DAC5", NULL, "I2S2" },
3796 { "IF2 DAC6", NULL, "I2S2" },
3797 { "IF2 DAC7", NULL, "I2S2" },
3798
91159eca
OC		 3799 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3800 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3801 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3802 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3803 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3804 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3805 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3806 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3807
3808 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3809 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3810 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3811 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3812 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3813 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3814 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3815 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3816
3817 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3818 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3819 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3820 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3821 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3822 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3823 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3824 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3825
3826 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3827 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3828 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3829 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3830 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3831 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3832 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3833 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3834
3835 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3836 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3837 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3838 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3839 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3840 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3841 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3842 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3843
3844 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3845 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3846 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3847 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3848 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3849 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3850 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3851 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3852
3853 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3854 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3855 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3856 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3857 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3858 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3859 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3860 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3861
3862 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3863 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3864 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3865 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3866 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3867 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3868 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3869 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3870
3871 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3872 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3873 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3874 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3875 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3876 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3877 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3878 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
0e826e86
OC		 3879
3880 { "IF3 DAC", NULL, "AIF3RX" },
3881 { "IF3 DAC", NULL, "I2S3" },
3882
3883 { "IF4 DAC", NULL, "AIF4RX" },
3884 { "IF4 DAC", NULL, "I2S4" },
3885
3886 { "IF3 DAC L", NULL, "IF3 DAC" },
3887 { "IF3 DAC R", NULL, "IF3 DAC" },
3888
3889 { "IF4 DAC L", NULL, "IF4 DAC" },
3890 { "IF4 DAC R", NULL, "IF4 DAC" },
3891
3892 { "SLB DAC0", NULL, "SLBRX" },
3893 { "SLB DAC1", NULL, "SLBRX" },
3894 { "SLB DAC2", NULL, "SLBRX" },
3895 { "SLB DAC3", NULL, "SLBRX" },
3896 { "SLB DAC4", NULL, "SLBRX" },
3897 { "SLB DAC5", NULL, "SLBRX" },
3898 { "SLB DAC6", NULL, "SLBRX" },
3899 { "SLB DAC7", NULL, "SLBRX" },
3900 { "SLB DAC0", NULL, "SLB" },
3901 { "SLB DAC1", NULL, "SLB" },
3902 { "SLB DAC2", NULL, "SLB" },
3903 { "SLB DAC3", NULL, "SLB" },
3904 { "SLB DAC4", NULL, "SLB" },
3905 { "SLB DAC5", NULL, "SLB" },
3906 { "SLB DAC6", NULL, "SLB" },
3907 { "SLB DAC7", NULL, "SLB" },
3908
3909 { "SLB DAC01", NULL, "SLB DAC0" },
3910 { "SLB DAC01", NULL, "SLB DAC1" },
3911 { "SLB DAC23", NULL, "SLB DAC2" },
3912 { "SLB DAC23", NULL, "SLB DAC3" },
3913 { "SLB DAC45", NULL, "SLB DAC4" },
3914 { "SLB DAC45", NULL, "SLB DAC5" },
3915 { "SLB DAC67", NULL, "SLB DAC6" },
3916 { "SLB DAC67", NULL, "SLB DAC7" },
3917
3918 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3919 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3920 { "ADDA1 Mux", "OB 67", "OB67" },
3921
3922 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3923 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3924 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3925 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3926 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3927 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3928
3929 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3930 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3931 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3932 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
0e826e86
OC		 3933
3934 { "DAC1 FS", NULL, "DAC1 MIXL" },
3935 { "DAC1 FS", NULL, "DAC1 MIXR" },
3936
70068776
OC		 3937 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3938 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
0e826e86
OC		 3939 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3940 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3941 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3942 { "DAC2 L Mux", "OB 2", "OutBound2" },
3943
70068776
OC		 3944 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3945 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
0e826e86
OC		 3946 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3947 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3948 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3949 { "DAC2 R Mux", "OB 3", "OutBound3" },
3950 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3951 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3952
70068776
OC		 3953 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3954 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
0e826e86
OC		 3955 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3956 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3957 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3958 { "DAC3 L Mux", "OB 4", "OutBound4" },
3959
70068776
OC		 3960 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3961 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
0e826e86
OC		 3962 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3963 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3964 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3965 { "DAC3 R Mux", "OB 5", "OutBound5" },
3966
70068776
OC		 3967 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3968 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
0e826e86
OC		 3969 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3970 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3971 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3972 { "DAC4 L Mux", "OB 6", "OutBound6" },
3973
70068776
OC		 3974 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3975 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
0e826e86
OC		 3976 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3977 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3978 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3979 { "DAC4 R Mux", "OB 7", "OutBound7" },
3980
3981 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3982 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3983 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3984 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3985 { "Sidetone Mux", "ADC1", "ADC 1" },
3986 { "Sidetone Mux", "ADC2", "ADC 2" },
90bdbb46 3987 { "Sidetone Mux", NULL, "Sidetone Power" },
0e826e86
OC		 3988
3989 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3990 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3991 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3992 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3993 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3994 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3995 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3996 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3997 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3998 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
38d595e2 3999 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4000
4001 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
4002 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
4003 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
4004 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
6800b5ba 4005 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
38d595e2 4006 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4007 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
4008 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
4009 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
4010 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
6800b5ba 4011 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
38d595e2 4012 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4013
4014 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4015 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4016 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
4017 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 4018 { "DD1 MIXL", NULL, "dac mono3 left filter" },
38d595e2 4019 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4020 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4021 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4022 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4023 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
6800b5ba 4024 { "DD1 MIXR", NULL, "dac mono3 right filter" },
38d595e2 4025 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4026
4027 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4028 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4029 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4030 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 4031 { "DD2 MIXL", NULL, "dac mono4 left filter" },
38d595e2 4032 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4033 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4034 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4035 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4036 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
6800b5ba 4037 { "DD2 MIXR", NULL, "dac mono4 right filter" },
38d595e2 4038 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
0e826e86
OC		 4039
4040 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4041 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4042 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4043 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4044 { "DD1 MIX", NULL, "DD1 MIXL" },
4045 { "DD1 MIX", NULL, "DD1 MIXR" },
4046 { "DD2 MIX", NULL, "DD2 MIXL" },
4047 { "DD2 MIX", NULL, "DD2 MIXR" },
4048
4049 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4050 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4051 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4052 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4053
4054 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4055 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4056 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4057 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4058
4059 { "DAC 1", NULL, "DAC12 SRC Mux" },
0e826e86 4060 { "DAC 2", NULL, "DAC12 SRC Mux" },
0e826e86 4061 { "DAC 3", NULL, "DAC3 SRC Mux" },
0e826e86
OC		 4062
4063 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4064 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4065 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4066 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4067 { "PDM1 L Mux", NULL, "PDM1 Power" },
4068 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4069 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4070 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4071 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4072 { "PDM1 R Mux", NULL, "PDM1 Power" },
4073 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4074 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4075 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4076 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4077 { "PDM2 L Mux", NULL, "PDM2 Power" },
4078 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4079 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4080 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4081 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4082 { "PDM2 R Mux", NULL, "PDM2 Power" },
4083
4084 { "LOUT1 amp", NULL, "DAC 1" },
4085 { "LOUT2 amp", NULL, "DAC 2" },
4086 { "LOUT3 amp", NULL, "DAC 3" },
4087
683996cb
OC		 4088 { "LOUT1 vref", NULL, "LOUT1 amp" },
4089 { "LOUT2 vref", NULL, "LOUT2 amp" },
4090 { "LOUT3 vref", NULL, "LOUT3 amp" },
4091
4092 { "LOUT1", NULL, "LOUT1 vref" },
4093 { "LOUT2", NULL, "LOUT2 vref" },
4094 { "LOUT3", NULL, "LOUT3 vref" },
0e826e86
OC		 4095
4096 { "PDM1L", NULL, "PDM1 L Mux" },
4097 { "PDM1R", NULL, "PDM1 R Mux" },
4098 { "PDM2L", NULL, "PDM2 L Mux" },
4099 { "PDM2R", NULL, "PDM2 R Mux" },
4100};
4101
2d15d974
BL		 4102static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4103 { "DMIC L2", NULL, "DMIC1 power" },
4104 { "DMIC R2", NULL, "DMIC1 power" },
4105};
4106
4107static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4108 { "DMIC L2", NULL, "DMIC2 power" },
4109 { "DMIC R2", NULL, "DMIC2 power" },
4110};
4111
0e826e86
OC		 4112static int rt5677_hw_params(struct snd_pcm_substream *substream,
4113 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4114{
4115 struct snd_soc_codec *codec = dai->codec;
4116 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4117 unsigned int val_len = 0, val_clk, mask_clk;
4118 int pre_div, bclk_ms, frame_size;
4119
4120 rt5677->lrck[dai->id] = params_rate(params);
30f14b43 4121 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86 4122 if (pre_div < 0) {
8a4bd60a
AP		 4123 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4124 rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86
OC		 4125 return -EINVAL;
4126 }
4127 frame_size = snd_soc_params_to_frame_size(params);
4128 if (frame_size < 0) {
4129 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4130 return -EINVAL;
4131 }
4132 bclk_ms = frame_size > 32;
4133 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4134
4135 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4136 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4137 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4138 bclk_ms, pre_div, dai->id);
4139
4140 switch (params_width(params)) {
4141 case 16:
4142 break;
4143 case 20:
4144 val_len |= RT5677_I2S_DL_20;
4145 break;
4146 case 24:
4147 val_len |= RT5677_I2S_DL_24;
4148 break;
4149 case 8:
4150 val_len |= RT5677_I2S_DL_8;
4151 break;
4152 default:
4153 return -EINVAL;
4154 }
4155
4156 switch (dai->id) {
4157 case RT5677_AIF1:
4158 mask_clk = RT5677_I2S_PD1_MASK;
4159 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4160 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4161 RT5677_I2S_DL_MASK, val_len);
4162 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4163 mask_clk, val_clk);
4164 break;
4165 case RT5677_AIF2:
4166 mask_clk = RT5677_I2S_PD2_MASK;
4167 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4168 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4169 RT5677_I2S_DL_MASK, val_len);
4170 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4171 mask_clk, val_clk);
4172 break;
4173 case RT5677_AIF3:
4174 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4175 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4176 pre_div << RT5677_I2S_PD3_SFT;
4177 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4178 RT5677_I2S_DL_MASK, val_len);
4179 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4180 mask_clk, val_clk);
4181 break;
4182 case RT5677_AIF4:
4183 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4184 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4185 pre_div << RT5677_I2S_PD4_SFT;
4186 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4187 RT5677_I2S_DL_MASK, val_len);
4188 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4189 mask_clk, val_clk);
4190 break;
4191 default:
4192 break;
4193 }
4194
4195 return 0;
4196}
4197
4198static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4199{
4200 struct snd_soc_codec *codec = dai->codec;
4201 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4202 unsigned int reg_val = 0;
4203
4204 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4205 case SND_SOC_DAIFMT_CBM_CFM:
4206 rt5677->master[dai->id] = 1;
4207 break;
4208 case SND_SOC_DAIFMT_CBS_CFS:
4209 reg_val |= RT5677_I2S_MS_S;
4210 rt5677->master[dai->id] = 0;
4211 break;
4212 default:
4213 return -EINVAL;
4214 }
4215
4216 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4217 case SND_SOC_DAIFMT_NB_NF:
4218 break;
4219 case SND_SOC_DAIFMT_IB_NF:
4220 reg_val |= RT5677_I2S_BP_INV;
4221 break;
4222 default:
4223 return -EINVAL;
4224 }
4225
4226 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4227 case SND_SOC_DAIFMT_I2S:
4228 break;
4229 case SND_SOC_DAIFMT_LEFT_J:
4230 reg_val |= RT5677_I2S_DF_LEFT;
4231 break;
4232 case SND_SOC_DAIFMT_DSP_A:
4233 reg_val |= RT5677_I2S_DF_PCM_A;
4234 break;
4235 case SND_SOC_DAIFMT_DSP_B:
4236 reg_val |= RT5677_I2S_DF_PCM_B;
4237 break;
4238 default:
4239 return -EINVAL;
4240 }
4241
4242 switch (dai->id) {
4243 case RT5677_AIF1:
4244 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4245 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4246 RT5677_I2S_DF_MASK, reg_val);
4247 break;
4248 case RT5677_AIF2:
4249 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4250 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4251 RT5677_I2S_DF_MASK, reg_val);
4252 break;
4253 case RT5677_AIF3:
4254 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4255 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4256 RT5677_I2S_DF_MASK, reg_val);
4257 break;
4258 case RT5677_AIF4:
4259 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4260 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4261 RT5677_I2S_DF_MASK, reg_val);
4262 break;
4263 default:
4264 break;
4265 }
4266
4267
4268 return 0;
4269}
4270
4271static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4272 int clk_id, unsigned int freq, int dir)
4273{
4274 struct snd_soc_codec *codec = dai->codec;
4275 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4276 unsigned int reg_val = 0;
4277
4278 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4279 return 0;
4280
4281 switch (clk_id) {
4282 case RT5677_SCLK_S_MCLK:
4283 reg_val |= RT5677_SCLK_SRC_MCLK;
4284 break;
4285 case RT5677_SCLK_S_PLL1:
4286 reg_val |= RT5677_SCLK_SRC_PLL1;
4287 break;
4288 case RT5677_SCLK_S_RCCLK:
4289 reg_val |= RT5677_SCLK_SRC_RCCLK;
4290 break;
4291 default:
4292 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4293 return -EINVAL;
4294 }
4295 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4296 RT5677_SCLK_SRC_MASK, reg_val);
4297 rt5677->sysclk = freq;
4298 rt5677->sysclk_src = clk_id;
4299
4300 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4301
4302 return 0;
4303}
4304
4305/**
4306 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4307 * @freq_in: external clock provided to codec.
4308 * @freq_out: target clock which codec works on.
4309 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4310 *
4311 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4312 *
4313 * Returns 0 for success or negative error code.
4314 */
4315static int rt5677_pll_calc(const unsigned int freq_in,
099d334e 4316 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
0e826e86 4317{
099d334e 4318 if (RT5677_PLL_INP_MIN > freq_in)
0e826e86
OC		 4319 return -EINVAL;
4320
099d334e 4321 return rl6231_pll_calc(freq_in, freq_out, pll_code);
0e826e86
OC		 4322}
4323
4324static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4325 unsigned int freq_in, unsigned int freq_out)
4326{
4327 struct snd_soc_codec *codec = dai->codec;
4328 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
099d334e 4329 struct rl6231_pll_code pll_code;
0e826e86
OC		 4330 int ret;
4331
4332 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4333 freq_out == rt5677->pll_out)
4334 return 0;
4335
4336 if (!freq_in || !freq_out) {
4337 dev_dbg(codec->dev, "PLL disabled\n");
4338
4339 rt5677->pll_in = 0;
4340 rt5677->pll_out = 0;
4341 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4342 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4343 return 0;
4344 }
4345
4346 switch (source) {
4347 case RT5677_PLL1_S_MCLK:
4348 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4349 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4350 break;
4351 case RT5677_PLL1_S_BCLK1:
4352 case RT5677_PLL1_S_BCLK2:
4353 case RT5677_PLL1_S_BCLK3:
4354 case RT5677_PLL1_S_BCLK4:
4355 switch (dai->id) {
4356 case RT5677_AIF1:
4357 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4358 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4359 break;
4360 case RT5677_AIF2:
4361 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4362 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4363 break;
4364 case RT5677_AIF3:
4365 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4366 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4367 break;
4368 case RT5677_AIF4:
4369 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4370 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4371 break;
4372 default:
4373 break;
4374 }
4375 break;
4376 default:
4377 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4378 return -EINVAL;
4379 }
4380
4381 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4382 if (ret < 0) {
4383 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4384 return ret;
4385 }
4386
099d334e
AL		 4387 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4388 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4389 pll_code.n_code, pll_code.k_code);
0e826e86
OC		 4390
4391 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
099d334e 4392 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
0e826e86
OC		 4393 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4394 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4395 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4396
4397 rt5677->pll_in = freq_in;
4398 rt5677->pll_out = freq_out;
4399 rt5677->pll_src = source;
4400
4401 return 0;
4402}
4403
48561afe
OC		 4404static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4405 unsigned int rx_mask, int slots, int slot_width)
4406{
4407 struct snd_soc_codec *codec = dai->codec;
e4b7e6a8 4408 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
9913b9f5 4409 unsigned int val = 0, slot_width_25 = 0;
48561afe
OC		 4410
4411 if (rx_mask || tx_mask)
4412 val |= (1 << 12);
4413
4414 switch (slots) {
4415 case 4:
4416 val |= (1 << 10);
4417 break;
4418 case 6:
4419 val |= (2 << 10);
4420 break;
4421 case 8:
4422 val |= (3 << 10);
4423 break;
4424 case 2:
4425 default:
4426 break;
4427 }
4428
4429 switch (slot_width) {
4430 case 20:
4431 val |= (1 << 8);
4432 break;
9913b9f5
OC		 4433 case 25:
4434 slot_width_25 = 0x8080;
48561afe
OC		 4435 case 24:
4436 val |= (2 << 8);
4437 break;
4438 case 32:
4439 val |= (3 << 8);
4440 break;
4441 case 16:
4442 default:
4443 break;
4444 }
4445
4446 switch (dai->id) {
4447 case RT5677_AIF1:
e4b7e6a8
OC		 4448 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4449 val);
9913b9f5
OC		 4450 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4451 slot_width_25);
48561afe
OC		 4452 break;
4453 case RT5677_AIF2:
e4b7e6a8
OC		 4454 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4455 val);
9913b9f5
OC		 4456 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4457 slot_width_25);
48561afe
OC		 4458 break;
4459 default:
4460 break;
4461 }
4462
4463 return 0;
4464}
4465
0e826e86
OC		 4466static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4467 enum snd_soc_bias_level level)
4468{
4469 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4470
4471 switch (level) {
4472 case SND_SOC_BIAS_ON:
4473 break;
4474
4475 case SND_SOC_BIAS_PREPARE:
6b43c2eb 4476 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
af48f1d0
OC		 4477 rt5677_set_dsp_vad(codec, false);
4478
0e826e86
OC		 4479 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4480 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4481 0x0055);
4482 regmap_update_bits(rt5677->regmap,
4483 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4484 0x0f00, 0x0f00);
4485 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
683996cb 4486 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
0e826e86
OC		 4487 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4488 RT5677_PWR_BG | RT5677_PWR_VREF2,
4489 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4490 RT5677_PWR_BG | RT5677_PWR_VREF2);
683996cb 4491 rt5677->is_vref_slow = false;
0e826e86
OC		 4492 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4493 RT5677_PWR_CORE, RT5677_PWR_CORE);
4494 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4495 0x1, 0x1);
4496 }
4497 break;
4498
4499 case SND_SOC_BIAS_STANDBY:
4500 break;
4501
4502 case SND_SOC_BIAS_OFF:
4503 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4504 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4505 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
f18803a3 4506 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
0e826e86
OC		 4507 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4508 regmap_update_bits(rt5677->regmap,
4509 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
af48f1d0
OC		 4510
4511 if (rt5677->dsp_vad_en)
4512 rt5677_set_dsp_vad(codec, true);
0e826e86
OC		 4513 break;
4514
4515 default:
4516 break;
4517 }
0e826e86
OC		 4518
4519 return 0;
4520}
4521
44caf764
OC		 4522#ifdef CONFIG_GPIOLIB
4523static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4524{
4525 return container_of(chip, struct rt5677_priv, gpio_chip);
4526}
4527
4528static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4529{
4530 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4531
4532 switch (offset) {
4533 case RT5677_GPIO1 ... RT5677_GPIO5:
4534 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4535 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4536 break;
4537
4538 case RT5677_GPIO6:
4539 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4540 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4541 break;
4542
4543 default:
4544 break;
4545 }
4546}
4547
4548static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4549 unsigned offset, int value)
4550{
4551 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4552
4553 switch (offset) {
4554 case RT5677_GPIO1 ... RT5677_GPIO5:
4555 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4556 0x3 << (offset * 3 + 1),
4557 (0x2 | !!value) << (offset * 3 + 1));
4558 break;
4559
4560 case RT5677_GPIO6:
4561 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4562 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4563 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4564 break;
4565
4566 default:
4567 break;
4568 }
4569
4570 return 0;
4571}
4572
4573static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4574{
4575 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4576 int value, ret;
4577
4578 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4579 if (ret < 0)
4580 return ret;
4581
4582 return (value & (0x1 << offset)) >> offset;
4583}
4584
4585static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4586{
4587 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4588
4589 switch (offset) {
4590 case RT5677_GPIO1 ... RT5677_GPIO5:
4591 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4592 0x1 << (offset * 3 + 2), 0x0);
4593 break;
4594
4595 case RT5677_GPIO6:
4596 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4597 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4598 break;
4599
4600 default:
4601 break;
4602 }
4603
4604 return 0;
4605}
4606
40eb90a1
AP		 4607/** Configures the gpio as
4608 * 0 - floating
4609 * 1 - pull down
4610 * 2 - pull up
4611 */
4612static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4613 int value)
4614{
4615 int shift;
4616
4617 switch (offset) {
4618 case RT5677_GPIO1 ... RT5677_GPIO2:
4619 shift = 2 * (1 - offset);
4620 regmap_update_bits(rt5677->regmap,
4621 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4622 0x3 << shift,
4623 (value & 0x3) << shift);
4624 break;
4625
4626 case RT5677_GPIO3 ... RT5677_GPIO6:
4627 shift = 2 * (9 - offset);
4628 regmap_update_bits(rt5677->regmap,
4629 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4630 0x3 << shift,
4631 (value & 0x3) << shift);
4632 break;
4633
4634 default:
4635 break;
4636 }
4637}
4638
5e3363ad
OC		 4639static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4640{
4641 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4642 struct regmap_irq_chip_data *data = rt5677->irq_data;
4643 int irq;
4644
4645 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4646 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4647 (rt5677->pdata.jd1_gpio == 2 &&
4648 offset == RT5677_GPIO2) ||
4649 (rt5677->pdata.jd1_gpio == 3 &&
4650 offset == RT5677_GPIO3)) {
4651 irq = RT5677_IRQ_JD1;
4652 } else {
4653 return -ENXIO;
4654 }
4655 }
4656
4657 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4658 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4659 (rt5677->pdata.jd2_gpio == 2 &&
4660 offset == RT5677_GPIO5) ||
4661 (rt5677->pdata.jd2_gpio == 3 &&
4662 offset == RT5677_GPIO6)) {
4663 irq = RT5677_IRQ_JD2;
4664 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4665 offset == RT5677_GPIO4) ||
4666 (rt5677->pdata.jd3_gpio == 2 &&
4667 offset == RT5677_GPIO5) ||
4668 (rt5677->pdata.jd3_gpio == 3 &&
4669 offset == RT5677_GPIO6)) {
4670 irq = RT5677_IRQ_JD3;
4671 } else {
4672 return -ENXIO;
4673 }
4674 }
4675
4676 return regmap_irq_get_virq(data, irq);
4677}
4678
44caf764
OC		 4679static struct gpio_chip rt5677_template_chip = {
4680 .label = "rt5677",
4681 .owner = THIS_MODULE,
4682 .direction_output = rt5677_gpio_direction_out,
4683 .set = rt5677_gpio_set,
4684 .direction_input = rt5677_gpio_direction_in,
4685 .get = rt5677_gpio_get,
5e3363ad 4686 .to_irq = rt5677_to_irq,
44caf764
OC		 4687 .can_sleep = 1,
4688};
4689
4690static void rt5677_init_gpio(struct i2c_client *i2c)
4691{
4692 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4693 int ret;
4694
4695 rt5677->gpio_chip = rt5677_template_chip;
4696 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
58383c78 4697 rt5677->gpio_chip.parent = &i2c->dev;
44caf764
OC		 4698 rt5677->gpio_chip.base = -1;
4699
4700 ret = gpiochip_add(&rt5677->gpio_chip);
4701 if (ret != 0)
4702 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4703}
4704
4705static void rt5677_free_gpio(struct i2c_client *i2c)
4706{
4707 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
44caf764 4708
5d5e63af 4709 gpiochip_remove(&rt5677->gpio_chip);
44caf764
OC		 4710}
4711#else
45b6e1d3
AP		 4712static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4713 int value)
4714{
4715}
4716
44caf764
OC		 4717static void rt5677_init_gpio(struct i2c_client *i2c)
4718{
4719}
4720
4721static void rt5677_free_gpio(struct i2c_client *i2c)
4722{
4723}
4724#endif
4725
0e826e86
OC		 4726static int rt5677_probe(struct snd_soc_codec *codec)
4727{
6b43c2eb 4728 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
0e826e86 4729 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
40eb90a1 4730 int i;
0e826e86
OC		 4731
4732 rt5677->codec = codec;
4733
2d15d974 4734 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
6b43c2eb 4735 snd_soc_dapm_add_routes(dapm,
2d15d974
BL		 4736 rt5677_dmic2_clk_2,
4737 ARRAY_SIZE(rt5677_dmic2_clk_2));
4738 } else { /*use dmic1 clock by default*/
6b43c2eb 4739 snd_soc_dapm_add_routes(dapm,
2d15d974
BL		 4740 rt5677_dmic2_clk_1,
4741 ARRAY_SIZE(rt5677_dmic2_clk_1));
4742 }
4743
bd1204cb 4744 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
0e826e86
OC		 4745
4746 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4747 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4748
40eb90a1
AP		 4749 for (i = 0; i < RT5677_GPIO_NUM; i++)
4750 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4751
5e3363ad
OC		 4752 if (rt5677->irq_data) {
4753 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4754 0x8000);
4755 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4756 0x0008);
4757
4758 if (rt5677->pdata.jd1_gpio)
4759 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4760 RT5677_SEL_GPIO_JD1_MASK,
4761 rt5677->pdata.jd1_gpio <<
4762 RT5677_SEL_GPIO_JD1_SFT);
4763
4764 if (rt5677->pdata.jd2_gpio)
4765 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4766 RT5677_SEL_GPIO_JD2_MASK,
4767 rt5677->pdata.jd2_gpio <<
4768 RT5677_SEL_GPIO_JD2_SFT);
4769
4770 if (rt5677->pdata.jd3_gpio)
4771 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4772 RT5677_SEL_GPIO_JD3_MASK,
4773 rt5677->pdata.jd3_gpio <<
4774 RT5677_SEL_GPIO_JD3_SFT);
4775 }
4776
af48f1d0 4777 mutex_init(&rt5677->dsp_cmd_lock);
6fe17da0 4778 mutex_init(&rt5677->dsp_pri_lock);
af48f1d0 4779
0e826e86
OC		 4780 return 0;
4781}
4782
4783static int rt5677_remove(struct snd_soc_codec *codec)
4784{
4785 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4786
4787 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
f285f161 4788 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
cdab0d4e 4789 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
0e826e86
OC		 4790
4791 return 0;
4792}
4793
4794#ifdef CONFIG_PM
4795static int rt5677_suspend(struct snd_soc_codec *codec)
4796{
4797 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4798
af48f1d0
OC		 4799 if (!rt5677->dsp_vad_en) {
4800 regcache_cache_only(rt5677->regmap, true);
4801 regcache_mark_dirty(rt5677->regmap);
af48f1d0 4802
f285f161 4803 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
cdab0d4e 4804 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
cbca4076 4805 }
0e826e86
OC		 4806
4807 return 0;
4808}
4809
4810static int rt5677_resume(struct snd_soc_codec *codec)
4811{
4812 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4813
af48f1d0 4814 if (!rt5677->dsp_vad_en) {
1aa844cd
BZ		 4815 rt5677->pll_src = 0;
4816 rt5677->pll_in = 0;
4817 rt5677->pll_out = 0;
f285f161 4818 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
cdab0d4e 4819 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
efd901ee 4820 if (rt5677->pow_ldo2 || rt5677->reset_pin)
cbca4076 4821 msleep(10);
cbca4076 4822
af48f1d0
OC		 4823 regcache_cache_only(rt5677->regmap, false);
4824 regcache_sync(rt5677->regmap);
4825 }
0e826e86
OC		 4826
4827 return 0;
4828}
4829#else
4830#define rt5677_suspend NULL
4831#define rt5677_resume NULL
4832#endif
4833
19ba484d
OC		 4834static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4835{
4836 struct i2c_client *client = context;
4837 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4838
6fe17da0
OC		 4839 if (rt5677->is_dsp_mode) {
4840 if (reg > 0xff) {
4841 mutex_lock(&rt5677->dsp_pri_lock);
4842 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4843 reg & 0xff);
4844 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4845 mutex_unlock(&rt5677->dsp_pri_lock);
4846 } else {
4847 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4848 }
4849 } else {
19ba484d 4850 regmap_read(rt5677->regmap_physical, reg, val);
6fe17da0 4851 }
19ba484d
OC		 4852
4853 return 0;
4854}
4855
4856static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4857{
4858 struct i2c_client *client = context;
4859 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4860
6fe17da0
OC		 4861 if (rt5677->is_dsp_mode) {
4862 if (reg > 0xff) {
4863 mutex_lock(&rt5677->dsp_pri_lock);
4864 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4865 reg & 0xff);
4866 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4867 val);
4868 mutex_unlock(&rt5677->dsp_pri_lock);
4869 } else {
4870 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4871 }
4872 } else {
19ba484d 4873 regmap_write(rt5677->regmap_physical, reg, val);
6fe17da0 4874 }
19ba484d
OC		 4875
4876 return 0;
4877}
4878
0e826e86
OC		 4879#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4880#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4881 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4882
64793047 4883static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
0e826e86
OC		 4884 .hw_params = rt5677_hw_params,
4885 .set_fmt = rt5677_set_dai_fmt,
4886 .set_sysclk = rt5677_set_dai_sysclk,
4887 .set_pll = rt5677_set_dai_pll,
48561afe 4888 .set_tdm_slot = rt5677_set_tdm_slot,
0e826e86
OC		 4889};
4890
4891static struct snd_soc_dai_driver rt5677_dai[] = {
4892 {
4893 .name = "rt5677-aif1",
4894 .id = RT5677_AIF1,
4895 .playback = {
4896 .stream_name = "AIF1 Playback",
4897 .channels_min = 1,
4898 .channels_max = 2,
4899 .rates = RT5677_STEREO_RATES,
4900 .formats = RT5677_FORMATS,
4901 },
4902 .capture = {
4903 .stream_name = "AIF1 Capture",
4904 .channels_min = 1,
4905 .channels_max = 2,
4906 .rates = RT5677_STEREO_RATES,
4907 .formats = RT5677_FORMATS,
4908 },
4909 .ops = &rt5677_aif_dai_ops,
4910 },
4911 {
4912 .name = "rt5677-aif2",
4913 .id = RT5677_AIF2,
4914 .playback = {
4915 .stream_name = "AIF2 Playback",
4916 .channels_min = 1,
4917 .channels_max = 2,
4918 .rates = RT5677_STEREO_RATES,
4919 .formats = RT5677_FORMATS,
4920 },
4921 .capture = {
4922 .stream_name = "AIF2 Capture",
4923 .channels_min = 1,
4924 .channels_max = 2,
4925 .rates = RT5677_STEREO_RATES,
4926 .formats = RT5677_FORMATS,
4927 },
4928 .ops = &rt5677_aif_dai_ops,
4929 },
4930 {
4931 .name = "rt5677-aif3",
4932 .id = RT5677_AIF3,
4933 .playback = {
4934 .stream_name = "AIF3 Playback",
4935 .channels_min = 1,
4936 .channels_max = 2,
4937 .rates = RT5677_STEREO_RATES,
4938 .formats = RT5677_FORMATS,
4939 },
4940 .capture = {
4941 .stream_name = "AIF3 Capture",
4942 .channels_min = 1,
4943 .channels_max = 2,
4944 .rates = RT5677_STEREO_RATES,
4945 .formats = RT5677_FORMATS,
4946 },
4947 .ops = &rt5677_aif_dai_ops,
4948 },
4949 {
4950 .name = "rt5677-aif4",
4951 .id = RT5677_AIF4,
4952 .playback = {
4953 .stream_name = "AIF4 Playback",
4954 .channels_min = 1,
4955 .channels_max = 2,
4956 .rates = RT5677_STEREO_RATES,
4957 .formats = RT5677_FORMATS,
4958 },
4959 .capture = {
4960 .stream_name = "AIF4 Capture",
4961 .channels_min = 1,
4962 .channels_max = 2,
4963 .rates = RT5677_STEREO_RATES,
4964 .formats = RT5677_FORMATS,
4965 },
4966 .ops = &rt5677_aif_dai_ops,
4967 },
4968 {
4969 .name = "rt5677-slimbus",
4970 .id = RT5677_AIF5,
4971 .playback = {
4972 .stream_name = "SLIMBus Playback",
4973 .channels_min = 1,
4974 .channels_max = 2,
4975 .rates = RT5677_STEREO_RATES,
4976 .formats = RT5677_FORMATS,
4977 },
4978 .capture = {
4979 .stream_name = "SLIMBus Capture",
4980 .channels_min = 1,
4981 .channels_max = 2,
4982 .rates = RT5677_STEREO_RATES,
4983 .formats = RT5677_FORMATS,
4984 },
4985 .ops = &rt5677_aif_dai_ops,
4986 },
4987};
4988
4989static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4990 .probe = rt5677_probe,
4991 .remove = rt5677_remove,
4992 .suspend = rt5677_suspend,
4993 .resume = rt5677_resume,
4994 .set_bias_level = rt5677_set_bias_level,
4995 .idle_bias_off = true,
4996 .controls = rt5677_snd_controls,
4997 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4998 .dapm_widgets = rt5677_dapm_widgets,
4999 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
5000 .dapm_routes = rt5677_dapm_routes,
5001 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
5002};
5003
19ba484d
OC		 5004static const struct regmap_config rt5677_regmap_physical = {
5005 .name = "physical",
5006 .reg_bits = 8,
5007 .val_bits = 16,
5008
6fe17da0
OC		 5009 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5010 RT5677_PR_SPACING),
19ba484d
OC		 5011 .readable_reg = rt5677_readable_register,
5012
5013 .cache_type = REGCACHE_NONE,
6fe17da0
OC		 5014 .ranges = rt5677_ranges,
5015 .num_ranges = ARRAY_SIZE(rt5677_ranges),
19ba484d
OC		 5016};
5017
0e826e86
OC		 5018static const struct regmap_config rt5677_regmap = {
5019 .reg_bits = 8,
5020 .val_bits = 16,
5021
5022 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5023 RT5677_PR_SPACING),
5024
5025 .volatile_reg = rt5677_volatile_register,
5026 .readable_reg = rt5677_readable_register,
19ba484d
OC		 5027 .reg_read = rt5677_read,
5028 .reg_write = rt5677_write,
0e826e86
OC		 5029
5030 .cache_type = REGCACHE_RBTREE,
5031 .reg_defaults = rt5677_reg,
5032 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5033 .ranges = rt5677_ranges,
5034 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5035};
5036
5037static const struct i2c_device_id rt5677_i2c_id[] = {
ab1f7095
OC		 5038 { "rt5677", RT5677 },
5039 { "rt5676", RT5676 },
0e826e86
OC		 5040 { }
5041};
5042MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
5043
9bfde721
BZ		 5044static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5045 struct device *dev)
f9f6a592 5046{
9bfde721
BZ		 5047 rt5677->pdata.in1_diff = device_property_read_bool(dev,
5048 "realtek,in1-differential");
5049 rt5677->pdata.in2_diff = device_property_read_bool(dev,
5050 "realtek,in2-differential");
5051 rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5052 "realtek,lout1-differential");
5053 rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5054 "realtek,lout2-differential");
5055 rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5056 "realtek,lout3-differential");
5057
5058 device_property_read_u8_array(dev, "realtek,gpio-config",
5059 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5060
5061 device_property_read_u32(dev, "realtek,jd1-gpio",
5062 &rt5677->pdata.jd1_gpio);
5063 device_property_read_u32(dev, "realtek,jd2-gpio",
5064 &rt5677->pdata.jd2_gpio);
5065 device_property_read_u32(dev, "realtek,jd3-gpio",
5066 &rt5677->pdata.jd3_gpio);
f9f6a592
AP		 5067}
5068
5e3363ad
OC		 5069static struct regmap_irq rt5677_irqs[] = {
5070 [RT5677_IRQ_JD1] = {
5071 .reg_offset = 0,
5072 .mask = RT5677_EN_IRQ_GPIO_JD1,
5073 },
5074 [RT5677_IRQ_JD2] = {
5075 .reg_offset = 0,
5076 .mask = RT5677_EN_IRQ_GPIO_JD2,
5077 },
5078 [RT5677_IRQ_JD3] = {
5079 .reg_offset = 0,
5080 .mask = RT5677_EN_IRQ_GPIO_JD3,
5081 },
5082};
5083
5084static struct regmap_irq_chip rt5677_irq_chip = {
5085 .name = "rt5677",
5086 .irqs = rt5677_irqs,
5087 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5088
5089 .num_regs = 1,
5090 .status_base = RT5677_IRQ_CTRL1,
5091 .mask_base = RT5677_IRQ_CTRL1,
5092 .mask_invert = 1,
5093};
5094
35d40d10 5095static int rt5677_init_irq(struct i2c_client *i2c)
5e3363ad
OC		 5096{
5097 int ret;
5098 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5099
5100 if (!rt5677->pdata.jd1_gpio &&
5101 !rt5677->pdata.jd2_gpio &&
5102 !rt5677->pdata.jd3_gpio)
5103 return 0;
5104
5105 if (!i2c->irq) {
5106 dev_err(&i2c->dev, "No interrupt specified\n");
5107 return -EINVAL;
5108 }
5109
5110 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5111 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5112 &rt5677_irq_chip, &rt5677->irq_data);
5113
5114 if (ret != 0) {
5115 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5116 return ret;
5117 }
5118
5119 return 0;
5120}
5121
35d40d10 5122static void rt5677_free_irq(struct i2c_client *i2c)
5e3363ad
OC		 5123{
5124 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5125
5126 if (rt5677->irq_data)
5127 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5128}
5129
0e826e86
OC		 5130static int rt5677_i2c_probe(struct i2c_client *i2c,
5131 const struct i2c_device_id *id)
5132{
5133 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5134 struct rt5677_priv *rt5677;
5135 int ret;
5136 unsigned int val;
5137
5138 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5139 GFP_KERNEL);
5140 if (rt5677 == NULL)
5141 return -ENOMEM;
5142
5143 i2c_set_clientdata(i2c, rt5677);
5144
ab1f7095
OC		 5145 rt5677->type = id->driver_data;
5146
0e826e86
OC		 5147 if (pdata)
5148 rt5677->pdata = *pdata;
9bfde721
BZ		 5149 else
5150 rt5677_read_device_properties(rt5677, &i2c->dev);
0e826e86 5151
efd901ee
BZ		 5152 /* pow-ldo2 and reset are optional. The codec pins may be statically
5153 * connected on the board without gpios. If the gpio device property
5154 * isn't specified, devm_gpiod_get_optional returns NULL.
5155 */
5156 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5157 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5158 if (IS_ERR(rt5677->pow_ldo2)) {
5159 ret = PTR_ERR(rt5677->pow_ldo2);
5160 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
f8163c86 5161 return ret;
b3b10e99 5162 }
efd901ee 5163 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
cdab0d4e 5164 "realtek,reset", GPIOD_OUT_LOW);
efd901ee
BZ		 5165 if (IS_ERR(rt5677->reset_pin)) {
5166 ret = PTR_ERR(rt5677->reset_pin);
5167 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
f8163c86 5168 return ret;
b3b10e99
AP		 5169 }
5170
efd901ee 5171 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
f9f6a592
AP		 5172 /* Wait a while until I2C bus becomes available. The datasheet
5173 * does not specify the exact we should wait but startup
5174 * sequence mentiones at least a few milliseconds.
5175 */
5176 msleep(10);
5177 }
5178
19ba484d
OC		 5179 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5180 &rt5677_regmap_physical);
5181 if (IS_ERR(rt5677->regmap_physical)) {
5182 ret = PTR_ERR(rt5677->regmap_physical);
5183 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5184 ret);
5185 return ret;
5186 }
5187
5188 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
0e826e86
OC		 5189 if (IS_ERR(rt5677->regmap)) {
5190 ret = PTR_ERR(rt5677->regmap);
5191 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5192 ret);
5193 return ret;
5194 }
5195
5196 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5197 if (val != RT5677_DEVICE_ID) {
5198 dev_err(&i2c->dev,
aa0bcc5c 5199 "Device with ID register %#x is not rt5677\n", val);
0e826e86
OC		 5200 return -ENODEV;
5201 }
5202
5203 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5204
5205 ret = regmap_register_patch(rt5677->regmap, init_list,
5206 ARRAY_SIZE(init_list));
5207 if (ret != 0)
5208 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5209
5210 if (rt5677->pdata.in1_diff)
5211 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5212 RT5677_IN_DF1, RT5677_IN_DF1);
5213
5214 if (rt5677->pdata.in2_diff)
5215 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5216 RT5677_IN_DF2, RT5677_IN_DF2);
5217
6f67c380
AP		 5218 if (rt5677->pdata.lout1_diff)
5219 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5220 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5221
5222 if (rt5677->pdata.lout2_diff)
5223 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5224 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5225
5226 if (rt5677->pdata.lout3_diff)
5227 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5228 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5229
2d15d974
BL		 5230 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5231 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5232 RT5677_GPIO5_FUNC_MASK,
5233 RT5677_GPIO5_FUNC_DMIC);
5234 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5235 RT5677_GPIO5_DIR_MASK,
5236 RT5677_GPIO5_DIR_OUT);
5237 }
5238
277880a3
OC		 5239 if (rt5677->pdata.micbias1_vdd_3v3)
5240 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5241 RT5677_MICBIAS1_CTRL_VDD_MASK,
5242 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5243
44caf764 5244 rt5677_init_gpio(i2c);
35d40d10 5245 rt5677_init_irq(i2c);
44caf764 5246
d0bdcb91
AL		 5247 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5248 rt5677_dai, ARRAY_SIZE(rt5677_dai));
0e826e86
OC		 5249}
5250
5251static int rt5677_i2c_remove(struct i2c_client *i2c)
5252{
5253 snd_soc_unregister_codec(&i2c->dev);
35d40d10 5254 rt5677_free_irq(i2c);
44caf764 5255 rt5677_free_gpio(i2c);
0e826e86
OC		 5256
5257 return 0;
5258}
5259
5260static struct i2c_driver rt5677_i2c_driver = {
5261 .driver = {
5262 .name = "rt5677",
0e826e86
OC		 5263 },
5264 .probe = rt5677_i2c_probe,
5265 .remove = rt5677_i2c_remove,
5266 .id_table = rt5677_i2c_id,
5267};
c8cfbec8 5268module_i2c_driver(rt5677_i2c_driver);
0e826e86
OC		 5269
5270MODULE_DESCRIPTION("ASoC RT5677 driver");
5271MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5272MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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