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ASoC: rt5677: Print more information if setting DAI clock failed
[deliverable/linux.git] / sound / soc / codecs / rt5677.c
CommitLineData
0e826e86
OC		 1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
f9f6a592 18#include <linux/of_gpio.h>
0e826e86
OC		 19#include <linux/regmap.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
af48f1d0 23#include <linux/firmware.h>
44caf764 24#include <linux/gpio.h>
0e826e86
OC		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
30f14b43 33#include "rl6231.h"
0e826e86 34#include "rt5677.h"
af48f1d0 35#include "rt5677-spi.h"
0e826e86
OC		 36
37#define RT5677_DEVICE_ID 0x6327
38
39#define RT5677_PR_RANGE_BASE (0xff + 1)
40#define RT5677_PR_SPACING 0x100
41
42#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43
44static const struct regmap_range_cfg rt5677_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
53 .window_len = 0x1,
54 },
55};
56
57static const struct reg_default init_list[] = {
58 {RT5677_PR_BASE + 0x3d, 0x364d},
59 {RT5677_PR_BASE + 0x17, 0x4fc0},
60 {RT5677_PR_BASE + 0x13, 0x0312},
61 {RT5677_PR_BASE + 0x1e, 0x0000},
62 {RT5677_PR_BASE + 0x12, 0x0eaa},
63 {RT5677_PR_BASE + 0x14, 0x018a},
64};
65#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
66
67static const struct reg_default rt5677_reg[] = {
68 {RT5677_RESET , 0x0000},
69 {RT5677_LOUT1 , 0xa800},
70 {RT5677_IN1 , 0x0000},
71 {RT5677_MICBIAS , 0x0000},
72 {RT5677_SLIMBUS_PARAM , 0x0000},
73 {RT5677_SLIMBUS_RX , 0x0000},
74 {RT5677_SLIMBUS_CTRL , 0x0000},
75 {RT5677_SIDETONE_CTRL , 0x000b},
76 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
77 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
78 {RT5677_DAC4_DIG_VOL , 0xafaf},
79 {RT5677_DAC3_DIG_VOL , 0xafaf},
80 {RT5677_DAC1_DIG_VOL , 0xafaf},
81 {RT5677_DAC2_DIG_VOL , 0xafaf},
82 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
83 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
84 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_STO1_2_ADC_BST , 0x0000},
86 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_ADC_BST_CTRL2 , 0x0000},
88 {RT5677_STO3_4_ADC_BST , 0x0000},
89 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_MIXER , 0xd4c0},
92 {RT5677_STO3_ADC_MIXER , 0xd4c0},
93 {RT5677_STO2_ADC_MIXER , 0xd4c0},
94 {RT5677_STO1_ADC_MIXER , 0xd4c0},
95 {RT5677_MONO_ADC_MIXER , 0xd4d1},
96 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
97 {RT5677_STO1_DAC_MIXER , 0xaaaa},
98 {RT5677_MONO_DAC_MIXER , 0xaaaa},
99 {RT5677_DD1_MIXER , 0xaaaa},
100 {RT5677_DD2_MIXER , 0xaaaa},
101 {RT5677_IF3_DATA , 0x0000},
102 {RT5677_IF4_DATA , 0x0000},
103 {RT5677_PDM_OUT_CTRL , 0x8888},
104 {RT5677_PDM_DATA_CTRL1 , 0x0000},
105 {RT5677_PDM_DATA_CTRL2 , 0x0000},
106 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
109 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
112 {RT5677_TDM1_CTRL1 , 0x0300},
113 {RT5677_TDM1_CTRL2 , 0x0000},
114 {RT5677_TDM1_CTRL3 , 0x4000},
115 {RT5677_TDM1_CTRL4 , 0x0123},
116 {RT5677_TDM1_CTRL5 , 0x4567},
117 {RT5677_TDM2_CTRL1 , 0x0300},
118 {RT5677_TDM2_CTRL2 , 0x0000},
119 {RT5677_TDM2_CTRL3 , 0x4000},
120 {RT5677_TDM2_CTRL4 , 0x0123},
121 {RT5677_TDM2_CTRL5 , 0x4567},
122 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
123 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
130 {RT5677_DMIC_CTRL1 , 0x1505},
131 {RT5677_DMIC_CTRL2 , 0x0055},
132 {RT5677_HAP_GENE_CTRL1 , 0x0111},
133 {RT5677_HAP_GENE_CTRL2 , 0x0064},
134 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
135 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
136 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
137 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
138 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
139 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
140 {RT5677_HAP_GENE_CTRL9 , 0xf000},
141 {RT5677_HAP_GENE_CTRL10 , 0x0000},
142 {RT5677_PWR_DIG1 , 0x0000},
143 {RT5677_PWR_DIG2 , 0x0000},
144 {RT5677_PWR_ANLG1 , 0x0055},
145 {RT5677_PWR_ANLG2 , 0x0000},
146 {RT5677_PWR_DSP1 , 0x0001},
147 {RT5677_PWR_DSP_ST , 0x0000},
148 {RT5677_PWR_DSP2 , 0x0000},
149 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
150 {RT5677_PRIV_INDEX , 0x0000},
151 {RT5677_PRIV_DATA , 0x0000},
152 {RT5677_I2S4_SDP , 0x8000},
153 {RT5677_I2S1_SDP , 0x8000},
154 {RT5677_I2S2_SDP , 0x8000},
155 {RT5677_I2S3_SDP , 0x8000},
156 {RT5677_CLK_TREE_CTRL1 , 0x1111},
157 {RT5677_CLK_TREE_CTRL2 , 0x1111},
158 {RT5677_CLK_TREE_CTRL3 , 0x0000},
159 {RT5677_PLL1_CTRL1 , 0x0000},
160 {RT5677_PLL1_CTRL2 , 0x0000},
161 {RT5677_PLL2_CTRL1 , 0x0c60},
162 {RT5677_PLL2_CTRL2 , 0x2000},
163 {RT5677_GLB_CLK1 , 0x0000},
164 {RT5677_GLB_CLK2 , 0x0000},
165 {RT5677_ASRC_1 , 0x0000},
166 {RT5677_ASRC_2 , 0x0000},
167 {RT5677_ASRC_3 , 0x0000},
168 {RT5677_ASRC_4 , 0x0000},
169 {RT5677_ASRC_5 , 0x0000},
170 {RT5677_ASRC_6 , 0x0000},
171 {RT5677_ASRC_7 , 0x0000},
172 {RT5677_ASRC_8 , 0x0000},
173 {RT5677_ASRC_9 , 0x0000},
174 {RT5677_ASRC_10 , 0x0000},
175 {RT5677_ASRC_11 , 0x0000},
176 {RT5677_ASRC_12 , 0x0008},
177 {RT5677_ASRC_13 , 0x0000},
178 {RT5677_ASRC_14 , 0x0000},
179 {RT5677_ASRC_15 , 0x0000},
180 {RT5677_ASRC_16 , 0x0000},
181 {RT5677_ASRC_17 , 0x0000},
182 {RT5677_ASRC_18 , 0x0000},
183 {RT5677_ASRC_19 , 0x0000},
184 {RT5677_ASRC_20 , 0x0000},
185 {RT5677_ASRC_21 , 0x000c},
186 {RT5677_ASRC_22 , 0x0000},
187 {RT5677_ASRC_23 , 0x0000},
188 {RT5677_VAD_CTRL1 , 0x2184},
189 {RT5677_VAD_CTRL2 , 0x010a},
190 {RT5677_VAD_CTRL3 , 0x0aea},
191 {RT5677_VAD_CTRL4 , 0x000c},
192 {RT5677_VAD_CTRL5 , 0x0000},
193 {RT5677_DSP_INB_CTRL1 , 0x0000},
194 {RT5677_DSP_INB_CTRL2 , 0x0000},
195 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
196 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
197 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
200 {RT5677_ADC_EQ_CTRL1 , 0x6000},
201 {RT5677_ADC_EQ_CTRL2 , 0x0000},
202 {RT5677_EQ_CTRL1 , 0xc000},
203 {RT5677_EQ_CTRL2 , 0x0000},
204 {RT5677_EQ_CTRL3 , 0x0000},
205 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
206 {RT5677_JD_CTRL1 , 0x0000},
207 {RT5677_JD_CTRL2 , 0x0000},
208 {RT5677_JD_CTRL3 , 0x0000},
209 {RT5677_IRQ_CTRL1 , 0x0000},
210 {RT5677_IRQ_CTRL2 , 0x0000},
211 {RT5677_GPIO_ST , 0x0000},
212 {RT5677_GPIO_CTRL1 , 0x0000},
213 {RT5677_GPIO_CTRL2 , 0x0000},
214 {RT5677_GPIO_CTRL3 , 0x0000},
215 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
216 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
217 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
218 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
219 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
220 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
221 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
222 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
224 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
225 {RT5677_MB_DRC_CTRL1 , 0x0f20},
226 {RT5677_DRC1_CTRL1 , 0x001f},
227 {RT5677_DRC1_CTRL2 , 0x020c},
228 {RT5677_DRC1_CTRL3 , 0x1f00},
229 {RT5677_DRC1_CTRL4 , 0x0000},
230 {RT5677_DRC1_CTRL5 , 0x0000},
231 {RT5677_DRC1_CTRL6 , 0x0029},
232 {RT5677_DRC2_CTRL1 , 0x001f},
233 {RT5677_DRC2_CTRL2 , 0x020c},
234 {RT5677_DRC2_CTRL3 , 0x1f00},
235 {RT5677_DRC2_CTRL4 , 0x0000},
236 {RT5677_DRC2_CTRL5 , 0x0000},
237 {RT5677_DRC2_CTRL6 , 0x0029},
238 {RT5677_DRC1_HL_CTRL1 , 0x8000},
239 {RT5677_DRC1_HL_CTRL2 , 0x0200},
240 {RT5677_DRC2_HL_CTRL1 , 0x8000},
241 {RT5677_DRC2_HL_CTRL2 , 0x0200},
242 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
243 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
244 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
246 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
247 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
248 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
250 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
251 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
252 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
254 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
255 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
256 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
258 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
259 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
260 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
262 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
263 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
264 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
265 {RT5677_DIG_MISC , 0x0000},
266 {RT5677_GEN_CTRL1 , 0x0000},
267 {RT5677_GEN_CTRL2 , 0x0000},
268 {RT5677_VENDOR_ID , 0x0000},
269 {RT5677_VENDOR_ID1 , 0x10ec},
270 {RT5677_VENDOR_ID2 , 0x6327},
271};
272
273static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
274{
275 int i;
276
277 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
278 if (reg >= rt5677_ranges[i].range_min &&
279 reg <= rt5677_ranges[i].range_max) {
280 return true;
281 }
282 }
283
284 switch (reg) {
285 case RT5677_RESET:
286 case RT5677_SLIMBUS_PARAM:
287 case RT5677_PDM_DATA_CTRL1:
288 case RT5677_PDM_DATA_CTRL2:
289 case RT5677_PDM1_DATA_CTRL4:
290 case RT5677_PDM2_DATA_CTRL4:
291 case RT5677_I2C_MASTER_CTRL1:
292 case RT5677_I2C_MASTER_CTRL7:
293 case RT5677_I2C_MASTER_CTRL8:
294 case RT5677_HAP_GENE_CTRL2:
295 case RT5677_PWR_DSP_ST:
296 case RT5677_PRIV_DATA:
297 case RT5677_PLL1_CTRL2:
298 case RT5677_PLL2_CTRL2:
299 case RT5677_ASRC_22:
300 case RT5677_ASRC_23:
301 case RT5677_VAD_CTRL5:
302 case RT5677_ADC_EQ_CTRL1:
303 case RT5677_EQ_CTRL1:
304 case RT5677_IRQ_CTRL1:
305 case RT5677_IRQ_CTRL2:
306 case RT5677_GPIO_ST:
307 case RT5677_DSP_INB1_SRC_CTRL4:
308 case RT5677_DSP_INB2_SRC_CTRL4:
309 case RT5677_DSP_INB3_SRC_CTRL4:
310 case RT5677_DSP_OUTB1_SRC_CTRL4:
311 case RT5677_DSP_OUTB2_SRC_CTRL4:
312 case RT5677_VENDOR_ID:
313 case RT5677_VENDOR_ID1:
314 case RT5677_VENDOR_ID2:
315 return true;
316 default:
317 return false;
318 }
319}
320
321static bool rt5677_readable_register(struct device *dev, unsigned int reg)
322{
323 int i;
324
325 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
326 if (reg >= rt5677_ranges[i].range_min &&
327 reg <= rt5677_ranges[i].range_max) {
328 return true;
329 }
330 }
331
332 switch (reg) {
333 case RT5677_RESET:
334 case RT5677_LOUT1:
335 case RT5677_IN1:
336 case RT5677_MICBIAS:
337 case RT5677_SLIMBUS_PARAM:
338 case RT5677_SLIMBUS_RX:
339 case RT5677_SLIMBUS_CTRL:
340 case RT5677_SIDETONE_CTRL:
341 case RT5677_ANA_DAC1_2_3_SRC:
342 case RT5677_IF_DSP_DAC3_4_MIXER:
343 case RT5677_DAC4_DIG_VOL:
344 case RT5677_DAC3_DIG_VOL:
345 case RT5677_DAC1_DIG_VOL:
346 case RT5677_DAC2_DIG_VOL:
347 case RT5677_IF_DSP_DAC2_MIXER:
348 case RT5677_STO1_ADC_DIG_VOL:
349 case RT5677_MONO_ADC_DIG_VOL:
350 case RT5677_STO1_2_ADC_BST:
351 case RT5677_STO2_ADC_DIG_VOL:
352 case RT5677_ADC_BST_CTRL2:
353 case RT5677_STO3_4_ADC_BST:
354 case RT5677_STO3_ADC_DIG_VOL:
355 case RT5677_STO4_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_MIXER:
357 case RT5677_STO3_ADC_MIXER:
358 case RT5677_STO2_ADC_MIXER:
359 case RT5677_STO1_ADC_MIXER:
360 case RT5677_MONO_ADC_MIXER:
361 case RT5677_ADC_IF_DSP_DAC1_MIXER:
362 case RT5677_STO1_DAC_MIXER:
363 case RT5677_MONO_DAC_MIXER:
364 case RT5677_DD1_MIXER:
365 case RT5677_DD2_MIXER:
366 case RT5677_IF3_DATA:
367 case RT5677_IF4_DATA:
368 case RT5677_PDM_OUT_CTRL:
369 case RT5677_PDM_DATA_CTRL1:
370 case RT5677_PDM_DATA_CTRL2:
371 case RT5677_PDM1_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL3:
373 case RT5677_PDM1_DATA_CTRL4:
374 case RT5677_PDM2_DATA_CTRL2:
375 case RT5677_PDM2_DATA_CTRL3:
376 case RT5677_PDM2_DATA_CTRL4:
377 case RT5677_TDM1_CTRL1:
378 case RT5677_TDM1_CTRL2:
379 case RT5677_TDM1_CTRL3:
380 case RT5677_TDM1_CTRL4:
381 case RT5677_TDM1_CTRL5:
382 case RT5677_TDM2_CTRL1:
383 case RT5677_TDM2_CTRL2:
384 case RT5677_TDM2_CTRL3:
385 case RT5677_TDM2_CTRL4:
386 case RT5677_TDM2_CTRL5:
387 case RT5677_I2C_MASTER_CTRL1:
388 case RT5677_I2C_MASTER_CTRL2:
389 case RT5677_I2C_MASTER_CTRL3:
390 case RT5677_I2C_MASTER_CTRL4:
391 case RT5677_I2C_MASTER_CTRL5:
392 case RT5677_I2C_MASTER_CTRL6:
393 case RT5677_I2C_MASTER_CTRL7:
394 case RT5677_I2C_MASTER_CTRL8:
395 case RT5677_DMIC_CTRL1:
396 case RT5677_DMIC_CTRL2:
397 case RT5677_HAP_GENE_CTRL1:
398 case RT5677_HAP_GENE_CTRL2:
399 case RT5677_HAP_GENE_CTRL3:
400 case RT5677_HAP_GENE_CTRL4:
401 case RT5677_HAP_GENE_CTRL5:
402 case RT5677_HAP_GENE_CTRL6:
403 case RT5677_HAP_GENE_CTRL7:
404 case RT5677_HAP_GENE_CTRL8:
405 case RT5677_HAP_GENE_CTRL9:
406 case RT5677_HAP_GENE_CTRL10:
407 case RT5677_PWR_DIG1:
408 case RT5677_PWR_DIG2:
409 case RT5677_PWR_ANLG1:
410 case RT5677_PWR_ANLG2:
411 case RT5677_PWR_DSP1:
412 case RT5677_PWR_DSP_ST:
413 case RT5677_PWR_DSP2:
414 case RT5677_ADC_DAC_HPF_CTRL1:
415 case RT5677_PRIV_INDEX:
416 case RT5677_PRIV_DATA:
417 case RT5677_I2S4_SDP:
418 case RT5677_I2S1_SDP:
419 case RT5677_I2S2_SDP:
420 case RT5677_I2S3_SDP:
421 case RT5677_CLK_TREE_CTRL1:
422 case RT5677_CLK_TREE_CTRL2:
423 case RT5677_CLK_TREE_CTRL3:
424 case RT5677_PLL1_CTRL1:
425 case RT5677_PLL1_CTRL2:
426 case RT5677_PLL2_CTRL1:
427 case RT5677_PLL2_CTRL2:
428 case RT5677_GLB_CLK1:
429 case RT5677_GLB_CLK2:
430 case RT5677_ASRC_1:
431 case RT5677_ASRC_2:
432 case RT5677_ASRC_3:
433 case RT5677_ASRC_4:
434 case RT5677_ASRC_5:
435 case RT5677_ASRC_6:
436 case RT5677_ASRC_7:
437 case RT5677_ASRC_8:
438 case RT5677_ASRC_9:
439 case RT5677_ASRC_10:
440 case RT5677_ASRC_11:
441 case RT5677_ASRC_12:
442 case RT5677_ASRC_13:
443 case RT5677_ASRC_14:
444 case RT5677_ASRC_15:
445 case RT5677_ASRC_16:
446 case RT5677_ASRC_17:
447 case RT5677_ASRC_18:
448 case RT5677_ASRC_19:
449 case RT5677_ASRC_20:
450 case RT5677_ASRC_21:
451 case RT5677_ASRC_22:
452 case RT5677_ASRC_23:
453 case RT5677_VAD_CTRL1:
454 case RT5677_VAD_CTRL2:
455 case RT5677_VAD_CTRL3:
456 case RT5677_VAD_CTRL4:
457 case RT5677_VAD_CTRL5:
458 case RT5677_DSP_INB_CTRL1:
459 case RT5677_DSP_INB_CTRL2:
460 case RT5677_DSP_IN_OUTB_CTRL:
461 case RT5677_DSP_OUTB0_1_DIG_VOL:
462 case RT5677_DSP_OUTB2_3_DIG_VOL:
463 case RT5677_DSP_OUTB4_5_DIG_VOL:
464 case RT5677_DSP_OUTB6_7_DIG_VOL:
465 case RT5677_ADC_EQ_CTRL1:
466 case RT5677_ADC_EQ_CTRL2:
467 case RT5677_EQ_CTRL1:
468 case RT5677_EQ_CTRL2:
469 case RT5677_EQ_CTRL3:
470 case RT5677_SOFT_VOL_ZERO_CROSS1:
471 case RT5677_JD_CTRL1:
472 case RT5677_JD_CTRL2:
473 case RT5677_JD_CTRL3:
474 case RT5677_IRQ_CTRL1:
475 case RT5677_IRQ_CTRL2:
476 case RT5677_GPIO_ST:
477 case RT5677_GPIO_CTRL1:
478 case RT5677_GPIO_CTRL2:
479 case RT5677_GPIO_CTRL3:
480 case RT5677_STO1_ADC_HI_FILTER1:
481 case RT5677_STO1_ADC_HI_FILTER2:
482 case RT5677_MONO_ADC_HI_FILTER1:
483 case RT5677_MONO_ADC_HI_FILTER2:
484 case RT5677_STO2_ADC_HI_FILTER1:
485 case RT5677_STO2_ADC_HI_FILTER2:
486 case RT5677_STO3_ADC_HI_FILTER1:
487 case RT5677_STO3_ADC_HI_FILTER2:
488 case RT5677_STO4_ADC_HI_FILTER1:
489 case RT5677_STO4_ADC_HI_FILTER2:
490 case RT5677_MB_DRC_CTRL1:
491 case RT5677_DRC1_CTRL1:
492 case RT5677_DRC1_CTRL2:
493 case RT5677_DRC1_CTRL3:
494 case RT5677_DRC1_CTRL4:
495 case RT5677_DRC1_CTRL5:
496 case RT5677_DRC1_CTRL6:
497 case RT5677_DRC2_CTRL1:
498 case RT5677_DRC2_CTRL2:
499 case RT5677_DRC2_CTRL3:
500 case RT5677_DRC2_CTRL4:
501 case RT5677_DRC2_CTRL5:
502 case RT5677_DRC2_CTRL6:
503 case RT5677_DRC1_HL_CTRL1:
504 case RT5677_DRC1_HL_CTRL2:
505 case RT5677_DRC2_HL_CTRL1:
506 case RT5677_DRC2_HL_CTRL2:
507 case RT5677_DSP_INB1_SRC_CTRL1:
508 case RT5677_DSP_INB1_SRC_CTRL2:
509 case RT5677_DSP_INB1_SRC_CTRL3:
510 case RT5677_DSP_INB1_SRC_CTRL4:
511 case RT5677_DSP_INB2_SRC_CTRL1:
512 case RT5677_DSP_INB2_SRC_CTRL2:
513 case RT5677_DSP_INB2_SRC_CTRL3:
514 case RT5677_DSP_INB2_SRC_CTRL4:
515 case RT5677_DSP_INB3_SRC_CTRL1:
516 case RT5677_DSP_INB3_SRC_CTRL2:
517 case RT5677_DSP_INB3_SRC_CTRL3:
518 case RT5677_DSP_INB3_SRC_CTRL4:
519 case RT5677_DSP_OUTB1_SRC_CTRL1:
520 case RT5677_DSP_OUTB1_SRC_CTRL2:
521 case RT5677_DSP_OUTB1_SRC_CTRL3:
522 case RT5677_DSP_OUTB1_SRC_CTRL4:
523 case RT5677_DSP_OUTB2_SRC_CTRL1:
524 case RT5677_DSP_OUTB2_SRC_CTRL2:
525 case RT5677_DSP_OUTB2_SRC_CTRL3:
526 case RT5677_DSP_OUTB2_SRC_CTRL4:
527 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
528 case RT5677_DSP_OUTB_45_MIXER_CTRL:
529 case RT5677_DSP_OUTB_67_MIXER_CTRL:
530 case RT5677_DIG_MISC:
531 case RT5677_GEN_CTRL1:
532 case RT5677_GEN_CTRL2:
533 case RT5677_VENDOR_ID:
534 case RT5677_VENDOR_ID1:
535 case RT5677_VENDOR_ID2:
536 return true;
537 default:
538 return false;
539 }
540}
541
af48f1d0
OC		 542/**
543 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
544 * @codec: SoC audio codec device.
545 * @addr: Address index.
546 * @value: Address data.
547 *
548 *
549 * Returns 0 for success or negative error code.
550 */
551static int rt5677_dsp_mode_i2c_write_addr(struct snd_soc_codec *codec,
552 unsigned int addr, unsigned int value, unsigned int opcode)
553{
554 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
555 int ret;
556
557 mutex_lock(&rt5677->dsp_cmd_lock);
558
559 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_ADDR_MSB, addr >> 16);
560 if (ret < 0) {
561 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
562 goto err;
563 }
564
565 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_ADDR_LSB,
566 addr & 0xffff);
567 if (ret < 0) {
568 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
569 goto err;
570 }
571
572 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_DATA_MSB,
573 value >> 16);
574 if (ret < 0) {
575 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
576 goto err;
577 }
578
579 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_DATA_LSB,
580 value & 0xffff);
581 if (ret < 0) {
582 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
583 goto err;
584 }
585
586 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_OP_CODE, opcode);
587 if (ret < 0) {
588 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
589 goto err;
590 }
591
592err:
593 mutex_unlock(&rt5677->dsp_cmd_lock);
594
595 return ret;
596}
597
598/**
599 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
600 * @codec: SoC audio codec device.
601 * @addr: Address index.
602 * @value: Address data.
603 *
604 * Returns 0 for success or negative error code.
605 */
606static int rt5677_dsp_mode_i2c_read_addr(
607 struct snd_soc_codec *codec, unsigned int addr, unsigned int *value)
608{
609 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
610 int ret;
611 unsigned int msb, lsb;
612
613 mutex_lock(&rt5677->dsp_cmd_lock);
614
615 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_ADDR_MSB, addr >> 16);
616 if (ret < 0) {
617 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
618 goto err;
619 }
620
621 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_ADDR_LSB,
622 addr & 0xffff);
623 if (ret < 0) {
624 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
625 goto err;
626 }
627
628 ret = regmap_write(rt5677->regmap, RT5677_DSP_I2C_OP_CODE , 0x0002);
629 if (ret < 0) {
630 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
631 goto err;
632 }
633
634 regmap_read(rt5677->regmap, RT5677_DSP_I2C_DATA_MSB, &msb);
635 regmap_read(rt5677->regmap, RT5677_DSP_I2C_DATA_LSB, &lsb);
636 *value = (msb << 16) | lsb;
637
638err:
639 mutex_unlock(&rt5677->dsp_cmd_lock);
640
641 return ret;
642}
643
644/**
645 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
646 * @codec: SoC audio codec device.
647 * @reg: Register index.
648 * @value: Register data.
649 *
650 *
651 * Returns 0 for success or negative error code.
652 */
653static int rt5677_dsp_mode_i2c_write(struct snd_soc_codec *codec,
654 unsigned int reg, unsigned int value)
655{
656 return rt5677_dsp_mode_i2c_write_addr(codec, 0x18020000 + reg * 2,
657 value, 0x0001);
658}
659
660/**
661 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
662 * @codec: SoC audio codec device.
663 * @reg: Register index.
664 *
665 *
666 * Returns Register value.
667 */
668static unsigned int rt5677_dsp_mode_i2c_read(
669 struct snd_soc_codec *codec, unsigned int reg)
670{
671 unsigned int value = 0;
672
673 rt5677_dsp_mode_i2c_read_addr(codec, 0x18020000 + reg * 2, &value);
674
675 return value;
676}
677
678/**
679 * rt5677_dsp_mode_i2c_update_bits - update register on DSP mode.
680 * @codec: audio codec
681 * @reg: register index.
682 * @mask: register mask
683 * @value: new value
684 *
685 *
686 * Returns 1 for change, 0 for no change, or negative error code.
687 */
688static int rt5677_dsp_mode_i2c_update_bits(struct snd_soc_codec *codec,
689 unsigned int reg, unsigned int mask, unsigned int value)
690{
691 unsigned int old, new;
692 int change, ret;
693
694 ret = rt5677_dsp_mode_i2c_read(codec, reg);
695 if (ret < 0) {
696 dev_err(codec->dev, "Failed to read reg: %d\n", ret);
697 goto err;
698 }
699
700 old = ret;
701 new = (old & ~mask) | (value & mask);
702 change = old != new;
703 if (change) {
704 ret = rt5677_dsp_mode_i2c_write(codec, reg, new);
705 if (ret < 0) {
706 dev_err(codec->dev,
707 "Failed to write reg: %d\n", ret);
708 goto err;
709 }
710 }
711 return change;
712
713err:
714 return ret;
715}
716
717static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
718{
719 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
720 static bool activity;
721 int ret;
722
723 if (on && !activity) {
724 activity = true;
725
726 regcache_cache_only(rt5677->regmap, false);
727 regcache_cache_bypass(rt5677->regmap, true);
728
729 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
730 regmap_update_bits(rt5677->regmap,
731 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
732 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
733 RT5677_LDO1_SEL_MASK, 0x0);
734 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
735 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
736 regmap_write(rt5677->regmap, RT5677_GLB_CLK2, 0x0080);
737 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
738 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07ff);
739
740 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
741 codec->dev);
742 if (ret == 0) {
743 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
744 release_firmware(rt5677->fw1);
745 }
746
747 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
748 codec->dev);
749 if (ret == 0) {
750 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
751 release_firmware(rt5677->fw2);
752 }
753
754 rt5677_dsp_mode_i2c_update_bits(codec, RT5677_PWR_DSP1, 0x1,
755 0x0);
756
757 regcache_cache_bypass(rt5677->regmap, false);
758 regcache_cache_only(rt5677->regmap, true);
759 } else if (!on && activity) {
760 activity = false;
761
762 regcache_cache_only(rt5677->regmap, false);
763 regcache_cache_bypass(rt5677->regmap, true);
764
765 rt5677_dsp_mode_i2c_update_bits(codec, RT5677_PWR_DSP1, 0x1,
766 0x1);
767 rt5677_dsp_mode_i2c_write(codec, RT5677_PWR_DSP1, 0x0001);
768
769 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
770
771 regcache_cache_bypass(rt5677->regmap, false);
772 regcache_mark_dirty(rt5677->regmap);
773 regcache_sync(rt5677->regmap);
774 }
775
776 return 0;
777}
778
0e826e86
OC		 779static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
780static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
781static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
782static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
783static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
90bdbb46 784static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
0e826e86
OC		 785
786/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
787static unsigned int bst_tlv[] = {
788 TLV_DB_RANGE_HEAD(7),
789 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
790 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
791 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
792 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
793 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
794 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
795 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
796};
797
af48f1d0
OC		 798static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
799 struct snd_ctl_elem_value *ucontrol)
800{
801 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
802 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
803
804 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
805
806 return 0;
807}
808
809static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
810 struct snd_ctl_elem_value *ucontrol)
811{
812 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
813 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
814
815 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
816
817 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
818 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
819
820 return 0;
821}
822
0e826e86
OC		 823static const struct snd_kcontrol_new rt5677_snd_controls[] = {
824 /* OUTPUT Control */
825 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
826 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
827 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
828 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
829 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
830 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
831
832 /* DAC Digital Volume */
833 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
834 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
835 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
836 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
837 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
838 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
839 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
840 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
841
842 /* IN1/IN2 Control */
843 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
844 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
845
846 /* ADC Digital Volume Control */
847 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
848 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
849 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
850 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
851 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
852 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
853 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
854 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
856 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
857
858 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
859 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
860 adc_vol_tlv),
861 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
862 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
863 adc_vol_tlv),
864 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
865 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
866 adc_vol_tlv),
867 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
868 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
869 adc_vol_tlv),
870 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
871 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
872 adc_vol_tlv),
873
90bdbb46
OC		 874 /* Sidetone Control */
875 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
876 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
877
0e826e86 878 /* ADC Boost Volume Control */
80220f29 879 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 880 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
881 adc_bst_tlv),
80220f29 882 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 883 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
884 adc_bst_tlv),
80220f29 885 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 886 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
887 adc_bst_tlv),
80220f29 888 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 889 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
890 adc_bst_tlv),
80220f29 891 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
0e826e86
OC		 892 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
893 adc_bst_tlv),
af48f1d0
OC		 894
895 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
896 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
0e826e86
OC		 897};
898
899/**
900 * set_dmic_clk - Set parameter of dmic.
901 *
902 * @w: DAPM widget.
903 * @kcontrol: The kcontrol of this widget.
904 * @event: Event id.
905 *
906 * Choose dmic clock between 1MHz and 3MHz.
907 * It is better for clock to approximate 3MHz.
908 */
909static int set_dmic_clk(struct snd_soc_dapm_widget *w,
910 struct snd_kcontrol *kcontrol, int event)
911{
912 struct snd_soc_codec *codec = w->codec;
913 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
9a53581e 914 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
0e826e86
OC		 915
916 if (idx < 0)
917 dev_err(codec->dev, "Failed to set DMIC clock\n");
918 else
919 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
920 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
921 return idx;
922}
923
924static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
925 struct snd_soc_dapm_widget *sink)
926{
927 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
928 unsigned int val;
929
930 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
931 val &= RT5677_SCLK_SRC_MASK;
932 if (val == RT5677_SCLK_SRC_PLL1)
933 return 1;
934 else
935 return 0;
936}
937
938/* Digital Mixer */
939static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
940 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
941 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
942 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
943 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
944};
945
946static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
947 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
948 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
949 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
950 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
951};
952
953static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
954 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
955 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
956 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
957 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
958};
959
960static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
961 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
962 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
963 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
964 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
965};
966
967static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
968 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
969 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
970 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
971 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
972};
973
974static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
975 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
976 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
977 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
978 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
979};
980
981static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
982 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
983 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
984 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
985 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
986};
987
988static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
989 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
990 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
991 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
992 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
993};
994
995static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
996 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
997 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
998 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
999 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1000};
1001
1002static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1003 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1004 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1005 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1006 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1007};
1008
1009static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1010 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1011 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1012 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1013 RT5677_M_DAC1_L_SFT, 1, 1),
1014};
1015
1016static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1017 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1018 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1019 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1020 RT5677_M_DAC1_R_SFT, 1, 1),
1021};
1022
1023static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1024 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1025 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1026 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1027 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1028 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1029 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1030 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1031 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1032};
1033
1034static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1035 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1036 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1037 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1038 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1039 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1040 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1041 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1042 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1043};
1044
1045static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1046 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1047 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1048 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1049 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1050 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1051 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1052 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1053 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1054};
1055
1056static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1057 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1058 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1059 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1060 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1061 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1062 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1063 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1064 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1065};
1066
1067static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1068 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1069 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1070 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1071 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1072 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1073 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1074 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1075 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1076};
1077
1078static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1079 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1080 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1081 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1082 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1083 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1084 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1085 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1086 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1087};
1088
1089static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1090 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1091 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1092 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1093 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1094 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1095 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1096 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1097 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1098};
1099
1100static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1101 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1102 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1103 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1104 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1105 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1106 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1107 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1108 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1109};
1110
1111static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1112 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1113 RT5677_DSP_IB_01_H_SFT, 1, 1),
1114 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1115 RT5677_DSP_IB_23_H_SFT, 1, 1),
1116 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1117 RT5677_DSP_IB_45_H_SFT, 1, 1),
1118 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1119 RT5677_DSP_IB_6_H_SFT, 1, 1),
1120 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1121 RT5677_DSP_IB_7_H_SFT, 1, 1),
1122 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1123 RT5677_DSP_IB_8_H_SFT, 1, 1),
1124 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1125 RT5677_DSP_IB_9_H_SFT, 1, 1),
1126};
1127
1128static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1129 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1130 RT5677_DSP_IB_01_L_SFT, 1, 1),
1131 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1132 RT5677_DSP_IB_23_L_SFT, 1, 1),
1133 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1134 RT5677_DSP_IB_45_L_SFT, 1, 1),
1135 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1136 RT5677_DSP_IB_6_L_SFT, 1, 1),
1137 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1138 RT5677_DSP_IB_7_L_SFT, 1, 1),
1139 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1140 RT5677_DSP_IB_8_L_SFT, 1, 1),
1141 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1142 RT5677_DSP_IB_9_L_SFT, 1, 1),
1143};
1144
1145static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1146 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1147 RT5677_DSP_IB_01_H_SFT, 1, 1),
1148 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1149 RT5677_DSP_IB_23_H_SFT, 1, 1),
1150 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1151 RT5677_DSP_IB_45_H_SFT, 1, 1),
1152 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1153 RT5677_DSP_IB_6_H_SFT, 1, 1),
1154 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1155 RT5677_DSP_IB_7_H_SFT, 1, 1),
1156 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1157 RT5677_DSP_IB_8_H_SFT, 1, 1),
1158 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1159 RT5677_DSP_IB_9_H_SFT, 1, 1),
1160};
1161
1162static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1163 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1164 RT5677_DSP_IB_01_L_SFT, 1, 1),
1165 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1166 RT5677_DSP_IB_23_L_SFT, 1, 1),
1167 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1168 RT5677_DSP_IB_45_L_SFT, 1, 1),
1169 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1170 RT5677_DSP_IB_6_L_SFT, 1, 1),
1171 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1172 RT5677_DSP_IB_7_L_SFT, 1, 1),
1173 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1174 RT5677_DSP_IB_8_L_SFT, 1, 1),
1175 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1176 RT5677_DSP_IB_9_L_SFT, 1, 1),
1177};
1178
1179static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1180 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1181 RT5677_DSP_IB_01_H_SFT, 1, 1),
1182 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1183 RT5677_DSP_IB_23_H_SFT, 1, 1),
1184 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1185 RT5677_DSP_IB_45_H_SFT, 1, 1),
1186 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1187 RT5677_DSP_IB_6_H_SFT, 1, 1),
1188 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1189 RT5677_DSP_IB_7_H_SFT, 1, 1),
1190 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1191 RT5677_DSP_IB_8_H_SFT, 1, 1),
1192 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1193 RT5677_DSP_IB_9_H_SFT, 1, 1),
1194};
1195
1196static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1197 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1198 RT5677_DSP_IB_01_L_SFT, 1, 1),
1199 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1200 RT5677_DSP_IB_23_L_SFT, 1, 1),
1201 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1202 RT5677_DSP_IB_45_L_SFT, 1, 1),
1203 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1204 RT5677_DSP_IB_6_L_SFT, 1, 1),
1205 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1206 RT5677_DSP_IB_7_L_SFT, 1, 1),
1207 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1208 RT5677_DSP_IB_8_L_SFT, 1, 1),
1209 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1210 RT5677_DSP_IB_9_L_SFT, 1, 1),
1211};
1212
1213
1214/* Mux */
1b7fd76a 1215/* DAC1 L/R Source */ /* MX-29 [10:8] */
0e826e86
OC		 1216static const char * const rt5677_dac1_src[] = {
1217 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1218 "OB 01"
1219};
1220
1221static SOC_ENUM_SINGLE_DECL(
1222 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1223 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1224
1225static const struct snd_kcontrol_new rt5677_dac1_mux =
1b7fd76a 1226 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
0e826e86 1227
1b7fd76a 1228/* ADDA1 L/R Source */ /* MX-29 [1:0] */
0e826e86
OC		 1229static const char * const rt5677_adda1_src[] = {
1230 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1231};
1232
1233static SOC_ENUM_SINGLE_DECL(
1234 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1235 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1236
1237static const struct snd_kcontrol_new rt5677_adda1_mux =
1b7fd76a 1238 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
0e826e86
OC		 1239
1240
1b7fd76a 1241/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
0e826e86
OC		 1242static const char * const rt5677_dac2l_src[] = {
1243 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1244 "OB 2",
1245};
1246
1247static SOC_ENUM_SINGLE_DECL(
1248 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1249 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1250
1251static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1b7fd76a 1252 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
0e826e86
OC		 1253
1254static const char * const rt5677_dac2r_src[] = {
1255 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1256 "OB 3", "Haptic Generator", "VAD ADC"
1257};
1258
1259static SOC_ENUM_SINGLE_DECL(
1260 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1261 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1262
1263static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1b7fd76a 1264 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
0e826e86 1265
1b7fd76a 1266/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
0e826e86
OC		 1267static const char * const rt5677_dac3l_src[] = {
1268 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1269 "SLB DAC 4", "OB 4"
1270};
1271
1272static SOC_ENUM_SINGLE_DECL(
1273 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1274 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1275
1276static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1b7fd76a 1277 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
0e826e86
OC		 1278
1279static const char * const rt5677_dac3r_src[] = {
1280 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1281 "SLB DAC 5", "OB 5"
1282};
1283
1284static SOC_ENUM_SINGLE_DECL(
1285 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1286 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1287
1288static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1b7fd76a 1289 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
0e826e86 1290
1b7fd76a 1291/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
0e826e86
OC		 1292static const char * const rt5677_dac4l_src[] = {
1293 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1294 "SLB DAC 6", "OB 6"
1295};
1296
1297static SOC_ENUM_SINGLE_DECL(
1298 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1299 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1300
1301static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1b7fd76a 1302 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
0e826e86
OC		 1303
1304static const char * const rt5677_dac4r_src[] = {
1305 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1306 "SLB DAC 7", "OB 7"
1307};
1308
1309static SOC_ENUM_SINGLE_DECL(
1310 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1311 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1312
1313static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1b7fd76a 1314 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
0e826e86
OC		 1315
1316/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1317static const char * const rt5677_iob_bypass_src[] = {
1318 "Bypass", "Pass SRC"
1319};
1320
1321static SOC_ENUM_SINGLE_DECL(
1322 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1323 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1324
1325static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1b7fd76a 1326 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
0e826e86
OC		 1327
1328static SOC_ENUM_SINGLE_DECL(
1329 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1330 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1331
1332static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1b7fd76a 1333 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
0e826e86
OC		 1334
1335static SOC_ENUM_SINGLE_DECL(
1336 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1337 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1338
1339static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1b7fd76a 1340 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
0e826e86
OC		 1341
1342static SOC_ENUM_SINGLE_DECL(
1343 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1344 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1345
1346static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1b7fd76a 1347 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
0e826e86
OC		 1348
1349static SOC_ENUM_SINGLE_DECL(
1350 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1351 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1352
1353static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1b7fd76a 1354 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
0e826e86
OC		 1355
1356/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1357static const char * const rt5677_stereo_adc2_src[] = {
1358 "DD MIX1", "DMIC", "Stereo DAC MIX"
1359};
1360
1361static SOC_ENUM_SINGLE_DECL(
1362 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1363 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1364
1365static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1b7fd76a 1366 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
0e826e86
OC		 1367
1368static SOC_ENUM_SINGLE_DECL(
1369 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1370 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1371
1372static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1b7fd76a 1373 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
0e826e86
OC		 1374
1375static SOC_ENUM_SINGLE_DECL(
1376 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1377 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1378
1379static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1b7fd76a 1380 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
0e826e86
OC		 1381
1382/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1383static const char * const rt5677_dmic_src[] = {
1384 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1385};
1386
1387static SOC_ENUM_SINGLE_DECL(
1388 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1389 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1390
1391static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1b7fd76a 1392 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
0e826e86
OC		 1393
1394static SOC_ENUM_SINGLE_DECL(
1395 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1396 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1397
1398static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1b7fd76a 1399 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
0e826e86
OC		 1400
1401static SOC_ENUM_SINGLE_DECL(
1402 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1403 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1404
1405static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1b7fd76a 1406 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
0e826e86
OC		 1407
1408static SOC_ENUM_SINGLE_DECL(
1409 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1410 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1411
1412static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1b7fd76a 1413 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
0e826e86
OC		 1414
1415static SOC_ENUM_SINGLE_DECL(
1416 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1417 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1418
1419static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1b7fd76a 1420 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
0e826e86
OC		 1421
1422static SOC_ENUM_SINGLE_DECL(
1423 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1424 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1425
1426static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1b7fd76a 1427 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
0e826e86 1428
1b7fd76a 1429/* Stereo2 ADC Source */ /* MX-26 [0] */
0e826e86
OC		 1430static const char * const rt5677_stereo2_adc_lr_src[] = {
1431 "L", "LR"
1432};
1433
1434static SOC_ENUM_SINGLE_DECL(
1435 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1436 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1437
1438static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1b7fd76a 1439 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
0e826e86
OC		 1440
1441/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1442static const char * const rt5677_stereo_adc1_src[] = {
1443 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1444};
1445
1446static SOC_ENUM_SINGLE_DECL(
1447 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1448 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1449
1450static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1b7fd76a 1451 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
0e826e86
OC		 1452
1453static SOC_ENUM_SINGLE_DECL(
1454 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1455 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1456
1457static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1b7fd76a 1458 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
0e826e86
OC		 1459
1460static SOC_ENUM_SINGLE_DECL(
1461 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1462 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1463
1464static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1b7fd76a 1465 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
0e826e86 1466
1b7fd76a 1467/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
0e826e86
OC		 1468static const char * const rt5677_mono_adc2_l_src[] = {
1469 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1470};
1471
1472static SOC_ENUM_SINGLE_DECL(
1473 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1474 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1475
1476static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1b7fd76a 1477 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
0e826e86 1478
1b7fd76a 1479/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
0e826e86
OC		 1480static const char * const rt5677_mono_adc1_l_src[] = {
1481 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1482};
1483
1484static SOC_ENUM_SINGLE_DECL(
1485 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1486 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1487
1488static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1b7fd76a 1489 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
0e826e86 1490
1b7fd76a 1491/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
0e826e86
OC		 1492static const char * const rt5677_mono_adc2_r_src[] = {
1493 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1494};
1495
1496static SOC_ENUM_SINGLE_DECL(
1497 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1498 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1499
1500static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1b7fd76a 1501 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
0e826e86 1502
1b7fd76a 1503/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
0e826e86
OC		 1504static const char * const rt5677_mono_adc1_r_src[] = {
1505 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1506};
1507
1508static SOC_ENUM_SINGLE_DECL(
1509 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1510 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1511
1512static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1b7fd76a 1513 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
0e826e86
OC		 1514
1515/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1516static const char * const rt5677_stereo4_adc2_src[] = {
1517 "DD MIX1", "DMIC", "DD MIX2"
1518};
1519
1520static SOC_ENUM_SINGLE_DECL(
1521 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1522 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1523
1524static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1b7fd76a 1525 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
0e826e86
OC		 1526
1527
1528/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1529static const char * const rt5677_stereo4_adc1_src[] = {
1530 "DD MIX1", "ADC1/2", "DD MIX2"
1531};
1532
1533static SOC_ENUM_SINGLE_DECL(
1534 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1535 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1536
1537static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1b7fd76a 1538 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
0e826e86
OC		 1539
1540/* InBound0/1 Source */ /* MX-A3 [14:12] */
1541static const char * const rt5677_inbound01_src[] = {
1542 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1543 "VAD ADC/DAC1 FS"
1544};
1545
1546static SOC_ENUM_SINGLE_DECL(
1547 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1548 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1549
1550static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1551 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1552
1553/* InBound2/3 Source */ /* MX-A3 [10:8] */
1554static const char * const rt5677_inbound23_src[] = {
1555 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1556 "DAC1 FS", "IF4 DAC"
1557};
1558
1559static SOC_ENUM_SINGLE_DECL(
1560 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1561 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1562
1563static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1564 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1565
1566/* InBound4/5 Source */ /* MX-A3 [6:4] */
1567static const char * const rt5677_inbound45_src[] = {
1568 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1569 "IF3 DAC"
1570};
1571
1572static SOC_ENUM_SINGLE_DECL(
1573 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1574 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1575
1576static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1577 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1578
1579/* InBound6 Source */ /* MX-A3 [2:0] */
1580static const char * const rt5677_inbound6_src[] = {
1581 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1582 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1583};
1584
1585static SOC_ENUM_SINGLE_DECL(
1586 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1587 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1588
1589static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1590 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1591
1592/* InBound7 Source */ /* MX-A4 [14:12] */
1593static const char * const rt5677_inbound7_src[] = {
1594 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1595 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1596};
1597
1598static SOC_ENUM_SINGLE_DECL(
1599 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1600 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1601
1602static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1603 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1604
1605/* InBound8 Source */ /* MX-A4 [10:8] */
1606static const char * const rt5677_inbound8_src[] = {
1607 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1608 "MONO ADC MIX L", "DACL1 FS"
1609};
1610
1611static SOC_ENUM_SINGLE_DECL(
1612 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1613 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1614
1615static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1616 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1617
1618/* InBound9 Source */ /* MX-A4 [6:4] */
1619static const char * const rt5677_inbound9_src[] = {
1620 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1621 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1622};
1623
1624static SOC_ENUM_SINGLE_DECL(
1625 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1626 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1627
1628static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1629 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1630
1631/* VAD Source */ /* MX-9F [6:4] */
1632static const char * const rt5677_vad_src[] = {
1633 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1634 "STO3 ADC MIX L"
1635};
1636
1637static SOC_ENUM_SINGLE_DECL(
1638 rt5677_vad_enum, RT5677_VAD_CTRL4,
1639 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1640
1641static const struct snd_kcontrol_new rt5677_vad_src_mux =
1642 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1643
1644/* Sidetone Source */ /* MX-13 [11:9] */
1645static const char * const rt5677_sidetone_src[] = {
1646 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1647};
1648
1649static SOC_ENUM_SINGLE_DECL(
1650 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1651 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1652
1653static const struct snd_kcontrol_new rt5677_sidetone_mux =
1654 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1655
1656/* DAC1/2 Source */ /* MX-15 [1:0] */
1657static const char * const rt5677_dac12_src[] = {
1658 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1659};
1660
1661static SOC_ENUM_SINGLE_DECL(
1662 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1663 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1664
1665static const struct snd_kcontrol_new rt5677_dac12_mux =
1666 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1667
1668/* DAC3 Source */ /* MX-15 [5:4] */
1669static const char * const rt5677_dac3_src[] = {
1670 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1671};
1672
1673static SOC_ENUM_SINGLE_DECL(
1674 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1675 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1676
1677static const struct snd_kcontrol_new rt5677_dac3_mux =
1678 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1679
1b7fd76a 1680/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
0e826e86
OC		 1681static const char * const rt5677_pdm_src[] = {
1682 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1683};
1684
1685static SOC_ENUM_SINGLE_DECL(
1686 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1687 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1688
1689static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1b7fd76a 1690 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
0e826e86
OC		 1691
1692static SOC_ENUM_SINGLE_DECL(
1693 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1694 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1695
1696static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1b7fd76a 1697 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
0e826e86
OC		 1698
1699static SOC_ENUM_SINGLE_DECL(
1700 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1701 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1702
1703static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1b7fd76a 1704 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
0e826e86
OC		 1705
1706static SOC_ENUM_SINGLE_DECL(
1707 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1708 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1709
1710static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1b7fd76a 1711 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
0e826e86
OC		 1712
1713/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
1714static const char * const rt5677_if12_adc1_src[] = {
1715 "STO1 ADC MIX", "OB01", "VAD ADC"
1716};
1717
1718static SOC_ENUM_SINGLE_DECL(
1719 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1720 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1721
1722static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1b7fd76a 1723 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
0e826e86
OC		 1724
1725static SOC_ENUM_SINGLE_DECL(
1726 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1727 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1728
1729static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1b7fd76a 1730 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
0e826e86
OC		 1731
1732static SOC_ENUM_SINGLE_DECL(
1733 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1734 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1735
1736static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1b7fd76a 1737 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
0e826e86
OC		 1738
1739/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1740static const char * const rt5677_if12_adc2_src[] = {
1741 "STO2 ADC MIX", "OB23"
1742};
1743
1744static SOC_ENUM_SINGLE_DECL(
1745 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1746 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1747
1748static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1b7fd76a 1749 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
0e826e86
OC		 1750
1751static SOC_ENUM_SINGLE_DECL(
1752 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1753 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1754
1755static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1b7fd76a 1756 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
0e826e86
OC		 1757
1758static SOC_ENUM_SINGLE_DECL(
1759 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1760 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1761
1762static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1b7fd76a 1763 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
0e826e86
OC		 1764
1765/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1766static const char * const rt5677_if12_adc3_src[] = {
1767 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1768};
1769
1770static SOC_ENUM_SINGLE_DECL(
1771 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1772 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1773
1774static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1b7fd76a 1775 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
0e826e86
OC		 1776
1777static SOC_ENUM_SINGLE_DECL(
1778 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1779 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1780
1781static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1b7fd76a 1782 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
0e826e86
OC		 1783
1784static SOC_ENUM_SINGLE_DECL(
1785 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1786 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1787
1788static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1b7fd76a 1789 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
0e826e86
OC		 1790
1791/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1792static const char * const rt5677_if12_adc4_src[] = {
1793 "STO4 ADC MIX", "OB67", "OB01"
1794};
1795
1796static SOC_ENUM_SINGLE_DECL(
1797 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1798 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1799
1800static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1b7fd76a 1801 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
0e826e86
OC		 1802
1803static SOC_ENUM_SINGLE_DECL(
1804 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1805 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1806
1807static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1b7fd76a 1808 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
0e826e86
OC		 1809
1810static SOC_ENUM_SINGLE_DECL(
1811 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1812 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1813
1814static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1b7fd76a 1815 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
0e826e86
OC		 1816
1817/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
1818static const char * const rt5677_if34_adc_src[] = {
1819 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1820 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1821};
1822
1823static SOC_ENUM_SINGLE_DECL(
1824 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1825 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1826
1827static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1b7fd76a 1828 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
0e826e86
OC		 1829
1830static SOC_ENUM_SINGLE_DECL(
1831 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1832 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1833
1834static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1b7fd76a 1835 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
0e826e86
OC		 1836
1837static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1838 struct snd_kcontrol *kcontrol, int event)
1839{
1840 struct snd_soc_codec *codec = w->codec;
1841 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1842
1843 switch (event) {
1844 case SND_SOC_DAPM_POST_PMU:
1845 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1846 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1847 break;
1848
1849 case SND_SOC_DAPM_PRE_PMD:
1850 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1851 RT5677_PWR_BST1_P, 0);
1852 break;
1853
1854 default:
1855 return 0;
1856 }
1857
1858 return 0;
1859}
1860
1861static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1862 struct snd_kcontrol *kcontrol, int event)
1863{
1864 struct snd_soc_codec *codec = w->codec;
1865 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1866
1867 switch (event) {
1868 case SND_SOC_DAPM_POST_PMU:
1869 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1870 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1871 break;
1872
1873 case SND_SOC_DAPM_PRE_PMD:
1874 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1875 RT5677_PWR_BST2_P, 0);
1876 break;
1877
1878 default:
1879 return 0;
1880 }
1881
1882 return 0;
1883}
1884
1885static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1886 struct snd_kcontrol *kcontrol, int event)
1887{
1888 struct snd_soc_codec *codec = w->codec;
1889 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1890
1891 switch (event) {
1892 case SND_SOC_DAPM_POST_PMU:
1893 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1894 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1895 break;
1896 default:
1897 return 0;
1898 }
1899
1900 return 0;
1901}
1902
1903static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1904 struct snd_kcontrol *kcontrol, int event)
1905{
1906 struct snd_soc_codec *codec = w->codec;
1907 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1908
1909 switch (event) {
1910 case SND_SOC_DAPM_POST_PMU:
1911 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1912 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
1913 break;
1914 default:
1915 return 0;
1916 }
1917
1918 return 0;
1919}
1920
1921static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1922 struct snd_kcontrol *kcontrol, int event)
1923{
1924 struct snd_soc_codec *codec = w->codec;
1925 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1926
1927 switch (event) {
1928 case SND_SOC_DAPM_POST_PMU:
1929 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1930 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1931 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
1932 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
1933 break;
f58c3b91
OC		 1934
1935 case SND_SOC_DAPM_PRE_PMD:
1936 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1937 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1938 RT5677_PWR_CLK_MB, 0);
1939 break;
1940
0e826e86
OC		 1941 default:
1942 return 0;
1943 }
1944
1945 return 0;
1946}
1947
1948static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1949 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
1950 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
1951 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
1952 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
1953
1954 /* Input Side */
1955 /* micbias */
3d0c03d9 1956 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
f58c3b91
OC		 1957 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
1958 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 1959
1960 /* Input Lines */
1961 SND_SOC_DAPM_INPUT("DMIC L1"),
1962 SND_SOC_DAPM_INPUT("DMIC R1"),
1963 SND_SOC_DAPM_INPUT("DMIC L2"),
1964 SND_SOC_DAPM_INPUT("DMIC R2"),
1965 SND_SOC_DAPM_INPUT("DMIC L3"),
1966 SND_SOC_DAPM_INPUT("DMIC R3"),
1967 SND_SOC_DAPM_INPUT("DMIC L4"),
1968 SND_SOC_DAPM_INPUT("DMIC R4"),
1969
1970 SND_SOC_DAPM_INPUT("IN1P"),
1971 SND_SOC_DAPM_INPUT("IN1N"),
1972 SND_SOC_DAPM_INPUT("IN2P"),
1973 SND_SOC_DAPM_INPUT("IN2N"),
1974
1975 SND_SOC_DAPM_INPUT("Haptic Generator"),
1976
2d15d974
BL		 1977 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1978 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1979 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1980 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1981
1982 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
1983 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
1984 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
1985 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
1986 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
1987 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
1988 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
1989 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
0e826e86
OC		 1990
1991 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1992 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1993
1994 /* Boost */
1995 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
1996 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
1997 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1998 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
1999 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2000 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2001
2002 /* ADCs */
2003 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2004 0, 0),
2005 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2006 0, 0),
2007 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2008
2009 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2010 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2011 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2012 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2013 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2014 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2015 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2016 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2017
2018 /* ADC Mux */
2019 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2020 &rt5677_sto1_dmic_mux),
2021 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2022 &rt5677_sto1_adc1_mux),
2023 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2024 &rt5677_sto1_adc2_mux),
2025 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2026 &rt5677_sto2_dmic_mux),
2027 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2028 &rt5677_sto2_adc1_mux),
2029 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2030 &rt5677_sto2_adc2_mux),
2031 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2032 &rt5677_sto2_adc_lr_mux),
2033 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2034 &rt5677_sto3_dmic_mux),
2035 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2036 &rt5677_sto3_adc1_mux),
2037 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2038 &rt5677_sto3_adc2_mux),
2039 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2040 &rt5677_sto4_dmic_mux),
2041 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2042 &rt5677_sto4_adc1_mux),
2043 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2044 &rt5677_sto4_adc2_mux),
2045 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2046 &rt5677_mono_dmic_l_mux),
2047 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2048 &rt5677_mono_dmic_r_mux),
2049 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2050 &rt5677_mono_adc2_l_mux),
2051 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2052 &rt5677_mono_adc1_l_mux),
2053 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2054 &rt5677_mono_adc1_r_mux),
2055 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2056 &rt5677_mono_adc2_r_mux),
2057
2058 /* ADC Mixer */
2059 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2060 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2061 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2062 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2063 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2064 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2065 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2066 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2067 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2068 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2069 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2070 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2071 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2072 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2073 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2074 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2075 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2076 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2077 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2078 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2079 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2080 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2081 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2082 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2083 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2084 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2085 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2086 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2087 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2088 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2089 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2090 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2091
2092 /* ADC PGA */
2093 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2094 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2095 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2096 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2097 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2098 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2099 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2100 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2101 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2102 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2103 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2104 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2105 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2106 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2107 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2108 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2109 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2110 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2111
2112 /* DSP */
2113 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2114 &rt5677_ib9_src_mux),
2115 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2116 &rt5677_ib8_src_mux),
2117 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2118 &rt5677_ib7_src_mux),
2119 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2120 &rt5677_ib6_src_mux),
2121 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2122 &rt5677_ib45_src_mux),
2123 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2124 &rt5677_ib23_src_mux),
2125 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2126 &rt5677_ib01_src_mux),
2127 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2128 &rt5677_ib45_bypass_src_mux),
2129 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2130 &rt5677_ib23_bypass_src_mux),
2131 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2132 &rt5677_ib01_bypass_src_mux),
2133 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2134 &rt5677_ob23_bypass_src_mux),
2135 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2136 &rt5677_ob01_bypass_src_mux),
2137
2138 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2139 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2140
2141 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2142 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2143 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2144 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2145 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2146 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2147
2148 /* Digital Interface */
2149 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2150 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2151 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2152 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2153 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2154 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2155 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2156 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2157 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2158 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2159 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2160 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2161 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2162 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2163 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2164 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2165 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2166 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2167
2168 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2169 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2170 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2171 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2172 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2173 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2174 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2175 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2176 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2177 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2178 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2179 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2180 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2181 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2182 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2183 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2184 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2185 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2186
2187 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2188 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2189 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2190 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2191 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2192 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2193 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2194 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2195
2196 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2197 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2198 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2199 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2200 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2201 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2202 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2203 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2204
2205 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2206 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2207 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2208 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2209 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2210 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2211 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2212 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2213 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2214 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2215 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2216 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2217 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2218 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2219 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2220 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2221 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2222 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2223
2224 /* Digital Interface Select */
2225 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2226 &rt5677_if1_adc1_mux),
2227 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2228 &rt5677_if1_adc2_mux),
2229 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2230 &rt5677_if1_adc3_mux),
2231 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2232 &rt5677_if1_adc4_mux),
2233 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2234 &rt5677_if2_adc1_mux),
2235 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2236 &rt5677_if2_adc2_mux),
2237 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2238 &rt5677_if2_adc3_mux),
2239 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2240 &rt5677_if2_adc4_mux),
2241 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2242 &rt5677_if3_adc_mux),
2243 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2244 &rt5677_if4_adc_mux),
2245 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2246 &rt5677_slb_adc1_mux),
2247 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2248 &rt5677_slb_adc2_mux),
2249 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2250 &rt5677_slb_adc3_mux),
2251 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2252 &rt5677_slb_adc4_mux),
2253
2254 /* Audio Interface */
2255 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2256 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2257 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2258 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2259 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2260 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2261 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2262 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2263 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2264 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2265
2266 /* Sidetone Mux */
2267 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2268 &rt5677_sidetone_mux),
90bdbb46
OC		 2269 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2270 RT5677_ST_EN_SFT, 0, NULL, 0),
2271
0e826e86
OC		 2272 /* VAD Mux*/
2273 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2274 &rt5677_vad_src_mux),
2275
2276 /* Tensilica DSP */
2277 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2278 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2279 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2280 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2281 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2282 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2283 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2284 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2285 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2286 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2287 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2288 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2289 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2290
2291 /* Output Side */
2292 /* DAC mixer before sound effect */
2293 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2294 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2295 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2296 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2297 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2298
2299 /* DAC Mux */
2300 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2301 &rt5677_dac1_mux),
2302 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2303 &rt5677_adda1_mux),
2304 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2305 &rt5677_dac12_mux),
2306 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2307 &rt5677_dac3_mux),
2308
2309 /* DAC2 channel Mux */
2310 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2311 &rt5677_dac2_l_mux),
2312 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2313 &rt5677_dac2_r_mux),
2314
2315 /* DAC3 channel Mux */
2316 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2317 &rt5677_dac3_l_mux),
2318 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2319 &rt5677_dac3_r_mux),
2320
2321 /* DAC4 channel Mux */
2322 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2323 &rt5677_dac4_l_mux),
2324 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2325 &rt5677_dac4_r_mux),
2326
2327 /* DAC Mixer */
2328 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2329 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2330 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2331 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2332 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2333 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2334
2335 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2336 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2337 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2338 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2339 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2340 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2341 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2342 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2343 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2344 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2345 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2346 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2347 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2348 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2349 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2350 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2351 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2352 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2353 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2354 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2355
2356 /* DACs */
2357 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2358 RT5677_PWR_DAC1_BIT, 0),
2359 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2360 RT5677_PWR_DAC2_BIT, 0),
2361 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2362 RT5677_PWR_DAC3_BIT, 0),
2363
2364 /* PDM */
2365 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2366 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2367 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2368 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2369
2370 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2371 1, &rt5677_pdm1_l_mux),
2372 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2373 1, &rt5677_pdm1_r_mux),
2374 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2375 1, &rt5677_pdm2_l_mux),
2376 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2377 1, &rt5677_pdm2_r_mux),
2378
2379 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2380 0, NULL, 0),
2381 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2382 0, NULL, 0),
2383 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2384 0, NULL, 0),
2385
2386 /* Output Lines */
2387 SND_SOC_DAPM_OUTPUT("LOUT1"),
2388 SND_SOC_DAPM_OUTPUT("LOUT2"),
2389 SND_SOC_DAPM_OUTPUT("LOUT3"),
2390 SND_SOC_DAPM_OUTPUT("PDM1L"),
2391 SND_SOC_DAPM_OUTPUT("PDM1R"),
2392 SND_SOC_DAPM_OUTPUT("PDM2L"),
2393 SND_SOC_DAPM_OUTPUT("PDM2R"),
2394};
2395
2396static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2397 { "DMIC1", NULL, "DMIC L1" },
2398 { "DMIC1", NULL, "DMIC R1" },
2399 { "DMIC2", NULL, "DMIC L2" },
2400 { "DMIC2", NULL, "DMIC R2" },
2401 { "DMIC3", NULL, "DMIC L3" },
2402 { "DMIC3", NULL, "DMIC R3" },
2403 { "DMIC4", NULL, "DMIC L4" },
2404 { "DMIC4", NULL, "DMIC R4" },
2405
2406 { "DMIC L1", NULL, "DMIC CLK" },
2407 { "DMIC R1", NULL, "DMIC CLK" },
2408 { "DMIC L2", NULL, "DMIC CLK" },
2409 { "DMIC R2", NULL, "DMIC CLK" },
2410 { "DMIC L3", NULL, "DMIC CLK" },
2411 { "DMIC R3", NULL, "DMIC CLK" },
2412 { "DMIC L4", NULL, "DMIC CLK" },
2413 { "DMIC R4", NULL, "DMIC CLK" },
2414
2d15d974
BL		 2415 { "DMIC L1", NULL, "DMIC1 power" },
2416 { "DMIC R1", NULL, "DMIC1 power" },
2417 { "DMIC L3", NULL, "DMIC3 power" },
2418 { "DMIC R3", NULL, "DMIC3 power" },
2419 { "DMIC L4", NULL, "DMIC4 power" },
2420 { "DMIC R4", NULL, "DMIC4 power" },
2421
0e826e86
OC		 2422 { "BST1", NULL, "IN1P" },
2423 { "BST1", NULL, "IN1N" },
2424 { "BST2", NULL, "IN2P" },
2425 { "BST2", NULL, "IN2N" },
2426
22e51345
BL		 2427 { "IN1P", NULL, "MICBIAS1" },
2428 { "IN1N", NULL, "MICBIAS1" },
2429 { "IN2P", NULL, "MICBIAS1" },
2430 { "IN2N", NULL, "MICBIAS1" },
0e826e86
OC		 2431
2432 { "ADC 1", NULL, "BST1" },
2433 { "ADC 1", NULL, "ADC 1 power" },
2434 { "ADC 1", NULL, "ADC1 clock" },
2435 { "ADC 2", NULL, "BST2" },
2436 { "ADC 2", NULL, "ADC 2 power" },
2437 { "ADC 2", NULL, "ADC2 clock" },
2438
2439 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2440 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2441 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2442 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2443
2444 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2445 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2446 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2447 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2448
2449 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2450 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2451 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2452 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2453
2454 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2455 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2456 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2457 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2458
2459 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2460 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2461 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2462 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2463
2464 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2465 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2466 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2467 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2468
2469 { "ADC 1_2", NULL, "ADC 1" },
2470 { "ADC 1_2", NULL, "ADC 2" },
2471
2472 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2473 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2474 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2475
2476 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2477 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2478 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2479
2480 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2481 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2482 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2483
2484 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2485 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2486 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2487
2488 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2489 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2490 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2491
2492 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2493 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2494 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2495
2496 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2497 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2498 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2499
2500 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2501 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2502 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2503
2504 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2505 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2506 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2507
2508 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2509 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2510 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2511
2512 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2513 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2514 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2515
2516 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2517 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2518 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2519
2520 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2521 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2522 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2523 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2524
2525 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2526 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2527 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2528
2529 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2530 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2531 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2532
2533 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2534 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2535
2536 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2537 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2538 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2539 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2540
2541 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2542 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2543
2544 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2545 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2546
2547 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2548 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2549 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2550
2551 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2552 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2553 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2554
2555 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2556 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2557
2558 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2559 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2560 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2561 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2562
2563 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2564 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2565 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2566
2567 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2568 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2569 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2570
2571 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2572 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2573
2574 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2575 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2576 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2577 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2578
2579 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2580 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2581 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2582
2583 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2584 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2585 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2586
2587 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2588 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2589
2590 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2591 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2592 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2593 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2594
2595 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2596 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2597 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2598 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2599
2600 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2601 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2602
2603 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2604 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2605 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2606 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2607 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2608
2609 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2610 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2611 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2612
2613 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2614 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2615
2616 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2617 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2618 { "IF1 ADC3 Mux", "OB45", "OB45" },
2619
2620 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2621 { "IF1 ADC4 Mux", "OB67", "OB67" },
2622 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2623
2624 { "AIF1TX", NULL, "I2S1" },
2625 { "AIF1TX", NULL, "IF1 ADC1 Mux" },
2626 { "AIF1TX", NULL, "IF1 ADC2 Mux" },
2627 { "AIF1TX", NULL, "IF1 ADC3 Mux" },
2628 { "AIF1TX", NULL, "IF1 ADC4 Mux" },
2629
2630 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2631 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2632 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2633
2634 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2635 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2636
2637 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2638 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2639 { "IF2 ADC3 Mux", "OB45", "OB45" },
2640
2641 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2642 { "IF2 ADC4 Mux", "OB67", "OB67" },
2643 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2644
2645 { "AIF2TX", NULL, "I2S2" },
2646 { "AIF2TX", NULL, "IF2 ADC1 Mux" },
2647 { "AIF2TX", NULL, "IF2 ADC2 Mux" },
2648 { "AIF2TX", NULL, "IF2 ADC3 Mux" },
2649 { "AIF2TX", NULL, "IF2 ADC4 Mux" },
2650
2651 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2652 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2653 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2654 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2655 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2656 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2657 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2658 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2659
2660 { "AIF3TX", NULL, "I2S3" },
2661 { "AIF3TX", NULL, "IF3 ADC Mux" },
2662
2663 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2664 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2665 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2666 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2667 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2668 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2669 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2670 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2671
2672 { "AIF4TX", NULL, "I2S4" },
2673 { "AIF4TX", NULL, "IF4 ADC Mux" },
2674
2675 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2676 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2677 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2678
2679 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2680 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2681
2682 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2683 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2684 { "SLB ADC3 Mux", "OB45", "OB45" },
2685
2686 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2687 { "SLB ADC4 Mux", "OB67", "OB67" },
2688 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2689
2690 { "SLBTX", NULL, "SLB" },
2691 { "SLBTX", NULL, "SLB ADC1 Mux" },
2692 { "SLBTX", NULL, "SLB ADC2 Mux" },
2693 { "SLBTX", NULL, "SLB ADC3 Mux" },
2694 { "SLBTX", NULL, "SLB ADC4 Mux" },
2695
2696 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2697 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2698 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2699 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2700 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2701
2702 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2703 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2704
2705 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2706 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2707 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2708 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2709 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2710 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2711
2712 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2713 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2714
2715 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2716 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2717 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2718 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2719 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2720
2721 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2722 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2723
2724 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2725 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2726 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2727 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2728 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2729 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2730 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2731 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2732
2733 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2734 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2735 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2736 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2737 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2738 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2739 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2740 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2741
2742 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2743 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2744 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2745 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2746 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2747 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2748
2749 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2750 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2751 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2752 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2753 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2754 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2755 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2756
2757 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2758 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2759 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2760 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2761 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2762 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2763 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2764
2765 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2766 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2767 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2768 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2769 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2770 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2771 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2772
2773 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2774 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2775 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2776 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2777 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2778 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2779 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2780
2781 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2782 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2783 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2784 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
2785 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
2786 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
2787 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
2788
2789 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2790 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2791 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2792 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
2793 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
2794 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
2795 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
2796
2797 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2798 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2799 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2800 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
2801 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
2802 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
2803 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
2804
2805 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
2806 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
2807 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
2808 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
2809
2810 { "OutBound2", NULL, "OB23 Bypass Mux" },
2811 { "OutBound3", NULL, "OB23 Bypass Mux" },
2812 { "OutBound4", NULL, "OB4 MIX" },
2813 { "OutBound5", NULL, "OB5 MIX" },
2814 { "OutBound6", NULL, "OB6 MIX" },
2815 { "OutBound7", NULL, "OB7 MIX" },
2816
2817 { "OB45", NULL, "OutBound4" },
2818 { "OB45", NULL, "OutBound5" },
2819 { "OB67", NULL, "OutBound6" },
2820 { "OB67", NULL, "OutBound7" },
2821
2822 { "IF1 DAC0", NULL, "AIF1RX" },
2823 { "IF1 DAC1", NULL, "AIF1RX" },
2824 { "IF1 DAC2", NULL, "AIF1RX" },
2825 { "IF1 DAC3", NULL, "AIF1RX" },
2826 { "IF1 DAC4", NULL, "AIF1RX" },
2827 { "IF1 DAC5", NULL, "AIF1RX" },
2828 { "IF1 DAC6", NULL, "AIF1RX" },
2829 { "IF1 DAC7", NULL, "AIF1RX" },
2830 { "IF1 DAC0", NULL, "I2S1" },
2831 { "IF1 DAC1", NULL, "I2S1" },
2832 { "IF1 DAC2", NULL, "I2S1" },
2833 { "IF1 DAC3", NULL, "I2S1" },
2834 { "IF1 DAC4", NULL, "I2S1" },
2835 { "IF1 DAC5", NULL, "I2S1" },
2836 { "IF1 DAC6", NULL, "I2S1" },
2837 { "IF1 DAC7", NULL, "I2S1" },
2838
2839 { "IF1 DAC01", NULL, "IF1 DAC0" },
2840 { "IF1 DAC01", NULL, "IF1 DAC1" },
2841 { "IF1 DAC23", NULL, "IF1 DAC2" },
2842 { "IF1 DAC23", NULL, "IF1 DAC3" },
2843 { "IF1 DAC45", NULL, "IF1 DAC4" },
2844 { "IF1 DAC45", NULL, "IF1 DAC5" },
2845 { "IF1 DAC67", NULL, "IF1 DAC6" },
2846 { "IF1 DAC67", NULL, "IF1 DAC7" },
2847
2848 { "IF2 DAC0", NULL, "AIF2RX" },
2849 { "IF2 DAC1", NULL, "AIF2RX" },
2850 { "IF2 DAC2", NULL, "AIF2RX" },
2851 { "IF2 DAC3", NULL, "AIF2RX" },
2852 { "IF2 DAC4", NULL, "AIF2RX" },
2853 { "IF2 DAC5", NULL, "AIF2RX" },
2854 { "IF2 DAC6", NULL, "AIF2RX" },
2855 { "IF2 DAC7", NULL, "AIF2RX" },
2856 { "IF2 DAC0", NULL, "I2S2" },
2857 { "IF2 DAC1", NULL, "I2S2" },
2858 { "IF2 DAC2", NULL, "I2S2" },
2859 { "IF2 DAC3", NULL, "I2S2" },
2860 { "IF2 DAC4", NULL, "I2S2" },
2861 { "IF2 DAC5", NULL, "I2S2" },
2862 { "IF2 DAC6", NULL, "I2S2" },
2863 { "IF2 DAC7", NULL, "I2S2" },
2864
2865 { "IF2 DAC01", NULL, "IF2 DAC0" },
2866 { "IF2 DAC01", NULL, "IF2 DAC1" },
2867 { "IF2 DAC23", NULL, "IF2 DAC2" },
2868 { "IF2 DAC23", NULL, "IF2 DAC3" },
2869 { "IF2 DAC45", NULL, "IF2 DAC4" },
2870 { "IF2 DAC45", NULL, "IF2 DAC5" },
2871 { "IF2 DAC67", NULL, "IF2 DAC6" },
2872 { "IF2 DAC67", NULL, "IF2 DAC7" },
2873
2874 { "IF3 DAC", NULL, "AIF3RX" },
2875 { "IF3 DAC", NULL, "I2S3" },
2876
2877 { "IF4 DAC", NULL, "AIF4RX" },
2878 { "IF4 DAC", NULL, "I2S4" },
2879
2880 { "IF3 DAC L", NULL, "IF3 DAC" },
2881 { "IF3 DAC R", NULL, "IF3 DAC" },
2882
2883 { "IF4 DAC L", NULL, "IF4 DAC" },
2884 { "IF4 DAC R", NULL, "IF4 DAC" },
2885
2886 { "SLB DAC0", NULL, "SLBRX" },
2887 { "SLB DAC1", NULL, "SLBRX" },
2888 { "SLB DAC2", NULL, "SLBRX" },
2889 { "SLB DAC3", NULL, "SLBRX" },
2890 { "SLB DAC4", NULL, "SLBRX" },
2891 { "SLB DAC5", NULL, "SLBRX" },
2892 { "SLB DAC6", NULL, "SLBRX" },
2893 { "SLB DAC7", NULL, "SLBRX" },
2894 { "SLB DAC0", NULL, "SLB" },
2895 { "SLB DAC1", NULL, "SLB" },
2896 { "SLB DAC2", NULL, "SLB" },
2897 { "SLB DAC3", NULL, "SLB" },
2898 { "SLB DAC4", NULL, "SLB" },
2899 { "SLB DAC5", NULL, "SLB" },
2900 { "SLB DAC6", NULL, "SLB" },
2901 { "SLB DAC7", NULL, "SLB" },
2902
2903 { "SLB DAC01", NULL, "SLB DAC0" },
2904 { "SLB DAC01", NULL, "SLB DAC1" },
2905 { "SLB DAC23", NULL, "SLB DAC2" },
2906 { "SLB DAC23", NULL, "SLB DAC3" },
2907 { "SLB DAC45", NULL, "SLB DAC4" },
2908 { "SLB DAC45", NULL, "SLB DAC5" },
2909 { "SLB DAC67", NULL, "SLB DAC6" },
2910 { "SLB DAC67", NULL, "SLB DAC7" },
2911
2912 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2913 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2914 { "ADDA1 Mux", "OB 67", "OB67" },
2915
2916 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
2917 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
2918 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
2919 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
2920 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
2921 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
2922
2923 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
2924 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
2925 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2926 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
2927 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
2928 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2929
2930 { "DAC1 FS", NULL, "DAC1 MIXL" },
2931 { "DAC1 FS", NULL, "DAC1 MIXR" },
2932
2933 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
2934 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
2935 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
2936 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
2937 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
2938 { "DAC2 L Mux", "OB 2", "OutBound2" },
2939
2940 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
2941 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
2942 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
2943 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
2944 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
2945 { "DAC2 R Mux", "OB 3", "OutBound3" },
2946 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
2947 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
2948
2949 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
2950 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
2951 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
2952 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
2953 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
2954 { "DAC3 L Mux", "OB 4", "OutBound4" },
2955
2956 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
2957 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
2958 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
2959 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
2960 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
2961 { "DAC3 R Mux", "OB 5", "OutBound5" },
2962
2963 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
2964 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
2965 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
2966 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
2967 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
2968 { "DAC4 L Mux", "OB 6", "OutBound6" },
2969
2970 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
2971 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
2972 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
2973 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
2974 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
2975 { "DAC4 R Mux", "OB 7", "OutBound7" },
2976
2977 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
2978 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
2979 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
2980 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
2981 { "Sidetone Mux", "ADC1", "ADC 1" },
2982 { "Sidetone Mux", "ADC2", "ADC 2" },
90bdbb46 2983 { "Sidetone Mux", NULL, "Sidetone Power" },
0e826e86
OC		 2984
2985 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
2986 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2987 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2988 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
2989 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2990 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
2991 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2992 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2993 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
2994 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2995
2996 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
2997 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2998 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2999 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3000 { "Mono DAC MIXL", NULL, "dac mono left filter" },
3001 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3002 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3003 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3004 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3005 { "Mono DAC MIXR", NULL, "dac mono right filter" },
3006
3007 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3008 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3009 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3010 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3011 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3012 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3013 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3014 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
3015
3016 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3017 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3018 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3019 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
3020 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3021 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3022 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3023 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
3024
3025 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3026 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3027 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3028 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3029 { "DD1 MIX", NULL, "DD1 MIXL" },
3030 { "DD1 MIX", NULL, "DD1 MIXR" },
3031 { "DD2 MIX", NULL, "DD2 MIXL" },
3032 { "DD2 MIX", NULL, "DD2 MIXR" },
3033
3034 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3035 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3036 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3037 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3038
3039 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3040 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3041 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3042 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3043
3044 { "DAC 1", NULL, "DAC12 SRC Mux" },
3045 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
3046 { "DAC 2", NULL, "DAC12 SRC Mux" },
3047 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
3048 { "DAC 3", NULL, "DAC3 SRC Mux" },
3049 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
3050
3051 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3052 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3053 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3054 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3055 { "PDM1 L Mux", NULL, "PDM1 Power" },
3056 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3057 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3058 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3059 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3060 { "PDM1 R Mux", NULL, "PDM1 Power" },
3061 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3062 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3063 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3064 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3065 { "PDM2 L Mux", NULL, "PDM2 Power" },
3066 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3067 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3068 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3069 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3070 { "PDM2 R Mux", NULL, "PDM2 Power" },
3071
3072 { "LOUT1 amp", NULL, "DAC 1" },
3073 { "LOUT2 amp", NULL, "DAC 2" },
3074 { "LOUT3 amp", NULL, "DAC 3" },
3075
3076 { "LOUT1", NULL, "LOUT1 amp" },
3077 { "LOUT2", NULL, "LOUT2 amp" },
3078 { "LOUT3", NULL, "LOUT3 amp" },
3079
3080 { "PDM1L", NULL, "PDM1 L Mux" },
3081 { "PDM1R", NULL, "PDM1 R Mux" },
3082 { "PDM2L", NULL, "PDM2 L Mux" },
3083 { "PDM2R", NULL, "PDM2 R Mux" },
3084};
3085
2d15d974
BL		 3086static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3087 { "DMIC L2", NULL, "DMIC1 power" },
3088 { "DMIC R2", NULL, "DMIC1 power" },
3089};
3090
3091static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3092 { "DMIC L2", NULL, "DMIC2 power" },
3093 { "DMIC R2", NULL, "DMIC2 power" },
3094};
3095
0e826e86
OC		 3096static int rt5677_hw_params(struct snd_pcm_substream *substream,
3097 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3098{
3099 struct snd_soc_codec *codec = dai->codec;
3100 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3101 unsigned int val_len = 0, val_clk, mask_clk;
3102 int pre_div, bclk_ms, frame_size;
3103
3104 rt5677->lrck[dai->id] = params_rate(params);
30f14b43 3105 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86 3106 if (pre_div < 0) {
8a4bd60a
AP		 3107 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3108 rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86
OC		 3109 return -EINVAL;
3110 }
3111 frame_size = snd_soc_params_to_frame_size(params);
3112 if (frame_size < 0) {
3113 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3114 return -EINVAL;
3115 }
3116 bclk_ms = frame_size > 32;
3117 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
3118
3119 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
3120 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
3121 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
3122 bclk_ms, pre_div, dai->id);
3123
3124 switch (params_width(params)) {
3125 case 16:
3126 break;
3127 case 20:
3128 val_len |= RT5677_I2S_DL_20;
3129 break;
3130 case 24:
3131 val_len |= RT5677_I2S_DL_24;
3132 break;
3133 case 8:
3134 val_len |= RT5677_I2S_DL_8;
3135 break;
3136 default:
3137 return -EINVAL;
3138 }
3139
3140 switch (dai->id) {
3141 case RT5677_AIF1:
3142 mask_clk = RT5677_I2S_PD1_MASK;
3143 val_clk = pre_div << RT5677_I2S_PD1_SFT;
3144 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3145 RT5677_I2S_DL_MASK, val_len);
3146 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3147 mask_clk, val_clk);
3148 break;
3149 case RT5677_AIF2:
3150 mask_clk = RT5677_I2S_PD2_MASK;
3151 val_clk = pre_div << RT5677_I2S_PD2_SFT;
3152 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3153 RT5677_I2S_DL_MASK, val_len);
3154 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3155 mask_clk, val_clk);
3156 break;
3157 case RT5677_AIF3:
3158 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
3159 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
3160 pre_div << RT5677_I2S_PD3_SFT;
3161 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3162 RT5677_I2S_DL_MASK, val_len);
3163 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3164 mask_clk, val_clk);
3165 break;
3166 case RT5677_AIF4:
3167 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
3168 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
3169 pre_div << RT5677_I2S_PD4_SFT;
3170 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3171 RT5677_I2S_DL_MASK, val_len);
3172 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3173 mask_clk, val_clk);
3174 break;
3175 default:
3176 break;
3177 }
3178
3179 return 0;
3180}
3181
3182static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3183{
3184 struct snd_soc_codec *codec = dai->codec;
3185 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3186 unsigned int reg_val = 0;
3187
3188 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3189 case SND_SOC_DAIFMT_CBM_CFM:
3190 rt5677->master[dai->id] = 1;
3191 break;
3192 case SND_SOC_DAIFMT_CBS_CFS:
3193 reg_val |= RT5677_I2S_MS_S;
3194 rt5677->master[dai->id] = 0;
3195 break;
3196 default:
3197 return -EINVAL;
3198 }
3199
3200 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3201 case SND_SOC_DAIFMT_NB_NF:
3202 break;
3203 case SND_SOC_DAIFMT_IB_NF:
3204 reg_val |= RT5677_I2S_BP_INV;
3205 break;
3206 default:
3207 return -EINVAL;
3208 }
3209
3210 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3211 case SND_SOC_DAIFMT_I2S:
3212 break;
3213 case SND_SOC_DAIFMT_LEFT_J:
3214 reg_val |= RT5677_I2S_DF_LEFT;
3215 break;
3216 case SND_SOC_DAIFMT_DSP_A:
3217 reg_val |= RT5677_I2S_DF_PCM_A;
3218 break;
3219 case SND_SOC_DAIFMT_DSP_B:
3220 reg_val |= RT5677_I2S_DF_PCM_B;
3221 break;
3222 default:
3223 return -EINVAL;
3224 }
3225
3226 switch (dai->id) {
3227 case RT5677_AIF1:
3228 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3229 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3230 RT5677_I2S_DF_MASK, reg_val);
3231 break;
3232 case RT5677_AIF2:
3233 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3234 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3235 RT5677_I2S_DF_MASK, reg_val);
3236 break;
3237 case RT5677_AIF3:
3238 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3239 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3240 RT5677_I2S_DF_MASK, reg_val);
3241 break;
3242 case RT5677_AIF4:
3243 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3244 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3245 RT5677_I2S_DF_MASK, reg_val);
3246 break;
3247 default:
3248 break;
3249 }
3250
3251
3252 return 0;
3253}
3254
3255static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3256 int clk_id, unsigned int freq, int dir)
3257{
3258 struct snd_soc_codec *codec = dai->codec;
3259 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3260 unsigned int reg_val = 0;
3261
3262 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
3263 return 0;
3264
3265 switch (clk_id) {
3266 case RT5677_SCLK_S_MCLK:
3267 reg_val |= RT5677_SCLK_SRC_MCLK;
3268 break;
3269 case RT5677_SCLK_S_PLL1:
3270 reg_val |= RT5677_SCLK_SRC_PLL1;
3271 break;
3272 case RT5677_SCLK_S_RCCLK:
3273 reg_val |= RT5677_SCLK_SRC_RCCLK;
3274 break;
3275 default:
3276 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3277 return -EINVAL;
3278 }
3279 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3280 RT5677_SCLK_SRC_MASK, reg_val);
3281 rt5677->sysclk = freq;
3282 rt5677->sysclk_src = clk_id;
3283
3284 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3285
3286 return 0;
3287}
3288
3289/**
3290 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3291 * @freq_in: external clock provided to codec.
3292 * @freq_out: target clock which codec works on.
3293 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3294 *
3295 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3296 *
3297 * Returns 0 for success or negative error code.
3298 */
3299static int rt5677_pll_calc(const unsigned int freq_in,
099d334e 3300 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
0e826e86 3301{
099d334e 3302 if (RT5677_PLL_INP_MIN > freq_in)
0e826e86
OC		 3303 return -EINVAL;
3304
099d334e 3305 return rl6231_pll_calc(freq_in, freq_out, pll_code);
0e826e86
OC		 3306}
3307
3308static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3309 unsigned int freq_in, unsigned int freq_out)
3310{
3311 struct snd_soc_codec *codec = dai->codec;
3312 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
099d334e 3313 struct rl6231_pll_code pll_code;
0e826e86
OC		 3314 int ret;
3315
3316 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3317 freq_out == rt5677->pll_out)
3318 return 0;
3319
3320 if (!freq_in || !freq_out) {
3321 dev_dbg(codec->dev, "PLL disabled\n");
3322
3323 rt5677->pll_in = 0;
3324 rt5677->pll_out = 0;
3325 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3326 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3327 return 0;
3328 }
3329
3330 switch (source) {
3331 case RT5677_PLL1_S_MCLK:
3332 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3333 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3334 break;
3335 case RT5677_PLL1_S_BCLK1:
3336 case RT5677_PLL1_S_BCLK2:
3337 case RT5677_PLL1_S_BCLK3:
3338 case RT5677_PLL1_S_BCLK4:
3339 switch (dai->id) {
3340 case RT5677_AIF1:
3341 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3342 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3343 break;
3344 case RT5677_AIF2:
3345 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3346 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3347 break;
3348 case RT5677_AIF3:
3349 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3350 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3351 break;
3352 case RT5677_AIF4:
3353 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3354 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3355 break;
3356 default:
3357 break;
3358 }
3359 break;
3360 default:
3361 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3362 return -EINVAL;
3363 }
3364
3365 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3366 if (ret < 0) {
3367 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3368 return ret;
3369 }
3370
099d334e
AL		 3371 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
3372 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3373 pll_code.n_code, pll_code.k_code);
0e826e86
OC		 3374
3375 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
099d334e 3376 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
0e826e86
OC		 3377 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3378 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3379 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3380
3381 rt5677->pll_in = freq_in;
3382 rt5677->pll_out = freq_out;
3383 rt5677->pll_src = source;
3384
3385 return 0;
3386}
3387
48561afe
OC		 3388static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3389 unsigned int rx_mask, int slots, int slot_width)
3390{
3391 struct snd_soc_codec *codec = dai->codec;
3392 unsigned int val = 0;
3393
3394 if (rx_mask || tx_mask)
3395 val |= (1 << 12);
3396
3397 switch (slots) {
3398 case 4:
3399 val |= (1 << 10);
3400 break;
3401 case 6:
3402 val |= (2 << 10);
3403 break;
3404 case 8:
3405 val |= (3 << 10);
3406 break;
3407 case 2:
3408 default:
3409 break;
3410 }
3411
3412 switch (slot_width) {
3413 case 20:
3414 val |= (1 << 8);
3415 break;
3416 case 24:
3417 val |= (2 << 8);
3418 break;
3419 case 32:
3420 val |= (3 << 8);
3421 break;
3422 case 16:
3423 default:
3424 break;
3425 }
3426
3427 switch (dai->id) {
3428 case RT5677_AIF1:
3429 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val);
3430 break;
3431 case RT5677_AIF2:
3432 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val);
3433 break;
3434 default:
3435 break;
3436 }
3437
3438 return 0;
3439}
3440
0e826e86
OC		 3441static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3442 enum snd_soc_bias_level level)
3443{
3444 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3445
3446 switch (level) {
3447 case SND_SOC_BIAS_ON:
3448 break;
3449
3450 case SND_SOC_BIAS_PREPARE:
3451 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
af48f1d0
OC		 3452 rt5677_set_dsp_vad(codec, false);
3453
0e826e86
OC		 3454 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3455 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3456 0x0055);
3457 regmap_update_bits(rt5677->regmap,
3458 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3459 0x0f00, 0x0f00);
3460 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3461 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3462 RT5677_PWR_BG | RT5677_PWR_VREF2,
3463 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3464 RT5677_PWR_BG | RT5677_PWR_VREF2);
3465 mdelay(20);
3466 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3467 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3468 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3469 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3470 RT5677_PWR_CORE, RT5677_PWR_CORE);
3471 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3472 0x1, 0x1);
3473 }
3474 break;
3475
3476 case SND_SOC_BIAS_STANDBY:
3477 break;
3478
3479 case SND_SOC_BIAS_OFF:
3480 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3481 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3482 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
f18803a3 3483 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
0e826e86
OC		 3484 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3485 regmap_update_bits(rt5677->regmap,
3486 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
af48f1d0
OC		 3487
3488 if (rt5677->dsp_vad_en)
3489 rt5677_set_dsp_vad(codec, true);
0e826e86
OC		 3490 break;
3491
3492 default:
3493 break;
3494 }
3495 codec->dapm.bias_level = level;
3496
3497 return 0;
3498}
3499
44caf764
OC		 3500#ifdef CONFIG_GPIOLIB
3501static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
3502{
3503 return container_of(chip, struct rt5677_priv, gpio_chip);
3504}
3505
3506static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3507{
3508 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3509
3510 switch (offset) {
3511 case RT5677_GPIO1 ... RT5677_GPIO5:
3512 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3513 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
3514 break;
3515
3516 case RT5677_GPIO6:
3517 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3518 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
3519 break;
3520
3521 default:
3522 break;
3523 }
3524}
3525
3526static int rt5677_gpio_direction_out(struct gpio_chip *chip,
3527 unsigned offset, int value)
3528{
3529 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3530
3531 switch (offset) {
3532 case RT5677_GPIO1 ... RT5677_GPIO5:
3533 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3534 0x3 << (offset * 3 + 1),
3535 (0x2 | !!value) << (offset * 3 + 1));
3536 break;
3537
3538 case RT5677_GPIO6:
3539 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3540 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
3541 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
3542 break;
3543
3544 default:
3545 break;
3546 }
3547
3548 return 0;
3549}
3550
3551static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
3552{
3553 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3554 int value, ret;
3555
3556 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
3557 if (ret < 0)
3558 return ret;
3559
3560 return (value & (0x1 << offset)) >> offset;
3561}
3562
3563static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
3564{
3565 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3566
3567 switch (offset) {
3568 case RT5677_GPIO1 ... RT5677_GPIO5:
3569 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3570 0x1 << (offset * 3 + 2), 0x0);
3571 break;
3572
3573 case RT5677_GPIO6:
3574 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3575 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
3576 break;
3577
3578 default:
3579 break;
3580 }
3581
3582 return 0;
3583}
3584
40eb90a1
AP		 3585/** Configures the gpio as
3586 * 0 - floating
3587 * 1 - pull down
3588 * 2 - pull up
3589 */
3590static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
3591 int value)
3592{
3593 int shift;
3594
3595 switch (offset) {
3596 case RT5677_GPIO1 ... RT5677_GPIO2:
3597 shift = 2 * (1 - offset);
3598 regmap_update_bits(rt5677->regmap,
3599 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
3600 0x3 << shift,
3601 (value & 0x3) << shift);
3602 break;
3603
3604 case RT5677_GPIO3 ... RT5677_GPIO6:
3605 shift = 2 * (9 - offset);
3606 regmap_update_bits(rt5677->regmap,
3607 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
3608 0x3 << shift,
3609 (value & 0x3) << shift);
3610 break;
3611
3612 default:
3613 break;
3614 }
3615}
3616
44caf764
OC		 3617static struct gpio_chip rt5677_template_chip = {
3618 .label = "rt5677",
3619 .owner = THIS_MODULE,
3620 .direction_output = rt5677_gpio_direction_out,
3621 .set = rt5677_gpio_set,
3622 .direction_input = rt5677_gpio_direction_in,
3623 .get = rt5677_gpio_get,
3624 .can_sleep = 1,
3625};
3626
3627static void rt5677_init_gpio(struct i2c_client *i2c)
3628{
3629 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
3630 int ret;
3631
3632 rt5677->gpio_chip = rt5677_template_chip;
3633 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
3634 rt5677->gpio_chip.dev = &i2c->dev;
3635 rt5677->gpio_chip.base = -1;
3636
3637 ret = gpiochip_add(&rt5677->gpio_chip);
3638 if (ret != 0)
3639 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
3640}
3641
3642static void rt5677_free_gpio(struct i2c_client *i2c)
3643{
3644 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
44caf764 3645
5d5e63af 3646 gpiochip_remove(&rt5677->gpio_chip);
44caf764
OC		 3647}
3648#else
3649static void rt5677_init_gpio(struct i2c_client *i2c)
3650{
3651}
3652
3653static void rt5677_free_gpio(struct i2c_client *i2c)
3654{
3655}
3656#endif
3657
0e826e86
OC		 3658static int rt5677_probe(struct snd_soc_codec *codec)
3659{
3660 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
40eb90a1 3661 int i;
0e826e86
OC		 3662
3663 rt5677->codec = codec;
3664
2d15d974
BL		 3665 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3666 snd_soc_dapm_add_routes(&codec->dapm,
3667 rt5677_dmic2_clk_2,
3668 ARRAY_SIZE(rt5677_dmic2_clk_2));
3669 } else { /*use dmic1 clock by default*/
3670 snd_soc_dapm_add_routes(&codec->dapm,
3671 rt5677_dmic2_clk_1,
3672 ARRAY_SIZE(rt5677_dmic2_clk_1));
3673 }
3674
0e826e86
OC		 3675 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3676
3677 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3678 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3679
40eb90a1
AP		 3680 for (i = 0; i < RT5677_GPIO_NUM; i++)
3681 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
3682
af48f1d0
OC		 3683 mutex_init(&rt5677->dsp_cmd_lock);
3684
0e826e86
OC		 3685 return 0;
3686}
3687
3688static int rt5677_remove(struct snd_soc_codec *codec)
3689{
3690 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3691
3692 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
f9f6a592
AP		 3693 if (gpio_is_valid(rt5677->pow_ldo2))
3694 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
0e826e86
OC		 3695
3696 return 0;
3697}
3698
3699#ifdef CONFIG_PM
3700static int rt5677_suspend(struct snd_soc_codec *codec)
3701{
3702 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3703
af48f1d0
OC		 3704 if (!rt5677->dsp_vad_en) {
3705 regcache_cache_only(rt5677->regmap, true);
3706 regcache_mark_dirty(rt5677->regmap);
3707 }
3708
f9f6a592
AP		 3709 if (gpio_is_valid(rt5677->pow_ldo2))
3710 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
0e826e86
OC		 3711
3712 return 0;
3713}
3714
3715static int rt5677_resume(struct snd_soc_codec *codec)
3716{
3717 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3718
f9f6a592
AP		 3719 if (gpio_is_valid(rt5677->pow_ldo2)) {
3720 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
3721 msleep(10);
3722 }
af48f1d0
OC		 3723
3724 if (!rt5677->dsp_vad_en) {
3725 regcache_cache_only(rt5677->regmap, false);
3726 regcache_sync(rt5677->regmap);
3727 }
0e826e86
OC		 3728
3729 return 0;
3730}
3731#else
3732#define rt5677_suspend NULL
3733#define rt5677_resume NULL
3734#endif
3735
3736#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3737#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3738 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3739
3740static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
3741 .hw_params = rt5677_hw_params,
3742 .set_fmt = rt5677_set_dai_fmt,
3743 .set_sysclk = rt5677_set_dai_sysclk,
3744 .set_pll = rt5677_set_dai_pll,
48561afe 3745 .set_tdm_slot = rt5677_set_tdm_slot,
0e826e86
OC		 3746};
3747
3748static struct snd_soc_dai_driver rt5677_dai[] = {
3749 {
3750 .name = "rt5677-aif1",
3751 .id = RT5677_AIF1,
3752 .playback = {
3753 .stream_name = "AIF1 Playback",
3754 .channels_min = 1,
3755 .channels_max = 2,
3756 .rates = RT5677_STEREO_RATES,
3757 .formats = RT5677_FORMATS,
3758 },
3759 .capture = {
3760 .stream_name = "AIF1 Capture",
3761 .channels_min = 1,
3762 .channels_max = 2,
3763 .rates = RT5677_STEREO_RATES,
3764 .formats = RT5677_FORMATS,
3765 },
3766 .ops = &rt5677_aif_dai_ops,
3767 },
3768 {
3769 .name = "rt5677-aif2",
3770 .id = RT5677_AIF2,
3771 .playback = {
3772 .stream_name = "AIF2 Playback",
3773 .channels_min = 1,
3774 .channels_max = 2,
3775 .rates = RT5677_STEREO_RATES,
3776 .formats = RT5677_FORMATS,
3777 },
3778 .capture = {
3779 .stream_name = "AIF2 Capture",
3780 .channels_min = 1,
3781 .channels_max = 2,
3782 .rates = RT5677_STEREO_RATES,
3783 .formats = RT5677_FORMATS,
3784 },
3785 .ops = &rt5677_aif_dai_ops,
3786 },
3787 {
3788 .name = "rt5677-aif3",
3789 .id = RT5677_AIF3,
3790 .playback = {
3791 .stream_name = "AIF3 Playback",
3792 .channels_min = 1,
3793 .channels_max = 2,
3794 .rates = RT5677_STEREO_RATES,
3795 .formats = RT5677_FORMATS,
3796 },
3797 .capture = {
3798 .stream_name = "AIF3 Capture",
3799 .channels_min = 1,
3800 .channels_max = 2,
3801 .rates = RT5677_STEREO_RATES,
3802 .formats = RT5677_FORMATS,
3803 },
3804 .ops = &rt5677_aif_dai_ops,
3805 },
3806 {
3807 .name = "rt5677-aif4",
3808 .id = RT5677_AIF4,
3809 .playback = {
3810 .stream_name = "AIF4 Playback",
3811 .channels_min = 1,
3812 .channels_max = 2,
3813 .rates = RT5677_STEREO_RATES,
3814 .formats = RT5677_FORMATS,
3815 },
3816 .capture = {
3817 .stream_name = "AIF4 Capture",
3818 .channels_min = 1,
3819 .channels_max = 2,
3820 .rates = RT5677_STEREO_RATES,
3821 .formats = RT5677_FORMATS,
3822 },
3823 .ops = &rt5677_aif_dai_ops,
3824 },
3825 {
3826 .name = "rt5677-slimbus",
3827 .id = RT5677_AIF5,
3828 .playback = {
3829 .stream_name = "SLIMBus Playback",
3830 .channels_min = 1,
3831 .channels_max = 2,
3832 .rates = RT5677_STEREO_RATES,
3833 .formats = RT5677_FORMATS,
3834 },
3835 .capture = {
3836 .stream_name = "SLIMBus Capture",
3837 .channels_min = 1,
3838 .channels_max = 2,
3839 .rates = RT5677_STEREO_RATES,
3840 .formats = RT5677_FORMATS,
3841 },
3842 .ops = &rt5677_aif_dai_ops,
3843 },
3844};
3845
3846static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
3847 .probe = rt5677_probe,
3848 .remove = rt5677_remove,
3849 .suspend = rt5677_suspend,
3850 .resume = rt5677_resume,
3851 .set_bias_level = rt5677_set_bias_level,
3852 .idle_bias_off = true,
3853 .controls = rt5677_snd_controls,
3854 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
3855 .dapm_widgets = rt5677_dapm_widgets,
3856 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
3857 .dapm_routes = rt5677_dapm_routes,
3858 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
3859};
3860
3861static const struct regmap_config rt5677_regmap = {
3862 .reg_bits = 8,
3863 .val_bits = 16,
3864
3865 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
3866 RT5677_PR_SPACING),
3867
3868 .volatile_reg = rt5677_volatile_register,
3869 .readable_reg = rt5677_readable_register,
3870
3871 .cache_type = REGCACHE_RBTREE,
3872 .reg_defaults = rt5677_reg,
3873 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
3874 .ranges = rt5677_ranges,
3875 .num_ranges = ARRAY_SIZE(rt5677_ranges),
3876};
3877
3878static const struct i2c_device_id rt5677_i2c_id[] = {
3879 { "rt5677", 0 },
3880 { }
3881};
3882MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
3883
f9f6a592
AP		 3884static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
3885{
6f67c380
AP		 3886 rt5677->pdata.in1_diff = of_property_read_bool(np,
3887 "realtek,in1-differential");
3888 rt5677->pdata.in2_diff = of_property_read_bool(np,
3889 "realtek,in2-differential");
3890 rt5677->pdata.lout1_diff = of_property_read_bool(np,
3891 "realtek,lout1-differential");
3892 rt5677->pdata.lout2_diff = of_property_read_bool(np,
3893 "realtek,lout2-differential");
3894 rt5677->pdata.lout3_diff = of_property_read_bool(np,
3895 "realtek,lout3-differential");
3896
f9f6a592
AP		 3897 rt5677->pow_ldo2 = of_get_named_gpio(np,
3898 "realtek,pow-ldo2-gpio", 0);
3899
3900 /*
3901 * POW_LDO2 is optional (it may be statically tied on the board).
3902 * -ENOENT means that the property doesn't exist, i.e. there is no
3903 * GPIO, so is not an error. Any other error code means the property
3904 * exists, but could not be parsed.
3905 */
3906 if (!gpio_is_valid(rt5677->pow_ldo2) &&
3907 (rt5677->pow_ldo2 != -ENOENT))
3908 return rt5677->pow_ldo2;
3909
40eb90a1
AP		 3910 of_property_read_u8_array(np, "realtek,gpio-config",
3911 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
3912
f9f6a592
AP		 3913 return 0;
3914}
3915
0e826e86
OC		 3916static int rt5677_i2c_probe(struct i2c_client *i2c,
3917 const struct i2c_device_id *id)
3918{
3919 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
3920 struct rt5677_priv *rt5677;
3921 int ret;
3922 unsigned int val;
3923
3924 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
3925 GFP_KERNEL);
3926 if (rt5677 == NULL)
3927 return -ENOMEM;
3928
3929 i2c_set_clientdata(i2c, rt5677);
3930
3931 if (pdata)
3932 rt5677->pdata = *pdata;
3933
f9f6a592
AP		 3934 if (i2c->dev.of_node) {
3935 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
3936 if (ret) {
3937 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
3938 ret);
3939 return ret;
3940 }
3941 } else {
3942 rt5677->pow_ldo2 = -EINVAL;
3943 }
3944
3945 if (gpio_is_valid(rt5677->pow_ldo2)) {
3946 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
3947 GPIOF_OUT_INIT_HIGH,
3948 "RT5677 POW_LDO2");
3949 if (ret < 0) {
3950 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
3951 rt5677->pow_ldo2, ret);
3952 return ret;
3953 }
3954 /* Wait a while until I2C bus becomes available. The datasheet
3955 * does not specify the exact we should wait but startup
3956 * sequence mentiones at least a few milliseconds.
3957 */
3958 msleep(10);
3959 }
3960
0e826e86
OC		 3961 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
3962 if (IS_ERR(rt5677->regmap)) {
3963 ret = PTR_ERR(rt5677->regmap);
3964 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3965 ret);
3966 return ret;
3967 }
3968
3969 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
3970 if (val != RT5677_DEVICE_ID) {
3971 dev_err(&i2c->dev,
3972 "Device with ID register %x is not rt5677\n", val);
3973 return -ENODEV;
3974 }
3975
3976 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3977
3978 ret = regmap_register_patch(rt5677->regmap, init_list,
3979 ARRAY_SIZE(init_list));
3980 if (ret != 0)
3981 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3982
3983 if (rt5677->pdata.in1_diff)
3984 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3985 RT5677_IN_DF1, RT5677_IN_DF1);
3986
3987 if (rt5677->pdata.in2_diff)
3988 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3989 RT5677_IN_DF2, RT5677_IN_DF2);
3990
6f67c380
AP		 3991 if (rt5677->pdata.lout1_diff)
3992 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
3993 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
3994
3995 if (rt5677->pdata.lout2_diff)
3996 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
3997 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
3998
3999 if (rt5677->pdata.lout3_diff)
4000 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4001 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
4002
2d15d974
BL		 4003 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4004 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
4005 RT5677_GPIO5_FUNC_MASK,
4006 RT5677_GPIO5_FUNC_DMIC);
4007 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4008 RT5677_GPIO5_DIR_MASK,
4009 RT5677_GPIO5_DIR_OUT);
4010 }
4011
44caf764
OC		 4012 rt5677_init_gpio(i2c);
4013
d0bdcb91
AL		 4014 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
4015 rt5677_dai, ARRAY_SIZE(rt5677_dai));
0e826e86
OC		 4016}
4017
4018static int rt5677_i2c_remove(struct i2c_client *i2c)
4019{
4020 snd_soc_unregister_codec(&i2c->dev);
44caf764 4021 rt5677_free_gpio(i2c);
0e826e86
OC		 4022
4023 return 0;
4024}
4025
4026static struct i2c_driver rt5677_i2c_driver = {
4027 .driver = {
4028 .name = "rt5677",
4029 .owner = THIS_MODULE,
4030 },
4031 .probe = rt5677_i2c_probe,
4032 .remove = rt5677_i2c_remove,
4033 .id_table = rt5677_i2c_id,
4034};
c8cfbec8 4035module_i2c_driver(rt5677_i2c_driver);
0e826e86
OC		 4036
4037MODULE_DESCRIPTION("ASoC RT5677 driver");
4038MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
4039MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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