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ASoC: wm8996: Fix wrong mask for setting WM8996_AIF_CLOCKING_2
[deliverable/linux.git] / sound / soc / codecs / sgtl5000.c
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9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
19#include <linux/platform_device.h>
20#include <linux/regulator/driver.h>
21#include <linux/regulator/machine.h>
22#include <linux/regulator/consumer.h>
58e49424 23#include <linux/of_device.h>
9b34e6cc
ZZ		 24#include <sound/core.h>
25#include <sound/tlv.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
9b34e6cc
ZZ		 31
32#include "sgtl5000.h"
33
34#define SGTL5000_DAP_REG_OFFSET 0x0100
35#define SGTL5000_MAX_REG_OFFSET 0x013A
36
151798f8
WS		 37/* default value of sgtl5000 registers */
38static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = {
39 [SGTL5000_CHIP_CLK_CTRL] = 0x0008,
40 [SGTL5000_CHIP_I2S_CTRL] = 0x0010,
41 [SGTL5000_CHIP_SSS_CTRL] = 0x0008,
42 [SGTL5000_CHIP_DAC_VOL] = 0x3c3c,
43 [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f,
44 [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818,
45 [SGTL5000_CHIP_ANA_CTRL] = 0x0111,
46 [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404,
47 [SGTL5000_CHIP_ANA_POWER] = 0x7060,
48 [SGTL5000_CHIP_PLL_CTRL] = 0x5000,
49 [SGTL5000_DAP_BASS_ENHANCE] = 0x0040,
50 [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f,
51 [SGTL5000_DAP_SURROUND] = 0x0040,
52 [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f,
53 [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f,
54 [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f,
55 [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f,
56 [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f,
57 [SGTL5000_DAP_MAIN_CHAN] = 0x8000,
58 [SGTL5000_DAP_AVC_CTRL] = 0x0510,
59 [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473,
60 [SGTL5000_DAP_AVC_ATTACK] = 0x0028,
61 [SGTL5000_DAP_AVC_DECAY] = 0x0050,
9b34e6cc
ZZ		 62};
63
64/* regulator supplies for sgtl5000, VDDD is an optional external supply */
65enum sgtl5000_regulator_supplies {
66 VDDA,
67 VDDIO,
68 VDDD,
69 SGTL5000_SUPPLY_NUM
70};
71
72/* vddd is optional supply */
73static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
74 "VDDA",
75 "VDDIO",
76 "VDDD"
77};
78
79#define LDO_CONSUMER_NAME "VDDD_LDO"
80#define LDO_VOLTAGE 1200000
81
82static struct regulator_consumer_supply ldo_consumer[] = {
83 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
84};
85
61a142b7 86static struct regulator_init_data ldo_init_data = {
9b34e6cc
ZZ		 87 .constraints = {
88 .min_uV = 850000,
89 .max_uV = 1600000,
90 .valid_modes_mask = REGULATOR_MODE_NORMAL,
91 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
92 },
93 .num_consumer_supplies = 1,
94 .consumer_supplies = &ldo_consumer[0],
95};
96
97/*
98 * sgtl5000 internal ldo regulator,
99 * enabled when VDDD not provided
100 */
101struct ldo_regulator {
102 struct regulator_desc desc;
103 struct regulator_dev *dev;
104 int voltage;
105 void *codec_data;
106 bool enabled;
107};
108
109/* sgtl5000 private structure in codec */
110struct sgtl5000_priv {
111 int sysclk; /* sysclk rate */
112 int master; /* i2s master or not */
113 int fmt; /* i2s data format */
114 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
115 struct ldo_regulator *ldo;
116};
117
118/*
119 * mic_bias power on/off share the same register bits with
120 * output impedance of mic bias, when power on mic bias, we
121 * need reclaim it to impedance value.
122 * 0x0 = Powered off
123 * 0x1 = 2Kohm
124 * 0x2 = 4Kohm
125 * 0x3 = 8Kohm
126 */
127static int mic_bias_event(struct snd_soc_dapm_widget *w,
128 struct snd_kcontrol *kcontrol, int event)
129{
130 switch (event) {
131 case SND_SOC_DAPM_POST_PMU:
132 /* change mic bias resistor to 4Kohm */
133 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8
AL		 134 SGTL5000_BIAS_R_MASK,
135 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 136 break;
137
138 case SND_SOC_DAPM_PRE_PMD:
9b34e6cc 139 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 140 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 141 break;
142 }
143 return 0;
144}
145
146/*
147 * using codec assist to small pop, hp_powerup or lineout_powerup
148 * should stay setting until vag_powerup is fully ramped down,
149 * vag fully ramped down require 400ms.
150 */
151static int small_pop_event(struct snd_soc_dapm_widget *w,
152 struct snd_kcontrol *kcontrol, int event)
153{
154 switch (event) {
155 case SND_SOC_DAPM_PRE_PMU:
156 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
157 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
158 break;
159
160 case SND_SOC_DAPM_PRE_PMD:
161 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
162 SGTL5000_VAG_POWERUP, 0);
163 msleep(400);
164 break;
165 default:
166 break;
167 }
168
169 return 0;
170}
171
172/* input sources for ADC */
173static const char *adc_mux_text[] = {
174 "MIC_IN", "LINE_IN"
175};
176
177static const struct soc_enum adc_enum =
178SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
179
180static const struct snd_kcontrol_new adc_mux =
181SOC_DAPM_ENUM("Capture Mux", adc_enum);
182
183/* input sources for DAC */
184static const char *dac_mux_text[] = {
185 "DAC", "LINE_IN"
186};
187
188static const struct soc_enum dac_enum =
189SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
190
191static const struct snd_kcontrol_new dac_mux =
192SOC_DAPM_ENUM("Headphone Mux", dac_enum);
193
194static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
195 SND_SOC_DAPM_INPUT("LINE_IN"),
196 SND_SOC_DAPM_INPUT("MIC_IN"),
197
198 SND_SOC_DAPM_OUTPUT("HP_OUT"),
199 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
200
201 SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
202 mic_bias_event,
203 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
204
205 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
206 small_pop_event,
207 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
208 SND_SOC_DAPM_PGA_E("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0,
209 small_pop_event,
210 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
211
212 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
213 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
214
215 /* aif for i2s input */
216 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
217 0, SGTL5000_CHIP_DIG_POWER,
218 0, 0),
219
220 /* aif for i2s output */
221 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
222 0, SGTL5000_CHIP_DIG_POWER,
223 1, 0),
224
225 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
226
227 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
228};
229
230/* routes for sgtl5000 */
231static const struct snd_soc_dapm_route audio_map[] = {
232 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
233 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
234
235 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
236 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
237
238 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
239 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
240 {"LO", NULL, "DAC"}, /* dac --> line_out */
241
242 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
243 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
244
245 {"LINE_OUT", NULL, "LO"},
246 {"HP_OUT", NULL, "HP"},
247};
248
249/* custom function to fetch info of PCM playback volume */
250static int dac_info_volsw(struct snd_kcontrol *kcontrol,
251 struct snd_ctl_elem_info *uinfo)
252{
253 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
254 uinfo->count = 2;
255 uinfo->value.integer.min = 0;
256 uinfo->value.integer.max = 0xfc - 0x3c;
257 return 0;
258}
259
260/*
261 * custom function to get of PCM playback volume
262 *
263 * dac volume register
264 * 15-------------8-7--------------0
265 * | R channel vol | L channel vol |
266 * -------------------------------
267 *
268 * PCM volume with 0.5017 dB steps from 0 to -90 dB
269 *
270 * register values map to dB
271 * 0x3B and less = Reserved
272 * 0x3C = 0 dB
273 * 0x3D = -0.5 dB
274 * 0xF0 = -90 dB
275 * 0xFC and greater = Muted
276 *
277 * register value map to userspace value
278 *
279 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
280 * ------------------------------
281 * userspace value 0xc0 0
282 */
283static int dac_get_volsw(struct snd_kcontrol *kcontrol,
284 struct snd_ctl_elem_value *ucontrol)
285{
286 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
287 int reg;
288 int l;
289 int r;
290
291 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
292
293 /* get left channel volume */
294 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
295
296 /* get right channel volume */
297 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
298
299 /* make sure value fall in (0x3c,0xfc) */
300 l = clamp(l, 0x3c, 0xfc);
301 r = clamp(r, 0x3c, 0xfc);
302
303 /* invert it and map to userspace value */
304 l = 0xfc - l;
305 r = 0xfc - r;
306
307 ucontrol->value.integer.value[0] = l;
308 ucontrol->value.integer.value[1] = r;
309
310 return 0;
311}
312
313/*
314 * custom function to put of PCM playback volume
315 *
316 * dac volume register
317 * 15-------------8-7--------------0
318 * | R channel vol | L channel vol |
319 * -------------------------------
320 *
321 * PCM volume with 0.5017 dB steps from 0 to -90 dB
322 *
323 * register values map to dB
324 * 0x3B and less = Reserved
325 * 0x3C = 0 dB
326 * 0x3D = -0.5 dB
327 * 0xF0 = -90 dB
328 * 0xFC and greater = Muted
329 *
330 * userspace value map to register value
331 *
332 * userspace value 0xc0 0
333 * ------------------------------
334 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
335 */
336static int dac_put_volsw(struct snd_kcontrol *kcontrol,
337 struct snd_ctl_elem_value *ucontrol)
338{
339 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
340 int reg;
341 int l;
342 int r;
343
344 l = ucontrol->value.integer.value[0];
345 r = ucontrol->value.integer.value[1];
346
347 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
348 l = clamp(l, 0, 0xfc - 0x3c);
349 r = clamp(r, 0, 0xfc - 0x3c);
350
351 /* invert it, get the value can be set to register */
352 l = 0xfc - l;
353 r = 0xfc - r;
354
355 /* shift to get the register value */
356 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
357 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
358
359 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
360
361 return 0;
362}
363
364static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
365
366/* tlv for mic gain, 0db 20db 30db 40db */
367static const unsigned int mic_gain_tlv[] = {
368 TLV_DB_RANGE_HEAD(4),
369 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
370 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
371};
372
373/* tlv for hp volume, -51.5db to 12.0db, step .5db */
374static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
375
376static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
377 /* SOC_DOUBLE_S8_TLV with invert */
378 {
379 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
380 .name = "PCM Playback Volume",
381 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
382 SNDRV_CTL_ELEM_ACCESS_READWRITE,
383 .info = dac_info_volsw,
384 .get = dac_get_volsw,
385 .put = dac_put_volsw,
386 },
387
388 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
389 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
390 SGTL5000_CHIP_ANA_ADC_CTRL,
391 8, 2, 0, capture_6db_attenuate),
392 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
393
394 SOC_DOUBLE_TLV("Headphone Playback Volume",
395 SGTL5000_CHIP_ANA_HP_CTRL,
396 0, 8,
397 0x7f, 1,
398 headphone_volume),
399 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
400 5, 1, 0),
401
402 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
403 0, 4, 0, mic_gain_tlv),
404};
405
406/* mute the codec used by alsa core */
407static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
408{
409 struct snd_soc_codec *codec = codec_dai->codec;
410 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
411
412 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
413 adcdac_ctrl, mute ? adcdac_ctrl : 0);
414
415 return 0;
416}
417
418/* set codec format */
419static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
420{
421 struct snd_soc_codec *codec = codec_dai->codec;
422 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
423 u16 i2sctl = 0;
424
425 sgtl5000->master = 0;
426 /*
427 * i2s clock and frame master setting.
428 * ONLY support:
429 * - clock and frame slave,
430 * - clock and frame master
431 */
432 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
433 case SND_SOC_DAIFMT_CBS_CFS:
434 break;
435 case SND_SOC_DAIFMT_CBM_CFM:
436 i2sctl |= SGTL5000_I2S_MASTER;
437 sgtl5000->master = 1;
438 break;
439 default:
440 return -EINVAL;
441 }
442
443 /* setting i2s data format */
444 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
445 case SND_SOC_DAIFMT_DSP_A:
446 i2sctl |= SGTL5000_I2S_MODE_PCM;
447 break;
448 case SND_SOC_DAIFMT_DSP_B:
449 i2sctl |= SGTL5000_I2S_MODE_PCM;
450 i2sctl |= SGTL5000_I2S_LRALIGN;
451 break;
452 case SND_SOC_DAIFMT_I2S:
453 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
454 break;
455 case SND_SOC_DAIFMT_RIGHT_J:
456 i2sctl |= SGTL5000_I2S_MODE_RJ;
457 i2sctl |= SGTL5000_I2S_LRPOL;
458 break;
459 case SND_SOC_DAIFMT_LEFT_J:
460 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
461 i2sctl |= SGTL5000_I2S_LRALIGN;
462 break;
463 default:
464 return -EINVAL;
465 }
466
467 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
468
469 /* Clock inversion */
470 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
471 case SND_SOC_DAIFMT_NB_NF:
472 break;
473 case SND_SOC_DAIFMT_IB_NF:
474 i2sctl |= SGTL5000_I2S_SCLK_INV;
475 break;
476 default:
477 return -EINVAL;
478 }
479
480 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
481
482 return 0;
483}
484
485/* set codec sysclk */
486static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
487 int clk_id, unsigned int freq, int dir)
488{
489 struct snd_soc_codec *codec = codec_dai->codec;
490 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
491
492 switch (clk_id) {
493 case SGTL5000_SYSCLK:
494 sgtl5000->sysclk = freq;
495 break;
496 default:
497 return -EINVAL;
498 }
499
500 return 0;
501}
502
503/*
504 * set clock according to i2s frame clock,
505 * sgtl5000 provide 2 clock sources.
506 * 1. sys_mclk. sample freq can only configure to
507 * 1/256, 1/384, 1/512 of sys_mclk.
508 * 2. pll. can derive any audio clocks.
509 *
510 * clock setting rules:
511 * 1. in slave mode, only sys_mclk can use.
512 * 2. as constraint by sys_mclk, sample freq should
513 * set to 32k, 44.1k and above.
514 * 3. using sys_mclk prefer to pll to save power.
515 */
516static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
517{
518 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
519 int clk_ctl = 0;
520 int sys_fs; /* sample freq */
521
522 /*
523 * sample freq should be divided by frame clock,
524 * if frame clock lower than 44.1khz, sample feq should set to
525 * 32khz or 44.1khz.
526 */
527 switch (frame_rate) {
528 case 8000:
529 case 16000:
530 sys_fs = 32000;
531 break;
532 case 11025:
533 case 22050:
534 sys_fs = 44100;
535 break;
536 default:
537 sys_fs = frame_rate;
538 break;
539 }
540
541 /* set divided factor of frame clock */
542 switch (sys_fs / frame_rate) {
543 case 4:
544 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
545 break;
546 case 2:
547 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
548 break;
549 case 1:
550 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
551 break;
552 default:
553 return -EINVAL;
554 }
555
556 /* set the sys_fs according to frame rate */
557 switch (sys_fs) {
558 case 32000:
559 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
560 break;
561 case 44100:
562 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
563 break;
564 case 48000:
565 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
566 break;
567 case 96000:
568 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
569 break;
570 default:
571 dev_err(codec->dev, "frame rate %d not supported\n",
572 frame_rate);
573 return -EINVAL;
574 }
575
576 /*
577 * calculate the divider of mclk/sample_freq,
578 * factor of freq =96k can only be 256, since mclk in range (12m,27m)
579 */
580 switch (sgtl5000->sysclk / sys_fs) {
581 case 256:
582 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
583 SGTL5000_MCLK_FREQ_SHIFT;
584 break;
585 case 384:
586 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
587 SGTL5000_MCLK_FREQ_SHIFT;
588 break;
589 case 512:
590 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
591 SGTL5000_MCLK_FREQ_SHIFT;
592 break;
593 default:
594 /* if mclk not satisify the divider, use pll */
595 if (sgtl5000->master) {
596 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
597 SGTL5000_MCLK_FREQ_SHIFT;
598 } else {
599 dev_err(codec->dev,
600 "PLL not supported in slave mode\n");
601 return -EINVAL;
602 }
603 }
604
605 /* if using pll, please check manual 6.4.2 for detail */
606 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
607 u64 out, t;
608 int div2;
609 int pll_ctl;
610 unsigned int in, int_div, frac_div;
611
612 if (sgtl5000->sysclk > 17000000) {
613 div2 = 1;
614 in = sgtl5000->sysclk / 2;
615 } else {
616 div2 = 0;
617 in = sgtl5000->sysclk;
618 }
619 if (sys_fs == 44100)
620 out = 180633600;
621 else
622 out = 196608000;
623 t = do_div(out, in);
624 int_div = out;
625 t *= 2048;
626 do_div(t, in);
627 frac_div = t;
628 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
629 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
630
631 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
632 if (div2)
633 snd_soc_update_bits(codec,
634 SGTL5000_CHIP_CLK_TOP_CTRL,
635 SGTL5000_INPUT_FREQ_DIV2,
636 SGTL5000_INPUT_FREQ_DIV2);
637 else
638 snd_soc_update_bits(codec,
639 SGTL5000_CHIP_CLK_TOP_CTRL,
640 SGTL5000_INPUT_FREQ_DIV2,
641 0);
642
643 /* power up pll */
644 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
645 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
646 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
647 } else {
648 /* power down pll */
649 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
650 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
651 0);
652 }
653
654 /* if using pll, clk_ctrl must be set after pll power up */
655 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
656
657 return 0;
658}
659
660/*
661 * Set PCM DAI bit size and sample rate.
662 * input: params_rate, params_fmt
663 */
664static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
665 struct snd_pcm_hw_params *params,
666 struct snd_soc_dai *dai)
667{
668 struct snd_soc_pcm_runtime *rtd = substream->private_data;
669 struct snd_soc_codec *codec = rtd->codec;
670 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
671 int channels = params_channels(params);
672 int i2s_ctl = 0;
673 int stereo;
674 int ret;
675
676 /* sysclk should already set */
677 if (!sgtl5000->sysclk) {
678 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
679 return -EFAULT;
680 }
681
682 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
683 stereo = SGTL5000_DAC_STEREO;
684 else
685 stereo = SGTL5000_ADC_STEREO;
686
687 /* set mono to save power */
688 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
689 channels == 1 ? 0 : stereo);
690
691 /* set codec clock base on lrclk */
692 ret = sgtl5000_set_clock(codec, params_rate(params));
693 if (ret)
694 return ret;
695
696 /* set i2s data format */
697 switch (params_format(params)) {
698 case SNDRV_PCM_FORMAT_S16_LE:
699 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
700 return -EINVAL;
701 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
702 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
703 SGTL5000_I2S_SCLKFREQ_SHIFT;
704 break;
705 case SNDRV_PCM_FORMAT_S20_3LE:
706 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
707 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
708 SGTL5000_I2S_SCLKFREQ_SHIFT;
709 break;
710 case SNDRV_PCM_FORMAT_S24_LE:
711 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
712 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
713 SGTL5000_I2S_SCLKFREQ_SHIFT;
714 break;
715 case SNDRV_PCM_FORMAT_S32_LE:
716 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
717 return -EINVAL;
718 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
719 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
720 SGTL5000_I2S_SCLKFREQ_SHIFT;
721 break;
722 default:
723 return -EINVAL;
724 }
725
726 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, i2s_ctl, i2s_ctl);
727
728 return 0;
729}
730
333802e9 731#ifdef CONFIG_REGULATOR
9b34e6cc
ZZ		 732static int ldo_regulator_is_enabled(struct regulator_dev *dev)
733{
734 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
735
736 return ldo->enabled;
737}
738
739static int ldo_regulator_enable(struct regulator_dev *dev)
740{
741 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
742 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
743 int reg;
744
745 if (ldo_regulator_is_enabled(dev))
746 return 0;
747
748 /* set regulator value firstly */
749 reg = (1600 - ldo->voltage / 1000) / 50;
750 reg = clamp(reg, 0x0, 0xf);
751
752 /* amend the voltage value, unit: uV */
753 ldo->voltage = (1600 - reg * 50) * 1000;
754
755 /* set voltage to register */
756 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 757 SGTL5000_LINREG_VDDD_MASK, reg);
9b34e6cc
ZZ		 758
759 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
760 SGTL5000_LINEREG_D_POWERUP,
761 SGTL5000_LINEREG_D_POWERUP);
762
763 /* when internal ldo enabled, simple digital power can be disabled */
764 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
765 SGTL5000_LINREG_SIMPLE_POWERUP,
766 0);
767
768 ldo->enabled = 1;
769 return 0;
770}
771
772static int ldo_regulator_disable(struct regulator_dev *dev)
773{
774 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
775 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
776
777 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
778 SGTL5000_LINEREG_D_POWERUP,
779 0);
780
781 /* clear voltage info */
782 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 783 SGTL5000_LINREG_VDDD_MASK, 0);
9b34e6cc
ZZ		 784
785 ldo->enabled = 0;
786
787 return 0;
788}
789
790static int ldo_regulator_get_voltage(struct regulator_dev *dev)
791{
792 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
793
794 return ldo->voltage;
795}
796
797static struct regulator_ops ldo_regulator_ops = {
798 .is_enabled = ldo_regulator_is_enabled,
799 .enable = ldo_regulator_enable,
800 .disable = ldo_regulator_disable,
801 .get_voltage = ldo_regulator_get_voltage,
802};
803
804static int ldo_regulator_register(struct snd_soc_codec *codec,
805 struct regulator_init_data *init_data,
806 int voltage)
807{
808 struct ldo_regulator *ldo;
5b13de7a 809 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
9b34e6cc
ZZ		 810
811 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
812
813 if (!ldo) {
814 dev_err(codec->dev, "failed to allocate ldo_regulator\n");
815 return -ENOMEM;
816 }
817
818 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
819 if (!ldo->desc.name) {
820 kfree(ldo);
821 dev_err(codec->dev, "failed to allocate decs name memory\n");
822 return -ENOMEM;
823 }
824
825 ldo->desc.type = REGULATOR_VOLTAGE;
826 ldo->desc.owner = THIS_MODULE;
827 ldo->desc.ops = &ldo_regulator_ops;
828 ldo->desc.n_voltages = 1;
829
830 ldo->codec_data = codec;
831 ldo->voltage = voltage;
832
833 ldo->dev = regulator_register(&ldo->desc, codec->dev,
834 init_data, ldo);
835 if (IS_ERR(ldo->dev)) {
62f75aaf
DC		 836 int ret = PTR_ERR(ldo->dev);
837
9b34e6cc
ZZ		 838 dev_err(codec->dev, "failed to register regulator\n");
839 kfree(ldo->desc.name);
840 kfree(ldo);
841
62f75aaf 842 return ret;
9b34e6cc 843 }
5b13de7a 844 sgtl5000->ldo = ldo;
9b34e6cc
ZZ		 845
846 return 0;
847}
848
849static int ldo_regulator_remove(struct snd_soc_codec *codec)
850{
851 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
852 struct ldo_regulator *ldo = sgtl5000->ldo;
853
854 if (!ldo)
855 return 0;
856
857 regulator_unregister(ldo->dev);
858 kfree(ldo->desc.name);
859 kfree(ldo);
860
861 return 0;
862}
333802e9
MB		 863#else
864static int ldo_regulator_register(struct snd_soc_codec *codec,
865 struct regulator_init_data *init_data,
866 int voltage)
867{
09bddc8e 868 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
333802e9
MB		 869 return -EINVAL;
870}
871
872static int ldo_regulator_remove(struct snd_soc_codec *codec)
873{
874 return 0;
875}
876#endif
9b34e6cc
ZZ		 877
878/*
879 * set dac bias
880 * common state changes:
881 * startup:
882 * off --> standby --> prepare --> on
883 * standby --> prepare --> on
884 *
885 * stop:
886 * on --> prepare --> standby
887 */
888static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
889 enum snd_soc_bias_level level)
890{
891 int ret;
892 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
893
894 switch (level) {
895 case SND_SOC_BIAS_ON:
896 case SND_SOC_BIAS_PREPARE:
897 break;
898 case SND_SOC_BIAS_STANDBY:
899 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
900 ret = regulator_bulk_enable(
901 ARRAY_SIZE(sgtl5000->supplies),
902 sgtl5000->supplies);
903 if (ret)
904 return ret;
905 udelay(10);
906 }
907
908 break;
909 case SND_SOC_BIAS_OFF:
910 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
911 sgtl5000->supplies);
912 break;
913 }
914
915 codec->dapm.bias_level = level;
916 return 0;
917}
918
919#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
920 SNDRV_PCM_FMTBIT_S20_3LE |\
921 SNDRV_PCM_FMTBIT_S24_LE |\
922 SNDRV_PCM_FMTBIT_S32_LE)
923
61a142b7 924static struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 925 .hw_params = sgtl5000_pcm_hw_params,
926 .digital_mute = sgtl5000_digital_mute,
927 .set_fmt = sgtl5000_set_dai_fmt,
928 .set_sysclk = sgtl5000_set_dai_sysclk,
929};
930
931static struct snd_soc_dai_driver sgtl5000_dai = {
932 .name = "sgtl5000",
933 .playback = {
934 .stream_name = "Playback",
935 .channels_min = 1,
936 .channels_max = 2,
937 /*
938 * only support 8~48K + 96K,
939 * TODO modify hw_param to support more
940 */
941 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
942 .formats = SGTL5000_FORMATS,
943 },
944 .capture = {
945 .stream_name = "Capture",
946 .channels_min = 1,
947 .channels_max = 2,
948 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
949 .formats = SGTL5000_FORMATS,
950 },
951 .ops = &sgtl5000_ops,
952 .symmetric_rates = 1,
953};
954
955static int sgtl5000_volatile_register(struct snd_soc_codec *codec,
956 unsigned int reg)
957{
958 switch (reg) {
959 case SGTL5000_CHIP_ID:
960 case SGTL5000_CHIP_ADCDAC_CTRL:
961 case SGTL5000_CHIP_ANA_STATUS:
962 return 1;
963 }
964
965 return 0;
966}
967
968#ifdef CONFIG_SUSPEND
969static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state)
970{
971 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
972
973 return 0;
974}
975
976/*
977 * restore all sgtl5000 registers,
978 * since a big hole between dap and regular registers,
979 * we will restore them respectively.
980 */
981static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
982{
983 u16 *cache = codec->reg_cache;
151798f8 984 u16 reg;
9b34e6cc
ZZ		 985
986 /* restore regular registers */
151798f8 987 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
9b34e6cc
ZZ		 988
989 /* this regs depends on the others */
990 if (reg == SGTL5000_CHIP_ANA_POWER ||
991 reg == SGTL5000_CHIP_CLK_CTRL ||
992 reg == SGTL5000_CHIP_LINREG_CTRL ||
993 reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
994 reg == SGTL5000_CHIP_CLK_CTRL)
995 continue;
996
151798f8 997 snd_soc_write(codec, reg, cache[reg]);
9b34e6cc
ZZ		 998 }
999
1000 /* restore dap registers */
151798f8
WS		 1001 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
1002 snd_soc_write(codec, reg, cache[reg]);
9b34e6cc
ZZ		 1003
1004 /*
1005 * restore power and other regs according
1006 * to set_power() and set_clock()
1007 */
1008 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
151798f8 1009 cache[SGTL5000_CHIP_LINREG_CTRL]);
9b34e6cc
ZZ		 1010
1011 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
151798f8 1012 cache[SGTL5000_CHIP_ANA_POWER]);
9b34e6cc
ZZ		 1013
1014 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
151798f8 1015 cache[SGTL5000_CHIP_CLK_CTRL]);
9b34e6cc
ZZ		 1016
1017 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
151798f8 1018 cache[SGTL5000_CHIP_REF_CTRL]);
9b34e6cc
ZZ		 1019
1020 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
151798f8 1021 cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
9b34e6cc
ZZ		 1022 return 0;
1023}
1024
1025static int sgtl5000_resume(struct snd_soc_codec *codec)
1026{
1027 /* Bring the codec back up to standby to enable regulators */
1028 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1029
1030 /* Restore registers by cached in memory */
1031 sgtl5000_restore_regs(codec);
1032 return 0;
1033}
1034#else
1035#define sgtl5000_suspend NULL
1036#define sgtl5000_resume NULL
1037#endif /* CONFIG_SUSPEND */
1038
1039/*
1040 * sgtl5000 has 3 internal power supplies:
1041 * 1. VAG, normally set to vdda/2
1042 * 2. chargepump, set to different value
1043 * according to voltage of vdda and vddio
1044 * 3. line out VAG, normally set to vddio/2
1045 *
1046 * and should be set according to:
1047 * 1. vddd provided by external or not
1048 * 2. vdda and vddio voltage value. > 3.1v or not
1049 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1050 */
1051static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1052{
1053 int vddd;
1054 int vdda;
1055 int vddio;
1056 u16 ana_pwr;
1057 u16 lreg_ctrl;
1058 int vag;
1059 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1060
1061 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1062 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1063 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1064
1065 vdda = vdda / 1000;
1066 vddio = vddio / 1000;
1067 vddd = vddd / 1000;
1068
1069 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1070 dev_err(codec->dev, "regulator voltage not set correctly\n");
1071
1072 return -EINVAL;
1073 }
1074
1075 /* according to datasheet, maximum voltage of supplies */
1076 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1077 dev_err(codec->dev,
1078 "exceed max voltage vdda %dmv vddio %dma vddd %dma\n",
1079 vdda, vddio, vddd);
1080
1081 return -EINVAL;
1082 }
1083
1084 /* reset value */
1085 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1086 ana_pwr |= SGTL5000_DAC_STEREO |
1087 SGTL5000_ADC_STEREO |
1088 SGTL5000_REFTOP_POWERUP;
1089 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1090
1091 if (vddio < 3100 && vdda < 3100) {
1092 /* enable internal oscillator used for charge pump */
1093 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1094 SGTL5000_INT_OSC_EN,
1095 SGTL5000_INT_OSC_EN);
1096 /* Enable VDDC charge pump */
1097 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1098 } else if (vddio >= 3100 && vdda >= 3100) {
1099 /*
1100 * if vddio and vddd > 3.1v,
1101 * charge pump should be clean before set ana_pwr
1102 */
1103 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1104 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1105
1106 /* VDDC use VDDIO rail */
1107 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1108 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1109 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1110 }
1111
1112 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1113
1114 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1115
1116 /* set voltage to register */
1117 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 1118 SGTL5000_LINREG_VDDD_MASK, 0x8);
9b34e6cc
ZZ		 1119
1120 /*
1121 * if vddd linear reg has been enabled,
1122 * simple digital supply should be clear to get
1123 * proper VDDD voltage.
1124 */
1125 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1126 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1127 SGTL5000_LINREG_SIMPLE_POWERUP,
1128 0);
1129 else
1130 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1131 SGTL5000_LINREG_SIMPLE_POWERUP |
1132 SGTL5000_STARTUP_POWERUP,
1133 0);
1134
1135 /*
1136 * set ADC/DAC VAG to vdda / 2,
1137 * should stay in range (0.8v, 1.575v)
1138 */
1139 vag = vdda / 2;
1140 if (vag <= SGTL5000_ANA_GND_BASE)
1141 vag = 0;
1142 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1143 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1144 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1145 else
1146 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1147
1148 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1149 vag << SGTL5000_ANA_GND_SHIFT,
1150 vag << SGTL5000_ANA_GND_SHIFT);
1151
1152 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1153 vag = vddio / 2;
1154 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1155 vag = 0;
1156 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1157 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1158 vag = SGTL5000_LINE_OUT_GND_MAX;
1159 else
1160 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1161 SGTL5000_LINE_OUT_GND_STP;
1162
1163 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1164 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1165 SGTL5000_LINE_OUT_CURRENT_360u <<
1166 SGTL5000_LINE_OUT_CURRENT_SHIFT,
1167 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1168 SGTL5000_LINE_OUT_CURRENT_360u <<
1169 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1170
1171 return 0;
1172}
1173
e94a4062
WS		 1174static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1175{
1176 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1177 int ret;
1178
1179 /* set internal ldo to 1.2v */
1180 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1181 if (ret) {
1182 dev_err(codec->dev,
1183 "Failed to register vddd internal supplies: %d\n", ret);
1184 return ret;
1185 }
1186
1187 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1188
1189 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1190 sgtl5000->supplies);
1191
1192 if (ret) {
1193 ldo_regulator_remove(codec);
1194 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1195 return ret;
1196 }
1197
1198 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1199 return 0;
1200}
1201
9b34e6cc
ZZ		 1202static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1203{
1204 u16 reg;
1205 int ret;
1206 int rev;
1207 int i;
1208 int external_vddd = 0;
1209 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1210
1211 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1212 sgtl5000->supplies[i].supply = supply_names[i];
1213
1214 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1215 sgtl5000->supplies);
1216 if (!ret)
1217 external_vddd = 1;
1218 else {
e94a4062
WS		 1219 ret = sgtl5000_replace_vddd_with_ldo(codec);
1220 if (ret)
9b34e6cc 1221 return ret;
9b34e6cc
ZZ		 1222 }
1223
1224 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1225 sgtl5000->supplies);
1226 if (ret)
1227 goto err_regulator_free;
1228
1229 /* wait for all power rails bring up */
1230 udelay(10);
1231
1232 /* read chip information */
1233 reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
1234 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1235 SGTL5000_PARTID_PART_ID) {
1236 dev_err(codec->dev,
1237 "Device with ID register %x is not a sgtl5000\n", reg);
1238 ret = -ENODEV;
1239 goto err_regulator_disable;
1240 }
1241
1242 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1243 dev_info(codec->dev, "sgtl5000 revision %d\n", rev);
1244
1245 /*
1246 * workaround for revision 0x11 and later,
1247 * roll back to use internal LDO
1248 */
1249 if (external_vddd && rev >= 0x11) {
9b34e6cc
ZZ		 1250 /* disable all regulator first */
1251 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1252 sgtl5000->supplies);
1253 /* free VDDD regulator */
1254 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1255 sgtl5000->supplies);
1256
e94a4062 1257 ret = sgtl5000_replace_vddd_with_ldo(codec);
9b34e6cc
ZZ		 1258 if (ret)
1259 return ret;
1260
9b34e6cc
ZZ		 1261 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1262 sgtl5000->supplies);
1263 if (ret)
1264 goto err_regulator_free;
1265
1266 /* wait for all power rails bring up */
1267 udelay(10);
1268 }
1269
1270 return 0;
1271
1272err_regulator_disable:
1273 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1274 sgtl5000->supplies);
1275err_regulator_free:
1276 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1277 sgtl5000->supplies);
1278 if (external_vddd)
1279 ldo_regulator_remove(codec);
1280 return ret;
1281
1282}
1283
1284static int sgtl5000_probe(struct snd_soc_codec *codec)
1285{
1286 int ret;
1287 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1288
1289 /* setup i2c data ops */
1290 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
1291 if (ret < 0) {
1292 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1293 return ret;
1294 }
1295
1296 ret = sgtl5000_enable_regulators(codec);
1297 if (ret)
1298 return ret;
1299
1300 /* power up sgtl5000 */
1301 ret = sgtl5000_set_power_regs(codec);
1302 if (ret)
1303 goto err;
1304
1305 /* enable small pop, introduce 400ms delay in turning off */
1306 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1307 SGTL5000_SMALL_POP,
1308 SGTL5000_SMALL_POP);
1309
1310 /* disable short cut detector */
1311 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1312
1313 /*
1314 * set i2s as default input of sound switch
1315 * TODO: add sound switch to control and dapm widge.
1316 */
1317 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1318 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1319 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1320 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1321
1322 /* enable dac volume ramp by default */
1323 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1324 SGTL5000_DAC_VOL_RAMP_EN |
1325 SGTL5000_DAC_MUTE_RIGHT |
1326 SGTL5000_DAC_MUTE_LEFT);
1327
1328 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1329
1330 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1331 SGTL5000_HP_ZCD_EN |
1332 SGTL5000_ADC_ZCD_EN);
1333
1334 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0);
1335
1336 /*
1337 * disable DAP
1338 * TODO:
1339 * Enable DAP in kcontrol and dapm.
1340 */
1341 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1342
1343 /* leading to standby state */
1344 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1345 if (ret)
1346 goto err;
1347
1348 snd_soc_add_controls(codec, sgtl5000_snd_controls,
1349 ARRAY_SIZE(sgtl5000_snd_controls));
1350
1351 snd_soc_dapm_new_controls(&codec->dapm, sgtl5000_dapm_widgets,
1352 ARRAY_SIZE(sgtl5000_dapm_widgets));
1353
1354 snd_soc_dapm_add_routes(&codec->dapm, audio_map,
1355 ARRAY_SIZE(audio_map));
1356
1357 snd_soc_dapm_new_widgets(&codec->dapm);
1358
1359 return 0;
1360
1361err:
1362 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1363 sgtl5000->supplies);
1364 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1365 sgtl5000->supplies);
1366 ldo_regulator_remove(codec);
1367
1368 return ret;
1369}
1370
1371static int sgtl5000_remove(struct snd_soc_codec *codec)
1372{
1373 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1374
1375 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1376
1377 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1378 sgtl5000->supplies);
1379 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1380 sgtl5000->supplies);
1381 ldo_regulator_remove(codec);
1382
1383 return 0;
1384}
1385
61a142b7 1386static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1387 .probe = sgtl5000_probe,
1388 .remove = sgtl5000_remove,
1389 .suspend = sgtl5000_suspend,
1390 .resume = sgtl5000_resume,
1391 .set_bias_level = sgtl5000_set_bias_level,
1392 .reg_cache_size = ARRAY_SIZE(sgtl5000_regs),
1393 .reg_word_size = sizeof(u16),
1394 .reg_cache_step = 2,
1395 .reg_cache_default = sgtl5000_regs,
1396 .volatile_register = sgtl5000_volatile_register,
1397};
1398
1399static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
1400 const struct i2c_device_id *id)
1401{
1402 struct sgtl5000_priv *sgtl5000;
1403 int ret;
1404
1405 sgtl5000 = kzalloc(sizeof(struct sgtl5000_priv), GFP_KERNEL);
1406 if (!sgtl5000)
1407 return -ENOMEM;
1408
9b34e6cc
ZZ		 1409 i2c_set_clientdata(client, sgtl5000);
1410
1411 ret = snd_soc_register_codec(&client->dev,
1412 &sgtl5000_driver, &sgtl5000_dai, 1);
1413 if (ret) {
1414 dev_err(&client->dev, "Failed to register codec: %d\n", ret);
1415 kfree(sgtl5000);
1416 return ret;
1417 }
1418
1419 return 0;
1420}
1421
1422static __devexit int sgtl5000_i2c_remove(struct i2c_client *client)
1423{
1424 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1425
1426 snd_soc_unregister_codec(&client->dev);
1427
1428 kfree(sgtl5000);
1429 return 0;
1430}
1431
1432static const struct i2c_device_id sgtl5000_id[] = {
1433 {"sgtl5000", 0},
1434 {},
1435};
1436
1437MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1438
58e49424
SG		 1439static const struct of_device_id sgtl5000_dt_ids[] = {
1440 { .compatible = "fsl,sgtl5000", },
1441 { /* sentinel */ }
1442};
4c54c6de 1443MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1444
9b34e6cc
ZZ		 1445static struct i2c_driver sgtl5000_i2c_driver = {
1446 .driver = {
1447 .name = "sgtl5000",
1448 .owner = THIS_MODULE,
58e49424 1449 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1450 },
1451 .probe = sgtl5000_i2c_probe,
1452 .remove = __devexit_p(sgtl5000_i2c_remove),
1453 .id_table = sgtl5000_id,
1454};
1455
1456static int __init sgtl5000_modinit(void)
1457{
1458 return i2c_add_driver(&sgtl5000_i2c_driver);
1459}
1460module_init(sgtl5000_modinit);
1461
1462static void __exit sgtl5000_exit(void)
1463{
1464 i2c_del_driver(&sgtl5000_i2c_driver);
1465}
1466module_exit(sgtl5000_exit);
1467
1468MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1469MODULE_AUTHOR("Zeng Zhaoming <zhaoming.zeng@freescale.com>");
1470MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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