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ASoC: sgtl5000: Initialize CHIP_ANA_POWER to power-on defaults
[deliverable/linux.git] / sound / soc / codecs / sgtl5000.c
CommitLineData
9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
bd0593f5 19#include <linux/log2.h>
e5d80e82 20#include <linux/regmap.h>
9b34e6cc
ZZ		 21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/regulator/consumer.h>
58e49424 24#include <linux/of_device.h>
9b34e6cc
ZZ		 25#include <sound/core.h>
26#include <sound/tlv.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
9b34e6cc
ZZ		 32
33#include "sgtl5000.h"
34
35#define SGTL5000_DAP_REG_OFFSET 0x0100
36#define SGTL5000_MAX_REG_OFFSET 0x013A
37
151798f8 38/* default value of sgtl5000 registers */
e5d80e82 39static const struct reg_default sgtl5000_reg_defaults[] = {
29aa37cd 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
e5d80e82
FE		 41 { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
42 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
016fcab8 43 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
29aa37cd 44 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
e5d80e82
FE		 45 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
46 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
29aa37cd 47 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
e5d80e82
FE		 48 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
49 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
29aa37cd
FE		 50 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
51 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
52 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
e5d80e82 53 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
e5d80e82 54 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
29aa37cd
FE		 55 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
56 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
57 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
58 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
59 { SGTL5000_DAP_CTRL, 0x0000 },
60 { SGTL5000_DAP_PEQ, 0x0000 },
e5d80e82
FE		 61 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
62 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
29aa37cd 63 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
e5d80e82
FE		 64 { SGTL5000_DAP_SURROUND, 0x0040 },
65 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
66 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
67 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
69 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
70 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
29aa37cd 71 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
e5d80e82
FE		 72 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
73 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
74 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
75 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
9b34e6cc
ZZ		 76};
77
78/* regulator supplies for sgtl5000, VDDD is an optional external supply */
79enum sgtl5000_regulator_supplies {
80 VDDA,
81 VDDIO,
82 VDDD,
83 SGTL5000_SUPPLY_NUM
84};
85
86/* vddd is optional supply */
87static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
88 "VDDA",
89 "VDDIO",
90 "VDDD"
91};
92
9b34e6cc 93#define LDO_VOLTAGE 1200000
3d632cc8 94#define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
9b34e6cc 95
bd0593f5
JMH		 96enum sgtl5000_micbias_resistor {
97 SGTL5000_MICBIAS_OFF = 0,
98 SGTL5000_MICBIAS_2K = 2,
99 SGTL5000_MICBIAS_4K = 4,
100 SGTL5000_MICBIAS_8K = 8,
101};
102
9b34e6cc
ZZ		 103/* sgtl5000 private structure in codec */
104struct sgtl5000_priv {
105 int sysclk; /* sysclk rate */
106 int master; /* i2s master or not */
107 int fmt; /* i2s data format */
108 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
940adb28 109 int num_supplies;
e5d80e82 110 struct regmap *regmap;
9e13f345 111 struct clk *mclk;
252e91ff 112 int revision;
bd0593f5 113 u8 micbias_resistor;
87357797 114 u8 micbias_voltage;
9b34e6cc
ZZ		 115};
116
117/*
118 * mic_bias power on/off share the same register bits with
119 * output impedance of mic bias, when power on mic bias, we
120 * need reclaim it to impedance value.
121 * 0x0 = Powered off
122 * 0x1 = 2Kohm
123 * 0x2 = 4Kohm
124 * 0x3 = 8Kohm
125 */
126static int mic_bias_event(struct snd_soc_dapm_widget *w,
127 struct snd_kcontrol *kcontrol, int event)
128{
73bffd17
LPC		 129 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
130 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
bd0593f5 131
9b34e6cc
ZZ		 132 switch (event) {
133 case SND_SOC_DAPM_POST_PMU:
bd0593f5 134 /* change mic bias resistor */
73bffd17 135 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
bd0593f5
JMH		 136 SGTL5000_BIAS_R_MASK,
137 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 138 break;
139
140 case SND_SOC_DAPM_PRE_PMD:
73bffd17 141 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 142 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 143 break;
144 }
145 return 0;
146}
147
148/*
f0cdcf3a
ZZ		 149 * As manual described, ADC/DAC only works when VAG powerup,
150 * So enabled VAG before ADC/DAC up.
151 * In power down case, we need wait 400ms when vag fully ramped down.
9b34e6cc 152 */
f0cdcf3a 153static int power_vag_event(struct snd_soc_dapm_widget *w,
9b34e6cc
ZZ		 154 struct snd_kcontrol *kcontrol, int event)
155{
73bffd17 156 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
f091f3f0
LW		 157 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
158
9b34e6cc 159 switch (event) {
dd4d2d6d 160 case SND_SOC_DAPM_POST_PMU:
73bffd17 161 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
9b34e6cc 162 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
c803cc2d 163 msleep(400);
9b34e6cc
ZZ		 164 break;
165
dd4d2d6d 166 case SND_SOC_DAPM_PRE_PMD:
f091f3f0
LW		 167 /*
168 * Don't clear VAG_POWERUP, when both DAC and ADC are
169 * operational to prevent inadvertently starving the
170 * other one of them.
171 */
73bffd17 172 if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) &
f091f3f0 173 mask) != mask) {
73bffd17 174 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
f091f3f0
LW		 175 SGTL5000_VAG_POWERUP, 0);
176 msleep(400);
177 }
9b34e6cc
ZZ		 178 break;
179 default:
180 break;
181 }
182
183 return 0;
184}
185
186/* input sources for ADC */
187static const char *adc_mux_text[] = {
188 "MIC_IN", "LINE_IN"
189};
190
c8ed6504
TI		 191static SOC_ENUM_SINGLE_DECL(adc_enum,
192 SGTL5000_CHIP_ANA_CTRL, 2,
193 adc_mux_text);
9b34e6cc
ZZ		 194
195static const struct snd_kcontrol_new adc_mux =
196SOC_DAPM_ENUM("Capture Mux", adc_enum);
197
198/* input sources for DAC */
199static const char *dac_mux_text[] = {
200 "DAC", "LINE_IN"
201};
202
c8ed6504
TI		 203static SOC_ENUM_SINGLE_DECL(dac_enum,
204 SGTL5000_CHIP_ANA_CTRL, 6,
205 dac_mux_text);
9b34e6cc
ZZ		 206
207static const struct snd_kcontrol_new dac_mux =
208SOC_DAPM_ENUM("Headphone Mux", dac_enum);
209
210static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
211 SND_SOC_DAPM_INPUT("LINE_IN"),
212 SND_SOC_DAPM_INPUT("MIC_IN"),
213
214 SND_SOC_DAPM_OUTPUT("HP_OUT"),
215 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
216
8fc8ec92
MB		 217 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
218 mic_bias_event,
219 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9b34e6cc 220
f0cdcf3a
ZZ		 221 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
222 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
9b34e6cc
ZZ		 223
224 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
225 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
226
227 /* aif for i2s input */
228 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
229 0, SGTL5000_CHIP_DIG_POWER,
230 0, 0),
231
232 /* aif for i2s output */
233 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
234 0, SGTL5000_CHIP_DIG_POWER,
235 1, 0),
236
f0cdcf3a 237 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
9b34e6cc 238 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
dd4d2d6d
MV		 239
240 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
241 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
9b34e6cc
ZZ		 242};
243
244/* routes for sgtl5000 */
89989637 245static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
9b34e6cc
ZZ		 246 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
247 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
248
249 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
250 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
251
252 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
253 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
254 {"LO", NULL, "DAC"}, /* dac --> line_out */
255
256 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
257 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
258
259 {"LINE_OUT", NULL, "LO"},
260 {"HP_OUT", NULL, "HP"},
261};
262
263/* custom function to fetch info of PCM playback volume */
264static int dac_info_volsw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_info *uinfo)
266{
267 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
268 uinfo->count = 2;
269 uinfo->value.integer.min = 0;
270 uinfo->value.integer.max = 0xfc - 0x3c;
271 return 0;
272}
273
274/*
275 * custom function to get of PCM playback volume
276 *
277 * dac volume register
278 * 15-------------8-7--------------0
279 * | R channel vol | L channel vol |
280 * -------------------------------
281 *
282 * PCM volume with 0.5017 dB steps from 0 to -90 dB
283 *
284 * register values map to dB
285 * 0x3B and less = Reserved
286 * 0x3C = 0 dB
287 * 0x3D = -0.5 dB
288 * 0xF0 = -90 dB
289 * 0xFC and greater = Muted
290 *
291 * register value map to userspace value
292 *
293 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
294 * ------------------------------
295 * userspace value 0xc0 0
296 */
297static int dac_get_volsw(struct snd_kcontrol *kcontrol,
298 struct snd_ctl_elem_value *ucontrol)
299{
ea53bf77 300 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 301 int reg;
302 int l;
303 int r;
304
305 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
306
307 /* get left channel volume */
308 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
309
310 /* get right channel volume */
311 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
312
313 /* make sure value fall in (0x3c,0xfc) */
314 l = clamp(l, 0x3c, 0xfc);
315 r = clamp(r, 0x3c, 0xfc);
316
317 /* invert it and map to userspace value */
318 l = 0xfc - l;
319 r = 0xfc - r;
320
321 ucontrol->value.integer.value[0] = l;
322 ucontrol->value.integer.value[1] = r;
323
324 return 0;
325}
326
327/*
328 * custom function to put of PCM playback volume
329 *
330 * dac volume register
331 * 15-------------8-7--------------0
332 * | R channel vol | L channel vol |
333 * -------------------------------
334 *
335 * PCM volume with 0.5017 dB steps from 0 to -90 dB
336 *
337 * register values map to dB
338 * 0x3B and less = Reserved
339 * 0x3C = 0 dB
340 * 0x3D = -0.5 dB
341 * 0xF0 = -90 dB
342 * 0xFC and greater = Muted
343 *
344 * userspace value map to register value
345 *
346 * userspace value 0xc0 0
347 * ------------------------------
348 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
349 */
350static int dac_put_volsw(struct snd_kcontrol *kcontrol,
351 struct snd_ctl_elem_value *ucontrol)
352{
ea53bf77 353 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 354 int reg;
355 int l;
356 int r;
357
358 l = ucontrol->value.integer.value[0];
359 r = ucontrol->value.integer.value[1];
360
361 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
362 l = clamp(l, 0, 0xfc - 0x3c);
363 r = clamp(r, 0, 0xfc - 0x3c);
364
365 /* invert it, get the value can be set to register */
366 l = 0xfc - l;
367 r = 0xfc - r;
368
369 /* shift to get the register value */
370 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
371 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
372
373 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
374
375 return 0;
376}
377
378static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
379
380/* tlv for mic gain, 0db 20db 30db 40db */
53eb1ca3 381static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
9b34e6cc 382 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
53eb1ca3
LPC		 383 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
384);
9b34e6cc
ZZ		 385
386/* tlv for hp volume, -51.5db to 12.0db, step .5db */
387static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
388
389static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
390 /* SOC_DOUBLE_S8_TLV with invert */
391 {
392 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
393 .name = "PCM Playback Volume",
394 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
395 SNDRV_CTL_ELEM_ACCESS_READWRITE,
396 .info = dac_info_volsw,
397 .get = dac_get_volsw,
398 .put = dac_put_volsw,
399 },
400
401 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
402 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
403 SGTL5000_CHIP_ANA_ADC_CTRL,
65f2b226 404 8, 1, 0, capture_6db_attenuate),
9b34e6cc
ZZ		 405 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
406
407 SOC_DOUBLE_TLV("Headphone Playback Volume",
408 SGTL5000_CHIP_ANA_HP_CTRL,
409 0, 8,
410 0x7f, 1,
411 headphone_volume),
412 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
413 5, 1, 0),
414
415 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
b50684da 416 0, 3, 0, mic_gain_tlv),
9b34e6cc
ZZ		 417};
418
419/* mute the codec used by alsa core */
420static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
421{
422 struct snd_soc_codec *codec = codec_dai->codec;
423 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
424
425 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
426 adcdac_ctrl, mute ? adcdac_ctrl : 0);
427
428 return 0;
429}
430
431/* set codec format */
432static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
433{
434 struct snd_soc_codec *codec = codec_dai->codec;
435 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
436 u16 i2sctl = 0;
437
438 sgtl5000->master = 0;
439 /*
440 * i2s clock and frame master setting.
441 * ONLY support:
442 * - clock and frame slave,
443 * - clock and frame master
444 */
445 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
446 case SND_SOC_DAIFMT_CBS_CFS:
447 break;
448 case SND_SOC_DAIFMT_CBM_CFM:
449 i2sctl |= SGTL5000_I2S_MASTER;
450 sgtl5000->master = 1;
451 break;
452 default:
453 return -EINVAL;
454 }
455
456 /* setting i2s data format */
457 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
458 case SND_SOC_DAIFMT_DSP_A:
9ee802ec 459 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 460 break;
461 case SND_SOC_DAIFMT_DSP_B:
9ee802ec 462 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 463 i2sctl |= SGTL5000_I2S_LRALIGN;
464 break;
465 case SND_SOC_DAIFMT_I2S:
9ee802ec 466 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 467 break;
468 case SND_SOC_DAIFMT_RIGHT_J:
9ee802ec 469 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 470 i2sctl |= SGTL5000_I2S_LRPOL;
471 break;
472 case SND_SOC_DAIFMT_LEFT_J:
9ee802ec 473 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 474 i2sctl |= SGTL5000_I2S_LRALIGN;
475 break;
476 default:
477 return -EINVAL;
478 }
479
480 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
481
482 /* Clock inversion */
483 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
484 case SND_SOC_DAIFMT_NB_NF:
485 break;
486 case SND_SOC_DAIFMT_IB_NF:
487 i2sctl |= SGTL5000_I2S_SCLK_INV;
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
494
495 return 0;
496}
497
498/* set codec sysclk */
499static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
500 int clk_id, unsigned int freq, int dir)
501{
502 struct snd_soc_codec *codec = codec_dai->codec;
503 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
504
505 switch (clk_id) {
506 case SGTL5000_SYSCLK:
507 sgtl5000->sysclk = freq;
508 break;
509 default:
510 return -EINVAL;
511 }
512
513 return 0;
514}
515
516/*
517 * set clock according to i2s frame clock,
7f6d75d7
FE		 518 * sgtl5000 provides 2 clock sources:
519 * 1. sys_mclk: sample freq can only be configured to
9b34e6cc 520 * 1/256, 1/384, 1/512 of sys_mclk.
7f6d75d7 521 * 2. pll: can derive any audio clocks.
9b34e6cc
ZZ		 522 *
523 * clock setting rules:
7f6d75d7
FE		 524 * 1. in slave mode, only sys_mclk can be used
525 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
526 * and above.
527 * 3. usage of sys_mclk is preferred over pll to save power.
9b34e6cc
ZZ		 528 */
529static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
530{
531 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
532 int clk_ctl = 0;
533 int sys_fs; /* sample freq */
534
535 /*
536 * sample freq should be divided by frame clock,
7f6d75d7
FE		 537 * if frame clock is lower than 44.1 kHz, sample freq should be set to
538 * 32 kHz or 44.1 kHz.
9b34e6cc
ZZ		 539 */
540 switch (frame_rate) {
541 case 8000:
542 case 16000:
543 sys_fs = 32000;
544 break;
545 case 11025:
546 case 22050:
547 sys_fs = 44100;
548 break;
549 default:
550 sys_fs = frame_rate;
551 break;
552 }
553
554 /* set divided factor of frame clock */
555 switch (sys_fs / frame_rate) {
556 case 4:
557 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
558 break;
559 case 2:
560 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
561 break;
562 case 1:
563 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
564 break;
565 default:
566 return -EINVAL;
567 }
568
569 /* set the sys_fs according to frame rate */
570 switch (sys_fs) {
571 case 32000:
572 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
573 break;
574 case 44100:
575 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
576 break;
577 case 48000:
578 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
579 break;
580 case 96000:
581 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
582 break;
583 default:
584 dev_err(codec->dev, "frame rate %d not supported\n",
585 frame_rate);
586 return -EINVAL;
587 }
588
589 /*
590 * calculate the divider of mclk/sample_freq,
7f6d75d7
FE		 591 * factor of freq = 96 kHz can only be 256, since mclk is in the range
592 * of 8 MHz - 27 MHz
9b34e6cc 593 */
2a4cfd10 594 switch (sgtl5000->sysclk / frame_rate) {
9b34e6cc
ZZ		 595 case 256:
596 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
597 SGTL5000_MCLK_FREQ_SHIFT;
598 break;
599 case 384:
600 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
601 SGTL5000_MCLK_FREQ_SHIFT;
602 break;
603 case 512:
604 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
605 SGTL5000_MCLK_FREQ_SHIFT;
606 break;
607 default:
7f6d75d7 608 /* if mclk does not satisfy the divider, use pll */
9b34e6cc
ZZ		 609 if (sgtl5000->master) {
610 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
611 SGTL5000_MCLK_FREQ_SHIFT;
612 } else {
613 dev_err(codec->dev,
614 "PLL not supported in slave mode\n");
fa558d01
FE		 615 dev_err(codec->dev, "%d ratio is not supported. "
616 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
2a4cfd10 617 sgtl5000->sysclk / frame_rate);
9b34e6cc
ZZ		 618 return -EINVAL;
619 }
620 }
621
622 /* if using pll, please check manual 6.4.2 for detail */
623 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
624 u64 out, t;
625 int div2;
626 int pll_ctl;
627 unsigned int in, int_div, frac_div;
628
629 if (sgtl5000->sysclk > 17000000) {
630 div2 = 1;
631 in = sgtl5000->sysclk / 2;
632 } else {
633 div2 = 0;
634 in = sgtl5000->sysclk;
635 }
636 if (sys_fs == 44100)
637 out = 180633600;
638 else
639 out = 196608000;
640 t = do_div(out, in);
641 int_div = out;
642 t *= 2048;
643 do_div(t, in);
644 frac_div = t;
645 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
646 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
647
648 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
649 if (div2)
650 snd_soc_update_bits(codec,
651 SGTL5000_CHIP_CLK_TOP_CTRL,
652 SGTL5000_INPUT_FREQ_DIV2,
653 SGTL5000_INPUT_FREQ_DIV2);
654 else
655 snd_soc_update_bits(codec,
656 SGTL5000_CHIP_CLK_TOP_CTRL,
657 SGTL5000_INPUT_FREQ_DIV2,
658 0);
659
660 /* power up pll */
661 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
662 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
663 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
e06e4c2d
OS		 664
665 /* if using pll, clk_ctrl must be set after pll power up */
666 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
9b34e6cc 667 } else {
e06e4c2d
OS		 668 /* otherwise, clk_ctrl must be set before pll power down */
669 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
670
9b34e6cc
ZZ		 671 /* power down pll */
672 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
673 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
674 0);
675 }
676
9b34e6cc
ZZ		 677 return 0;
678}
679
680/*
681 * Set PCM DAI bit size and sample rate.
682 * input: params_rate, params_fmt
683 */
684static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
685 struct snd_pcm_hw_params *params,
686 struct snd_soc_dai *dai)
687{
e6968a17 688 struct snd_soc_codec *codec = dai->codec;
9b34e6cc
ZZ		 689 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
690 int channels = params_channels(params);
691 int i2s_ctl = 0;
692 int stereo;
693 int ret;
694
695 /* sysclk should already set */
696 if (!sgtl5000->sysclk) {
697 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
698 return -EFAULT;
699 }
700
701 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
702 stereo = SGTL5000_DAC_STEREO;
703 else
704 stereo = SGTL5000_ADC_STEREO;
705
706 /* set mono to save power */
707 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
708 channels == 1 ? 0 : stereo);
709
710 /* set codec clock base on lrclk */
711 ret = sgtl5000_set_clock(codec, params_rate(params));
712 if (ret)
713 return ret;
714
715 /* set i2s data format */
dacc2aef
MB		 716 switch (params_width(params)) {
717 case 16:
9b34e6cc
ZZ		 718 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
719 return -EINVAL;
720 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
721 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
722 SGTL5000_I2S_SCLKFREQ_SHIFT;
723 break;
dacc2aef 724 case 20:
9b34e6cc
ZZ		 725 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
726 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
727 SGTL5000_I2S_SCLKFREQ_SHIFT;
728 break;
dacc2aef 729 case 24:
9b34e6cc
ZZ		 730 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
731 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
732 SGTL5000_I2S_SCLKFREQ_SHIFT;
733 break;
dacc2aef 734 case 32:
9b34e6cc
ZZ		 735 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
736 return -EINVAL;
737 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
738 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
739 SGTL5000_I2S_SCLKFREQ_SHIFT;
740 break;
741 default:
742 return -EINVAL;
743 }
744
33cb92cf
AL		 745 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
746 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
747 i2s_ctl);
9b34e6cc
ZZ		 748
749 return 0;
750}
751
9b34e6cc
ZZ		 752/*
753 * set dac bias
754 * common state changes:
755 * startup:
756 * off --> standby --> prepare --> on
757 * standby --> prepare --> on
758 *
759 * stop:
760 * on --> prepare --> standby
761 */
762static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
763 enum snd_soc_bias_level level)
764{
765 int ret;
766 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
767
768 switch (level) {
769 case SND_SOC_BIAS_ON:
770 case SND_SOC_BIAS_PREPARE:
771 break;
772 case SND_SOC_BIAS_STANDBY:
8533eb24 773 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
9b34e6cc 774 ret = regulator_bulk_enable(
940adb28 775 sgtl5000->num_supplies,
9b34e6cc
ZZ		 776 sgtl5000->supplies);
777 if (ret)
778 return ret;
779 udelay(10);
2bdc1bb2
MB		 780
781 regcache_cache_only(sgtl5000->regmap, false);
782
783 ret = regcache_sync(sgtl5000->regmap);
784 if (ret != 0) {
785 dev_err(codec->dev,
786 "Failed to restore cache: %d\n", ret);
787
788 regcache_cache_only(sgtl5000->regmap, true);
940adb28 789 regulator_bulk_disable(sgtl5000->num_supplies,
2bdc1bb2
MB		 790 sgtl5000->supplies);
791
792 return ret;
793 }
9b34e6cc
ZZ		 794 }
795
796 break;
797 case SND_SOC_BIAS_OFF:
2bdc1bb2 798 regcache_cache_only(sgtl5000->regmap, true);
940adb28
EN		 799 regulator_bulk_disable(sgtl5000->num_supplies,
800 sgtl5000->supplies);
9b34e6cc
ZZ		 801 break;
802 }
803
9b34e6cc
ZZ		 804 return 0;
805}
806
807#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
808 SNDRV_PCM_FMTBIT_S20_3LE |\
809 SNDRV_PCM_FMTBIT_S24_LE |\
810 SNDRV_PCM_FMTBIT_S32_LE)
811
85e7652d 812static const struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 813 .hw_params = sgtl5000_pcm_hw_params,
814 .digital_mute = sgtl5000_digital_mute,
815 .set_fmt = sgtl5000_set_dai_fmt,
816 .set_sysclk = sgtl5000_set_dai_sysclk,
817};
818
819static struct snd_soc_dai_driver sgtl5000_dai = {
820 .name = "sgtl5000",
821 .playback = {
822 .stream_name = "Playback",
823 .channels_min = 1,
824 .channels_max = 2,
825 /*
826 * only support 8~48K + 96K,
827 * TODO modify hw_param to support more
828 */
829 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
830 .formats = SGTL5000_FORMATS,
831 },
832 .capture = {
833 .stream_name = "Capture",
834 .channels_min = 1,
835 .channels_max = 2,
836 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
837 .formats = SGTL5000_FORMATS,
838 },
839 .ops = &sgtl5000_ops,
840 .symmetric_rates = 1,
841};
842
e5d80e82 843static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
9b34e6cc
ZZ		 844{
845 switch (reg) {
846 case SGTL5000_CHIP_ID:
847 case SGTL5000_CHIP_ADCDAC_CTRL:
848 case SGTL5000_CHIP_ANA_STATUS:
e5d80e82 849 return true;
9b34e6cc
ZZ		 850 }
851
e5d80e82
FE		 852 return false;
853}
854
855static bool sgtl5000_readable(struct device *dev, unsigned int reg)
856{
857 switch (reg) {
858 case SGTL5000_CHIP_ID:
859 case SGTL5000_CHIP_DIG_POWER:
860 case SGTL5000_CHIP_CLK_CTRL:
861 case SGTL5000_CHIP_I2S_CTRL:
862 case SGTL5000_CHIP_SSS_CTRL:
863 case SGTL5000_CHIP_ADCDAC_CTRL:
864 case SGTL5000_CHIP_DAC_VOL:
865 case SGTL5000_CHIP_PAD_STRENGTH:
866 case SGTL5000_CHIP_ANA_ADC_CTRL:
867 case SGTL5000_CHIP_ANA_HP_CTRL:
868 case SGTL5000_CHIP_ANA_CTRL:
869 case SGTL5000_CHIP_LINREG_CTRL:
870 case SGTL5000_CHIP_REF_CTRL:
871 case SGTL5000_CHIP_MIC_CTRL:
872 case SGTL5000_CHIP_LINE_OUT_CTRL:
873 case SGTL5000_CHIP_LINE_OUT_VOL:
874 case SGTL5000_CHIP_ANA_POWER:
875 case SGTL5000_CHIP_PLL_CTRL:
876 case SGTL5000_CHIP_CLK_TOP_CTRL:
877 case SGTL5000_CHIP_ANA_STATUS:
878 case SGTL5000_CHIP_SHORT_CTRL:
879 case SGTL5000_CHIP_ANA_TEST2:
880 case SGTL5000_DAP_CTRL:
881 case SGTL5000_DAP_PEQ:
882 case SGTL5000_DAP_BASS_ENHANCE:
883 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
884 case SGTL5000_DAP_AUDIO_EQ:
885 case SGTL5000_DAP_SURROUND:
886 case SGTL5000_DAP_FLT_COEF_ACCESS:
887 case SGTL5000_DAP_COEF_WR_B0_MSB:
888 case SGTL5000_DAP_COEF_WR_B0_LSB:
889 case SGTL5000_DAP_EQ_BASS_BAND0:
890 case SGTL5000_DAP_EQ_BASS_BAND1:
891 case SGTL5000_DAP_EQ_BASS_BAND2:
892 case SGTL5000_DAP_EQ_BASS_BAND3:
893 case SGTL5000_DAP_EQ_BASS_BAND4:
894 case SGTL5000_DAP_MAIN_CHAN:
895 case SGTL5000_DAP_MIX_CHAN:
896 case SGTL5000_DAP_AVC_CTRL:
897 case SGTL5000_DAP_AVC_THRESHOLD:
898 case SGTL5000_DAP_AVC_ATTACK:
899 case SGTL5000_DAP_AVC_DECAY:
900 case SGTL5000_DAP_COEF_WR_B1_MSB:
901 case SGTL5000_DAP_COEF_WR_B1_LSB:
902 case SGTL5000_DAP_COEF_WR_B2_MSB:
903 case SGTL5000_DAP_COEF_WR_B2_LSB:
904 case SGTL5000_DAP_COEF_WR_A1_MSB:
905 case SGTL5000_DAP_COEF_WR_A1_LSB:
906 case SGTL5000_DAP_COEF_WR_A2_MSB:
907 case SGTL5000_DAP_COEF_WR_A2_LSB:
908 return true;
909
910 default:
911 return false;
912 }
9b34e6cc
ZZ		 913}
914
1f39d939
AS		 915/*
916 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
917 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
918 * The calculatation was done for all possible register values which
919 * is the array index and the following formula: 10^((idx−15)/40) * 100
920 */
921static const u8 vol_quot_table[] = {
922 42, 45, 47, 50, 53, 56, 60, 63,
923 67, 71, 75, 79, 84, 89, 94, 100,
924 106, 112, 119, 126, 133, 141, 150, 158,
925 168, 178, 188, 200, 211, 224, 237, 251
926};
927
9b34e6cc
ZZ		 928/*
929 * sgtl5000 has 3 internal power supplies:
930 * 1. VAG, normally set to vdda/2
7f6d75d7 931 * 2. charge pump, set to different value
9b34e6cc
ZZ		 932 * according to voltage of vdda and vddio
933 * 3. line out VAG, normally set to vddio/2
934 *
935 * and should be set according to:
936 * 1. vddd provided by external or not
937 * 2. vdda and vddio voltage value. > 3.1v or not
9b34e6cc
ZZ		 938 */
939static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
940{
941 int vddd;
942 int vdda;
943 int vddio;
944 u16 ana_pwr;
945 u16 lreg_ctrl;
946 int vag;
d2b7c2aa 947 int lo_vag;
1f39d939
AS		 948 int vol_quot;
949 int lo_vol;
950 size_t i;
9b34e6cc
ZZ		 951 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
952
953 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
954 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
940adb28
EN		 955 vddd = (sgtl5000->num_supplies > VDDD)
956 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
957 : LDO_VOLTAGE;
9b34e6cc
ZZ		 958
959 vdda = vdda / 1000;
960 vddio = vddio / 1000;
961 vddd = vddd / 1000;
962
963 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
964 dev_err(codec->dev, "regulator voltage not set correctly\n");
965
966 return -EINVAL;
967 }
968
969 /* according to datasheet, maximum voltage of supplies */
970 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
971 dev_err(codec->dev,
cf1ee98d 972 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
9b34e6cc
ZZ		 973 vdda, vddio, vddd);
974
975 return -EINVAL;
976 }
977
978 /* reset value */
979 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
980 ana_pwr |= SGTL5000_DAC_STEREO |
981 SGTL5000_ADC_STEREO |
982 SGTL5000_REFTOP_POWERUP;
983 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
984
985 if (vddio < 3100 && vdda < 3100) {
986 /* enable internal oscillator used for charge pump */
987 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
988 SGTL5000_INT_OSC_EN,
989 SGTL5000_INT_OSC_EN);
990 /* Enable VDDC charge pump */
991 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
992 } else if (vddio >= 3100 && vdda >= 3100) {
c7d910b8 993 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
9b34e6cc
ZZ		 994 /* VDDC use VDDIO rail */
995 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
996 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
997 SGTL5000_VDDC_MAN_ASSN_SHIFT;
998 }
999
1000 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1001
1002 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1003
9b34e6cc
ZZ		 1004 /*
1005 * set ADC/DAC VAG to vdda / 2,
1006 * should stay in range (0.8v, 1.575v)
1007 */
1008 vag = vdda / 2;
1009 if (vag <= SGTL5000_ANA_GND_BASE)
1010 vag = 0;
1011 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1012 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1013 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1014 else
1015 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1016
1017 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
33cb92cf 1018 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
9b34e6cc
ZZ		 1019
1020 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
d2b7c2aa
AS		 1021 lo_vag = vddio / 2;
1022 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1023 lo_vag = 0;
1024 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
9b34e6cc 1025 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
d2b7c2aa 1026 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
9b34e6cc 1027 else
d2b7c2aa 1028 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
9b34e6cc
ZZ		 1029 SGTL5000_LINE_OUT_GND_STP;
1030
1031 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
33cb92cf
AL		 1032 SGTL5000_LINE_OUT_CURRENT_MASK |
1033 SGTL5000_LINE_OUT_GND_MASK,
d2b7c2aa 1034 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
9b34e6cc
ZZ		 1035 SGTL5000_LINE_OUT_CURRENT_360u <<
1036 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1037
1f39d939
AS		 1038 /*
1039 * Set lineout output level in range (0..31)
1040 * the same value is used for right and left channel
1041 *
1042 * Searching for a suitable index solving this formula:
1043 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1044 */
1045 vol_quot = (vag * 100) / lo_vag;
1046 lo_vol = 0;
1047 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1048 if (vol_quot >= vol_quot_table[i])
1049 lo_vol = i;
1050 else
1051 break;
1052 }
1053
1054 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1055 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1056 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1057 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1058 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1059
9b34e6cc
ZZ		 1060 return 0;
1061}
1062
940adb28 1063static int sgtl5000_enable_regulators(struct i2c_client *client)
9b34e6cc 1064{
9b34e6cc 1065 int ret;
9b34e6cc
ZZ		 1066 int i;
1067 int external_vddd = 0;
11db0da8 1068 struct regulator *vddd;
940adb28 1069 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc
ZZ		 1070
1071 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1072 sgtl5000->supplies[i].supply = supply_names[i];
1073
940adb28
EN		 1074 vddd = regulator_get_optional(&client->dev, "VDDD");
1075 if (IS_ERR(vddd)) {
1076 /* See if it's just not registered yet */
1077 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1078 return -EPROBE_DEFER;
1079 } else {
1080 external_vddd = 1;
1081 regulator_put(vddd);
9b34e6cc
ZZ		 1082 }
1083
940adb28
EN		 1084 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1085 - 1 + external_vddd;
1086 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
11db0da8
SG		 1087 sgtl5000->supplies);
1088 if (ret)
940adb28 1089 return ret;
9b34e6cc 1090
940adb28
EN		 1091 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1092 sgtl5000->supplies);
1093 if (!ret)
1094 usleep_range(10, 20);
1095 else
1096 regulator_bulk_free(sgtl5000->num_supplies,
1097 sgtl5000->supplies);
9b34e6cc 1098
9b34e6cc 1099 return ret;
9b34e6cc
ZZ		 1100}
1101
1102static int sgtl5000_probe(struct snd_soc_codec *codec)
1103{
1104 int ret;
1105 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1106
9b34e6cc
ZZ		 1107 /* power up sgtl5000 */
1108 ret = sgtl5000_set_power_regs(codec);
1109 if (ret)
1110 goto err;
1111
1112 /* enable small pop, introduce 400ms delay in turning off */
1113 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
c251ea7b 1114 SGTL5000_SMALL_POP, 1);
9b34e6cc
ZZ		 1115
1116 /* disable short cut detector */
1117 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1118
1119 /*
1120 * set i2s as default input of sound switch
1121 * TODO: add sound switch to control and dapm widge.
1122 */
1123 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1124 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1125 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1126 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1127
1128 /* enable dac volume ramp by default */
1129 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1130 SGTL5000_DAC_VOL_RAMP_EN |
1131 SGTL5000_DAC_MUTE_RIGHT |
1132 SGTL5000_DAC_MUTE_LEFT);
1133
1134 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1135
1136 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1137 SGTL5000_HP_ZCD_EN |
1138 SGTL5000_ADC_ZCD_EN);
1139
bd0593f5
JMH		 1140 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1141 SGTL5000_BIAS_R_MASK,
1142 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc 1143
87357797 1144 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
e256da84
GR		 1145 SGTL5000_BIAS_VOLT_MASK,
1146 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
9b34e6cc
ZZ		 1147 /*
1148 * disable DAP
1149 * TODO:
1150 * Enable DAP in kcontrol and dapm.
1151 */
1152 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1153
9b34e6cc
ZZ		 1154 return 0;
1155
1156err:
9b34e6cc
ZZ		 1157 return ret;
1158}
1159
1160static int sgtl5000_remove(struct snd_soc_codec *codec)
1161{
9b34e6cc
ZZ		 1162 return 0;
1163}
1164
61a142b7 1165static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1166 .probe = sgtl5000_probe,
1167 .remove = sgtl5000_remove,
9b34e6cc 1168 .set_bias_level = sgtl5000_set_bias_level,
e649057a 1169 .suspend_bias_off = true,
89989637
FE		 1170 .controls = sgtl5000_snd_controls,
1171 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
5e0ac527
MB		 1172 .dapm_widgets = sgtl5000_dapm_widgets,
1173 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1174 .dapm_routes = sgtl5000_dapm_routes,
1175 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
9b34e6cc
ZZ		 1176};
1177
e5d80e82
FE		 1178static const struct regmap_config sgtl5000_regmap = {
1179 .reg_bits = 16,
1180 .val_bits = 16,
cb23e852 1181 .reg_stride = 2,
e5d80e82
FE		 1182
1183 .max_register = SGTL5000_MAX_REG_OFFSET,
1184 .volatile_reg = sgtl5000_volatile,
1185 .readable_reg = sgtl5000_readable,
1186
1187 .cache_type = REGCACHE_RBTREE,
1188 .reg_defaults = sgtl5000_reg_defaults,
1189 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1190};
1191
af8ee112
FE		 1192/*
1193 * Write all the default values from sgtl5000_reg_defaults[] array into the
1194 * sgtl5000 registers, to make sure we always start with the sane registers
1195 * values as stated in the datasheet.
1196 *
1197 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1198 * we follow this approach to guarantee we always start from the default values
1199 * and avoid problems like, not being able to probe after an audio playback
1200 * followed by a system reset or a 'reboot' command in Linux
1201 */
f219b169 1202static void sgtl5000_fill_defaults(struct i2c_client *client)
af8ee112 1203{
f219b169 1204 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
af8ee112
FE		 1205 int i, ret, val, index;
1206
1207 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1208 val = sgtl5000_reg_defaults[i].def;
1209 index = sgtl5000_reg_defaults[i].reg;
1210 ret = regmap_write(sgtl5000->regmap, index, val);
1211 if (ret)
f219b169
EN		 1212 dev_err(&client->dev,
1213 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1214 __func__, ret, index, val);
af8ee112 1215 }
af8ee112
FE		 1216}
1217
7a79e94e
BP		 1218static int sgtl5000_i2c_probe(struct i2c_client *client,
1219 const struct i2c_device_id *id)
9b34e6cc
ZZ		 1220{
1221 struct sgtl5000_priv *sgtl5000;
b871f1ad 1222 int ret, reg, rev;
bd0593f5
JMH		 1223 struct device_node *np = client->dev.of_node;
1224 u32 value;
3d632cc8 1225 u16 ana_pwr;
9b34e6cc 1226
3f7256fe 1227 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
9b34e6cc
ZZ		 1228 if (!sgtl5000)
1229 return -ENOMEM;
1230
940adb28
EN		 1231 i2c_set_clientdata(client, sgtl5000);
1232
1233 ret = sgtl5000_enable_regulators(client);
1234 if (ret)
1235 return ret;
1236
e5d80e82
FE		 1237 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1238 if (IS_ERR(sgtl5000->regmap)) {
1239 ret = PTR_ERR(sgtl5000->regmap);
1240 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
940adb28 1241 goto disable_regs;
e5d80e82
FE		 1242 }
1243
9e13f345
FE		 1244 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1245 if (IS_ERR(sgtl5000->mclk)) {
1246 ret = PTR_ERR(sgtl5000->mclk);
1247 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
46a5905e
SG		 1248 /* Defer the probe to see if the clk will be provided later */
1249 if (ret == -ENOENT)
940adb28
EN		 1250 ret = -EPROBE_DEFER;
1251 goto disable_regs;
9e13f345
FE		 1252 }
1253
1254 ret = clk_prepare_enable(sgtl5000->mclk);
940adb28
EN		 1255 if (ret) {
1256 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1257 goto disable_regs;
1258 }
9e13f345 1259
58cc9c9a
EN		 1260 /* Need 8 clocks before I2C accesses */
1261 udelay(1);
1262
b871f1ad
FE		 1263 /* read chip information */
1264 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
940adb28
EN		 1265 if (ret) {
1266 dev_err(&client->dev, "Error reading chip id %d\n", ret);
9e13f345 1267 goto disable_clk;
940adb28 1268 }
b871f1ad
FE		 1269
1270 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1271 SGTL5000_PARTID_PART_ID) {
1272 dev_err(&client->dev,
1273 "Device with ID register %x is not a sgtl5000\n", reg);
9e13f345
FE		 1274 ret = -ENODEV;
1275 goto disable_clk;
b871f1ad
FE		 1276 }
1277
1278 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1279 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
252e91ff 1280 sgtl5000->revision = rev;
b871f1ad 1281
940adb28 1282 /* Follow section 2.2.1.1 of AN3663 */
3d632cc8 1283 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
940adb28
EN		 1284 if (sgtl5000->num_supplies <= VDDD) {
1285 /* internal VDDD at 1.2V */
3d632cc8
EN		 1286 ret = regmap_update_bits(sgtl5000->regmap,
1287 SGTL5000_CHIP_LINREG_CTRL,
1288 SGTL5000_LINREG_VDDD_MASK,
1289 LINREG_VDDD);
1290 if (ret)
1291 dev_err(&client->dev,
1292 "Error %d setting LINREG_VDDD\n", ret);
1293
1294 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1295 dev_info(&client->dev,
1296 "Using internal LDO instead of VDDD: check ER1\n");
940adb28
EN		 1297 } else {
1298 /* using external LDO for VDDD
1299 * Clear startup powerup and simple powerup
1300 * bits to save power
1301 */
3d632cc8
EN		 1302 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1303 | SGTL5000_LINREG_SIMPLE_POWERUP);
940adb28
EN		 1304 dev_dbg(&client->dev, "Using external VDDD\n");
1305 }
3d632cc8
EN		 1306 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1307 if (ret)
1308 dev_err(&client->dev,
1309 "Error %d setting CHIP_ANA_POWER to %04x\n",
1310 ret, ana_pwr);
940adb28 1311
bd0593f5
JMH		 1312 if (np) {
1313 if (!of_property_read_u32(np,
1314 "micbias-resistor-k-ohms", &value)) {
1315 switch (value) {
1316 case SGTL5000_MICBIAS_OFF:
1317 sgtl5000->micbias_resistor = 0;
1318 break;
1319 case SGTL5000_MICBIAS_2K:
1320 sgtl5000->micbias_resistor = 1;
1321 break;
1322 case SGTL5000_MICBIAS_4K:
1323 sgtl5000->micbias_resistor = 2;
1324 break;
1325 case SGTL5000_MICBIAS_8K:
1326 sgtl5000->micbias_resistor = 3;
1327 break;
1328 default:
1329 sgtl5000->micbias_resistor = 2;
1330 dev_err(&client->dev,
1331 "Unsuitable MicBias resistor\n");
1332 }
1333 } else {
1334 /* default is 4Kohms */
1335 sgtl5000->micbias_resistor = 2;
1336 }
87357797
JMH		 1337 if (!of_property_read_u32(np,
1338 "micbias-voltage-m-volts", &value)) {
1339 /* 1250mV => 0 */
1340 /* steps of 250mV */
1341 if ((value >= 1250) && (value <= 3000))
1342 sgtl5000->micbias_voltage = (value / 250) - 5;
1343 else {
1344 sgtl5000->micbias_voltage = 0;
bd0593f5 1345 dev_err(&client->dev,
fb97d75b 1346 "Unsuitable MicBias voltage\n");
bd0593f5
JMH		 1347 }
1348 } else {
87357797 1349 sgtl5000->micbias_voltage = 0;
bd0593f5
JMH		 1350 }
1351 }
1352
af8ee112 1353 /* Ensure sgtl5000 will start with sane register values */
f219b169 1354 sgtl5000_fill_defaults(client);
af8ee112 1355
9b34e6cc
ZZ		 1356 ret = snd_soc_register_codec(&client->dev,
1357 &sgtl5000_driver, &sgtl5000_dai, 1);
9e13f345
FE		 1358 if (ret)
1359 goto disable_clk;
1360
1361 return 0;
1362
1363disable_clk:
1364 clk_disable_unprepare(sgtl5000->mclk);
940adb28
EN		 1365
1366disable_regs:
1367 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1368 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1369
512fa7c4 1370 return ret;
9b34e6cc
ZZ		 1371}
1372
7a79e94e 1373static int sgtl5000_i2c_remove(struct i2c_client *client)
9b34e6cc 1374{
7c647af4 1375 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc 1376
9e13f345
FE		 1377 snd_soc_unregister_codec(&client->dev);
1378 clk_disable_unprepare(sgtl5000->mclk);
940adb28
EN		 1379 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1380 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1381
9b34e6cc
ZZ		 1382 return 0;
1383}
1384
1385static const struct i2c_device_id sgtl5000_id[] = {
1386 {"sgtl5000", 0},
1387 {},
1388};
1389
1390MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1391
58e49424
SG		 1392static const struct of_device_id sgtl5000_dt_ids[] = {
1393 { .compatible = "fsl,sgtl5000", },
1394 { /* sentinel */ }
1395};
4c54c6de 1396MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1397
9b34e6cc
ZZ		 1398static struct i2c_driver sgtl5000_i2c_driver = {
1399 .driver = {
1400 .name = "sgtl5000",
58e49424 1401 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1402 },
1403 .probe = sgtl5000_i2c_probe,
7a79e94e 1404 .remove = sgtl5000_i2c_remove,
9b34e6cc
ZZ		 1405 .id_table = sgtl5000_id,
1406};
1407
67d45090 1408module_i2c_driver(sgtl5000_i2c_driver);
9b34e6cc
ZZ		 1409
1410MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
f7cb8a4b 1411MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
9b34e6cc 1412MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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