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ASoC: sgtl5000: Fix define for SGTL5000_BIAS_R_MASK
[deliverable/linux.git] / sound / soc / codecs / sgtl5000.c
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9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
19#include <linux/platform_device.h>
20#include <linux/regulator/driver.h>
21#include <linux/regulator/machine.h>
22#include <linux/regulator/consumer.h>
58e49424 23#include <linux/of_device.h>
9b34e6cc
ZZ		 24#include <sound/core.h>
25#include <sound/tlv.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
9b34e6cc
ZZ		 31
32#include "sgtl5000.h"
33
34#define SGTL5000_DAP_REG_OFFSET 0x0100
35#define SGTL5000_MAX_REG_OFFSET 0x013A
36
151798f8
WS		 37/* default value of sgtl5000 registers */
38static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = {
39 [SGTL5000_CHIP_CLK_CTRL] = 0x0008,
40 [SGTL5000_CHIP_I2S_CTRL] = 0x0010,
41 [SGTL5000_CHIP_SSS_CTRL] = 0x0008,
42 [SGTL5000_CHIP_DAC_VOL] = 0x3c3c,
43 [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f,
44 [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818,
45 [SGTL5000_CHIP_ANA_CTRL] = 0x0111,
46 [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404,
47 [SGTL5000_CHIP_ANA_POWER] = 0x7060,
48 [SGTL5000_CHIP_PLL_CTRL] = 0x5000,
49 [SGTL5000_DAP_BASS_ENHANCE] = 0x0040,
50 [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f,
51 [SGTL5000_DAP_SURROUND] = 0x0040,
52 [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f,
53 [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f,
54 [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f,
55 [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f,
56 [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f,
57 [SGTL5000_DAP_MAIN_CHAN] = 0x8000,
58 [SGTL5000_DAP_AVC_CTRL] = 0x0510,
59 [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473,
60 [SGTL5000_DAP_AVC_ATTACK] = 0x0028,
61 [SGTL5000_DAP_AVC_DECAY] = 0x0050,
9b34e6cc
ZZ		 62};
63
64/* regulator supplies for sgtl5000, VDDD is an optional external supply */
65enum sgtl5000_regulator_supplies {
66 VDDA,
67 VDDIO,
68 VDDD,
69 SGTL5000_SUPPLY_NUM
70};
71
72/* vddd is optional supply */
73static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
74 "VDDA",
75 "VDDIO",
76 "VDDD"
77};
78
79#define LDO_CONSUMER_NAME "VDDD_LDO"
80#define LDO_VOLTAGE 1200000
81
82static struct regulator_consumer_supply ldo_consumer[] = {
83 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
84};
85
61a142b7 86static struct regulator_init_data ldo_init_data = {
9b34e6cc
ZZ		 87 .constraints = {
88 .min_uV = 850000,
89 .max_uV = 1600000,
90 .valid_modes_mask = REGULATOR_MODE_NORMAL,
91 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
92 },
93 .num_consumer_supplies = 1,
94 .consumer_supplies = &ldo_consumer[0],
95};
96
97/*
98 * sgtl5000 internal ldo regulator,
99 * enabled when VDDD not provided
100 */
101struct ldo_regulator {
102 struct regulator_desc desc;
103 struct regulator_dev *dev;
104 int voltage;
105 void *codec_data;
106 bool enabled;
107};
108
109/* sgtl5000 private structure in codec */
110struct sgtl5000_priv {
111 int sysclk; /* sysclk rate */
112 int master; /* i2s master or not */
113 int fmt; /* i2s data format */
114 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
115 struct ldo_regulator *ldo;
116};
117
118/*
119 * mic_bias power on/off share the same register bits with
120 * output impedance of mic bias, when power on mic bias, we
121 * need reclaim it to impedance value.
122 * 0x0 = Powered off
123 * 0x1 = 2Kohm
124 * 0x2 = 4Kohm
125 * 0x3 = 8Kohm
126 */
127static int mic_bias_event(struct snd_soc_dapm_widget *w,
128 struct snd_kcontrol *kcontrol, int event)
129{
130 switch (event) {
131 case SND_SOC_DAPM_POST_PMU:
132 /* change mic bias resistor to 4Kohm */
133 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
134 SGTL5000_BIAS_R_4k, SGTL5000_BIAS_R_4k);
135 break;
136
137 case SND_SOC_DAPM_PRE_PMD:
138 /*
139 * SGTL5000_BIAS_R_8k as mask to clean the two bits
140 * of mic bias and output impedance
141 */
142 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
143 SGTL5000_BIAS_R_8k, 0);
144 break;
145 }
146 return 0;
147}
148
149/*
150 * using codec assist to small pop, hp_powerup or lineout_powerup
151 * should stay setting until vag_powerup is fully ramped down,
152 * vag fully ramped down require 400ms.
153 */
154static int small_pop_event(struct snd_soc_dapm_widget *w,
155 struct snd_kcontrol *kcontrol, int event)
156{
157 switch (event) {
158 case SND_SOC_DAPM_PRE_PMU:
159 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
160 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
161 break;
162
163 case SND_SOC_DAPM_PRE_PMD:
164 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
165 SGTL5000_VAG_POWERUP, 0);
166 msleep(400);
167 break;
168 default:
169 break;
170 }
171
172 return 0;
173}
174
175/* input sources for ADC */
176static const char *adc_mux_text[] = {
177 "MIC_IN", "LINE_IN"
178};
179
180static const struct soc_enum adc_enum =
181SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
182
183static const struct snd_kcontrol_new adc_mux =
184SOC_DAPM_ENUM("Capture Mux", adc_enum);
185
186/* input sources for DAC */
187static const char *dac_mux_text[] = {
188 "DAC", "LINE_IN"
189};
190
191static const struct soc_enum dac_enum =
192SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
193
194static const struct snd_kcontrol_new dac_mux =
195SOC_DAPM_ENUM("Headphone Mux", dac_enum);
196
197static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
198 SND_SOC_DAPM_INPUT("LINE_IN"),
199 SND_SOC_DAPM_INPUT("MIC_IN"),
200
201 SND_SOC_DAPM_OUTPUT("HP_OUT"),
202 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
203
204 SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
205 mic_bias_event,
206 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
207
208 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
209 small_pop_event,
210 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
211 SND_SOC_DAPM_PGA_E("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0,
212 small_pop_event,
213 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
214
215 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
216 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
217
218 /* aif for i2s input */
219 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
220 0, SGTL5000_CHIP_DIG_POWER,
221 0, 0),
222
223 /* aif for i2s output */
224 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
225 0, SGTL5000_CHIP_DIG_POWER,
226 1, 0),
227
228 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
229
230 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
231};
232
233/* routes for sgtl5000 */
234static const struct snd_soc_dapm_route audio_map[] = {
235 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
236 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
237
238 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
239 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
240
241 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
242 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
243 {"LO", NULL, "DAC"}, /* dac --> line_out */
244
245 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
246 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
247
248 {"LINE_OUT", NULL, "LO"},
249 {"HP_OUT", NULL, "HP"},
250};
251
252/* custom function to fetch info of PCM playback volume */
253static int dac_info_volsw(struct snd_kcontrol *kcontrol,
254 struct snd_ctl_elem_info *uinfo)
255{
256 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
257 uinfo->count = 2;
258 uinfo->value.integer.min = 0;
259 uinfo->value.integer.max = 0xfc - 0x3c;
260 return 0;
261}
262
263/*
264 * custom function to get of PCM playback volume
265 *
266 * dac volume register
267 * 15-------------8-7--------------0
268 * | R channel vol | L channel vol |
269 * -------------------------------
270 *
271 * PCM volume with 0.5017 dB steps from 0 to -90 dB
272 *
273 * register values map to dB
274 * 0x3B and less = Reserved
275 * 0x3C = 0 dB
276 * 0x3D = -0.5 dB
277 * 0xF0 = -90 dB
278 * 0xFC and greater = Muted
279 *
280 * register value map to userspace value
281 *
282 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
283 * ------------------------------
284 * userspace value 0xc0 0
285 */
286static int dac_get_volsw(struct snd_kcontrol *kcontrol,
287 struct snd_ctl_elem_value *ucontrol)
288{
289 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
290 int reg;
291 int l;
292 int r;
293
294 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
295
296 /* get left channel volume */
297 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
298
299 /* get right channel volume */
300 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
301
302 /* make sure value fall in (0x3c,0xfc) */
303 l = clamp(l, 0x3c, 0xfc);
304 r = clamp(r, 0x3c, 0xfc);
305
306 /* invert it and map to userspace value */
307 l = 0xfc - l;
308 r = 0xfc - r;
309
310 ucontrol->value.integer.value[0] = l;
311 ucontrol->value.integer.value[1] = r;
312
313 return 0;
314}
315
316/*
317 * custom function to put of PCM playback volume
318 *
319 * dac volume register
320 * 15-------------8-7--------------0
321 * | R channel vol | L channel vol |
322 * -------------------------------
323 *
324 * PCM volume with 0.5017 dB steps from 0 to -90 dB
325 *
326 * register values map to dB
327 * 0x3B and less = Reserved
328 * 0x3C = 0 dB
329 * 0x3D = -0.5 dB
330 * 0xF0 = -90 dB
331 * 0xFC and greater = Muted
332 *
333 * userspace value map to register value
334 *
335 * userspace value 0xc0 0
336 * ------------------------------
337 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
338 */
339static int dac_put_volsw(struct snd_kcontrol *kcontrol,
340 struct snd_ctl_elem_value *ucontrol)
341{
342 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
343 int reg;
344 int l;
345 int r;
346
347 l = ucontrol->value.integer.value[0];
348 r = ucontrol->value.integer.value[1];
349
350 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
351 l = clamp(l, 0, 0xfc - 0x3c);
352 r = clamp(r, 0, 0xfc - 0x3c);
353
354 /* invert it, get the value can be set to register */
355 l = 0xfc - l;
356 r = 0xfc - r;
357
358 /* shift to get the register value */
359 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
360 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
361
362 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
363
364 return 0;
365}
366
367static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
368
369/* tlv for mic gain, 0db 20db 30db 40db */
370static const unsigned int mic_gain_tlv[] = {
371 TLV_DB_RANGE_HEAD(4),
372 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
373 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
374};
375
376/* tlv for hp volume, -51.5db to 12.0db, step .5db */
377static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
378
379static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
380 /* SOC_DOUBLE_S8_TLV with invert */
381 {
382 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
383 .name = "PCM Playback Volume",
384 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
385 SNDRV_CTL_ELEM_ACCESS_READWRITE,
386 .info = dac_info_volsw,
387 .get = dac_get_volsw,
388 .put = dac_put_volsw,
389 },
390
391 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
392 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
393 SGTL5000_CHIP_ANA_ADC_CTRL,
394 8, 2, 0, capture_6db_attenuate),
395 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
396
397 SOC_DOUBLE_TLV("Headphone Playback Volume",
398 SGTL5000_CHIP_ANA_HP_CTRL,
399 0, 8,
400 0x7f, 1,
401 headphone_volume),
402 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
403 5, 1, 0),
404
405 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
406 0, 4, 0, mic_gain_tlv),
407};
408
409/* mute the codec used by alsa core */
410static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
411{
412 struct snd_soc_codec *codec = codec_dai->codec;
413 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
414
415 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
416 adcdac_ctrl, mute ? adcdac_ctrl : 0);
417
418 return 0;
419}
420
421/* set codec format */
422static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
423{
424 struct snd_soc_codec *codec = codec_dai->codec;
425 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
426 u16 i2sctl = 0;
427
428 sgtl5000->master = 0;
429 /*
430 * i2s clock and frame master setting.
431 * ONLY support:
432 * - clock and frame slave,
433 * - clock and frame master
434 */
435 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
436 case SND_SOC_DAIFMT_CBS_CFS:
437 break;
438 case SND_SOC_DAIFMT_CBM_CFM:
439 i2sctl |= SGTL5000_I2S_MASTER;
440 sgtl5000->master = 1;
441 break;
442 default:
443 return -EINVAL;
444 }
445
446 /* setting i2s data format */
447 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
448 case SND_SOC_DAIFMT_DSP_A:
449 i2sctl |= SGTL5000_I2S_MODE_PCM;
450 break;
451 case SND_SOC_DAIFMT_DSP_B:
452 i2sctl |= SGTL5000_I2S_MODE_PCM;
453 i2sctl |= SGTL5000_I2S_LRALIGN;
454 break;
455 case SND_SOC_DAIFMT_I2S:
456 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
457 break;
458 case SND_SOC_DAIFMT_RIGHT_J:
459 i2sctl |= SGTL5000_I2S_MODE_RJ;
460 i2sctl |= SGTL5000_I2S_LRPOL;
461 break;
462 case SND_SOC_DAIFMT_LEFT_J:
463 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
464 i2sctl |= SGTL5000_I2S_LRALIGN;
465 break;
466 default:
467 return -EINVAL;
468 }
469
470 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
471
472 /* Clock inversion */
473 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
474 case SND_SOC_DAIFMT_NB_NF:
475 break;
476 case SND_SOC_DAIFMT_IB_NF:
477 i2sctl |= SGTL5000_I2S_SCLK_INV;
478 break;
479 default:
480 return -EINVAL;
481 }
482
483 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
484
485 return 0;
486}
487
488/* set codec sysclk */
489static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
490 int clk_id, unsigned int freq, int dir)
491{
492 struct snd_soc_codec *codec = codec_dai->codec;
493 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
494
495 switch (clk_id) {
496 case SGTL5000_SYSCLK:
497 sgtl5000->sysclk = freq;
498 break;
499 default:
500 return -EINVAL;
501 }
502
503 return 0;
504}
505
506/*
507 * set clock according to i2s frame clock,
508 * sgtl5000 provide 2 clock sources.
509 * 1. sys_mclk. sample freq can only configure to
510 * 1/256, 1/384, 1/512 of sys_mclk.
511 * 2. pll. can derive any audio clocks.
512 *
513 * clock setting rules:
514 * 1. in slave mode, only sys_mclk can use.
515 * 2. as constraint by sys_mclk, sample freq should
516 * set to 32k, 44.1k and above.
517 * 3. using sys_mclk prefer to pll to save power.
518 */
519static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
520{
521 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
522 int clk_ctl = 0;
523 int sys_fs; /* sample freq */
524
525 /*
526 * sample freq should be divided by frame clock,
527 * if frame clock lower than 44.1khz, sample feq should set to
528 * 32khz or 44.1khz.
529 */
530 switch (frame_rate) {
531 case 8000:
532 case 16000:
533 sys_fs = 32000;
534 break;
535 case 11025:
536 case 22050:
537 sys_fs = 44100;
538 break;
539 default:
540 sys_fs = frame_rate;
541 break;
542 }
543
544 /* set divided factor of frame clock */
545 switch (sys_fs / frame_rate) {
546 case 4:
547 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
548 break;
549 case 2:
550 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
551 break;
552 case 1:
553 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
554 break;
555 default:
556 return -EINVAL;
557 }
558
559 /* set the sys_fs according to frame rate */
560 switch (sys_fs) {
561 case 32000:
562 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
563 break;
564 case 44100:
565 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
566 break;
567 case 48000:
568 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
569 break;
570 case 96000:
571 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
572 break;
573 default:
574 dev_err(codec->dev, "frame rate %d not supported\n",
575 frame_rate);
576 return -EINVAL;
577 }
578
579 /*
580 * calculate the divider of mclk/sample_freq,
581 * factor of freq =96k can only be 256, since mclk in range (12m,27m)
582 */
583 switch (sgtl5000->sysclk / sys_fs) {
584 case 256:
585 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
586 SGTL5000_MCLK_FREQ_SHIFT;
587 break;
588 case 384:
589 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
590 SGTL5000_MCLK_FREQ_SHIFT;
591 break;
592 case 512:
593 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
594 SGTL5000_MCLK_FREQ_SHIFT;
595 break;
596 default:
597 /* if mclk not satisify the divider, use pll */
598 if (sgtl5000->master) {
599 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
600 SGTL5000_MCLK_FREQ_SHIFT;
601 } else {
602 dev_err(codec->dev,
603 "PLL not supported in slave mode\n");
604 return -EINVAL;
605 }
606 }
607
608 /* if using pll, please check manual 6.4.2 for detail */
609 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
610 u64 out, t;
611 int div2;
612 int pll_ctl;
613 unsigned int in, int_div, frac_div;
614
615 if (sgtl5000->sysclk > 17000000) {
616 div2 = 1;
617 in = sgtl5000->sysclk / 2;
618 } else {
619 div2 = 0;
620 in = sgtl5000->sysclk;
621 }
622 if (sys_fs == 44100)
623 out = 180633600;
624 else
625 out = 196608000;
626 t = do_div(out, in);
627 int_div = out;
628 t *= 2048;
629 do_div(t, in);
630 frac_div = t;
631 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
632 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
633
634 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
635 if (div2)
636 snd_soc_update_bits(codec,
637 SGTL5000_CHIP_CLK_TOP_CTRL,
638 SGTL5000_INPUT_FREQ_DIV2,
639 SGTL5000_INPUT_FREQ_DIV2);
640 else
641 snd_soc_update_bits(codec,
642 SGTL5000_CHIP_CLK_TOP_CTRL,
643 SGTL5000_INPUT_FREQ_DIV2,
644 0);
645
646 /* power up pll */
647 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
648 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
649 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
650 } else {
651 /* power down pll */
652 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
653 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
654 0);
655 }
656
657 /* if using pll, clk_ctrl must be set after pll power up */
658 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
659
660 return 0;
661}
662
663/*
664 * Set PCM DAI bit size and sample rate.
665 * input: params_rate, params_fmt
666 */
667static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
668 struct snd_pcm_hw_params *params,
669 struct snd_soc_dai *dai)
670{
671 struct snd_soc_pcm_runtime *rtd = substream->private_data;
672 struct snd_soc_codec *codec = rtd->codec;
673 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
674 int channels = params_channels(params);
675 int i2s_ctl = 0;
676 int stereo;
677 int ret;
678
679 /* sysclk should already set */
680 if (!sgtl5000->sysclk) {
681 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
682 return -EFAULT;
683 }
684
685 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
686 stereo = SGTL5000_DAC_STEREO;
687 else
688 stereo = SGTL5000_ADC_STEREO;
689
690 /* set mono to save power */
691 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
692 channels == 1 ? 0 : stereo);
693
694 /* set codec clock base on lrclk */
695 ret = sgtl5000_set_clock(codec, params_rate(params));
696 if (ret)
697 return ret;
698
699 /* set i2s data format */
700 switch (params_format(params)) {
701 case SNDRV_PCM_FORMAT_S16_LE:
702 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
703 return -EINVAL;
704 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
705 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
706 SGTL5000_I2S_SCLKFREQ_SHIFT;
707 break;
708 case SNDRV_PCM_FORMAT_S20_3LE:
709 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
710 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
711 SGTL5000_I2S_SCLKFREQ_SHIFT;
712 break;
713 case SNDRV_PCM_FORMAT_S24_LE:
714 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
715 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
716 SGTL5000_I2S_SCLKFREQ_SHIFT;
717 break;
718 case SNDRV_PCM_FORMAT_S32_LE:
719 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
720 return -EINVAL;
721 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
722 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
723 SGTL5000_I2S_SCLKFREQ_SHIFT;
724 break;
725 default:
726 return -EINVAL;
727 }
728
729 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, i2s_ctl, i2s_ctl);
730
731 return 0;
732}
733
333802e9 734#ifdef CONFIG_REGULATOR
9b34e6cc
ZZ		 735static int ldo_regulator_is_enabled(struct regulator_dev *dev)
736{
737 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
738
739 return ldo->enabled;
740}
741
742static int ldo_regulator_enable(struct regulator_dev *dev)
743{
744 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
745 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
746 int reg;
747
748 if (ldo_regulator_is_enabled(dev))
749 return 0;
750
751 /* set regulator value firstly */
752 reg = (1600 - ldo->voltage / 1000) / 50;
753 reg = clamp(reg, 0x0, 0xf);
754
755 /* amend the voltage value, unit: uV */
756 ldo->voltage = (1600 - reg * 50) * 1000;
757
758 /* set voltage to register */
759 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
760 (0x1 << 4) - 1, reg);
761
762 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
763 SGTL5000_LINEREG_D_POWERUP,
764 SGTL5000_LINEREG_D_POWERUP);
765
766 /* when internal ldo enabled, simple digital power can be disabled */
767 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
768 SGTL5000_LINREG_SIMPLE_POWERUP,
769 0);
770
771 ldo->enabled = 1;
772 return 0;
773}
774
775static int ldo_regulator_disable(struct regulator_dev *dev)
776{
777 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
778 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
779
780 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
781 SGTL5000_LINEREG_D_POWERUP,
782 0);
783
784 /* clear voltage info */
785 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
786 (0x1 << 4) - 1, 0);
787
788 ldo->enabled = 0;
789
790 return 0;
791}
792
793static int ldo_regulator_get_voltage(struct regulator_dev *dev)
794{
795 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
796
797 return ldo->voltage;
798}
799
800static struct regulator_ops ldo_regulator_ops = {
801 .is_enabled = ldo_regulator_is_enabled,
802 .enable = ldo_regulator_enable,
803 .disable = ldo_regulator_disable,
804 .get_voltage = ldo_regulator_get_voltage,
805};
806
807static int ldo_regulator_register(struct snd_soc_codec *codec,
808 struct regulator_init_data *init_data,
809 int voltage)
810{
811 struct ldo_regulator *ldo;
812
813 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
814
815 if (!ldo) {
816 dev_err(codec->dev, "failed to allocate ldo_regulator\n");
817 return -ENOMEM;
818 }
819
820 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
821 if (!ldo->desc.name) {
822 kfree(ldo);
823 dev_err(codec->dev, "failed to allocate decs name memory\n");
824 return -ENOMEM;
825 }
826
827 ldo->desc.type = REGULATOR_VOLTAGE;
828 ldo->desc.owner = THIS_MODULE;
829 ldo->desc.ops = &ldo_regulator_ops;
830 ldo->desc.n_voltages = 1;
831
832 ldo->codec_data = codec;
833 ldo->voltage = voltage;
834
835 ldo->dev = regulator_register(&ldo->desc, codec->dev,
836 init_data, ldo);
837 if (IS_ERR(ldo->dev)) {
62f75aaf
DC		 838 int ret = PTR_ERR(ldo->dev);
839
9b34e6cc
ZZ		 840 dev_err(codec->dev, "failed to register regulator\n");
841 kfree(ldo->desc.name);
842 kfree(ldo);
843
62f75aaf 844 return ret;
9b34e6cc
ZZ		 845 }
846
847 return 0;
848}
849
850static int ldo_regulator_remove(struct snd_soc_codec *codec)
851{
852 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
853 struct ldo_regulator *ldo = sgtl5000->ldo;
854
855 if (!ldo)
856 return 0;
857
858 regulator_unregister(ldo->dev);
859 kfree(ldo->desc.name);
860 kfree(ldo);
861
862 return 0;
863}
333802e9
MB		 864#else
865static int ldo_regulator_register(struct snd_soc_codec *codec,
866 struct regulator_init_data *init_data,
867 int voltage)
868{
09bddc8e 869 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
333802e9
MB		 870 return -EINVAL;
871}
872
873static int ldo_regulator_remove(struct snd_soc_codec *codec)
874{
875 return 0;
876}
877#endif
9b34e6cc
ZZ		 878
879/*
880 * set dac bias
881 * common state changes:
882 * startup:
883 * off --> standby --> prepare --> on
884 * standby --> prepare --> on
885 *
886 * stop:
887 * on --> prepare --> standby
888 */
889static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
890 enum snd_soc_bias_level level)
891{
892 int ret;
893 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
894
895 switch (level) {
896 case SND_SOC_BIAS_ON:
897 case SND_SOC_BIAS_PREPARE:
898 break;
899 case SND_SOC_BIAS_STANDBY:
900 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
901 ret = regulator_bulk_enable(
902 ARRAY_SIZE(sgtl5000->supplies),
903 sgtl5000->supplies);
904 if (ret)
905 return ret;
906 udelay(10);
907 }
908
909 break;
910 case SND_SOC_BIAS_OFF:
911 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
912 sgtl5000->supplies);
913 break;
914 }
915
916 codec->dapm.bias_level = level;
917 return 0;
918}
919
920#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
921 SNDRV_PCM_FMTBIT_S20_3LE |\
922 SNDRV_PCM_FMTBIT_S24_LE |\
923 SNDRV_PCM_FMTBIT_S32_LE)
924
61a142b7 925static struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 926 .hw_params = sgtl5000_pcm_hw_params,
927 .digital_mute = sgtl5000_digital_mute,
928 .set_fmt = sgtl5000_set_dai_fmt,
929 .set_sysclk = sgtl5000_set_dai_sysclk,
930};
931
932static struct snd_soc_dai_driver sgtl5000_dai = {
933 .name = "sgtl5000",
934 .playback = {
935 .stream_name = "Playback",
936 .channels_min = 1,
937 .channels_max = 2,
938 /*
939 * only support 8~48K + 96K,
940 * TODO modify hw_param to support more
941 */
942 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
943 .formats = SGTL5000_FORMATS,
944 },
945 .capture = {
946 .stream_name = "Capture",
947 .channels_min = 1,
948 .channels_max = 2,
949 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
950 .formats = SGTL5000_FORMATS,
951 },
952 .ops = &sgtl5000_ops,
953 .symmetric_rates = 1,
954};
955
956static int sgtl5000_volatile_register(struct snd_soc_codec *codec,
957 unsigned int reg)
958{
959 switch (reg) {
960 case SGTL5000_CHIP_ID:
961 case SGTL5000_CHIP_ADCDAC_CTRL:
962 case SGTL5000_CHIP_ANA_STATUS:
963 return 1;
964 }
965
966 return 0;
967}
968
969#ifdef CONFIG_SUSPEND
970static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state)
971{
972 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
973
974 return 0;
975}
976
977/*
978 * restore all sgtl5000 registers,
979 * since a big hole between dap and regular registers,
980 * we will restore them respectively.
981 */
982static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
983{
984 u16 *cache = codec->reg_cache;
151798f8 985 u16 reg;
9b34e6cc
ZZ		 986
987 /* restore regular registers */
151798f8 988 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
9b34e6cc
ZZ		 989
990 /* this regs depends on the others */
991 if (reg == SGTL5000_CHIP_ANA_POWER ||
992 reg == SGTL5000_CHIP_CLK_CTRL ||
993 reg == SGTL5000_CHIP_LINREG_CTRL ||
994 reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
995 reg == SGTL5000_CHIP_CLK_CTRL)
996 continue;
997
151798f8 998 snd_soc_write(codec, reg, cache[reg]);
9b34e6cc
ZZ		 999 }
1000
1001 /* restore dap registers */
151798f8
WS		 1002 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
1003 snd_soc_write(codec, reg, cache[reg]);
9b34e6cc
ZZ		 1004
1005 /*
1006 * restore power and other regs according
1007 * to set_power() and set_clock()
1008 */
1009 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
151798f8 1010 cache[SGTL5000_CHIP_LINREG_CTRL]);
9b34e6cc
ZZ		 1011
1012 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
151798f8 1013 cache[SGTL5000_CHIP_ANA_POWER]);
9b34e6cc
ZZ		 1014
1015 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
151798f8 1016 cache[SGTL5000_CHIP_CLK_CTRL]);
9b34e6cc
ZZ		 1017
1018 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
151798f8 1019 cache[SGTL5000_CHIP_REF_CTRL]);
9b34e6cc
ZZ		 1020
1021 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
151798f8 1022 cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
9b34e6cc
ZZ		 1023 return 0;
1024}
1025
1026static int sgtl5000_resume(struct snd_soc_codec *codec)
1027{
1028 /* Bring the codec back up to standby to enable regulators */
1029 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1030
1031 /* Restore registers by cached in memory */
1032 sgtl5000_restore_regs(codec);
1033 return 0;
1034}
1035#else
1036#define sgtl5000_suspend NULL
1037#define sgtl5000_resume NULL
1038#endif /* CONFIG_SUSPEND */
1039
1040/*
1041 * sgtl5000 has 3 internal power supplies:
1042 * 1. VAG, normally set to vdda/2
1043 * 2. chargepump, set to different value
1044 * according to voltage of vdda and vddio
1045 * 3. line out VAG, normally set to vddio/2
1046 *
1047 * and should be set according to:
1048 * 1. vddd provided by external or not
1049 * 2. vdda and vddio voltage value. > 3.1v or not
1050 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1051 */
1052static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1053{
1054 int vddd;
1055 int vdda;
1056 int vddio;
1057 u16 ana_pwr;
1058 u16 lreg_ctrl;
1059 int vag;
1060 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1061
1062 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1063 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1064 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1065
1066 vdda = vdda / 1000;
1067 vddio = vddio / 1000;
1068 vddd = vddd / 1000;
1069
1070 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1071 dev_err(codec->dev, "regulator voltage not set correctly\n");
1072
1073 return -EINVAL;
1074 }
1075
1076 /* according to datasheet, maximum voltage of supplies */
1077 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1078 dev_err(codec->dev,
1079 "exceed max voltage vdda %dmv vddio %dma vddd %dma\n",
1080 vdda, vddio, vddd);
1081
1082 return -EINVAL;
1083 }
1084
1085 /* reset value */
1086 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1087 ana_pwr |= SGTL5000_DAC_STEREO |
1088 SGTL5000_ADC_STEREO |
1089 SGTL5000_REFTOP_POWERUP;
1090 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1091
1092 if (vddio < 3100 && vdda < 3100) {
1093 /* enable internal oscillator used for charge pump */
1094 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1095 SGTL5000_INT_OSC_EN,
1096 SGTL5000_INT_OSC_EN);
1097 /* Enable VDDC charge pump */
1098 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1099 } else if (vddio >= 3100 && vdda >= 3100) {
1100 /*
1101 * if vddio and vddd > 3.1v,
1102 * charge pump should be clean before set ana_pwr
1103 */
1104 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1105 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1106
1107 /* VDDC use VDDIO rail */
1108 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1109 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1110 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1111 }
1112
1113 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1114
1115 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1116
1117 /* set voltage to register */
1118 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1119 (0x1 << 4) - 1, 0x8);
1120
1121 /*
1122 * if vddd linear reg has been enabled,
1123 * simple digital supply should be clear to get
1124 * proper VDDD voltage.
1125 */
1126 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1127 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1128 SGTL5000_LINREG_SIMPLE_POWERUP,
1129 0);
1130 else
1131 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1132 SGTL5000_LINREG_SIMPLE_POWERUP |
1133 SGTL5000_STARTUP_POWERUP,
1134 0);
1135
1136 /*
1137 * set ADC/DAC VAG to vdda / 2,
1138 * should stay in range (0.8v, 1.575v)
1139 */
1140 vag = vdda / 2;
1141 if (vag <= SGTL5000_ANA_GND_BASE)
1142 vag = 0;
1143 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1144 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1145 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1146 else
1147 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1148
1149 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1150 vag << SGTL5000_ANA_GND_SHIFT,
1151 vag << SGTL5000_ANA_GND_SHIFT);
1152
1153 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1154 vag = vddio / 2;
1155 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1156 vag = 0;
1157 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1158 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1159 vag = SGTL5000_LINE_OUT_GND_MAX;
1160 else
1161 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1162 SGTL5000_LINE_OUT_GND_STP;
1163
1164 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1165 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1166 SGTL5000_LINE_OUT_CURRENT_360u <<
1167 SGTL5000_LINE_OUT_CURRENT_SHIFT,
1168 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1169 SGTL5000_LINE_OUT_CURRENT_360u <<
1170 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1171
1172 return 0;
1173}
1174
e94a4062
WS		 1175static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1176{
1177 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1178 int ret;
1179
1180 /* set internal ldo to 1.2v */
1181 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1182 if (ret) {
1183 dev_err(codec->dev,
1184 "Failed to register vddd internal supplies: %d\n", ret);
1185 return ret;
1186 }
1187
1188 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1189
1190 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1191 sgtl5000->supplies);
1192
1193 if (ret) {
1194 ldo_regulator_remove(codec);
1195 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1196 return ret;
1197 }
1198
1199 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1200 return 0;
1201}
1202
9b34e6cc
ZZ		 1203static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1204{
1205 u16 reg;
1206 int ret;
1207 int rev;
1208 int i;
1209 int external_vddd = 0;
1210 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1211
1212 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1213 sgtl5000->supplies[i].supply = supply_names[i];
1214
1215 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1216 sgtl5000->supplies);
1217 if (!ret)
1218 external_vddd = 1;
1219 else {
e94a4062
WS		 1220 ret = sgtl5000_replace_vddd_with_ldo(codec);
1221 if (ret)
9b34e6cc 1222 return ret;
9b34e6cc
ZZ		 1223 }
1224
1225 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1226 sgtl5000->supplies);
1227 if (ret)
1228 goto err_regulator_free;
1229
1230 /* wait for all power rails bring up */
1231 udelay(10);
1232
1233 /* read chip information */
1234 reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
1235 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1236 SGTL5000_PARTID_PART_ID) {
1237 dev_err(codec->dev,
1238 "Device with ID register %x is not a sgtl5000\n", reg);
1239 ret = -ENODEV;
1240 goto err_regulator_disable;
1241 }
1242
1243 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1244 dev_info(codec->dev, "sgtl5000 revision %d\n", rev);
1245
1246 /*
1247 * workaround for revision 0x11 and later,
1248 * roll back to use internal LDO
1249 */
1250 if (external_vddd && rev >= 0x11) {
9b34e6cc
ZZ		 1251 /* disable all regulator first */
1252 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1253 sgtl5000->supplies);
1254 /* free VDDD regulator */
1255 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1256 sgtl5000->supplies);
1257
e94a4062 1258 ret = sgtl5000_replace_vddd_with_ldo(codec);
9b34e6cc
ZZ		 1259 if (ret)
1260 return ret;
1261
9b34e6cc
ZZ		 1262 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1263 sgtl5000->supplies);
1264 if (ret)
1265 goto err_regulator_free;
1266
1267 /* wait for all power rails bring up */
1268 udelay(10);
1269 }
1270
1271 return 0;
1272
1273err_regulator_disable:
1274 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1275 sgtl5000->supplies);
1276err_regulator_free:
1277 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1278 sgtl5000->supplies);
1279 if (external_vddd)
1280 ldo_regulator_remove(codec);
1281 return ret;
1282
1283}
1284
1285static int sgtl5000_probe(struct snd_soc_codec *codec)
1286{
1287 int ret;
1288 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1289
1290 /* setup i2c data ops */
1291 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
1292 if (ret < 0) {
1293 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1294 return ret;
1295 }
1296
1297 ret = sgtl5000_enable_regulators(codec);
1298 if (ret)
1299 return ret;
1300
1301 /* power up sgtl5000 */
1302 ret = sgtl5000_set_power_regs(codec);
1303 if (ret)
1304 goto err;
1305
1306 /* enable small pop, introduce 400ms delay in turning off */
1307 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1308 SGTL5000_SMALL_POP,
1309 SGTL5000_SMALL_POP);
1310
1311 /* disable short cut detector */
1312 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1313
1314 /*
1315 * set i2s as default input of sound switch
1316 * TODO: add sound switch to control and dapm widge.
1317 */
1318 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1319 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1320 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1321 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1322
1323 /* enable dac volume ramp by default */
1324 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1325 SGTL5000_DAC_VOL_RAMP_EN |
1326 SGTL5000_DAC_MUTE_RIGHT |
1327 SGTL5000_DAC_MUTE_LEFT);
1328
1329 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1330
1331 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1332 SGTL5000_HP_ZCD_EN |
1333 SGTL5000_ADC_ZCD_EN);
1334
1335 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0);
1336
1337 /*
1338 * disable DAP
1339 * TODO:
1340 * Enable DAP in kcontrol and dapm.
1341 */
1342 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1343
1344 /* leading to standby state */
1345 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1346 if (ret)
1347 goto err;
1348
1349 snd_soc_add_controls(codec, sgtl5000_snd_controls,
1350 ARRAY_SIZE(sgtl5000_snd_controls));
1351
1352 snd_soc_dapm_new_controls(&codec->dapm, sgtl5000_dapm_widgets,
1353 ARRAY_SIZE(sgtl5000_dapm_widgets));
1354
1355 snd_soc_dapm_add_routes(&codec->dapm, audio_map,
1356 ARRAY_SIZE(audio_map));
1357
1358 snd_soc_dapm_new_widgets(&codec->dapm);
1359
1360 return 0;
1361
1362err:
1363 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1364 sgtl5000->supplies);
1365 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1366 sgtl5000->supplies);
1367 ldo_regulator_remove(codec);
1368
1369 return ret;
1370}
1371
1372static int sgtl5000_remove(struct snd_soc_codec *codec)
1373{
1374 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1375
1376 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1377
1378 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1379 sgtl5000->supplies);
1380 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1381 sgtl5000->supplies);
1382 ldo_regulator_remove(codec);
1383
1384 return 0;
1385}
1386
61a142b7 1387static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1388 .probe = sgtl5000_probe,
1389 .remove = sgtl5000_remove,
1390 .suspend = sgtl5000_suspend,
1391 .resume = sgtl5000_resume,
1392 .set_bias_level = sgtl5000_set_bias_level,
1393 .reg_cache_size = ARRAY_SIZE(sgtl5000_regs),
1394 .reg_word_size = sizeof(u16),
1395 .reg_cache_step = 2,
1396 .reg_cache_default = sgtl5000_regs,
1397 .volatile_register = sgtl5000_volatile_register,
1398};
1399
1400static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
1401 const struct i2c_device_id *id)
1402{
1403 struct sgtl5000_priv *sgtl5000;
1404 int ret;
1405
1406 sgtl5000 = kzalloc(sizeof(struct sgtl5000_priv), GFP_KERNEL);
1407 if (!sgtl5000)
1408 return -ENOMEM;
1409
9b34e6cc
ZZ		 1410 i2c_set_clientdata(client, sgtl5000);
1411
1412 ret = snd_soc_register_codec(&client->dev,
1413 &sgtl5000_driver, &sgtl5000_dai, 1);
1414 if (ret) {
1415 dev_err(&client->dev, "Failed to register codec: %d\n", ret);
1416 kfree(sgtl5000);
1417 return ret;
1418 }
1419
1420 return 0;
1421}
1422
1423static __devexit int sgtl5000_i2c_remove(struct i2c_client *client)
1424{
1425 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1426
1427 snd_soc_unregister_codec(&client->dev);
1428
1429 kfree(sgtl5000);
1430 return 0;
1431}
1432
1433static const struct i2c_device_id sgtl5000_id[] = {
1434 {"sgtl5000", 0},
1435 {},
1436};
1437
1438MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1439
58e49424
SG		 1440static const struct of_device_id sgtl5000_dt_ids[] = {
1441 { .compatible = "fsl,sgtl5000", },
1442 { /* sentinel */ }
1443};
4c54c6de 1444MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1445
9b34e6cc
ZZ		 1446static struct i2c_driver sgtl5000_i2c_driver = {
1447 .driver = {
1448 .name = "sgtl5000",
1449 .owner = THIS_MODULE,
58e49424 1450 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1451 },
1452 .probe = sgtl5000_i2c_probe,
1453 .remove = __devexit_p(sgtl5000_i2c_remove),
1454 .id_table = sgtl5000_id,
1455};
1456
1457static int __init sgtl5000_modinit(void)
1458{
1459 return i2c_add_driver(&sgtl5000_i2c_driver);
1460}
1461module_init(sgtl5000_modinit);
1462
1463static void __exit sgtl5000_exit(void)
1464{
1465 i2c_del_driver(&sgtl5000_i2c_driver);
1466}
1467module_exit(sgtl5000_exit);
1468
1469MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1470MODULE_AUTHOR("Zeng Zhaoming <zhaoming.zeng@freescale.com>");
1471MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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