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9b34e6cc ZZ |
1 | /* |
2 | * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/clk.h> | |
e5d80e82 | 19 | #include <linux/regmap.h> |
9b34e6cc ZZ |
20 | #include <linux/regulator/driver.h> |
21 | #include <linux/regulator/machine.h> | |
22 | #include <linux/regulator/consumer.h> | |
58e49424 | 23 | #include <linux/of_device.h> |
9b34e6cc ZZ |
24 | #include <sound/core.h> |
25 | #include <sound/tlv.h> | |
26 | #include <sound/pcm.h> | |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/soc.h> | |
29 | #include <sound/soc-dapm.h> | |
30 | #include <sound/initval.h> | |
9b34e6cc ZZ |
31 | |
32 | #include "sgtl5000.h" | |
33 | ||
34 | #define SGTL5000_DAP_REG_OFFSET 0x0100 | |
35 | #define SGTL5000_MAX_REG_OFFSET 0x013A | |
36 | ||
151798f8 | 37 | /* default value of sgtl5000 registers */ |
e5d80e82 FE |
38 | static const struct reg_default sgtl5000_reg_defaults[] = { |
39 | { SGTL5000_CHIP_CLK_CTRL, 0x0008 }, | |
40 | { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, | |
016fcab8 | 41 | { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, |
e5d80e82 FE |
42 | { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, |
43 | { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, | |
44 | { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, | |
45 | { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, | |
46 | { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, | |
47 | { SGTL5000_CHIP_ANA_POWER, 0x7060 }, | |
48 | { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, | |
49 | { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, | |
50 | { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, | |
51 | { SGTL5000_DAP_SURROUND, 0x0040 }, | |
52 | { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, | |
53 | { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, | |
54 | { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, | |
55 | { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, | |
56 | { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, | |
57 | { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, | |
58 | { SGTL5000_DAP_AVC_CTRL, 0x0510 }, | |
59 | { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, | |
60 | { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, | |
61 | { SGTL5000_DAP_AVC_DECAY, 0x0050 }, | |
9b34e6cc ZZ |
62 | }; |
63 | ||
64 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ | |
65 | enum sgtl5000_regulator_supplies { | |
66 | VDDA, | |
67 | VDDIO, | |
68 | VDDD, | |
69 | SGTL5000_SUPPLY_NUM | |
70 | }; | |
71 | ||
72 | /* vddd is optional supply */ | |
73 | static const char *supply_names[SGTL5000_SUPPLY_NUM] = { | |
74 | "VDDA", | |
75 | "VDDIO", | |
76 | "VDDD" | |
77 | }; | |
78 | ||
79 | #define LDO_CONSUMER_NAME "VDDD_LDO" | |
80 | #define LDO_VOLTAGE 1200000 | |
81 | ||
82 | static struct regulator_consumer_supply ldo_consumer[] = { | |
83 | REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), | |
84 | }; | |
85 | ||
61a142b7 | 86 | static struct regulator_init_data ldo_init_data = { |
9b34e6cc | 87 | .constraints = { |
cd041f64 FE |
88 | .min_uV = 1200000, |
89 | .max_uV = 1200000, | |
9b34e6cc ZZ |
90 | .valid_modes_mask = REGULATOR_MODE_NORMAL, |
91 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
92 | }, | |
93 | .num_consumer_supplies = 1, | |
94 | .consumer_supplies = &ldo_consumer[0], | |
95 | }; | |
96 | ||
97 | /* | |
98 | * sgtl5000 internal ldo regulator, | |
99 | * enabled when VDDD not provided | |
100 | */ | |
101 | struct ldo_regulator { | |
102 | struct regulator_desc desc; | |
103 | struct regulator_dev *dev; | |
104 | int voltage; | |
105 | void *codec_data; | |
106 | bool enabled; | |
107 | }; | |
108 | ||
109 | /* sgtl5000 private structure in codec */ | |
110 | struct sgtl5000_priv { | |
111 | int sysclk; /* sysclk rate */ | |
112 | int master; /* i2s master or not */ | |
113 | int fmt; /* i2s data format */ | |
114 | struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; | |
115 | struct ldo_regulator *ldo; | |
e5d80e82 | 116 | struct regmap *regmap; |
9e13f345 | 117 | struct clk *mclk; |
252e91ff | 118 | int revision; |
9b34e6cc ZZ |
119 | }; |
120 | ||
121 | /* | |
122 | * mic_bias power on/off share the same register bits with | |
123 | * output impedance of mic bias, when power on mic bias, we | |
124 | * need reclaim it to impedance value. | |
125 | * 0x0 = Powered off | |
126 | * 0x1 = 2Kohm | |
127 | * 0x2 = 4Kohm | |
128 | * 0x3 = 8Kohm | |
129 | */ | |
130 | static int mic_bias_event(struct snd_soc_dapm_widget *w, | |
131 | struct snd_kcontrol *kcontrol, int event) | |
132 | { | |
133 | switch (event) { | |
134 | case SND_SOC_DAPM_POST_PMU: | |
135 | /* change mic bias resistor to 4Kohm */ | |
136 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, | |
dc56c5a8 AL |
137 | SGTL5000_BIAS_R_MASK, |
138 | SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT); | |
9b34e6cc ZZ |
139 | break; |
140 | ||
141 | case SND_SOC_DAPM_PRE_PMD: | |
9b34e6cc | 142 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, |
dc56c5a8 | 143 | SGTL5000_BIAS_R_MASK, 0); |
9b34e6cc ZZ |
144 | break; |
145 | } | |
146 | return 0; | |
147 | } | |
148 | ||
149 | /* | |
f0cdcf3a ZZ |
150 | * As manual described, ADC/DAC only works when VAG powerup, |
151 | * So enabled VAG before ADC/DAC up. | |
152 | * In power down case, we need wait 400ms when vag fully ramped down. | |
9b34e6cc | 153 | */ |
f0cdcf3a | 154 | static int power_vag_event(struct snd_soc_dapm_widget *w, |
9b34e6cc ZZ |
155 | struct snd_kcontrol *kcontrol, int event) |
156 | { | |
f091f3f0 LW |
157 | const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; |
158 | ||
9b34e6cc | 159 | switch (event) { |
dd4d2d6d | 160 | case SND_SOC_DAPM_POST_PMU: |
9b34e6cc ZZ |
161 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, |
162 | SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); | |
163 | break; | |
164 | ||
dd4d2d6d | 165 | case SND_SOC_DAPM_PRE_PMD: |
f091f3f0 LW |
166 | /* |
167 | * Don't clear VAG_POWERUP, when both DAC and ADC are | |
168 | * operational to prevent inadvertently starving the | |
169 | * other one of them. | |
170 | */ | |
171 | if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) & | |
172 | mask) != mask) { | |
173 | snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, | |
174 | SGTL5000_VAG_POWERUP, 0); | |
175 | msleep(400); | |
176 | } | |
9b34e6cc ZZ |
177 | break; |
178 | default: | |
179 | break; | |
180 | } | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | /* input sources for ADC */ | |
186 | static const char *adc_mux_text[] = { | |
187 | "MIC_IN", "LINE_IN" | |
188 | }; | |
189 | ||
c8ed6504 TI |
190 | static SOC_ENUM_SINGLE_DECL(adc_enum, |
191 | SGTL5000_CHIP_ANA_CTRL, 2, | |
192 | adc_mux_text); | |
9b34e6cc ZZ |
193 | |
194 | static const struct snd_kcontrol_new adc_mux = | |
195 | SOC_DAPM_ENUM("Capture Mux", adc_enum); | |
196 | ||
197 | /* input sources for DAC */ | |
198 | static const char *dac_mux_text[] = { | |
199 | "DAC", "LINE_IN" | |
200 | }; | |
201 | ||
c8ed6504 TI |
202 | static SOC_ENUM_SINGLE_DECL(dac_enum, |
203 | SGTL5000_CHIP_ANA_CTRL, 6, | |
204 | dac_mux_text); | |
9b34e6cc ZZ |
205 | |
206 | static const struct snd_kcontrol_new dac_mux = | |
207 | SOC_DAPM_ENUM("Headphone Mux", dac_enum); | |
208 | ||
209 | static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { | |
210 | SND_SOC_DAPM_INPUT("LINE_IN"), | |
211 | SND_SOC_DAPM_INPUT("MIC_IN"), | |
212 | ||
213 | SND_SOC_DAPM_OUTPUT("HP_OUT"), | |
214 | SND_SOC_DAPM_OUTPUT("LINE_OUT"), | |
215 | ||
8fc8ec92 MB |
216 | SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, |
217 | mic_bias_event, | |
218 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
9b34e6cc | 219 | |
f0cdcf3a ZZ |
220 | SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), |
221 | SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), | |
9b34e6cc ZZ |
222 | |
223 | SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), | |
224 | SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), | |
225 | ||
226 | /* aif for i2s input */ | |
227 | SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", | |
228 | 0, SGTL5000_CHIP_DIG_POWER, | |
229 | 0, 0), | |
230 | ||
231 | /* aif for i2s output */ | |
232 | SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", | |
233 | 0, SGTL5000_CHIP_DIG_POWER, | |
234 | 1, 0), | |
235 | ||
f0cdcf3a | 236 | SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), |
9b34e6cc | 237 | SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), |
dd4d2d6d MV |
238 | |
239 | SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), | |
240 | SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), | |
9b34e6cc ZZ |
241 | }; |
242 | ||
243 | /* routes for sgtl5000 */ | |
89989637 | 244 | static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { |
9b34e6cc ZZ |
245 | {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ |
246 | {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ | |
247 | ||
248 | {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ | |
249 | {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ | |
250 | ||
251 | {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ | |
252 | {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ | |
253 | {"LO", NULL, "DAC"}, /* dac --> line_out */ | |
254 | ||
255 | {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ | |
256 | {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ | |
257 | ||
258 | {"LINE_OUT", NULL, "LO"}, | |
259 | {"HP_OUT", NULL, "HP"}, | |
260 | }; | |
261 | ||
262 | /* custom function to fetch info of PCM playback volume */ | |
263 | static int dac_info_volsw(struct snd_kcontrol *kcontrol, | |
264 | struct snd_ctl_elem_info *uinfo) | |
265 | { | |
266 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
267 | uinfo->count = 2; | |
268 | uinfo->value.integer.min = 0; | |
269 | uinfo->value.integer.max = 0xfc - 0x3c; | |
270 | return 0; | |
271 | } | |
272 | ||
273 | /* | |
274 | * custom function to get of PCM playback volume | |
275 | * | |
276 | * dac volume register | |
277 | * 15-------------8-7--------------0 | |
278 | * | R channel vol | L channel vol | | |
279 | * ------------------------------- | |
280 | * | |
281 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
282 | * | |
283 | * register values map to dB | |
284 | * 0x3B and less = Reserved | |
285 | * 0x3C = 0 dB | |
286 | * 0x3D = -0.5 dB | |
287 | * 0xF0 = -90 dB | |
288 | * 0xFC and greater = Muted | |
289 | * | |
290 | * register value map to userspace value | |
291 | * | |
292 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
293 | * ------------------------------ | |
294 | * userspace value 0xc0 0 | |
295 | */ | |
296 | static int dac_get_volsw(struct snd_kcontrol *kcontrol, | |
297 | struct snd_ctl_elem_value *ucontrol) | |
298 | { | |
299 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
300 | int reg; | |
301 | int l; | |
302 | int r; | |
303 | ||
304 | reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); | |
305 | ||
306 | /* get left channel volume */ | |
307 | l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; | |
308 | ||
309 | /* get right channel volume */ | |
310 | r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
311 | ||
312 | /* make sure value fall in (0x3c,0xfc) */ | |
313 | l = clamp(l, 0x3c, 0xfc); | |
314 | r = clamp(r, 0x3c, 0xfc); | |
315 | ||
316 | /* invert it and map to userspace value */ | |
317 | l = 0xfc - l; | |
318 | r = 0xfc - r; | |
319 | ||
320 | ucontrol->value.integer.value[0] = l; | |
321 | ucontrol->value.integer.value[1] = r; | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | /* | |
327 | * custom function to put of PCM playback volume | |
328 | * | |
329 | * dac volume register | |
330 | * 15-------------8-7--------------0 | |
331 | * | R channel vol | L channel vol | | |
332 | * ------------------------------- | |
333 | * | |
334 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
335 | * | |
336 | * register values map to dB | |
337 | * 0x3B and less = Reserved | |
338 | * 0x3C = 0 dB | |
339 | * 0x3D = -0.5 dB | |
340 | * 0xF0 = -90 dB | |
341 | * 0xFC and greater = Muted | |
342 | * | |
343 | * userspace value map to register value | |
344 | * | |
345 | * userspace value 0xc0 0 | |
346 | * ------------------------------ | |
347 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
348 | */ | |
349 | static int dac_put_volsw(struct snd_kcontrol *kcontrol, | |
350 | struct snd_ctl_elem_value *ucontrol) | |
351 | { | |
352 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
353 | int reg; | |
354 | int l; | |
355 | int r; | |
356 | ||
357 | l = ucontrol->value.integer.value[0]; | |
358 | r = ucontrol->value.integer.value[1]; | |
359 | ||
360 | /* make sure userspace volume fall in (0, 0xfc-0x3c) */ | |
361 | l = clamp(l, 0, 0xfc - 0x3c); | |
362 | r = clamp(r, 0, 0xfc - 0x3c); | |
363 | ||
364 | /* invert it, get the value can be set to register */ | |
365 | l = 0xfc - l; | |
366 | r = 0xfc - r; | |
367 | ||
368 | /* shift to get the register value */ | |
369 | reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | | |
370 | r << SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
371 | ||
372 | snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); | |
378 | ||
379 | /* tlv for mic gain, 0db 20db 30db 40db */ | |
380 | static const unsigned int mic_gain_tlv[] = { | |
740fb9d5 | 381 | TLV_DB_RANGE_HEAD(2), |
9b34e6cc ZZ |
382 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
383 | 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), | |
384 | }; | |
385 | ||
386 | /* tlv for hp volume, -51.5db to 12.0db, step .5db */ | |
387 | static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); | |
388 | ||
389 | static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { | |
390 | /* SOC_DOUBLE_S8_TLV with invert */ | |
391 | { | |
392 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
393 | .name = "PCM Playback Volume", | |
394 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | | |
395 | SNDRV_CTL_ELEM_ACCESS_READWRITE, | |
396 | .info = dac_info_volsw, | |
397 | .get = dac_get_volsw, | |
398 | .put = dac_put_volsw, | |
399 | }, | |
400 | ||
401 | SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), | |
402 | SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", | |
403 | SGTL5000_CHIP_ANA_ADC_CTRL, | |
65f2b226 | 404 | 8, 1, 0, capture_6db_attenuate), |
9b34e6cc ZZ |
405 | SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), |
406 | ||
407 | SOC_DOUBLE_TLV("Headphone Playback Volume", | |
408 | SGTL5000_CHIP_ANA_HP_CTRL, | |
409 | 0, 8, | |
410 | 0x7f, 1, | |
411 | headphone_volume), | |
412 | SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, | |
413 | 5, 1, 0), | |
414 | ||
415 | SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, | |
b50684da | 416 | 0, 3, 0, mic_gain_tlv), |
9b34e6cc ZZ |
417 | }; |
418 | ||
419 | /* mute the codec used by alsa core */ | |
420 | static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
421 | { | |
422 | struct snd_soc_codec *codec = codec_dai->codec; | |
423 | u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; | |
424 | ||
425 | snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, | |
426 | adcdac_ctrl, mute ? adcdac_ctrl : 0); | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431 | /* set codec format */ | |
432 | static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
433 | { | |
434 | struct snd_soc_codec *codec = codec_dai->codec; | |
435 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
436 | u16 i2sctl = 0; | |
437 | ||
438 | sgtl5000->master = 0; | |
439 | /* | |
440 | * i2s clock and frame master setting. | |
441 | * ONLY support: | |
442 | * - clock and frame slave, | |
443 | * - clock and frame master | |
444 | */ | |
445 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
446 | case SND_SOC_DAIFMT_CBS_CFS: | |
447 | break; | |
448 | case SND_SOC_DAIFMT_CBM_CFM: | |
449 | i2sctl |= SGTL5000_I2S_MASTER; | |
450 | sgtl5000->master = 1; | |
451 | break; | |
452 | default: | |
453 | return -EINVAL; | |
454 | } | |
455 | ||
456 | /* setting i2s data format */ | |
457 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
458 | case SND_SOC_DAIFMT_DSP_A: | |
459 | i2sctl |= SGTL5000_I2S_MODE_PCM; | |
460 | break; | |
461 | case SND_SOC_DAIFMT_DSP_B: | |
462 | i2sctl |= SGTL5000_I2S_MODE_PCM; | |
463 | i2sctl |= SGTL5000_I2S_LRALIGN; | |
464 | break; | |
465 | case SND_SOC_DAIFMT_I2S: | |
466 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; | |
467 | break; | |
468 | case SND_SOC_DAIFMT_RIGHT_J: | |
469 | i2sctl |= SGTL5000_I2S_MODE_RJ; | |
470 | i2sctl |= SGTL5000_I2S_LRPOL; | |
471 | break; | |
472 | case SND_SOC_DAIFMT_LEFT_J: | |
473 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; | |
474 | i2sctl |= SGTL5000_I2S_LRALIGN; | |
475 | break; | |
476 | default: | |
477 | return -EINVAL; | |
478 | } | |
479 | ||
480 | sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
481 | ||
482 | /* Clock inversion */ | |
483 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
484 | case SND_SOC_DAIFMT_NB_NF: | |
485 | break; | |
486 | case SND_SOC_DAIFMT_IB_NF: | |
487 | i2sctl |= SGTL5000_I2S_SCLK_INV; | |
488 | break; | |
489 | default: | |
490 | return -EINVAL; | |
491 | } | |
492 | ||
493 | snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
498 | /* set codec sysclk */ | |
499 | static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
500 | int clk_id, unsigned int freq, int dir) | |
501 | { | |
502 | struct snd_soc_codec *codec = codec_dai->codec; | |
503 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
504 | ||
505 | switch (clk_id) { | |
506 | case SGTL5000_SYSCLK: | |
507 | sgtl5000->sysclk = freq; | |
508 | break; | |
509 | default: | |
510 | return -EINVAL; | |
511 | } | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
516 | /* | |
517 | * set clock according to i2s frame clock, | |
518 | * sgtl5000 provide 2 clock sources. | |
519 | * 1. sys_mclk. sample freq can only configure to | |
520 | * 1/256, 1/384, 1/512 of sys_mclk. | |
521 | * 2. pll. can derive any audio clocks. | |
522 | * | |
523 | * clock setting rules: | |
524 | * 1. in slave mode, only sys_mclk can use. | |
525 | * 2. as constraint by sys_mclk, sample freq should | |
526 | * set to 32k, 44.1k and above. | |
527 | * 3. using sys_mclk prefer to pll to save power. | |
528 | */ | |
529 | static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) | |
530 | { | |
531 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
532 | int clk_ctl = 0; | |
533 | int sys_fs; /* sample freq */ | |
534 | ||
535 | /* | |
536 | * sample freq should be divided by frame clock, | |
537 | * if frame clock lower than 44.1khz, sample feq should set to | |
538 | * 32khz or 44.1khz. | |
539 | */ | |
540 | switch (frame_rate) { | |
541 | case 8000: | |
542 | case 16000: | |
543 | sys_fs = 32000; | |
544 | break; | |
545 | case 11025: | |
546 | case 22050: | |
547 | sys_fs = 44100; | |
548 | break; | |
549 | default: | |
550 | sys_fs = frame_rate; | |
551 | break; | |
552 | } | |
553 | ||
554 | /* set divided factor of frame clock */ | |
555 | switch (sys_fs / frame_rate) { | |
556 | case 4: | |
557 | clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; | |
558 | break; | |
559 | case 2: | |
560 | clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; | |
561 | break; | |
562 | case 1: | |
563 | clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; | |
564 | break; | |
565 | default: | |
566 | return -EINVAL; | |
567 | } | |
568 | ||
569 | /* set the sys_fs according to frame rate */ | |
570 | switch (sys_fs) { | |
571 | case 32000: | |
572 | clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; | |
573 | break; | |
574 | case 44100: | |
575 | clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; | |
576 | break; | |
577 | case 48000: | |
578 | clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; | |
579 | break; | |
580 | case 96000: | |
581 | clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; | |
582 | break; | |
583 | default: | |
584 | dev_err(codec->dev, "frame rate %d not supported\n", | |
585 | frame_rate); | |
586 | return -EINVAL; | |
587 | } | |
588 | ||
589 | /* | |
590 | * calculate the divider of mclk/sample_freq, | |
591 | * factor of freq =96k can only be 256, since mclk in range (12m,27m) | |
592 | */ | |
593 | switch (sgtl5000->sysclk / sys_fs) { | |
594 | case 256: | |
595 | clk_ctl |= SGTL5000_MCLK_FREQ_256FS << | |
596 | SGTL5000_MCLK_FREQ_SHIFT; | |
597 | break; | |
598 | case 384: | |
599 | clk_ctl |= SGTL5000_MCLK_FREQ_384FS << | |
600 | SGTL5000_MCLK_FREQ_SHIFT; | |
601 | break; | |
602 | case 512: | |
603 | clk_ctl |= SGTL5000_MCLK_FREQ_512FS << | |
604 | SGTL5000_MCLK_FREQ_SHIFT; | |
605 | break; | |
606 | default: | |
607 | /* if mclk not satisify the divider, use pll */ | |
608 | if (sgtl5000->master) { | |
609 | clk_ctl |= SGTL5000_MCLK_FREQ_PLL << | |
610 | SGTL5000_MCLK_FREQ_SHIFT; | |
611 | } else { | |
612 | dev_err(codec->dev, | |
613 | "PLL not supported in slave mode\n"); | |
614 | return -EINVAL; | |
615 | } | |
616 | } | |
617 | ||
618 | /* if using pll, please check manual 6.4.2 for detail */ | |
619 | if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { | |
620 | u64 out, t; | |
621 | int div2; | |
622 | int pll_ctl; | |
623 | unsigned int in, int_div, frac_div; | |
624 | ||
625 | if (sgtl5000->sysclk > 17000000) { | |
626 | div2 = 1; | |
627 | in = sgtl5000->sysclk / 2; | |
628 | } else { | |
629 | div2 = 0; | |
630 | in = sgtl5000->sysclk; | |
631 | } | |
632 | if (sys_fs == 44100) | |
633 | out = 180633600; | |
634 | else | |
635 | out = 196608000; | |
636 | t = do_div(out, in); | |
637 | int_div = out; | |
638 | t *= 2048; | |
639 | do_div(t, in); | |
640 | frac_div = t; | |
641 | pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | | |
642 | frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; | |
643 | ||
644 | snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); | |
645 | if (div2) | |
646 | snd_soc_update_bits(codec, | |
647 | SGTL5000_CHIP_CLK_TOP_CTRL, | |
648 | SGTL5000_INPUT_FREQ_DIV2, | |
649 | SGTL5000_INPUT_FREQ_DIV2); | |
650 | else | |
651 | snd_soc_update_bits(codec, | |
652 | SGTL5000_CHIP_CLK_TOP_CTRL, | |
653 | SGTL5000_INPUT_FREQ_DIV2, | |
654 | 0); | |
655 | ||
656 | /* power up pll */ | |
657 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
658 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, | |
659 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); | |
e06e4c2d OS |
660 | |
661 | /* if using pll, clk_ctrl must be set after pll power up */ | |
662 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); | |
9b34e6cc | 663 | } else { |
e06e4c2d OS |
664 | /* otherwise, clk_ctrl must be set before pll power down */ |
665 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); | |
666 | ||
9b34e6cc ZZ |
667 | /* power down pll */ |
668 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
669 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, | |
670 | 0); | |
671 | } | |
672 | ||
9b34e6cc ZZ |
673 | return 0; |
674 | } | |
675 | ||
676 | /* | |
677 | * Set PCM DAI bit size and sample rate. | |
678 | * input: params_rate, params_fmt | |
679 | */ | |
680 | static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, | |
681 | struct snd_pcm_hw_params *params, | |
682 | struct snd_soc_dai *dai) | |
683 | { | |
e6968a17 | 684 | struct snd_soc_codec *codec = dai->codec; |
9b34e6cc ZZ |
685 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); |
686 | int channels = params_channels(params); | |
687 | int i2s_ctl = 0; | |
688 | int stereo; | |
689 | int ret; | |
690 | ||
691 | /* sysclk should already set */ | |
692 | if (!sgtl5000->sysclk) { | |
693 | dev_err(codec->dev, "%s: set sysclk first!\n", __func__); | |
694 | return -EFAULT; | |
695 | } | |
696 | ||
697 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
698 | stereo = SGTL5000_DAC_STEREO; | |
699 | else | |
700 | stereo = SGTL5000_ADC_STEREO; | |
701 | ||
702 | /* set mono to save power */ | |
703 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, | |
704 | channels == 1 ? 0 : stereo); | |
705 | ||
706 | /* set codec clock base on lrclk */ | |
707 | ret = sgtl5000_set_clock(codec, params_rate(params)); | |
708 | if (ret) | |
709 | return ret; | |
710 | ||
711 | /* set i2s data format */ | |
712 | switch (params_format(params)) { | |
713 | case SNDRV_PCM_FORMAT_S16_LE: | |
714 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) | |
715 | return -EINVAL; | |
716 | i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; | |
717 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << | |
718 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
719 | break; | |
720 | case SNDRV_PCM_FORMAT_S20_3LE: | |
721 | i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; | |
722 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
723 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
724 | break; | |
725 | case SNDRV_PCM_FORMAT_S24_LE: | |
726 | i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; | |
727 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
728 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
729 | break; | |
730 | case SNDRV_PCM_FORMAT_S32_LE: | |
731 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) | |
732 | return -EINVAL; | |
733 | i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; | |
734 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
735 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
736 | break; | |
737 | default: | |
738 | return -EINVAL; | |
739 | } | |
740 | ||
33cb92cf AL |
741 | snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, |
742 | SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, | |
743 | i2s_ctl); | |
9b34e6cc ZZ |
744 | |
745 | return 0; | |
746 | } | |
747 | ||
333802e9 | 748 | #ifdef CONFIG_REGULATOR |
9b34e6cc ZZ |
749 | static int ldo_regulator_is_enabled(struct regulator_dev *dev) |
750 | { | |
751 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
752 | ||
753 | return ldo->enabled; | |
754 | } | |
755 | ||
756 | static int ldo_regulator_enable(struct regulator_dev *dev) | |
757 | { | |
758 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
759 | struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; | |
760 | int reg; | |
761 | ||
762 | if (ldo_regulator_is_enabled(dev)) | |
763 | return 0; | |
764 | ||
765 | /* set regulator value firstly */ | |
766 | reg = (1600 - ldo->voltage / 1000) / 50; | |
767 | reg = clamp(reg, 0x0, 0xf); | |
768 | ||
769 | /* amend the voltage value, unit: uV */ | |
770 | ldo->voltage = (1600 - reg * 50) * 1000; | |
771 | ||
772 | /* set voltage to register */ | |
773 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, | |
064a4bce | 774 | SGTL5000_LINREG_VDDD_MASK, reg); |
9b34e6cc ZZ |
775 | |
776 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
777 | SGTL5000_LINEREG_D_POWERUP, | |
778 | SGTL5000_LINEREG_D_POWERUP); | |
779 | ||
780 | /* when internal ldo enabled, simple digital power can be disabled */ | |
781 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
782 | SGTL5000_LINREG_SIMPLE_POWERUP, | |
783 | 0); | |
784 | ||
785 | ldo->enabled = 1; | |
786 | return 0; | |
787 | } | |
788 | ||
789 | static int ldo_regulator_disable(struct regulator_dev *dev) | |
790 | { | |
791 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
792 | struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; | |
793 | ||
794 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
795 | SGTL5000_LINEREG_D_POWERUP, | |
796 | 0); | |
797 | ||
798 | /* clear voltage info */ | |
799 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, | |
064a4bce | 800 | SGTL5000_LINREG_VDDD_MASK, 0); |
9b34e6cc ZZ |
801 | |
802 | ldo->enabled = 0; | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
807 | static int ldo_regulator_get_voltage(struct regulator_dev *dev) | |
808 | { | |
809 | struct ldo_regulator *ldo = rdev_get_drvdata(dev); | |
810 | ||
811 | return ldo->voltage; | |
812 | } | |
813 | ||
814 | static struct regulator_ops ldo_regulator_ops = { | |
815 | .is_enabled = ldo_regulator_is_enabled, | |
816 | .enable = ldo_regulator_enable, | |
817 | .disable = ldo_regulator_disable, | |
818 | .get_voltage = ldo_regulator_get_voltage, | |
819 | }; | |
820 | ||
821 | static int ldo_regulator_register(struct snd_soc_codec *codec, | |
822 | struct regulator_init_data *init_data, | |
823 | int voltage) | |
824 | { | |
825 | struct ldo_regulator *ldo; | |
5b13de7a | 826 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); |
c172708d | 827 | struct regulator_config config = { }; |
9b34e6cc ZZ |
828 | |
829 | ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); | |
830 | ||
831 | if (!ldo) { | |
832 | dev_err(codec->dev, "failed to allocate ldo_regulator\n"); | |
833 | return -ENOMEM; | |
834 | } | |
835 | ||
836 | ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); | |
837 | if (!ldo->desc.name) { | |
838 | kfree(ldo); | |
839 | dev_err(codec->dev, "failed to allocate decs name memory\n"); | |
840 | return -ENOMEM; | |
841 | } | |
842 | ||
843 | ldo->desc.type = REGULATOR_VOLTAGE; | |
844 | ldo->desc.owner = THIS_MODULE; | |
845 | ldo->desc.ops = &ldo_regulator_ops; | |
846 | ldo->desc.n_voltages = 1; | |
847 | ||
848 | ldo->codec_data = codec; | |
849 | ldo->voltage = voltage; | |
850 | ||
c172708d MB |
851 | config.dev = codec->dev; |
852 | config.driver_data = ldo; | |
853 | config.init_data = init_data; | |
854 | ||
855 | ldo->dev = regulator_register(&ldo->desc, &config); | |
9b34e6cc | 856 | if (IS_ERR(ldo->dev)) { |
62f75aaf DC |
857 | int ret = PTR_ERR(ldo->dev); |
858 | ||
9b34e6cc ZZ |
859 | dev_err(codec->dev, "failed to register regulator\n"); |
860 | kfree(ldo->desc.name); | |
861 | kfree(ldo); | |
862 | ||
62f75aaf | 863 | return ret; |
9b34e6cc | 864 | } |
5b13de7a | 865 | sgtl5000->ldo = ldo; |
9b34e6cc ZZ |
866 | |
867 | return 0; | |
868 | } | |
869 | ||
870 | static int ldo_regulator_remove(struct snd_soc_codec *codec) | |
871 | { | |
872 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
873 | struct ldo_regulator *ldo = sgtl5000->ldo; | |
874 | ||
875 | if (!ldo) | |
876 | return 0; | |
877 | ||
878 | regulator_unregister(ldo->dev); | |
879 | kfree(ldo->desc.name); | |
880 | kfree(ldo); | |
881 | ||
882 | return 0; | |
883 | } | |
333802e9 MB |
884 | #else |
885 | static int ldo_regulator_register(struct snd_soc_codec *codec, | |
886 | struct regulator_init_data *init_data, | |
887 | int voltage) | |
888 | { | |
09bddc8e | 889 | dev_err(codec->dev, "this setup needs regulator support in the kernel\n"); |
333802e9 MB |
890 | return -EINVAL; |
891 | } | |
892 | ||
893 | static int ldo_regulator_remove(struct snd_soc_codec *codec) | |
894 | { | |
895 | return 0; | |
896 | } | |
897 | #endif | |
9b34e6cc ZZ |
898 | |
899 | /* | |
900 | * set dac bias | |
901 | * common state changes: | |
902 | * startup: | |
903 | * off --> standby --> prepare --> on | |
904 | * standby --> prepare --> on | |
905 | * | |
906 | * stop: | |
907 | * on --> prepare --> standby | |
908 | */ | |
909 | static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, | |
910 | enum snd_soc_bias_level level) | |
911 | { | |
912 | int ret; | |
913 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
914 | ||
915 | switch (level) { | |
916 | case SND_SOC_BIAS_ON: | |
917 | case SND_SOC_BIAS_PREPARE: | |
918 | break; | |
919 | case SND_SOC_BIAS_STANDBY: | |
920 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
921 | ret = regulator_bulk_enable( | |
922 | ARRAY_SIZE(sgtl5000->supplies), | |
923 | sgtl5000->supplies); | |
924 | if (ret) | |
925 | return ret; | |
926 | udelay(10); | |
2bdc1bb2 MB |
927 | |
928 | regcache_cache_only(sgtl5000->regmap, false); | |
929 | ||
930 | ret = regcache_sync(sgtl5000->regmap); | |
931 | if (ret != 0) { | |
932 | dev_err(codec->dev, | |
933 | "Failed to restore cache: %d\n", ret); | |
934 | ||
935 | regcache_cache_only(sgtl5000->regmap, true); | |
936 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
937 | sgtl5000->supplies); | |
938 | ||
939 | return ret; | |
940 | } | |
9b34e6cc ZZ |
941 | } |
942 | ||
943 | break; | |
944 | case SND_SOC_BIAS_OFF: | |
2bdc1bb2 | 945 | regcache_cache_only(sgtl5000->regmap, true); |
9b34e6cc ZZ |
946 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), |
947 | sgtl5000->supplies); | |
948 | break; | |
949 | } | |
950 | ||
951 | codec->dapm.bias_level = level; | |
952 | return 0; | |
953 | } | |
954 | ||
955 | #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
956 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
957 | SNDRV_PCM_FMTBIT_S24_LE |\ | |
958 | SNDRV_PCM_FMTBIT_S32_LE) | |
959 | ||
85e7652d | 960 | static const struct snd_soc_dai_ops sgtl5000_ops = { |
9b34e6cc ZZ |
961 | .hw_params = sgtl5000_pcm_hw_params, |
962 | .digital_mute = sgtl5000_digital_mute, | |
963 | .set_fmt = sgtl5000_set_dai_fmt, | |
964 | .set_sysclk = sgtl5000_set_dai_sysclk, | |
965 | }; | |
966 | ||
967 | static struct snd_soc_dai_driver sgtl5000_dai = { | |
968 | .name = "sgtl5000", | |
969 | .playback = { | |
970 | .stream_name = "Playback", | |
971 | .channels_min = 1, | |
972 | .channels_max = 2, | |
973 | /* | |
974 | * only support 8~48K + 96K, | |
975 | * TODO modify hw_param to support more | |
976 | */ | |
977 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
978 | .formats = SGTL5000_FORMATS, | |
979 | }, | |
980 | .capture = { | |
981 | .stream_name = "Capture", | |
982 | .channels_min = 1, | |
983 | .channels_max = 2, | |
984 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
985 | .formats = SGTL5000_FORMATS, | |
986 | }, | |
987 | .ops = &sgtl5000_ops, | |
988 | .symmetric_rates = 1, | |
989 | }; | |
990 | ||
e5d80e82 | 991 | static bool sgtl5000_volatile(struct device *dev, unsigned int reg) |
9b34e6cc ZZ |
992 | { |
993 | switch (reg) { | |
994 | case SGTL5000_CHIP_ID: | |
995 | case SGTL5000_CHIP_ADCDAC_CTRL: | |
996 | case SGTL5000_CHIP_ANA_STATUS: | |
e5d80e82 | 997 | return true; |
9b34e6cc ZZ |
998 | } |
999 | ||
e5d80e82 FE |
1000 | return false; |
1001 | } | |
1002 | ||
1003 | static bool sgtl5000_readable(struct device *dev, unsigned int reg) | |
1004 | { | |
1005 | switch (reg) { | |
1006 | case SGTL5000_CHIP_ID: | |
1007 | case SGTL5000_CHIP_DIG_POWER: | |
1008 | case SGTL5000_CHIP_CLK_CTRL: | |
1009 | case SGTL5000_CHIP_I2S_CTRL: | |
1010 | case SGTL5000_CHIP_SSS_CTRL: | |
1011 | case SGTL5000_CHIP_ADCDAC_CTRL: | |
1012 | case SGTL5000_CHIP_DAC_VOL: | |
1013 | case SGTL5000_CHIP_PAD_STRENGTH: | |
1014 | case SGTL5000_CHIP_ANA_ADC_CTRL: | |
1015 | case SGTL5000_CHIP_ANA_HP_CTRL: | |
1016 | case SGTL5000_CHIP_ANA_CTRL: | |
1017 | case SGTL5000_CHIP_LINREG_CTRL: | |
1018 | case SGTL5000_CHIP_REF_CTRL: | |
1019 | case SGTL5000_CHIP_MIC_CTRL: | |
1020 | case SGTL5000_CHIP_LINE_OUT_CTRL: | |
1021 | case SGTL5000_CHIP_LINE_OUT_VOL: | |
1022 | case SGTL5000_CHIP_ANA_POWER: | |
1023 | case SGTL5000_CHIP_PLL_CTRL: | |
1024 | case SGTL5000_CHIP_CLK_TOP_CTRL: | |
1025 | case SGTL5000_CHIP_ANA_STATUS: | |
1026 | case SGTL5000_CHIP_SHORT_CTRL: | |
1027 | case SGTL5000_CHIP_ANA_TEST2: | |
1028 | case SGTL5000_DAP_CTRL: | |
1029 | case SGTL5000_DAP_PEQ: | |
1030 | case SGTL5000_DAP_BASS_ENHANCE: | |
1031 | case SGTL5000_DAP_BASS_ENHANCE_CTRL: | |
1032 | case SGTL5000_DAP_AUDIO_EQ: | |
1033 | case SGTL5000_DAP_SURROUND: | |
1034 | case SGTL5000_DAP_FLT_COEF_ACCESS: | |
1035 | case SGTL5000_DAP_COEF_WR_B0_MSB: | |
1036 | case SGTL5000_DAP_COEF_WR_B0_LSB: | |
1037 | case SGTL5000_DAP_EQ_BASS_BAND0: | |
1038 | case SGTL5000_DAP_EQ_BASS_BAND1: | |
1039 | case SGTL5000_DAP_EQ_BASS_BAND2: | |
1040 | case SGTL5000_DAP_EQ_BASS_BAND3: | |
1041 | case SGTL5000_DAP_EQ_BASS_BAND4: | |
1042 | case SGTL5000_DAP_MAIN_CHAN: | |
1043 | case SGTL5000_DAP_MIX_CHAN: | |
1044 | case SGTL5000_DAP_AVC_CTRL: | |
1045 | case SGTL5000_DAP_AVC_THRESHOLD: | |
1046 | case SGTL5000_DAP_AVC_ATTACK: | |
1047 | case SGTL5000_DAP_AVC_DECAY: | |
1048 | case SGTL5000_DAP_COEF_WR_B1_MSB: | |
1049 | case SGTL5000_DAP_COEF_WR_B1_LSB: | |
1050 | case SGTL5000_DAP_COEF_WR_B2_MSB: | |
1051 | case SGTL5000_DAP_COEF_WR_B2_LSB: | |
1052 | case SGTL5000_DAP_COEF_WR_A1_MSB: | |
1053 | case SGTL5000_DAP_COEF_WR_A1_LSB: | |
1054 | case SGTL5000_DAP_COEF_WR_A2_MSB: | |
1055 | case SGTL5000_DAP_COEF_WR_A2_LSB: | |
1056 | return true; | |
1057 | ||
1058 | default: | |
1059 | return false; | |
1060 | } | |
9b34e6cc ZZ |
1061 | } |
1062 | ||
1063 | #ifdef CONFIG_SUSPEND | |
84b315ee | 1064 | static int sgtl5000_suspend(struct snd_soc_codec *codec) |
9b34e6cc ZZ |
1065 | { |
1066 | sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
1071 | /* | |
1072 | * restore all sgtl5000 registers, | |
1073 | * since a big hole between dap and regular registers, | |
1074 | * we will restore them respectively. | |
1075 | */ | |
1076 | static int sgtl5000_restore_regs(struct snd_soc_codec *codec) | |
1077 | { | |
1078 | u16 *cache = codec->reg_cache; | |
151798f8 | 1079 | u16 reg; |
9b34e6cc ZZ |
1080 | |
1081 | /* restore regular registers */ | |
151798f8 | 1082 | for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { |
9b34e6cc | 1083 | |
bb362e2e | 1084 | /* These regs should restore in particular order */ |
9b34e6cc ZZ |
1085 | if (reg == SGTL5000_CHIP_ANA_POWER || |
1086 | reg == SGTL5000_CHIP_CLK_CTRL || | |
1087 | reg == SGTL5000_CHIP_LINREG_CTRL || | |
1088 | reg == SGTL5000_CHIP_LINE_OUT_CTRL || | |
bb362e2e | 1089 | reg == SGTL5000_CHIP_REF_CTRL) |
9b34e6cc ZZ |
1090 | continue; |
1091 | ||
151798f8 | 1092 | snd_soc_write(codec, reg, cache[reg]); |
9b34e6cc ZZ |
1093 | } |
1094 | ||
1095 | /* restore dap registers */ | |
151798f8 WS |
1096 | for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2) |
1097 | snd_soc_write(codec, reg, cache[reg]); | |
9b34e6cc ZZ |
1098 | |
1099 | /* | |
bb362e2e ZZ |
1100 | * restore these regs according to the power setting sequence in |
1101 | * sgtl5000_set_power_regs() and clock setting sequence in | |
1102 | * sgtl5000_set_clock(). | |
1103 | * | |
1104 | * The order of restore is: | |
1105 | * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after | |
1106 | * SGTL5000_CHIP_ANA_POWER PLL bits set | |
1107 | * 2. SGTL5000_CHIP_LINREG_CTRL should be set before | |
1108 | * SGTL5000_CHIP_ANA_POWER LINREG_D restored | |
1109 | * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage, | |
1110 | * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored | |
9b34e6cc ZZ |
1111 | */ |
1112 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, | |
151798f8 | 1113 | cache[SGTL5000_CHIP_LINREG_CTRL]); |
9b34e6cc ZZ |
1114 | |
1115 | snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, | |
151798f8 | 1116 | cache[SGTL5000_CHIP_ANA_POWER]); |
9b34e6cc ZZ |
1117 | |
1118 | snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, | |
151798f8 | 1119 | cache[SGTL5000_CHIP_CLK_CTRL]); |
9b34e6cc ZZ |
1120 | |
1121 | snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, | |
151798f8 | 1122 | cache[SGTL5000_CHIP_REF_CTRL]); |
9b34e6cc ZZ |
1123 | |
1124 | snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, | |
151798f8 | 1125 | cache[SGTL5000_CHIP_LINE_OUT_CTRL]); |
9b34e6cc ZZ |
1126 | return 0; |
1127 | } | |
1128 | ||
1129 | static int sgtl5000_resume(struct snd_soc_codec *codec) | |
1130 | { | |
1131 | /* Bring the codec back up to standby to enable regulators */ | |
1132 | sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1133 | ||
1134 | /* Restore registers by cached in memory */ | |
1135 | sgtl5000_restore_regs(codec); | |
1136 | return 0; | |
1137 | } | |
1138 | #else | |
1139 | #define sgtl5000_suspend NULL | |
1140 | #define sgtl5000_resume NULL | |
1141 | #endif /* CONFIG_SUSPEND */ | |
1142 | ||
1143 | /* | |
1144 | * sgtl5000 has 3 internal power supplies: | |
1145 | * 1. VAG, normally set to vdda/2 | |
1146 | * 2. chargepump, set to different value | |
1147 | * according to voltage of vdda and vddio | |
1148 | * 3. line out VAG, normally set to vddio/2 | |
1149 | * | |
1150 | * and should be set according to: | |
1151 | * 1. vddd provided by external or not | |
1152 | * 2. vdda and vddio voltage value. > 3.1v or not | |
1153 | * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. | |
1154 | */ | |
1155 | static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) | |
1156 | { | |
1157 | int vddd; | |
1158 | int vdda; | |
1159 | int vddio; | |
1160 | u16 ana_pwr; | |
1161 | u16 lreg_ctrl; | |
1162 | int vag; | |
1163 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1164 | ||
1165 | vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); | |
1166 | vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); | |
1167 | vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); | |
1168 | ||
1169 | vdda = vdda / 1000; | |
1170 | vddio = vddio / 1000; | |
1171 | vddd = vddd / 1000; | |
1172 | ||
1173 | if (vdda <= 0 || vddio <= 0 || vddd < 0) { | |
1174 | dev_err(codec->dev, "regulator voltage not set correctly\n"); | |
1175 | ||
1176 | return -EINVAL; | |
1177 | } | |
1178 | ||
1179 | /* according to datasheet, maximum voltage of supplies */ | |
1180 | if (vdda > 3600 || vddio > 3600 || vddd > 1980) { | |
1181 | dev_err(codec->dev, | |
cf1ee98d | 1182 | "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", |
9b34e6cc ZZ |
1183 | vdda, vddio, vddd); |
1184 | ||
1185 | return -EINVAL; | |
1186 | } | |
1187 | ||
1188 | /* reset value */ | |
1189 | ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); | |
1190 | ana_pwr |= SGTL5000_DAC_STEREO | | |
1191 | SGTL5000_ADC_STEREO | | |
1192 | SGTL5000_REFTOP_POWERUP; | |
1193 | lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); | |
1194 | ||
1195 | if (vddio < 3100 && vdda < 3100) { | |
1196 | /* enable internal oscillator used for charge pump */ | |
1197 | snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, | |
1198 | SGTL5000_INT_OSC_EN, | |
1199 | SGTL5000_INT_OSC_EN); | |
1200 | /* Enable VDDC charge pump */ | |
1201 | ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; | |
1202 | } else if (vddio >= 3100 && vdda >= 3100) { | |
1203 | /* | |
1204 | * if vddio and vddd > 3.1v, | |
1205 | * charge pump should be clean before set ana_pwr | |
1206 | */ | |
1207 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
1208 | SGTL5000_VDDC_CHRGPMP_POWERUP, 0); | |
1209 | ||
1210 | /* VDDC use VDDIO rail */ | |
1211 | lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; | |
1212 | lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << | |
1213 | SGTL5000_VDDC_MAN_ASSN_SHIFT; | |
1214 | } | |
1215 | ||
1216 | snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); | |
1217 | ||
1218 | snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); | |
1219 | ||
1220 | /* set voltage to register */ | |
1221 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, | |
064a4bce | 1222 | SGTL5000_LINREG_VDDD_MASK, 0x8); |
9b34e6cc ZZ |
1223 | |
1224 | /* | |
1225 | * if vddd linear reg has been enabled, | |
1226 | * simple digital supply should be clear to get | |
1227 | * proper VDDD voltage. | |
1228 | */ | |
1229 | if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) | |
1230 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
1231 | SGTL5000_LINREG_SIMPLE_POWERUP, | |
1232 | 0); | |
1233 | else | |
1234 | snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, | |
1235 | SGTL5000_LINREG_SIMPLE_POWERUP | | |
1236 | SGTL5000_STARTUP_POWERUP, | |
1237 | 0); | |
1238 | ||
1239 | /* | |
1240 | * set ADC/DAC VAG to vdda / 2, | |
1241 | * should stay in range (0.8v, 1.575v) | |
1242 | */ | |
1243 | vag = vdda / 2; | |
1244 | if (vag <= SGTL5000_ANA_GND_BASE) | |
1245 | vag = 0; | |
1246 | else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * | |
1247 | (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) | |
1248 | vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; | |
1249 | else | |
1250 | vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; | |
1251 | ||
1252 | snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, | |
33cb92cf | 1253 | SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); |
9b34e6cc ZZ |
1254 | |
1255 | /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ | |
1256 | vag = vddio / 2; | |
1257 | if (vag <= SGTL5000_LINE_OUT_GND_BASE) | |
1258 | vag = 0; | |
1259 | else if (vag >= SGTL5000_LINE_OUT_GND_BASE + | |
1260 | SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) | |
1261 | vag = SGTL5000_LINE_OUT_GND_MAX; | |
1262 | else | |
1263 | vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / | |
1264 | SGTL5000_LINE_OUT_GND_STP; | |
1265 | ||
1266 | snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, | |
33cb92cf AL |
1267 | SGTL5000_LINE_OUT_CURRENT_MASK | |
1268 | SGTL5000_LINE_OUT_GND_MASK, | |
9b34e6cc ZZ |
1269 | vag << SGTL5000_LINE_OUT_GND_SHIFT | |
1270 | SGTL5000_LINE_OUT_CURRENT_360u << | |
1271 | SGTL5000_LINE_OUT_CURRENT_SHIFT); | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | ||
e94a4062 WS |
1276 | static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) |
1277 | { | |
1278 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1279 | int ret; | |
1280 | ||
1281 | /* set internal ldo to 1.2v */ | |
1282 | ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE); | |
1283 | if (ret) { | |
1284 | dev_err(codec->dev, | |
1285 | "Failed to register vddd internal supplies: %d\n", ret); | |
1286 | return ret; | |
1287 | } | |
1288 | ||
1289 | sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; | |
1290 | ||
e94a4062 WS |
1291 | dev_info(codec->dev, "Using internal LDO instead of VDDD\n"); |
1292 | return 0; | |
1293 | } | |
1294 | ||
9b34e6cc ZZ |
1295 | static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) |
1296 | { | |
9b34e6cc | 1297 | int ret; |
9b34e6cc ZZ |
1298 | int i; |
1299 | int external_vddd = 0; | |
1300 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
11db0da8 | 1301 | struct regulator *vddd; |
9b34e6cc ZZ |
1302 | |
1303 | for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) | |
1304 | sgtl5000->supplies[i].supply = supply_names[i]; | |
1305 | ||
11db0da8 SG |
1306 | /* External VDDD only works before revision 0x11 */ |
1307 | if (sgtl5000->revision < 0x11) { | |
1308 | vddd = regulator_get_optional(codec->dev, "VDDD"); | |
1309 | if (IS_ERR(vddd)) { | |
1310 | /* See if it's just not registered yet */ | |
1311 | if (PTR_ERR(vddd) == -EPROBE_DEFER) | |
1312 | return -EPROBE_DEFER; | |
1313 | } else { | |
1314 | external_vddd = 1; | |
1315 | regulator_put(vddd); | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | if (!external_vddd) { | |
e94a4062 WS |
1320 | ret = sgtl5000_replace_vddd_with_ldo(codec); |
1321 | if (ret) | |
9b34e6cc | 1322 | return ret; |
9b34e6cc ZZ |
1323 | } |
1324 | ||
63e54cd9 | 1325 | ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), |
11db0da8 SG |
1326 | sgtl5000->supplies); |
1327 | if (ret) | |
1328 | goto err_ldo_remove; | |
1329 | ||
9b34e6cc ZZ |
1330 | ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), |
1331 | sgtl5000->supplies); | |
1332 | if (ret) | |
63e54cd9 | 1333 | goto err_ldo_remove; |
9b34e6cc ZZ |
1334 | |
1335 | /* wait for all power rails bring up */ | |
1336 | udelay(10); | |
1337 | ||
9b34e6cc ZZ |
1338 | return 0; |
1339 | ||
11db0da8 SG |
1340 | err_ldo_remove: |
1341 | if (!external_vddd) | |
9b34e6cc ZZ |
1342 | ldo_regulator_remove(codec); |
1343 | return ret; | |
1344 | ||
1345 | } | |
1346 | ||
1347 | static int sgtl5000_probe(struct snd_soc_codec *codec) | |
1348 | { | |
1349 | int ret; | |
1350 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1351 | ||
9b34e6cc ZZ |
1352 | ret = sgtl5000_enable_regulators(codec); |
1353 | if (ret) | |
1354 | return ret; | |
1355 | ||
1356 | /* power up sgtl5000 */ | |
1357 | ret = sgtl5000_set_power_regs(codec); | |
1358 | if (ret) | |
1359 | goto err; | |
1360 | ||
1361 | /* enable small pop, introduce 400ms delay in turning off */ | |
1362 | snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, | |
1363 | SGTL5000_SMALL_POP, | |
1364 | SGTL5000_SMALL_POP); | |
1365 | ||
1366 | /* disable short cut detector */ | |
1367 | snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); | |
1368 | ||
1369 | /* | |
1370 | * set i2s as default input of sound switch | |
1371 | * TODO: add sound switch to control and dapm widge. | |
1372 | */ | |
1373 | snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, | |
1374 | SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); | |
1375 | snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, | |
1376 | SGTL5000_ADC_EN | SGTL5000_DAC_EN); | |
1377 | ||
1378 | /* enable dac volume ramp by default */ | |
1379 | snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, | |
1380 | SGTL5000_DAC_VOL_RAMP_EN | | |
1381 | SGTL5000_DAC_MUTE_RIGHT | | |
1382 | SGTL5000_DAC_MUTE_LEFT); | |
1383 | ||
1384 | snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); | |
1385 | ||
1386 | snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, | |
1387 | SGTL5000_HP_ZCD_EN | | |
1388 | SGTL5000_ADC_ZCD_EN); | |
1389 | ||
b50684da | 1390 | snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2); |
9b34e6cc ZZ |
1391 | |
1392 | /* | |
1393 | * disable DAP | |
1394 | * TODO: | |
1395 | * Enable DAP in kcontrol and dapm. | |
1396 | */ | |
1397 | snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); | |
1398 | ||
1399 | /* leading to standby state */ | |
1400 | ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1401 | if (ret) | |
1402 | goto err; | |
1403 | ||
9b34e6cc ZZ |
1404 | return 0; |
1405 | ||
1406 | err: | |
1407 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1408 | sgtl5000->supplies); | |
9b34e6cc ZZ |
1409 | ldo_regulator_remove(codec); |
1410 | ||
1411 | return ret; | |
1412 | } | |
1413 | ||
1414 | static int sgtl5000_remove(struct snd_soc_codec *codec) | |
1415 | { | |
1416 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | |
1417 | ||
1418 | sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1419 | ||
1420 | regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), | |
1421 | sgtl5000->supplies); | |
9b34e6cc ZZ |
1422 | ldo_regulator_remove(codec); |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
61a142b7 | 1427 | static struct snd_soc_codec_driver sgtl5000_driver = { |
9b34e6cc ZZ |
1428 | .probe = sgtl5000_probe, |
1429 | .remove = sgtl5000_remove, | |
1430 | .suspend = sgtl5000_suspend, | |
1431 | .resume = sgtl5000_resume, | |
1432 | .set_bias_level = sgtl5000_set_bias_level, | |
89989637 FE |
1433 | .controls = sgtl5000_snd_controls, |
1434 | .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), | |
5e0ac527 MB |
1435 | .dapm_widgets = sgtl5000_dapm_widgets, |
1436 | .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), | |
1437 | .dapm_routes = sgtl5000_dapm_routes, | |
1438 | .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), | |
9b34e6cc ZZ |
1439 | }; |
1440 | ||
e5d80e82 FE |
1441 | static const struct regmap_config sgtl5000_regmap = { |
1442 | .reg_bits = 16, | |
1443 | .val_bits = 16, | |
cb23e852 | 1444 | .reg_stride = 2, |
e5d80e82 FE |
1445 | |
1446 | .max_register = SGTL5000_MAX_REG_OFFSET, | |
1447 | .volatile_reg = sgtl5000_volatile, | |
1448 | .readable_reg = sgtl5000_readable, | |
1449 | ||
1450 | .cache_type = REGCACHE_RBTREE, | |
1451 | .reg_defaults = sgtl5000_reg_defaults, | |
1452 | .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), | |
1453 | }; | |
1454 | ||
af8ee112 FE |
1455 | /* |
1456 | * Write all the default values from sgtl5000_reg_defaults[] array into the | |
1457 | * sgtl5000 registers, to make sure we always start with the sane registers | |
1458 | * values as stated in the datasheet. | |
1459 | * | |
1460 | * Since sgtl5000 does not have a reset line, nor a reset command in software, | |
1461 | * we follow this approach to guarantee we always start from the default values | |
1462 | * and avoid problems like, not being able to probe after an audio playback | |
1463 | * followed by a system reset or a 'reboot' command in Linux | |
1464 | */ | |
1465 | static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000) | |
1466 | { | |
1467 | int i, ret, val, index; | |
1468 | ||
1469 | for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { | |
1470 | val = sgtl5000_reg_defaults[i].def; | |
1471 | index = sgtl5000_reg_defaults[i].reg; | |
1472 | ret = regmap_write(sgtl5000->regmap, index, val); | |
1473 | if (ret) | |
1474 | return ret; | |
1475 | } | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
7a79e94e BP |
1480 | static int sgtl5000_i2c_probe(struct i2c_client *client, |
1481 | const struct i2c_device_id *id) | |
9b34e6cc ZZ |
1482 | { |
1483 | struct sgtl5000_priv *sgtl5000; | |
b871f1ad | 1484 | int ret, reg, rev; |
9b34e6cc | 1485 | |
512fa7c4 FE |
1486 | sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv), |
1487 | GFP_KERNEL); | |
9b34e6cc ZZ |
1488 | if (!sgtl5000) |
1489 | return -ENOMEM; | |
1490 | ||
e5d80e82 FE |
1491 | sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); |
1492 | if (IS_ERR(sgtl5000->regmap)) { | |
1493 | ret = PTR_ERR(sgtl5000->regmap); | |
1494 | dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); | |
1495 | return ret; | |
1496 | } | |
1497 | ||
9e13f345 FE |
1498 | sgtl5000->mclk = devm_clk_get(&client->dev, NULL); |
1499 | if (IS_ERR(sgtl5000->mclk)) { | |
1500 | ret = PTR_ERR(sgtl5000->mclk); | |
1501 | dev_err(&client->dev, "Failed to get mclock: %d\n", ret); | |
46a5905e SG |
1502 | /* Defer the probe to see if the clk will be provided later */ |
1503 | if (ret == -ENOENT) | |
1504 | return -EPROBE_DEFER; | |
9e13f345 FE |
1505 | return ret; |
1506 | } | |
1507 | ||
1508 | ret = clk_prepare_enable(sgtl5000->mclk); | |
1509 | if (ret) | |
1510 | return ret; | |
1511 | ||
b871f1ad FE |
1512 | /* read chip information */ |
1513 | ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); | |
1514 | if (ret) | |
9e13f345 | 1515 | goto disable_clk; |
b871f1ad FE |
1516 | |
1517 | if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != | |
1518 | SGTL5000_PARTID_PART_ID) { | |
1519 | dev_err(&client->dev, | |
1520 | "Device with ID register %x is not a sgtl5000\n", reg); | |
9e13f345 FE |
1521 | ret = -ENODEV; |
1522 | goto disable_clk; | |
b871f1ad FE |
1523 | } |
1524 | ||
1525 | rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; | |
1526 | dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); | |
252e91ff | 1527 | sgtl5000->revision = rev; |
b871f1ad | 1528 | |
9b34e6cc ZZ |
1529 | i2c_set_clientdata(client, sgtl5000); |
1530 | ||
af8ee112 FE |
1531 | /* Ensure sgtl5000 will start with sane register values */ |
1532 | ret = sgtl5000_fill_defaults(sgtl5000); | |
1533 | if (ret) | |
9e13f345 | 1534 | goto disable_clk; |
af8ee112 | 1535 | |
9b34e6cc ZZ |
1536 | ret = snd_soc_register_codec(&client->dev, |
1537 | &sgtl5000_driver, &sgtl5000_dai, 1); | |
9e13f345 FE |
1538 | if (ret) |
1539 | goto disable_clk; | |
1540 | ||
1541 | return 0; | |
1542 | ||
1543 | disable_clk: | |
1544 | clk_disable_unprepare(sgtl5000->mclk); | |
512fa7c4 | 1545 | return ret; |
9b34e6cc ZZ |
1546 | } |
1547 | ||
7a79e94e | 1548 | static int sgtl5000_i2c_remove(struct i2c_client *client) |
9b34e6cc | 1549 | { |
7c647af4 | 1550 | struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); |
9b34e6cc | 1551 | |
9e13f345 FE |
1552 | snd_soc_unregister_codec(&client->dev); |
1553 | clk_disable_unprepare(sgtl5000->mclk); | |
9b34e6cc ZZ |
1554 | return 0; |
1555 | } | |
1556 | ||
1557 | static const struct i2c_device_id sgtl5000_id[] = { | |
1558 | {"sgtl5000", 0}, | |
1559 | {}, | |
1560 | }; | |
1561 | ||
1562 | MODULE_DEVICE_TABLE(i2c, sgtl5000_id); | |
1563 | ||
58e49424 SG |
1564 | static const struct of_device_id sgtl5000_dt_ids[] = { |
1565 | { .compatible = "fsl,sgtl5000", }, | |
1566 | { /* sentinel */ } | |
1567 | }; | |
4c54c6de | 1568 | MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); |
58e49424 | 1569 | |
9b34e6cc ZZ |
1570 | static struct i2c_driver sgtl5000_i2c_driver = { |
1571 | .driver = { | |
1572 | .name = "sgtl5000", | |
1573 | .owner = THIS_MODULE, | |
58e49424 | 1574 | .of_match_table = sgtl5000_dt_ids, |
9b34e6cc ZZ |
1575 | }, |
1576 | .probe = sgtl5000_i2c_probe, | |
7a79e94e | 1577 | .remove = sgtl5000_i2c_remove, |
9b34e6cc ZZ |
1578 | .id_table = sgtl5000_id, |
1579 | }; | |
1580 | ||
67d45090 | 1581 | module_i2c_driver(sgtl5000_i2c_driver); |
9b34e6cc ZZ |
1582 | |
1583 | MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); | |
f7cb8a4b | 1584 | MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); |
9b34e6cc | 1585 | MODULE_LICENSE("GPL"); |