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ASoC: sgtl5000: Cleanup the comments
[deliverable/linux.git] / sound / soc / codecs / sgtl5000.c
CommitLineData
9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
e5d80e82 19#include <linux/regmap.h>
9b34e6cc
ZZ		 20#include <linux/regulator/driver.h>
21#include <linux/regulator/machine.h>
22#include <linux/regulator/consumer.h>
58e49424 23#include <linux/of_device.h>
9b34e6cc
ZZ		 24#include <sound/core.h>
25#include <sound/tlv.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
9b34e6cc
ZZ		 31
32#include "sgtl5000.h"
33
34#define SGTL5000_DAP_REG_OFFSET 0x0100
35#define SGTL5000_MAX_REG_OFFSET 0x013A
36
151798f8 37/* default value of sgtl5000 registers */
e5d80e82 38static const struct reg_default sgtl5000_reg_defaults[] = {
29aa37cd 39 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
e5d80e82
FE		 40 { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
41 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
016fcab8 42 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
29aa37cd 43 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
e5d80e82
FE		 44 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
45 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
29aa37cd 46 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
e5d80e82
FE		 47 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
48 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
29aa37cd
FE		 49 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
50 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
51 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
52 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
e5d80e82
FE		 53 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
54 { SGTL5000_CHIP_ANA_POWER, 0x7060 },
55 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
29aa37cd
FE		 56 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
57 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
58 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
59 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
60 { SGTL5000_DAP_CTRL, 0x0000 },
61 { SGTL5000_DAP_PEQ, 0x0000 },
e5d80e82
FE		 62 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
63 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
29aa37cd 64 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
e5d80e82
FE		 65 { SGTL5000_DAP_SURROUND, 0x0040 },
66 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
67 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
69 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
70 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
71 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
29aa37cd 72 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
e5d80e82
FE		 73 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
74 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
75 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
76 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
9b34e6cc
ZZ		 77};
78
79/* regulator supplies for sgtl5000, VDDD is an optional external supply */
80enum sgtl5000_regulator_supplies {
81 VDDA,
82 VDDIO,
83 VDDD,
84 SGTL5000_SUPPLY_NUM
85};
86
87/* vddd is optional supply */
88static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
89 "VDDA",
90 "VDDIO",
91 "VDDD"
92};
93
94#define LDO_CONSUMER_NAME "VDDD_LDO"
95#define LDO_VOLTAGE 1200000
96
97static struct regulator_consumer_supply ldo_consumer[] = {
98 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
99};
100
61a142b7 101static struct regulator_init_data ldo_init_data = {
9b34e6cc 102 .constraints = {
cd041f64
FE		 103 .min_uV = 1200000,
104 .max_uV = 1200000,
9b34e6cc
ZZ		 105 .valid_modes_mask = REGULATOR_MODE_NORMAL,
106 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
107 },
108 .num_consumer_supplies = 1,
109 .consumer_supplies = &ldo_consumer[0],
110};
111
112/*
113 * sgtl5000 internal ldo regulator,
114 * enabled when VDDD not provided
115 */
116struct ldo_regulator {
117 struct regulator_desc desc;
118 struct regulator_dev *dev;
119 int voltage;
120 void *codec_data;
121 bool enabled;
122};
123
124/* sgtl5000 private structure in codec */
125struct sgtl5000_priv {
126 int sysclk; /* sysclk rate */
127 int master; /* i2s master or not */
128 int fmt; /* i2s data format */
129 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
130 struct ldo_regulator *ldo;
e5d80e82 131 struct regmap *regmap;
9e13f345 132 struct clk *mclk;
252e91ff 133 int revision;
9b34e6cc
ZZ		 134};
135
136/*
137 * mic_bias power on/off share the same register bits with
138 * output impedance of mic bias, when power on mic bias, we
139 * need reclaim it to impedance value.
140 * 0x0 = Powered off
141 * 0x1 = 2Kohm
142 * 0x2 = 4Kohm
143 * 0x3 = 8Kohm
144 */
145static int mic_bias_event(struct snd_soc_dapm_widget *w,
146 struct snd_kcontrol *kcontrol, int event)
147{
148 switch (event) {
149 case SND_SOC_DAPM_POST_PMU:
150 /* change mic bias resistor to 4Kohm */
151 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8
AL		 152 SGTL5000_BIAS_R_MASK,
153 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 154 break;
155
156 case SND_SOC_DAPM_PRE_PMD:
9b34e6cc 157 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 158 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 159 break;
160 }
161 return 0;
162}
163
164/*
f0cdcf3a
ZZ		 165 * As manual described, ADC/DAC only works when VAG powerup,
166 * So enabled VAG before ADC/DAC up.
167 * In power down case, we need wait 400ms when vag fully ramped down.
9b34e6cc 168 */
f0cdcf3a 169static int power_vag_event(struct snd_soc_dapm_widget *w,
9b34e6cc
ZZ		 170 struct snd_kcontrol *kcontrol, int event)
171{
f091f3f0
LW		 172 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
173
9b34e6cc 174 switch (event) {
dd4d2d6d 175 case SND_SOC_DAPM_POST_PMU:
9b34e6cc
ZZ		 176 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
177 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
178 break;
179
dd4d2d6d 180 case SND_SOC_DAPM_PRE_PMD:
f091f3f0
LW		 181 /*
182 * Don't clear VAG_POWERUP, when both DAC and ADC are
183 * operational to prevent inadvertently starving the
184 * other one of them.
185 */
186 if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) &
187 mask) != mask) {
188 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
189 SGTL5000_VAG_POWERUP, 0);
190 msleep(400);
191 }
9b34e6cc
ZZ		 192 break;
193 default:
194 break;
195 }
196
197 return 0;
198}
199
200/* input sources for ADC */
201static const char *adc_mux_text[] = {
202 "MIC_IN", "LINE_IN"
203};
204
c8ed6504
TI		 205static SOC_ENUM_SINGLE_DECL(adc_enum,
206 SGTL5000_CHIP_ANA_CTRL, 2,
207 adc_mux_text);
9b34e6cc
ZZ		 208
209static const struct snd_kcontrol_new adc_mux =
210SOC_DAPM_ENUM("Capture Mux", adc_enum);
211
212/* input sources for DAC */
213static const char *dac_mux_text[] = {
214 "DAC", "LINE_IN"
215};
216
c8ed6504
TI		 217static SOC_ENUM_SINGLE_DECL(dac_enum,
218 SGTL5000_CHIP_ANA_CTRL, 6,
219 dac_mux_text);
9b34e6cc
ZZ		 220
221static const struct snd_kcontrol_new dac_mux =
222SOC_DAPM_ENUM("Headphone Mux", dac_enum);
223
224static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
225 SND_SOC_DAPM_INPUT("LINE_IN"),
226 SND_SOC_DAPM_INPUT("MIC_IN"),
227
228 SND_SOC_DAPM_OUTPUT("HP_OUT"),
229 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
230
8fc8ec92
MB		 231 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
232 mic_bias_event,
233 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9b34e6cc 234
f0cdcf3a
ZZ		 235 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
236 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
9b34e6cc
ZZ		 237
238 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
239 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
240
241 /* aif for i2s input */
242 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
243 0, SGTL5000_CHIP_DIG_POWER,
244 0, 0),
245
246 /* aif for i2s output */
247 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
248 0, SGTL5000_CHIP_DIG_POWER,
249 1, 0),
250
f0cdcf3a 251 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
9b34e6cc 252 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
dd4d2d6d
MV		 253
254 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
255 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
9b34e6cc
ZZ		 256};
257
258/* routes for sgtl5000 */
89989637 259static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
9b34e6cc
ZZ		 260 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
261 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
262
263 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
264 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
265
266 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
267 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
268 {"LO", NULL, "DAC"}, /* dac --> line_out */
269
270 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
271 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
272
273 {"LINE_OUT", NULL, "LO"},
274 {"HP_OUT", NULL, "HP"},
275};
276
277/* custom function to fetch info of PCM playback volume */
278static int dac_info_volsw(struct snd_kcontrol *kcontrol,
279 struct snd_ctl_elem_info *uinfo)
280{
281 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
282 uinfo->count = 2;
283 uinfo->value.integer.min = 0;
284 uinfo->value.integer.max = 0xfc - 0x3c;
285 return 0;
286}
287
288/*
289 * custom function to get of PCM playback volume
290 *
291 * dac volume register
292 * 15-------------8-7--------------0
293 * | R channel vol | L channel vol |
294 * -------------------------------
295 *
296 * PCM volume with 0.5017 dB steps from 0 to -90 dB
297 *
298 * register values map to dB
299 * 0x3B and less = Reserved
300 * 0x3C = 0 dB
301 * 0x3D = -0.5 dB
302 * 0xF0 = -90 dB
303 * 0xFC and greater = Muted
304 *
305 * register value map to userspace value
306 *
307 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
308 * ------------------------------
309 * userspace value 0xc0 0
310 */
311static int dac_get_volsw(struct snd_kcontrol *kcontrol,
312 struct snd_ctl_elem_value *ucontrol)
313{
ea53bf77 314 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 315 int reg;
316 int l;
317 int r;
318
319 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
320
321 /* get left channel volume */
322 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
323
324 /* get right channel volume */
325 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
326
327 /* make sure value fall in (0x3c,0xfc) */
328 l = clamp(l, 0x3c, 0xfc);
329 r = clamp(r, 0x3c, 0xfc);
330
331 /* invert it and map to userspace value */
332 l = 0xfc - l;
333 r = 0xfc - r;
334
335 ucontrol->value.integer.value[0] = l;
336 ucontrol->value.integer.value[1] = r;
337
338 return 0;
339}
340
341/*
342 * custom function to put of PCM playback volume
343 *
344 * dac volume register
345 * 15-------------8-7--------------0
346 * | R channel vol | L channel vol |
347 * -------------------------------
348 *
349 * PCM volume with 0.5017 dB steps from 0 to -90 dB
350 *
351 * register values map to dB
352 * 0x3B and less = Reserved
353 * 0x3C = 0 dB
354 * 0x3D = -0.5 dB
355 * 0xF0 = -90 dB
356 * 0xFC and greater = Muted
357 *
358 * userspace value map to register value
359 *
360 * userspace value 0xc0 0
361 * ------------------------------
362 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
363 */
364static int dac_put_volsw(struct snd_kcontrol *kcontrol,
365 struct snd_ctl_elem_value *ucontrol)
366{
ea53bf77 367 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 368 int reg;
369 int l;
370 int r;
371
372 l = ucontrol->value.integer.value[0];
373 r = ucontrol->value.integer.value[1];
374
375 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
376 l = clamp(l, 0, 0xfc - 0x3c);
377 r = clamp(r, 0, 0xfc - 0x3c);
378
379 /* invert it, get the value can be set to register */
380 l = 0xfc - l;
381 r = 0xfc - r;
382
383 /* shift to get the register value */
384 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
385 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
386
387 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
388
389 return 0;
390}
391
392static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
393
394/* tlv for mic gain, 0db 20db 30db 40db */
395static const unsigned int mic_gain_tlv[] = {
740fb9d5 396 TLV_DB_RANGE_HEAD(2),
9b34e6cc
ZZ		 397 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
398 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
399};
400
401/* tlv for hp volume, -51.5db to 12.0db, step .5db */
402static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
403
404static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
405 /* SOC_DOUBLE_S8_TLV with invert */
406 {
407 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
408 .name = "PCM Playback Volume",
409 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
410 SNDRV_CTL_ELEM_ACCESS_READWRITE,
411 .info = dac_info_volsw,
412 .get = dac_get_volsw,
413 .put = dac_put_volsw,
414 },
415
416 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
417 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
418 SGTL5000_CHIP_ANA_ADC_CTRL,
65f2b226 419 8, 1, 0, capture_6db_attenuate),
9b34e6cc
ZZ		 420 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
421
422 SOC_DOUBLE_TLV("Headphone Playback Volume",
423 SGTL5000_CHIP_ANA_HP_CTRL,
424 0, 8,
425 0x7f, 1,
426 headphone_volume),
427 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
428 5, 1, 0),
429
430 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
b50684da 431 0, 3, 0, mic_gain_tlv),
9b34e6cc
ZZ		 432};
433
434/* mute the codec used by alsa core */
435static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
436{
437 struct snd_soc_codec *codec = codec_dai->codec;
438 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
439
440 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
441 adcdac_ctrl, mute ? adcdac_ctrl : 0);
442
443 return 0;
444}
445
446/* set codec format */
447static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
448{
449 struct snd_soc_codec *codec = codec_dai->codec;
450 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
451 u16 i2sctl = 0;
452
453 sgtl5000->master = 0;
454 /*
455 * i2s clock and frame master setting.
456 * ONLY support:
457 * - clock and frame slave,
458 * - clock and frame master
459 */
460 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
461 case SND_SOC_DAIFMT_CBS_CFS:
462 break;
463 case SND_SOC_DAIFMT_CBM_CFM:
464 i2sctl |= SGTL5000_I2S_MASTER;
465 sgtl5000->master = 1;
466 break;
467 default:
468 return -EINVAL;
469 }
470
471 /* setting i2s data format */
472 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
473 case SND_SOC_DAIFMT_DSP_A:
474 i2sctl |= SGTL5000_I2S_MODE_PCM;
475 break;
476 case SND_SOC_DAIFMT_DSP_B:
477 i2sctl |= SGTL5000_I2S_MODE_PCM;
478 i2sctl |= SGTL5000_I2S_LRALIGN;
479 break;
480 case SND_SOC_DAIFMT_I2S:
481 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
482 break;
483 case SND_SOC_DAIFMT_RIGHT_J:
484 i2sctl |= SGTL5000_I2S_MODE_RJ;
485 i2sctl |= SGTL5000_I2S_LRPOL;
486 break;
487 case SND_SOC_DAIFMT_LEFT_J:
488 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
489 i2sctl |= SGTL5000_I2S_LRALIGN;
490 break;
491 default:
492 return -EINVAL;
493 }
494
495 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
496
497 /* Clock inversion */
498 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
499 case SND_SOC_DAIFMT_NB_NF:
500 break;
501 case SND_SOC_DAIFMT_IB_NF:
502 i2sctl |= SGTL5000_I2S_SCLK_INV;
503 break;
504 default:
505 return -EINVAL;
506 }
507
508 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
509
510 return 0;
511}
512
513/* set codec sysclk */
514static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
515 int clk_id, unsigned int freq, int dir)
516{
517 struct snd_soc_codec *codec = codec_dai->codec;
518 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
519
520 switch (clk_id) {
521 case SGTL5000_SYSCLK:
522 sgtl5000->sysclk = freq;
523 break;
524 default:
525 return -EINVAL;
526 }
527
528 return 0;
529}
530
531/*
532 * set clock according to i2s frame clock,
7f6d75d7
FE		 533 * sgtl5000 provides 2 clock sources:
534 * 1. sys_mclk: sample freq can only be configured to
9b34e6cc 535 * 1/256, 1/384, 1/512 of sys_mclk.
7f6d75d7 536 * 2. pll: can derive any audio clocks.
9b34e6cc
ZZ		 537 *
538 * clock setting rules:
7f6d75d7
FE		 539 * 1. in slave mode, only sys_mclk can be used
540 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
541 * and above.
542 * 3. usage of sys_mclk is preferred over pll to save power.
9b34e6cc
ZZ		 543 */
544static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
545{
546 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
547 int clk_ctl = 0;
548 int sys_fs; /* sample freq */
549
550 /*
551 * sample freq should be divided by frame clock,
7f6d75d7
FE		 552 * if frame clock is lower than 44.1 kHz, sample freq should be set to
553 * 32 kHz or 44.1 kHz.
9b34e6cc
ZZ		 554 */
555 switch (frame_rate) {
556 case 8000:
557 case 16000:
558 sys_fs = 32000;
559 break;
560 case 11025:
561 case 22050:
562 sys_fs = 44100;
563 break;
564 default:
565 sys_fs = frame_rate;
566 break;
567 }
568
569 /* set divided factor of frame clock */
570 switch (sys_fs / frame_rate) {
571 case 4:
572 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
573 break;
574 case 2:
575 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
576 break;
577 case 1:
578 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
579 break;
580 default:
581 return -EINVAL;
582 }
583
584 /* set the sys_fs according to frame rate */
585 switch (sys_fs) {
586 case 32000:
587 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
588 break;
589 case 44100:
590 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
591 break;
592 case 48000:
593 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
594 break;
595 case 96000:
596 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
597 break;
598 default:
599 dev_err(codec->dev, "frame rate %d not supported\n",
600 frame_rate);
601 return -EINVAL;
602 }
603
604 /*
605 * calculate the divider of mclk/sample_freq,
7f6d75d7
FE		 606 * factor of freq = 96 kHz can only be 256, since mclk is in the range
607 * of 8 MHz - 27 MHz
9b34e6cc
ZZ		 608 */
609 switch (sgtl5000->sysclk / sys_fs) {
610 case 256:
611 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
612 SGTL5000_MCLK_FREQ_SHIFT;
613 break;
614 case 384:
615 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
616 SGTL5000_MCLK_FREQ_SHIFT;
617 break;
618 case 512:
619 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
620 SGTL5000_MCLK_FREQ_SHIFT;
621 break;
622 default:
7f6d75d7 623 /* if mclk does not satisfy the divider, use pll */
9b34e6cc
ZZ		 624 if (sgtl5000->master) {
625 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
626 SGTL5000_MCLK_FREQ_SHIFT;
627 } else {
628 dev_err(codec->dev,
629 "PLL not supported in slave mode\n");
fa558d01
FE		 630 dev_err(codec->dev, "%d ratio is not supported. "
631 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
632 sgtl5000->sysclk / sys_fs);
9b34e6cc
ZZ		 633 return -EINVAL;
634 }
635 }
636
637 /* if using pll, please check manual 6.4.2 for detail */
638 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
639 u64 out, t;
640 int div2;
641 int pll_ctl;
642 unsigned int in, int_div, frac_div;
643
644 if (sgtl5000->sysclk > 17000000) {
645 div2 = 1;
646 in = sgtl5000->sysclk / 2;
647 } else {
648 div2 = 0;
649 in = sgtl5000->sysclk;
650 }
651 if (sys_fs == 44100)
652 out = 180633600;
653 else
654 out = 196608000;
655 t = do_div(out, in);
656 int_div = out;
657 t *= 2048;
658 do_div(t, in);
659 frac_div = t;
660 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
661 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
662
663 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
664 if (div2)
665 snd_soc_update_bits(codec,
666 SGTL5000_CHIP_CLK_TOP_CTRL,
667 SGTL5000_INPUT_FREQ_DIV2,
668 SGTL5000_INPUT_FREQ_DIV2);
669 else
670 snd_soc_update_bits(codec,
671 SGTL5000_CHIP_CLK_TOP_CTRL,
672 SGTL5000_INPUT_FREQ_DIV2,
673 0);
674
675 /* power up pll */
676 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
677 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
678 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
e06e4c2d
OS		 679
680 /* if using pll, clk_ctrl must be set after pll power up */
681 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
9b34e6cc 682 } else {
e06e4c2d
OS		 683 /* otherwise, clk_ctrl must be set before pll power down */
684 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
685
9b34e6cc
ZZ		 686 /* power down pll */
687 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
688 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
689 0);
690 }
691
9b34e6cc
ZZ		 692 return 0;
693}
694
695/*
696 * Set PCM DAI bit size and sample rate.
697 * input: params_rate, params_fmt
698 */
699static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
700 struct snd_pcm_hw_params *params,
701 struct snd_soc_dai *dai)
702{
e6968a17 703 struct snd_soc_codec *codec = dai->codec;
9b34e6cc
ZZ		 704 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
705 int channels = params_channels(params);
706 int i2s_ctl = 0;
707 int stereo;
708 int ret;
709
710 /* sysclk should already set */
711 if (!sgtl5000->sysclk) {
712 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
713 return -EFAULT;
714 }
715
716 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
717 stereo = SGTL5000_DAC_STEREO;
718 else
719 stereo = SGTL5000_ADC_STEREO;
720
721 /* set mono to save power */
722 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
723 channels == 1 ? 0 : stereo);
724
725 /* set codec clock base on lrclk */
726 ret = sgtl5000_set_clock(codec, params_rate(params));
727 if (ret)
728 return ret;
729
730 /* set i2s data format */
dacc2aef
MB		 731 switch (params_width(params)) {
732 case 16:
9b34e6cc
ZZ		 733 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
734 return -EINVAL;
735 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
736 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
737 SGTL5000_I2S_SCLKFREQ_SHIFT;
738 break;
dacc2aef 739 case 20:
9b34e6cc
ZZ		 740 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
741 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
742 SGTL5000_I2S_SCLKFREQ_SHIFT;
743 break;
dacc2aef 744 case 24:
9b34e6cc
ZZ		 745 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
746 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
747 SGTL5000_I2S_SCLKFREQ_SHIFT;
748 break;
dacc2aef 749 case 32:
9b34e6cc
ZZ		 750 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
751 return -EINVAL;
752 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
753 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
754 SGTL5000_I2S_SCLKFREQ_SHIFT;
755 break;
756 default:
757 return -EINVAL;
758 }
759
33cb92cf
AL		 760 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
761 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
762 i2s_ctl);
9b34e6cc
ZZ		 763
764 return 0;
765}
766
333802e9 767#ifdef CONFIG_REGULATOR
9b34e6cc
ZZ		 768static int ldo_regulator_is_enabled(struct regulator_dev *dev)
769{
770 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
771
772 return ldo->enabled;
773}
774
775static int ldo_regulator_enable(struct regulator_dev *dev)
776{
777 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
778 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
779 int reg;
780
781 if (ldo_regulator_is_enabled(dev))
782 return 0;
783
784 /* set regulator value firstly */
785 reg = (1600 - ldo->voltage / 1000) / 50;
786 reg = clamp(reg, 0x0, 0xf);
787
788 /* amend the voltage value, unit: uV */
789 ldo->voltage = (1600 - reg * 50) * 1000;
790
791 /* set voltage to register */
792 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 793 SGTL5000_LINREG_VDDD_MASK, reg);
9b34e6cc
ZZ		 794
795 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
796 SGTL5000_LINEREG_D_POWERUP,
797 SGTL5000_LINEREG_D_POWERUP);
798
7f6d75d7 799 /* when internal ldo is enabled, simple digital power can be disabled */
9b34e6cc
ZZ		 800 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
801 SGTL5000_LINREG_SIMPLE_POWERUP,
802 0);
803
804 ldo->enabled = 1;
805 return 0;
806}
807
808static int ldo_regulator_disable(struct regulator_dev *dev)
809{
810 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
811 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
812
813 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
814 SGTL5000_LINEREG_D_POWERUP,
815 0);
816
817 /* clear voltage info */
818 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 819 SGTL5000_LINREG_VDDD_MASK, 0);
9b34e6cc
ZZ		 820
821 ldo->enabled = 0;
822
823 return 0;
824}
825
826static int ldo_regulator_get_voltage(struct regulator_dev *dev)
827{
828 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
829
830 return ldo->voltage;
831}
832
833static struct regulator_ops ldo_regulator_ops = {
834 .is_enabled = ldo_regulator_is_enabled,
835 .enable = ldo_regulator_enable,
836 .disable = ldo_regulator_disable,
837 .get_voltage = ldo_regulator_get_voltage,
838};
839
840static int ldo_regulator_register(struct snd_soc_codec *codec,
841 struct regulator_init_data *init_data,
842 int voltage)
843{
844 struct ldo_regulator *ldo;
5b13de7a 845 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
c172708d 846 struct regulator_config config = { };
9b34e6cc
ZZ		 847
848 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
849
be813334 850 if (!ldo)
9b34e6cc 851 return -ENOMEM;
9b34e6cc
ZZ		 852
853 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
854 if (!ldo->desc.name) {
855 kfree(ldo);
856 dev_err(codec->dev, "failed to allocate decs name memory\n");
857 return -ENOMEM;
858 }
859
860 ldo->desc.type = REGULATOR_VOLTAGE;
861 ldo->desc.owner = THIS_MODULE;
862 ldo->desc.ops = &ldo_regulator_ops;
863 ldo->desc.n_voltages = 1;
864
865 ldo->codec_data = codec;
866 ldo->voltage = voltage;
867
c172708d
MB		 868 config.dev = codec->dev;
869 config.driver_data = ldo;
870 config.init_data = init_data;
871
872 ldo->dev = regulator_register(&ldo->desc, &config);
9b34e6cc 873 if (IS_ERR(ldo->dev)) {
62f75aaf
DC		 874 int ret = PTR_ERR(ldo->dev);
875
9b34e6cc
ZZ		 876 dev_err(codec->dev, "failed to register regulator\n");
877 kfree(ldo->desc.name);
878 kfree(ldo);
879
62f75aaf 880 return ret;
9b34e6cc 881 }
5b13de7a 882 sgtl5000->ldo = ldo;
9b34e6cc
ZZ		 883
884 return 0;
885}
886
887static int ldo_regulator_remove(struct snd_soc_codec *codec)
888{
889 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
890 struct ldo_regulator *ldo = sgtl5000->ldo;
891
892 if (!ldo)
893 return 0;
894
895 regulator_unregister(ldo->dev);
896 kfree(ldo->desc.name);
897 kfree(ldo);
898
899 return 0;
900}
333802e9
MB		 901#else
902static int ldo_regulator_register(struct snd_soc_codec *codec,
903 struct regulator_init_data *init_data,
904 int voltage)
905{
09bddc8e 906 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
333802e9
MB		 907 return -EINVAL;
908}
909
910static int ldo_regulator_remove(struct snd_soc_codec *codec)
911{
912 return 0;
913}
914#endif
9b34e6cc
ZZ		 915
916/*
917 * set dac bias
918 * common state changes:
919 * startup:
920 * off --> standby --> prepare --> on
921 * standby --> prepare --> on
922 *
923 * stop:
924 * on --> prepare --> standby
925 */
926static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
927 enum snd_soc_bias_level level)
928{
929 int ret;
930 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
931
932 switch (level) {
933 case SND_SOC_BIAS_ON:
934 case SND_SOC_BIAS_PREPARE:
935 break;
936 case SND_SOC_BIAS_STANDBY:
937 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
938 ret = regulator_bulk_enable(
939 ARRAY_SIZE(sgtl5000->supplies),
940 sgtl5000->supplies);
941 if (ret)
942 return ret;
943 udelay(10);
2bdc1bb2
MB		 944
945 regcache_cache_only(sgtl5000->regmap, false);
946
947 ret = regcache_sync(sgtl5000->regmap);
948 if (ret != 0) {
949 dev_err(codec->dev,
950 "Failed to restore cache: %d\n", ret);
951
952 regcache_cache_only(sgtl5000->regmap, true);
953 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
954 sgtl5000->supplies);
955
956 return ret;
957 }
9b34e6cc
ZZ		 958 }
959
960 break;
961 case SND_SOC_BIAS_OFF:
2bdc1bb2 962 regcache_cache_only(sgtl5000->regmap, true);
9b34e6cc
ZZ		 963 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
964 sgtl5000->supplies);
965 break;
966 }
967
968 codec->dapm.bias_level = level;
969 return 0;
970}
971
972#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
973 SNDRV_PCM_FMTBIT_S20_3LE |\
974 SNDRV_PCM_FMTBIT_S24_LE |\
975 SNDRV_PCM_FMTBIT_S32_LE)
976
85e7652d 977static const struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 978 .hw_params = sgtl5000_pcm_hw_params,
979 .digital_mute = sgtl5000_digital_mute,
980 .set_fmt = sgtl5000_set_dai_fmt,
981 .set_sysclk = sgtl5000_set_dai_sysclk,
982};
983
984static struct snd_soc_dai_driver sgtl5000_dai = {
985 .name = "sgtl5000",
986 .playback = {
987 .stream_name = "Playback",
988 .channels_min = 1,
989 .channels_max = 2,
990 /*
991 * only support 8~48K + 96K,
992 * TODO modify hw_param to support more
993 */
994 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
995 .formats = SGTL5000_FORMATS,
996 },
997 .capture = {
998 .stream_name = "Capture",
999 .channels_min = 1,
1000 .channels_max = 2,
1001 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1002 .formats = SGTL5000_FORMATS,
1003 },
1004 .ops = &sgtl5000_ops,
1005 .symmetric_rates = 1,
1006};
1007
e5d80e82 1008static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
9b34e6cc
ZZ		 1009{
1010 switch (reg) {
1011 case SGTL5000_CHIP_ID:
1012 case SGTL5000_CHIP_ADCDAC_CTRL:
1013 case SGTL5000_CHIP_ANA_STATUS:
e5d80e82 1014 return true;
9b34e6cc
ZZ		 1015 }
1016
e5d80e82
FE		 1017 return false;
1018}
1019
1020static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1021{
1022 switch (reg) {
1023 case SGTL5000_CHIP_ID:
1024 case SGTL5000_CHIP_DIG_POWER:
1025 case SGTL5000_CHIP_CLK_CTRL:
1026 case SGTL5000_CHIP_I2S_CTRL:
1027 case SGTL5000_CHIP_SSS_CTRL:
1028 case SGTL5000_CHIP_ADCDAC_CTRL:
1029 case SGTL5000_CHIP_DAC_VOL:
1030 case SGTL5000_CHIP_PAD_STRENGTH:
1031 case SGTL5000_CHIP_ANA_ADC_CTRL:
1032 case SGTL5000_CHIP_ANA_HP_CTRL:
1033 case SGTL5000_CHIP_ANA_CTRL:
1034 case SGTL5000_CHIP_LINREG_CTRL:
1035 case SGTL5000_CHIP_REF_CTRL:
1036 case SGTL5000_CHIP_MIC_CTRL:
1037 case SGTL5000_CHIP_LINE_OUT_CTRL:
1038 case SGTL5000_CHIP_LINE_OUT_VOL:
1039 case SGTL5000_CHIP_ANA_POWER:
1040 case SGTL5000_CHIP_PLL_CTRL:
1041 case SGTL5000_CHIP_CLK_TOP_CTRL:
1042 case SGTL5000_CHIP_ANA_STATUS:
1043 case SGTL5000_CHIP_SHORT_CTRL:
1044 case SGTL5000_CHIP_ANA_TEST2:
1045 case SGTL5000_DAP_CTRL:
1046 case SGTL5000_DAP_PEQ:
1047 case SGTL5000_DAP_BASS_ENHANCE:
1048 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1049 case SGTL5000_DAP_AUDIO_EQ:
1050 case SGTL5000_DAP_SURROUND:
1051 case SGTL5000_DAP_FLT_COEF_ACCESS:
1052 case SGTL5000_DAP_COEF_WR_B0_MSB:
1053 case SGTL5000_DAP_COEF_WR_B0_LSB:
1054 case SGTL5000_DAP_EQ_BASS_BAND0:
1055 case SGTL5000_DAP_EQ_BASS_BAND1:
1056 case SGTL5000_DAP_EQ_BASS_BAND2:
1057 case SGTL5000_DAP_EQ_BASS_BAND3:
1058 case SGTL5000_DAP_EQ_BASS_BAND4:
1059 case SGTL5000_DAP_MAIN_CHAN:
1060 case SGTL5000_DAP_MIX_CHAN:
1061 case SGTL5000_DAP_AVC_CTRL:
1062 case SGTL5000_DAP_AVC_THRESHOLD:
1063 case SGTL5000_DAP_AVC_ATTACK:
1064 case SGTL5000_DAP_AVC_DECAY:
1065 case SGTL5000_DAP_COEF_WR_B1_MSB:
1066 case SGTL5000_DAP_COEF_WR_B1_LSB:
1067 case SGTL5000_DAP_COEF_WR_B2_MSB:
1068 case SGTL5000_DAP_COEF_WR_B2_LSB:
1069 case SGTL5000_DAP_COEF_WR_A1_MSB:
1070 case SGTL5000_DAP_COEF_WR_A1_LSB:
1071 case SGTL5000_DAP_COEF_WR_A2_MSB:
1072 case SGTL5000_DAP_COEF_WR_A2_LSB:
1073 return true;
1074
1075 default:
1076 return false;
1077 }
9b34e6cc
ZZ		 1078}
1079
9b34e6cc
ZZ		 1080/*
1081 * sgtl5000 has 3 internal power supplies:
1082 * 1. VAG, normally set to vdda/2
7f6d75d7 1083 * 2. charge pump, set to different value
9b34e6cc
ZZ		 1084 * according to voltage of vdda and vddio
1085 * 3. line out VAG, normally set to vddio/2
1086 *
1087 * and should be set according to:
1088 * 1. vddd provided by external or not
1089 * 2. vdda and vddio voltage value. > 3.1v or not
1090 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1091 */
1092static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1093{
1094 int vddd;
1095 int vdda;
1096 int vddio;
1097 u16 ana_pwr;
1098 u16 lreg_ctrl;
1099 int vag;
1100 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1101
1102 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1103 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1104 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1105
1106 vdda = vdda / 1000;
1107 vddio = vddio / 1000;
1108 vddd = vddd / 1000;
1109
1110 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1111 dev_err(codec->dev, "regulator voltage not set correctly\n");
1112
1113 return -EINVAL;
1114 }
1115
1116 /* according to datasheet, maximum voltage of supplies */
1117 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1118 dev_err(codec->dev,
cf1ee98d 1119 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
9b34e6cc
ZZ		 1120 vdda, vddio, vddd);
1121
1122 return -EINVAL;
1123 }
1124
1125 /* reset value */
1126 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1127 ana_pwr |= SGTL5000_DAC_STEREO |
1128 SGTL5000_ADC_STEREO |
1129 SGTL5000_REFTOP_POWERUP;
1130 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1131
1132 if (vddio < 3100 && vdda < 3100) {
1133 /* enable internal oscillator used for charge pump */
1134 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1135 SGTL5000_INT_OSC_EN,
1136 SGTL5000_INT_OSC_EN);
1137 /* Enable VDDC charge pump */
1138 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1139 } else if (vddio >= 3100 && vdda >= 3100) {
1140 /*
1141 * if vddio and vddd > 3.1v,
1142 * charge pump should be clean before set ana_pwr
1143 */
1144 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1145 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1146
1147 /* VDDC use VDDIO rail */
1148 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1149 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1150 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1151 }
1152
1153 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1154
1155 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1156
1157 /* set voltage to register */
1158 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 1159 SGTL5000_LINREG_VDDD_MASK, 0x8);
9b34e6cc
ZZ		 1160
1161 /*
1162 * if vddd linear reg has been enabled,
1163 * simple digital supply should be clear to get
1164 * proper VDDD voltage.
1165 */
1166 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1167 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1168 SGTL5000_LINREG_SIMPLE_POWERUP,
1169 0);
1170 else
1171 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1172 SGTL5000_LINREG_SIMPLE_POWERUP |
1173 SGTL5000_STARTUP_POWERUP,
1174 0);
1175
1176 /*
1177 * set ADC/DAC VAG to vdda / 2,
1178 * should stay in range (0.8v, 1.575v)
1179 */
1180 vag = vdda / 2;
1181 if (vag <= SGTL5000_ANA_GND_BASE)
1182 vag = 0;
1183 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1184 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1185 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1186 else
1187 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1188
1189 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
33cb92cf 1190 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
9b34e6cc
ZZ		 1191
1192 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1193 vag = vddio / 2;
1194 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1195 vag = 0;
1196 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1197 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1198 vag = SGTL5000_LINE_OUT_GND_MAX;
1199 else
1200 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1201 SGTL5000_LINE_OUT_GND_STP;
1202
1203 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
33cb92cf
AL		 1204 SGTL5000_LINE_OUT_CURRENT_MASK |
1205 SGTL5000_LINE_OUT_GND_MASK,
9b34e6cc
ZZ		 1206 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1207 SGTL5000_LINE_OUT_CURRENT_360u <<
1208 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1209
1210 return 0;
1211}
1212
e94a4062
WS		 1213static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1214{
1215 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1216 int ret;
1217
1218 /* set internal ldo to 1.2v */
1219 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1220 if (ret) {
1221 dev_err(codec->dev,
1222 "Failed to register vddd internal supplies: %d\n", ret);
1223 return ret;
1224 }
1225
1226 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1227
e94a4062
WS		 1228 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1229 return 0;
1230}
1231
9b34e6cc
ZZ		 1232static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1233{
9b34e6cc 1234 int ret;
9b34e6cc
ZZ		 1235 int i;
1236 int external_vddd = 0;
1237 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
11db0da8 1238 struct regulator *vddd;
9b34e6cc
ZZ		 1239
1240 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1241 sgtl5000->supplies[i].supply = supply_names[i];
1242
11db0da8
SG		 1243 /* External VDDD only works before revision 0x11 */
1244 if (sgtl5000->revision < 0x11) {
1245 vddd = regulator_get_optional(codec->dev, "VDDD");
1246 if (IS_ERR(vddd)) {
1247 /* See if it's just not registered yet */
1248 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1249 return -EPROBE_DEFER;
1250 } else {
1251 external_vddd = 1;
1252 regulator_put(vddd);
1253 }
1254 }
1255
1256 if (!external_vddd) {
e94a4062
WS		 1257 ret = sgtl5000_replace_vddd_with_ldo(codec);
1258 if (ret)
9b34e6cc 1259 return ret;
9b34e6cc
ZZ		 1260 }
1261
e42be7e1 1262 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
11db0da8
SG		 1263 sgtl5000->supplies);
1264 if (ret)
1265 goto err_ldo_remove;
1266
9b34e6cc
ZZ		 1267 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1268 sgtl5000->supplies);
1269 if (ret)
e42be7e1 1270 goto err_regulator_free;
9b34e6cc
ZZ		 1271
1272 /* wait for all power rails bring up */
1273 udelay(10);
1274
9b34e6cc
ZZ		 1275 return 0;
1276
e42be7e1
FE		 1277err_regulator_free:
1278 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1279 sgtl5000->supplies);
11db0da8
SG		 1280err_ldo_remove:
1281 if (!external_vddd)
9b34e6cc
ZZ		 1282 ldo_regulator_remove(codec);
1283 return ret;
1284
1285}
1286
1287static int sgtl5000_probe(struct snd_soc_codec *codec)
1288{
1289 int ret;
1290 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1291
9b34e6cc
ZZ		 1292 ret = sgtl5000_enable_regulators(codec);
1293 if (ret)
1294 return ret;
1295
1296 /* power up sgtl5000 */
1297 ret = sgtl5000_set_power_regs(codec);
1298 if (ret)
1299 goto err;
1300
1301 /* enable small pop, introduce 400ms delay in turning off */
1302 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1303 SGTL5000_SMALL_POP,
1304 SGTL5000_SMALL_POP);
1305
1306 /* disable short cut detector */
1307 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1308
1309 /*
1310 * set i2s as default input of sound switch
1311 * TODO: add sound switch to control and dapm widge.
1312 */
1313 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1314 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1315 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1316 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1317
1318 /* enable dac volume ramp by default */
1319 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1320 SGTL5000_DAC_VOL_RAMP_EN |
1321 SGTL5000_DAC_MUTE_RIGHT |
1322 SGTL5000_DAC_MUTE_LEFT);
1323
1324 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1325
1326 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1327 SGTL5000_HP_ZCD_EN |
1328 SGTL5000_ADC_ZCD_EN);
1329
b50684da 1330 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2);
9b34e6cc
ZZ		 1331
1332 /*
1333 * disable DAP
1334 * TODO:
1335 * Enable DAP in kcontrol and dapm.
1336 */
1337 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1338
9b34e6cc
ZZ		 1339 return 0;
1340
1341err:
1342 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1343 sgtl5000->supplies);
e42be7e1
FE		 1344 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1345 sgtl5000->supplies);
9b34e6cc
ZZ		 1346 ldo_regulator_remove(codec);
1347
1348 return ret;
1349}
1350
1351static int sgtl5000_remove(struct snd_soc_codec *codec)
1352{
1353 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1354
9b34e6cc
ZZ		 1355 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1356 sgtl5000->supplies);
e42be7e1
FE		 1357 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1358 sgtl5000->supplies);
9b34e6cc
ZZ		 1359 ldo_regulator_remove(codec);
1360
1361 return 0;
1362}
1363
61a142b7 1364static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1365 .probe = sgtl5000_probe,
1366 .remove = sgtl5000_remove,
9b34e6cc 1367 .set_bias_level = sgtl5000_set_bias_level,
e649057a 1368 .suspend_bias_off = true,
89989637
FE		 1369 .controls = sgtl5000_snd_controls,
1370 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
5e0ac527
MB		 1371 .dapm_widgets = sgtl5000_dapm_widgets,
1372 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1373 .dapm_routes = sgtl5000_dapm_routes,
1374 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
9b34e6cc
ZZ		 1375};
1376
e5d80e82
FE		 1377static const struct regmap_config sgtl5000_regmap = {
1378 .reg_bits = 16,
1379 .val_bits = 16,
cb23e852 1380 .reg_stride = 2,
e5d80e82
FE		 1381
1382 .max_register = SGTL5000_MAX_REG_OFFSET,
1383 .volatile_reg = sgtl5000_volatile,
1384 .readable_reg = sgtl5000_readable,
1385
1386 .cache_type = REGCACHE_RBTREE,
1387 .reg_defaults = sgtl5000_reg_defaults,
1388 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1389};
1390
af8ee112
FE		 1391/*
1392 * Write all the default values from sgtl5000_reg_defaults[] array into the
1393 * sgtl5000 registers, to make sure we always start with the sane registers
1394 * values as stated in the datasheet.
1395 *
1396 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1397 * we follow this approach to guarantee we always start from the default values
1398 * and avoid problems like, not being able to probe after an audio playback
1399 * followed by a system reset or a 'reboot' command in Linux
1400 */
1401static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
1402{
1403 int i, ret, val, index;
1404
1405 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1406 val = sgtl5000_reg_defaults[i].def;
1407 index = sgtl5000_reg_defaults[i].reg;
1408 ret = regmap_write(sgtl5000->regmap, index, val);
1409 if (ret)
1410 return ret;
1411 }
1412
1413 return 0;
1414}
1415
7a79e94e
BP		 1416static int sgtl5000_i2c_probe(struct i2c_client *client,
1417 const struct i2c_device_id *id)
9b34e6cc
ZZ		 1418{
1419 struct sgtl5000_priv *sgtl5000;
b871f1ad 1420 int ret, reg, rev;
6f4d2b31 1421 unsigned int mclk;
9b34e6cc 1422
512fa7c4
FE		 1423 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
1424 GFP_KERNEL);
9b34e6cc
ZZ		 1425 if (!sgtl5000)
1426 return -ENOMEM;
1427
e5d80e82
FE		 1428 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1429 if (IS_ERR(sgtl5000->regmap)) {
1430 ret = PTR_ERR(sgtl5000->regmap);
1431 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1432 return ret;
1433 }
1434
9e13f345
FE		 1435 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1436 if (IS_ERR(sgtl5000->mclk)) {
1437 ret = PTR_ERR(sgtl5000->mclk);
1438 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
46a5905e
SG		 1439 /* Defer the probe to see if the clk will be provided later */
1440 if (ret == -ENOENT)
1441 return -EPROBE_DEFER;
9e13f345
FE		 1442 return ret;
1443 }
1444
6f4d2b31
FE		 1445 /* SGTL5000 SYS_MCLK should be between 8 and 27 MHz */
1446 mclk = clk_get_rate(sgtl5000->mclk);
1447 if (mclk < 8000000 || mclk > 27000000) {
1448 dev_err(&client->dev, "Invalid SYS_CLK frequency: %u.%03uMHz\n",
1449 mclk / 1000000, mclk / 1000 % 1000);
1450 return -EINVAL;
1451 }
1452
9e13f345
FE		 1453 ret = clk_prepare_enable(sgtl5000->mclk);
1454 if (ret)
1455 return ret;
1456
b871f1ad
FE		 1457 /* read chip information */
1458 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1459 if (ret)
9e13f345 1460 goto disable_clk;
b871f1ad
FE		 1461
1462 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1463 SGTL5000_PARTID_PART_ID) {
1464 dev_err(&client->dev,
1465 "Device with ID register %x is not a sgtl5000\n", reg);
9e13f345
FE		 1466 ret = -ENODEV;
1467 goto disable_clk;
b871f1ad
FE		 1468 }
1469
1470 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1471 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
252e91ff 1472 sgtl5000->revision = rev;
b871f1ad 1473
9b34e6cc
ZZ		 1474 i2c_set_clientdata(client, sgtl5000);
1475
af8ee112
FE		 1476 /* Ensure sgtl5000 will start with sane register values */
1477 ret = sgtl5000_fill_defaults(sgtl5000);
1478 if (ret)
9e13f345 1479 goto disable_clk;
af8ee112 1480
9b34e6cc
ZZ		 1481 ret = snd_soc_register_codec(&client->dev,
1482 &sgtl5000_driver, &sgtl5000_dai, 1);
9e13f345
FE		 1483 if (ret)
1484 goto disable_clk;
1485
1486 return 0;
1487
1488disable_clk:
1489 clk_disable_unprepare(sgtl5000->mclk);
512fa7c4 1490 return ret;
9b34e6cc
ZZ		 1491}
1492
7a79e94e 1493static int sgtl5000_i2c_remove(struct i2c_client *client)
9b34e6cc 1494{
7c647af4 1495 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc 1496
9e13f345
FE		 1497 snd_soc_unregister_codec(&client->dev);
1498 clk_disable_unprepare(sgtl5000->mclk);
9b34e6cc
ZZ		 1499 return 0;
1500}
1501
1502static const struct i2c_device_id sgtl5000_id[] = {
1503 {"sgtl5000", 0},
1504 {},
1505};
1506
1507MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1508
58e49424
SG		 1509static const struct of_device_id sgtl5000_dt_ids[] = {
1510 { .compatible = "fsl,sgtl5000", },
1511 { /* sentinel */ }
1512};
4c54c6de 1513MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1514
9b34e6cc
ZZ		 1515static struct i2c_driver sgtl5000_i2c_driver = {
1516 .driver = {
1517 .name = "sgtl5000",
1518 .owner = THIS_MODULE,
58e49424 1519 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1520 },
1521 .probe = sgtl5000_i2c_probe,
7a79e94e 1522 .remove = sgtl5000_i2c_remove,
9b34e6cc
ZZ		 1523 .id_table = sgtl5000_id,
1524};
1525
67d45090 1526module_i2c_driver(sgtl5000_i2c_driver);
9b34e6cc
ZZ		 1527
1528MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
f7cb8a4b 1529MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
9b34e6cc 1530MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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