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ASoC: sgtl5000: Do not disable regulators in SND_SOC_BIAS_OFF
[deliverable/linux.git] / sound / soc / codecs / sgtl5000.c
CommitLineData
9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
bd0593f5 19#include <linux/log2.h>
e5d80e82 20#include <linux/regmap.h>
9b34e6cc
ZZ		 21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/regulator/consumer.h>
58e49424 24#include <linux/of_device.h>
9b34e6cc
ZZ		 25#include <sound/core.h>
26#include <sound/tlv.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
9b34e6cc
ZZ		 32
33#include "sgtl5000.h"
34
35#define SGTL5000_DAP_REG_OFFSET 0x0100
36#define SGTL5000_MAX_REG_OFFSET 0x013A
37
151798f8 38/* default value of sgtl5000 registers */
e5d80e82 39static const struct reg_default sgtl5000_reg_defaults[] = {
29aa37cd 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
e5d80e82 41 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
016fcab8 42 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
29aa37cd 43 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
e5d80e82
FE		 44 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
45 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
29aa37cd 46 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
e5d80e82
FE		 47 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
48 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
29aa37cd
FE		 49 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
50 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
51 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
e5d80e82 52 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
e5d80e82 53 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
29aa37cd
FE		 54 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
55 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
56 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
57 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
58 { SGTL5000_DAP_CTRL, 0x0000 },
59 { SGTL5000_DAP_PEQ, 0x0000 },
e5d80e82
FE		 60 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
61 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
29aa37cd 62 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
e5d80e82
FE		 63 { SGTL5000_DAP_SURROUND, 0x0040 },
64 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
65 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
66 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
67 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
69 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
29aa37cd 70 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
e5d80e82
FE		 71 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
72 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
73 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
74 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
9b34e6cc
ZZ		 75};
76
77/* regulator supplies for sgtl5000, VDDD is an optional external supply */
78enum sgtl5000_regulator_supplies {
79 VDDA,
80 VDDIO,
81 VDDD,
82 SGTL5000_SUPPLY_NUM
83};
84
85/* vddd is optional supply */
86static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
87 "VDDA",
88 "VDDIO",
89 "VDDD"
90};
91
9b34e6cc 92#define LDO_VOLTAGE 1200000
3d632cc8 93#define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
9b34e6cc 94
bd0593f5
JMH		 95enum sgtl5000_micbias_resistor {
96 SGTL5000_MICBIAS_OFF = 0,
97 SGTL5000_MICBIAS_2K = 2,
98 SGTL5000_MICBIAS_4K = 4,
99 SGTL5000_MICBIAS_8K = 8,
100};
101
9b34e6cc
ZZ		 102/* sgtl5000 private structure in codec */
103struct sgtl5000_priv {
104 int sysclk; /* sysclk rate */
105 int master; /* i2s master or not */
106 int fmt; /* i2s data format */
107 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
940adb28 108 int num_supplies;
e5d80e82 109 struct regmap *regmap;
9e13f345 110 struct clk *mclk;
252e91ff 111 int revision;
bd0593f5 112 u8 micbias_resistor;
87357797 113 u8 micbias_voltage;
9b34e6cc
ZZ		 114};
115
116/*
117 * mic_bias power on/off share the same register bits with
118 * output impedance of mic bias, when power on mic bias, we
119 * need reclaim it to impedance value.
120 * 0x0 = Powered off
121 * 0x1 = 2Kohm
122 * 0x2 = 4Kohm
123 * 0x3 = 8Kohm
124 */
125static int mic_bias_event(struct snd_soc_dapm_widget *w,
126 struct snd_kcontrol *kcontrol, int event)
127{
73bffd17
LPC		 128 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
129 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
bd0593f5 130
9b34e6cc
ZZ		 131 switch (event) {
132 case SND_SOC_DAPM_POST_PMU:
bd0593f5 133 /* change mic bias resistor */
73bffd17 134 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
bd0593f5
JMH		 135 SGTL5000_BIAS_R_MASK,
136 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 137 break;
138
139 case SND_SOC_DAPM_PRE_PMD:
73bffd17 140 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 141 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 142 break;
143 }
144 return 0;
145}
146
147/*
f0cdcf3a
ZZ		 148 * As manual described, ADC/DAC only works when VAG powerup,
149 * So enabled VAG before ADC/DAC up.
150 * In power down case, we need wait 400ms when vag fully ramped down.
9b34e6cc 151 */
f0cdcf3a 152static int power_vag_event(struct snd_soc_dapm_widget *w,
9b34e6cc
ZZ		 153 struct snd_kcontrol *kcontrol, int event)
154{
73bffd17 155 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
f091f3f0
LW		 156 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
157
9b34e6cc 158 switch (event) {
dd4d2d6d 159 case SND_SOC_DAPM_POST_PMU:
73bffd17 160 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
9b34e6cc 161 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
c803cc2d 162 msleep(400);
9b34e6cc
ZZ		 163 break;
164
dd4d2d6d 165 case SND_SOC_DAPM_PRE_PMD:
f091f3f0
LW		 166 /*
167 * Don't clear VAG_POWERUP, when both DAC and ADC are
168 * operational to prevent inadvertently starving the
169 * other one of them.
170 */
73bffd17 171 if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) &
f091f3f0 172 mask) != mask) {
73bffd17 173 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
f091f3f0
LW		 174 SGTL5000_VAG_POWERUP, 0);
175 msleep(400);
176 }
9b34e6cc
ZZ		 177 break;
178 default:
179 break;
180 }
181
182 return 0;
183}
184
185/* input sources for ADC */
186static const char *adc_mux_text[] = {
187 "MIC_IN", "LINE_IN"
188};
189
c8ed6504
TI		 190static SOC_ENUM_SINGLE_DECL(adc_enum,
191 SGTL5000_CHIP_ANA_CTRL, 2,
192 adc_mux_text);
9b34e6cc
ZZ		 193
194static const struct snd_kcontrol_new adc_mux =
195SOC_DAPM_ENUM("Capture Mux", adc_enum);
196
197/* input sources for DAC */
198static const char *dac_mux_text[] = {
199 "DAC", "LINE_IN"
200};
201
c8ed6504
TI		 202static SOC_ENUM_SINGLE_DECL(dac_enum,
203 SGTL5000_CHIP_ANA_CTRL, 6,
204 dac_mux_text);
9b34e6cc
ZZ		 205
206static const struct snd_kcontrol_new dac_mux =
207SOC_DAPM_ENUM("Headphone Mux", dac_enum);
208
209static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
210 SND_SOC_DAPM_INPUT("LINE_IN"),
211 SND_SOC_DAPM_INPUT("MIC_IN"),
212
213 SND_SOC_DAPM_OUTPUT("HP_OUT"),
214 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
215
8fc8ec92
MB		 216 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
217 mic_bias_event,
218 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9b34e6cc 219
f0cdcf3a
ZZ		 220 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
221 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
9b34e6cc
ZZ		 222
223 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
224 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
225
226 /* aif for i2s input */
227 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
228 0, SGTL5000_CHIP_DIG_POWER,
229 0, 0),
230
231 /* aif for i2s output */
232 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
233 0, SGTL5000_CHIP_DIG_POWER,
234 1, 0),
235
f0cdcf3a 236 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
9b34e6cc 237 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
dd4d2d6d
MV		 238
239 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
240 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
9b34e6cc
ZZ		 241};
242
243/* routes for sgtl5000 */
89989637 244static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
9b34e6cc
ZZ		 245 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
246 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
247
248 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
249 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
250
251 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
252 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
253 {"LO", NULL, "DAC"}, /* dac --> line_out */
254
255 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
256 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
257
258 {"LINE_OUT", NULL, "LO"},
259 {"HP_OUT", NULL, "HP"},
260};
261
262/* custom function to fetch info of PCM playback volume */
263static int dac_info_volsw(struct snd_kcontrol *kcontrol,
264 struct snd_ctl_elem_info *uinfo)
265{
266 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
267 uinfo->count = 2;
268 uinfo->value.integer.min = 0;
269 uinfo->value.integer.max = 0xfc - 0x3c;
270 return 0;
271}
272
273/*
274 * custom function to get of PCM playback volume
275 *
276 * dac volume register
277 * 15-------------8-7--------------0
278 * | R channel vol | L channel vol |
279 * -------------------------------
280 *
281 * PCM volume with 0.5017 dB steps from 0 to -90 dB
282 *
283 * register values map to dB
284 * 0x3B and less = Reserved
285 * 0x3C = 0 dB
286 * 0x3D = -0.5 dB
287 * 0xF0 = -90 dB
288 * 0xFC and greater = Muted
289 *
290 * register value map to userspace value
291 *
292 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
293 * ------------------------------
294 * userspace value 0xc0 0
295 */
296static int dac_get_volsw(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
298{
ea53bf77 299 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 300 int reg;
301 int l;
302 int r;
303
304 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
305
306 /* get left channel volume */
307 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
308
309 /* get right channel volume */
310 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
311
312 /* make sure value fall in (0x3c,0xfc) */
313 l = clamp(l, 0x3c, 0xfc);
314 r = clamp(r, 0x3c, 0xfc);
315
316 /* invert it and map to userspace value */
317 l = 0xfc - l;
318 r = 0xfc - r;
319
320 ucontrol->value.integer.value[0] = l;
321 ucontrol->value.integer.value[1] = r;
322
323 return 0;
324}
325
326/*
327 * custom function to put of PCM playback volume
328 *
329 * dac volume register
330 * 15-------------8-7--------------0
331 * | R channel vol | L channel vol |
332 * -------------------------------
333 *
334 * PCM volume with 0.5017 dB steps from 0 to -90 dB
335 *
336 * register values map to dB
337 * 0x3B and less = Reserved
338 * 0x3C = 0 dB
339 * 0x3D = -0.5 dB
340 * 0xF0 = -90 dB
341 * 0xFC and greater = Muted
342 *
343 * userspace value map to register value
344 *
345 * userspace value 0xc0 0
346 * ------------------------------
347 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
348 */
349static int dac_put_volsw(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol)
351{
ea53bf77 352 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 353 int reg;
354 int l;
355 int r;
356
357 l = ucontrol->value.integer.value[0];
358 r = ucontrol->value.integer.value[1];
359
360 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
361 l = clamp(l, 0, 0xfc - 0x3c);
362 r = clamp(r, 0, 0xfc - 0x3c);
363
364 /* invert it, get the value can be set to register */
365 l = 0xfc - l;
366 r = 0xfc - r;
367
368 /* shift to get the register value */
369 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
370 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
371
372 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
373
374 return 0;
375}
376
377static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
378
379/* tlv for mic gain, 0db 20db 30db 40db */
53eb1ca3 380static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
9b34e6cc 381 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
53eb1ca3
LPC		 382 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
383);
9b34e6cc
ZZ		 384
385/* tlv for hp volume, -51.5db to 12.0db, step .5db */
386static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
387
388static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
389 /* SOC_DOUBLE_S8_TLV with invert */
390 {
391 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
392 .name = "PCM Playback Volume",
393 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
394 SNDRV_CTL_ELEM_ACCESS_READWRITE,
395 .info = dac_info_volsw,
396 .get = dac_get_volsw,
397 .put = dac_put_volsw,
398 },
399
400 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
401 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
402 SGTL5000_CHIP_ANA_ADC_CTRL,
65f2b226 403 8, 1, 0, capture_6db_attenuate),
9b34e6cc
ZZ		 404 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
405
406 SOC_DOUBLE_TLV("Headphone Playback Volume",
407 SGTL5000_CHIP_ANA_HP_CTRL,
408 0, 8,
409 0x7f, 1,
410 headphone_volume),
411 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
412 5, 1, 0),
413
414 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
b50684da 415 0, 3, 0, mic_gain_tlv),
9b34e6cc
ZZ		 416};
417
418/* mute the codec used by alsa core */
419static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
420{
421 struct snd_soc_codec *codec = codec_dai->codec;
422 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
423
424 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
425 adcdac_ctrl, mute ? adcdac_ctrl : 0);
426
427 return 0;
428}
429
430/* set codec format */
431static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
432{
433 struct snd_soc_codec *codec = codec_dai->codec;
434 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
435 u16 i2sctl = 0;
436
437 sgtl5000->master = 0;
438 /*
439 * i2s clock and frame master setting.
440 * ONLY support:
441 * - clock and frame slave,
442 * - clock and frame master
443 */
444 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
445 case SND_SOC_DAIFMT_CBS_CFS:
446 break;
447 case SND_SOC_DAIFMT_CBM_CFM:
448 i2sctl |= SGTL5000_I2S_MASTER;
449 sgtl5000->master = 1;
450 break;
451 default:
452 return -EINVAL;
453 }
454
455 /* setting i2s data format */
456 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
457 case SND_SOC_DAIFMT_DSP_A:
9ee802ec 458 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 459 break;
460 case SND_SOC_DAIFMT_DSP_B:
9ee802ec 461 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 462 i2sctl |= SGTL5000_I2S_LRALIGN;
463 break;
464 case SND_SOC_DAIFMT_I2S:
9ee802ec 465 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 466 break;
467 case SND_SOC_DAIFMT_RIGHT_J:
9ee802ec 468 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 469 i2sctl |= SGTL5000_I2S_LRPOL;
470 break;
471 case SND_SOC_DAIFMT_LEFT_J:
9ee802ec 472 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 473 i2sctl |= SGTL5000_I2S_LRALIGN;
474 break;
475 default:
476 return -EINVAL;
477 }
478
479 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
480
481 /* Clock inversion */
482 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
483 case SND_SOC_DAIFMT_NB_NF:
484 break;
485 case SND_SOC_DAIFMT_IB_NF:
486 i2sctl |= SGTL5000_I2S_SCLK_INV;
487 break;
488 default:
489 return -EINVAL;
490 }
491
492 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
493
494 return 0;
495}
496
497/* set codec sysclk */
498static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
499 int clk_id, unsigned int freq, int dir)
500{
501 struct snd_soc_codec *codec = codec_dai->codec;
502 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
503
504 switch (clk_id) {
505 case SGTL5000_SYSCLK:
506 sgtl5000->sysclk = freq;
507 break;
508 default:
509 return -EINVAL;
510 }
511
512 return 0;
513}
514
515/*
516 * set clock according to i2s frame clock,
7f6d75d7
FE		 517 * sgtl5000 provides 2 clock sources:
518 * 1. sys_mclk: sample freq can only be configured to
9b34e6cc 519 * 1/256, 1/384, 1/512 of sys_mclk.
7f6d75d7 520 * 2. pll: can derive any audio clocks.
9b34e6cc
ZZ		 521 *
522 * clock setting rules:
7f6d75d7
FE		 523 * 1. in slave mode, only sys_mclk can be used
524 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
525 * and above.
526 * 3. usage of sys_mclk is preferred over pll to save power.
9b34e6cc
ZZ		 527 */
528static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
529{
530 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
531 int clk_ctl = 0;
532 int sys_fs; /* sample freq */
533
534 /*
535 * sample freq should be divided by frame clock,
7f6d75d7
FE		 536 * if frame clock is lower than 44.1 kHz, sample freq should be set to
537 * 32 kHz or 44.1 kHz.
9b34e6cc
ZZ		 538 */
539 switch (frame_rate) {
540 case 8000:
541 case 16000:
542 sys_fs = 32000;
543 break;
544 case 11025:
545 case 22050:
546 sys_fs = 44100;
547 break;
548 default:
549 sys_fs = frame_rate;
550 break;
551 }
552
553 /* set divided factor of frame clock */
554 switch (sys_fs / frame_rate) {
555 case 4:
556 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
557 break;
558 case 2:
559 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
560 break;
561 case 1:
562 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
563 break;
564 default:
565 return -EINVAL;
566 }
567
568 /* set the sys_fs according to frame rate */
569 switch (sys_fs) {
570 case 32000:
571 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
572 break;
573 case 44100:
574 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
575 break;
576 case 48000:
577 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
578 break;
579 case 96000:
580 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
581 break;
582 default:
583 dev_err(codec->dev, "frame rate %d not supported\n",
584 frame_rate);
585 return -EINVAL;
586 }
587
588 /*
589 * calculate the divider of mclk/sample_freq,
7f6d75d7
FE		 590 * factor of freq = 96 kHz can only be 256, since mclk is in the range
591 * of 8 MHz - 27 MHz
9b34e6cc 592 */
2a4cfd10 593 switch (sgtl5000->sysclk / frame_rate) {
9b34e6cc
ZZ		 594 case 256:
595 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
596 SGTL5000_MCLK_FREQ_SHIFT;
597 break;
598 case 384:
599 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
600 SGTL5000_MCLK_FREQ_SHIFT;
601 break;
602 case 512:
603 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
604 SGTL5000_MCLK_FREQ_SHIFT;
605 break;
606 default:
7f6d75d7 607 /* if mclk does not satisfy the divider, use pll */
9b34e6cc
ZZ		 608 if (sgtl5000->master) {
609 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
610 SGTL5000_MCLK_FREQ_SHIFT;
611 } else {
612 dev_err(codec->dev,
613 "PLL not supported in slave mode\n");
fa558d01
FE		 614 dev_err(codec->dev, "%d ratio is not supported. "
615 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
2a4cfd10 616 sgtl5000->sysclk / frame_rate);
9b34e6cc
ZZ		 617 return -EINVAL;
618 }
619 }
620
621 /* if using pll, please check manual 6.4.2 for detail */
622 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
623 u64 out, t;
624 int div2;
625 int pll_ctl;
626 unsigned int in, int_div, frac_div;
627
628 if (sgtl5000->sysclk > 17000000) {
629 div2 = 1;
630 in = sgtl5000->sysclk / 2;
631 } else {
632 div2 = 0;
633 in = sgtl5000->sysclk;
634 }
635 if (sys_fs == 44100)
636 out = 180633600;
637 else
638 out = 196608000;
639 t = do_div(out, in);
640 int_div = out;
641 t *= 2048;
642 do_div(t, in);
643 frac_div = t;
644 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
645 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
646
647 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
648 if (div2)
649 snd_soc_update_bits(codec,
650 SGTL5000_CHIP_CLK_TOP_CTRL,
651 SGTL5000_INPUT_FREQ_DIV2,
652 SGTL5000_INPUT_FREQ_DIV2);
653 else
654 snd_soc_update_bits(codec,
655 SGTL5000_CHIP_CLK_TOP_CTRL,
656 SGTL5000_INPUT_FREQ_DIV2,
657 0);
658
659 /* power up pll */
660 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
661 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
662 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
e06e4c2d
OS		 663
664 /* if using pll, clk_ctrl must be set after pll power up */
665 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
9b34e6cc 666 } else {
e06e4c2d
OS		 667 /* otherwise, clk_ctrl must be set before pll power down */
668 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
669
9b34e6cc
ZZ		 670 /* power down pll */
671 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
672 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
673 0);
674 }
675
9b34e6cc
ZZ		 676 return 0;
677}
678
679/*
680 * Set PCM DAI bit size and sample rate.
681 * input: params_rate, params_fmt
682 */
683static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
684 struct snd_pcm_hw_params *params,
685 struct snd_soc_dai *dai)
686{
e6968a17 687 struct snd_soc_codec *codec = dai->codec;
9b34e6cc
ZZ		 688 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
689 int channels = params_channels(params);
690 int i2s_ctl = 0;
691 int stereo;
692 int ret;
693
694 /* sysclk should already set */
695 if (!sgtl5000->sysclk) {
696 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
697 return -EFAULT;
698 }
699
700 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
701 stereo = SGTL5000_DAC_STEREO;
702 else
703 stereo = SGTL5000_ADC_STEREO;
704
705 /* set mono to save power */
706 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
707 channels == 1 ? 0 : stereo);
708
709 /* set codec clock base on lrclk */
710 ret = sgtl5000_set_clock(codec, params_rate(params));
711 if (ret)
712 return ret;
713
714 /* set i2s data format */
dacc2aef
MB		 715 switch (params_width(params)) {
716 case 16:
9b34e6cc
ZZ		 717 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
718 return -EINVAL;
719 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
720 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
721 SGTL5000_I2S_SCLKFREQ_SHIFT;
722 break;
dacc2aef 723 case 20:
9b34e6cc
ZZ		 724 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
725 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
726 SGTL5000_I2S_SCLKFREQ_SHIFT;
727 break;
dacc2aef 728 case 24:
9b34e6cc
ZZ		 729 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
730 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
731 SGTL5000_I2S_SCLKFREQ_SHIFT;
732 break;
dacc2aef 733 case 32:
9b34e6cc
ZZ		 734 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
735 return -EINVAL;
736 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
737 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
738 SGTL5000_I2S_SCLKFREQ_SHIFT;
739 break;
740 default:
741 return -EINVAL;
742 }
743
33cb92cf
AL		 744 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
745 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
746 i2s_ctl);
9b34e6cc
ZZ		 747
748 return 0;
749}
750
9b34e6cc
ZZ		 751/*
752 * set dac bias
753 * common state changes:
754 * startup:
755 * off --> standby --> prepare --> on
756 * standby --> prepare --> on
757 *
758 * stop:
759 * on --> prepare --> standby
760 */
761static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
762 enum snd_soc_bias_level level)
763{
9b34e6cc
ZZ		 764 switch (level) {
765 case SND_SOC_BIAS_ON:
766 case SND_SOC_BIAS_PREPARE:
9b34e6cc 767 case SND_SOC_BIAS_STANDBY:
8419caa7
EN		 768 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
769 SGTL5000_REFTOP_POWERUP,
770 SGTL5000_REFTOP_POWERUP);
9b34e6cc
ZZ		 771 break;
772 case SND_SOC_BIAS_OFF:
8419caa7
EN		 773 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
774 SGTL5000_REFTOP_POWERUP, 0);
9b34e6cc
ZZ		 775 break;
776 }
777
9b34e6cc
ZZ		 778 return 0;
779}
780
781#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
782 SNDRV_PCM_FMTBIT_S20_3LE |\
783 SNDRV_PCM_FMTBIT_S24_LE |\
784 SNDRV_PCM_FMTBIT_S32_LE)
785
85e7652d 786static const struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 787 .hw_params = sgtl5000_pcm_hw_params,
788 .digital_mute = sgtl5000_digital_mute,
789 .set_fmt = sgtl5000_set_dai_fmt,
790 .set_sysclk = sgtl5000_set_dai_sysclk,
791};
792
793static struct snd_soc_dai_driver sgtl5000_dai = {
794 .name = "sgtl5000",
795 .playback = {
796 .stream_name = "Playback",
797 .channels_min = 1,
798 .channels_max = 2,
799 /*
800 * only support 8~48K + 96K,
801 * TODO modify hw_param to support more
802 */
803 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
804 .formats = SGTL5000_FORMATS,
805 },
806 .capture = {
807 .stream_name = "Capture",
808 .channels_min = 1,
809 .channels_max = 2,
810 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
811 .formats = SGTL5000_FORMATS,
812 },
813 .ops = &sgtl5000_ops,
814 .symmetric_rates = 1,
815};
816
e5d80e82 817static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
9b34e6cc
ZZ		 818{
819 switch (reg) {
820 case SGTL5000_CHIP_ID:
821 case SGTL5000_CHIP_ADCDAC_CTRL:
822 case SGTL5000_CHIP_ANA_STATUS:
e5d80e82 823 return true;
9b34e6cc
ZZ		 824 }
825
e5d80e82
FE		 826 return false;
827}
828
829static bool sgtl5000_readable(struct device *dev, unsigned int reg)
830{
831 switch (reg) {
832 case SGTL5000_CHIP_ID:
833 case SGTL5000_CHIP_DIG_POWER:
834 case SGTL5000_CHIP_CLK_CTRL:
835 case SGTL5000_CHIP_I2S_CTRL:
836 case SGTL5000_CHIP_SSS_CTRL:
837 case SGTL5000_CHIP_ADCDAC_CTRL:
838 case SGTL5000_CHIP_DAC_VOL:
839 case SGTL5000_CHIP_PAD_STRENGTH:
840 case SGTL5000_CHIP_ANA_ADC_CTRL:
841 case SGTL5000_CHIP_ANA_HP_CTRL:
842 case SGTL5000_CHIP_ANA_CTRL:
843 case SGTL5000_CHIP_LINREG_CTRL:
844 case SGTL5000_CHIP_REF_CTRL:
845 case SGTL5000_CHIP_MIC_CTRL:
846 case SGTL5000_CHIP_LINE_OUT_CTRL:
847 case SGTL5000_CHIP_LINE_OUT_VOL:
848 case SGTL5000_CHIP_ANA_POWER:
849 case SGTL5000_CHIP_PLL_CTRL:
850 case SGTL5000_CHIP_CLK_TOP_CTRL:
851 case SGTL5000_CHIP_ANA_STATUS:
852 case SGTL5000_CHIP_SHORT_CTRL:
853 case SGTL5000_CHIP_ANA_TEST2:
854 case SGTL5000_DAP_CTRL:
855 case SGTL5000_DAP_PEQ:
856 case SGTL5000_DAP_BASS_ENHANCE:
857 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
858 case SGTL5000_DAP_AUDIO_EQ:
859 case SGTL5000_DAP_SURROUND:
860 case SGTL5000_DAP_FLT_COEF_ACCESS:
861 case SGTL5000_DAP_COEF_WR_B0_MSB:
862 case SGTL5000_DAP_COEF_WR_B0_LSB:
863 case SGTL5000_DAP_EQ_BASS_BAND0:
864 case SGTL5000_DAP_EQ_BASS_BAND1:
865 case SGTL5000_DAP_EQ_BASS_BAND2:
866 case SGTL5000_DAP_EQ_BASS_BAND3:
867 case SGTL5000_DAP_EQ_BASS_BAND4:
868 case SGTL5000_DAP_MAIN_CHAN:
869 case SGTL5000_DAP_MIX_CHAN:
870 case SGTL5000_DAP_AVC_CTRL:
871 case SGTL5000_DAP_AVC_THRESHOLD:
872 case SGTL5000_DAP_AVC_ATTACK:
873 case SGTL5000_DAP_AVC_DECAY:
874 case SGTL5000_DAP_COEF_WR_B1_MSB:
875 case SGTL5000_DAP_COEF_WR_B1_LSB:
876 case SGTL5000_DAP_COEF_WR_B2_MSB:
877 case SGTL5000_DAP_COEF_WR_B2_LSB:
878 case SGTL5000_DAP_COEF_WR_A1_MSB:
879 case SGTL5000_DAP_COEF_WR_A1_LSB:
880 case SGTL5000_DAP_COEF_WR_A2_MSB:
881 case SGTL5000_DAP_COEF_WR_A2_LSB:
882 return true;
883
884 default:
885 return false;
886 }
9b34e6cc
ZZ		 887}
888
1f39d939
AS		 889/*
890 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
891 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
892 * The calculatation was done for all possible register values which
893 * is the array index and the following formula: 10^((idx−15)/40) * 100
894 */
895static const u8 vol_quot_table[] = {
896 42, 45, 47, 50, 53, 56, 60, 63,
897 67, 71, 75, 79, 84, 89, 94, 100,
898 106, 112, 119, 126, 133, 141, 150, 158,
899 168, 178, 188, 200, 211, 224, 237, 251
900};
901
9b34e6cc
ZZ		 902/*
903 * sgtl5000 has 3 internal power supplies:
904 * 1. VAG, normally set to vdda/2
7f6d75d7 905 * 2. charge pump, set to different value
9b34e6cc
ZZ		 906 * according to voltage of vdda and vddio
907 * 3. line out VAG, normally set to vddio/2
908 *
909 * and should be set according to:
910 * 1. vddd provided by external or not
911 * 2. vdda and vddio voltage value. > 3.1v or not
9b34e6cc
ZZ		 912 */
913static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
914{
915 int vddd;
916 int vdda;
917 int vddio;
918 u16 ana_pwr;
919 u16 lreg_ctrl;
920 int vag;
d2b7c2aa 921 int lo_vag;
1f39d939
AS		 922 int vol_quot;
923 int lo_vol;
924 size_t i;
9b34e6cc
ZZ		 925 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
926
927 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
928 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
940adb28
EN		 929 vddd = (sgtl5000->num_supplies > VDDD)
930 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
931 : LDO_VOLTAGE;
9b34e6cc
ZZ		 932
933 vdda = vdda / 1000;
934 vddio = vddio / 1000;
935 vddd = vddd / 1000;
936
937 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
938 dev_err(codec->dev, "regulator voltage not set correctly\n");
939
940 return -EINVAL;
941 }
942
943 /* according to datasheet, maximum voltage of supplies */
944 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
945 dev_err(codec->dev,
cf1ee98d 946 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
9b34e6cc
ZZ		 947 vdda, vddio, vddd);
948
949 return -EINVAL;
950 }
951
952 /* reset value */
953 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
954 ana_pwr |= SGTL5000_DAC_STEREO |
955 SGTL5000_ADC_STEREO |
956 SGTL5000_REFTOP_POWERUP;
957 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
958
959 if (vddio < 3100 && vdda < 3100) {
960 /* enable internal oscillator used for charge pump */
961 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
962 SGTL5000_INT_OSC_EN,
963 SGTL5000_INT_OSC_EN);
964 /* Enable VDDC charge pump */
965 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
966 } else if (vddio >= 3100 && vdda >= 3100) {
c7d910b8 967 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
9b34e6cc
ZZ		 968 /* VDDC use VDDIO rail */
969 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
970 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
971 SGTL5000_VDDC_MAN_ASSN_SHIFT;
972 }
973
974 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
975
976 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
977
9b34e6cc
ZZ		 978 /*
979 * set ADC/DAC VAG to vdda / 2,
980 * should stay in range (0.8v, 1.575v)
981 */
982 vag = vdda / 2;
983 if (vag <= SGTL5000_ANA_GND_BASE)
984 vag = 0;
985 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
986 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
987 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
988 else
989 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
990
991 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
33cb92cf 992 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
9b34e6cc
ZZ		 993
994 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
d2b7c2aa
AS		 995 lo_vag = vddio / 2;
996 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
997 lo_vag = 0;
998 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
9b34e6cc 999 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
d2b7c2aa 1000 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
9b34e6cc 1001 else
d2b7c2aa 1002 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
9b34e6cc
ZZ		 1003 SGTL5000_LINE_OUT_GND_STP;
1004
1005 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
33cb92cf
AL		 1006 SGTL5000_LINE_OUT_CURRENT_MASK |
1007 SGTL5000_LINE_OUT_GND_MASK,
d2b7c2aa 1008 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
9b34e6cc
ZZ		 1009 SGTL5000_LINE_OUT_CURRENT_360u <<
1010 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1011
1f39d939
AS		 1012 /*
1013 * Set lineout output level in range (0..31)
1014 * the same value is used for right and left channel
1015 *
1016 * Searching for a suitable index solving this formula:
1017 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1018 */
1019 vol_quot = (vag * 100) / lo_vag;
1020 lo_vol = 0;
1021 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1022 if (vol_quot >= vol_quot_table[i])
1023 lo_vol = i;
1024 else
1025 break;
1026 }
1027
1028 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1029 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1030 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1031 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1032 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1033
9b34e6cc
ZZ		 1034 return 0;
1035}
1036
940adb28 1037static int sgtl5000_enable_regulators(struct i2c_client *client)
9b34e6cc 1038{
9b34e6cc 1039 int ret;
9b34e6cc
ZZ		 1040 int i;
1041 int external_vddd = 0;
11db0da8 1042 struct regulator *vddd;
940adb28 1043 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc
ZZ		 1044
1045 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1046 sgtl5000->supplies[i].supply = supply_names[i];
1047
940adb28
EN		 1048 vddd = regulator_get_optional(&client->dev, "VDDD");
1049 if (IS_ERR(vddd)) {
1050 /* See if it's just not registered yet */
1051 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1052 return -EPROBE_DEFER;
1053 } else {
1054 external_vddd = 1;
1055 regulator_put(vddd);
9b34e6cc
ZZ		 1056 }
1057
940adb28
EN		 1058 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1059 - 1 + external_vddd;
1060 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
11db0da8
SG		 1061 sgtl5000->supplies);
1062 if (ret)
940adb28 1063 return ret;
9b34e6cc 1064
940adb28
EN		 1065 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1066 sgtl5000->supplies);
1067 if (!ret)
1068 usleep_range(10, 20);
1069 else
1070 regulator_bulk_free(sgtl5000->num_supplies,
1071 sgtl5000->supplies);
9b34e6cc 1072
9b34e6cc 1073 return ret;
9b34e6cc
ZZ		 1074}
1075
1076static int sgtl5000_probe(struct snd_soc_codec *codec)
1077{
1078 int ret;
1079 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1080
9b34e6cc
ZZ		 1081 /* power up sgtl5000 */
1082 ret = sgtl5000_set_power_regs(codec);
1083 if (ret)
1084 goto err;
1085
1086 /* enable small pop, introduce 400ms delay in turning off */
1087 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
c251ea7b 1088 SGTL5000_SMALL_POP, 1);
9b34e6cc
ZZ		 1089
1090 /* disable short cut detector */
1091 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1092
1093 /*
1094 * set i2s as default input of sound switch
1095 * TODO: add sound switch to control and dapm widge.
1096 */
1097 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1098 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1099 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1100 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1101
1102 /* enable dac volume ramp by default */
1103 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1104 SGTL5000_DAC_VOL_RAMP_EN |
1105 SGTL5000_DAC_MUTE_RIGHT |
1106 SGTL5000_DAC_MUTE_LEFT);
1107
1108 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1109
1110 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1111 SGTL5000_HP_ZCD_EN |
1112 SGTL5000_ADC_ZCD_EN);
1113
bd0593f5
JMH		 1114 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1115 SGTL5000_BIAS_R_MASK,
1116 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc 1117
87357797 1118 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
e256da84
GR		 1119 SGTL5000_BIAS_VOLT_MASK,
1120 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
9b34e6cc
ZZ		 1121 /*
1122 * disable DAP
1123 * TODO:
1124 * Enable DAP in kcontrol and dapm.
1125 */
1126 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1127
9b34e6cc
ZZ		 1128 return 0;
1129
1130err:
9b34e6cc
ZZ		 1131 return ret;
1132}
1133
1134static int sgtl5000_remove(struct snd_soc_codec *codec)
1135{
9b34e6cc
ZZ		 1136 return 0;
1137}
1138
61a142b7 1139static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1140 .probe = sgtl5000_probe,
1141 .remove = sgtl5000_remove,
9b34e6cc 1142 .set_bias_level = sgtl5000_set_bias_level,
e649057a 1143 .suspend_bias_off = true,
89989637
FE		 1144 .controls = sgtl5000_snd_controls,
1145 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
5e0ac527
MB		 1146 .dapm_widgets = sgtl5000_dapm_widgets,
1147 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1148 .dapm_routes = sgtl5000_dapm_routes,
1149 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
9b34e6cc
ZZ		 1150};
1151
e5d80e82
FE		 1152static const struct regmap_config sgtl5000_regmap = {
1153 .reg_bits = 16,
1154 .val_bits = 16,
cb23e852 1155 .reg_stride = 2,
e5d80e82
FE		 1156
1157 .max_register = SGTL5000_MAX_REG_OFFSET,
1158 .volatile_reg = sgtl5000_volatile,
1159 .readable_reg = sgtl5000_readable,
1160
1161 .cache_type = REGCACHE_RBTREE,
1162 .reg_defaults = sgtl5000_reg_defaults,
1163 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1164};
1165
af8ee112
FE		 1166/*
1167 * Write all the default values from sgtl5000_reg_defaults[] array into the
1168 * sgtl5000 registers, to make sure we always start with the sane registers
1169 * values as stated in the datasheet.
1170 *
1171 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1172 * we follow this approach to guarantee we always start from the default values
1173 * and avoid problems like, not being able to probe after an audio playback
1174 * followed by a system reset or a 'reboot' command in Linux
1175 */
f219b169 1176static void sgtl5000_fill_defaults(struct i2c_client *client)
af8ee112 1177{
f219b169 1178 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
af8ee112
FE		 1179 int i, ret, val, index;
1180
1181 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1182 val = sgtl5000_reg_defaults[i].def;
1183 index = sgtl5000_reg_defaults[i].reg;
1184 ret = regmap_write(sgtl5000->regmap, index, val);
1185 if (ret)
f219b169
EN		 1186 dev_err(&client->dev,
1187 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1188 __func__, ret, index, val);
af8ee112 1189 }
af8ee112
FE		 1190}
1191
7a79e94e
BP		 1192static int sgtl5000_i2c_probe(struct i2c_client *client,
1193 const struct i2c_device_id *id)
9b34e6cc
ZZ		 1194{
1195 struct sgtl5000_priv *sgtl5000;
b871f1ad 1196 int ret, reg, rev;
bd0593f5
JMH		 1197 struct device_node *np = client->dev.of_node;
1198 u32 value;
3d632cc8 1199 u16 ana_pwr;
9b34e6cc 1200
3f7256fe 1201 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
9b34e6cc
ZZ		 1202 if (!sgtl5000)
1203 return -ENOMEM;
1204
940adb28
EN		 1205 i2c_set_clientdata(client, sgtl5000);
1206
1207 ret = sgtl5000_enable_regulators(client);
1208 if (ret)
1209 return ret;
1210
e5d80e82
FE		 1211 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1212 if (IS_ERR(sgtl5000->regmap)) {
1213 ret = PTR_ERR(sgtl5000->regmap);
1214 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
940adb28 1215 goto disable_regs;
e5d80e82
FE		 1216 }
1217
9e13f345
FE		 1218 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1219 if (IS_ERR(sgtl5000->mclk)) {
1220 ret = PTR_ERR(sgtl5000->mclk);
1221 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
46a5905e
SG		 1222 /* Defer the probe to see if the clk will be provided later */
1223 if (ret == -ENOENT)
940adb28
EN		 1224 ret = -EPROBE_DEFER;
1225 goto disable_regs;
9e13f345
FE		 1226 }
1227
1228 ret = clk_prepare_enable(sgtl5000->mclk);
940adb28
EN		 1229 if (ret) {
1230 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1231 goto disable_regs;
1232 }
9e13f345 1233
58cc9c9a
EN		 1234 /* Need 8 clocks before I2C accesses */
1235 udelay(1);
1236
b871f1ad
FE		 1237 /* read chip information */
1238 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
940adb28
EN		 1239 if (ret) {
1240 dev_err(&client->dev, "Error reading chip id %d\n", ret);
9e13f345 1241 goto disable_clk;
940adb28 1242 }
b871f1ad
FE		 1243
1244 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1245 SGTL5000_PARTID_PART_ID) {
1246 dev_err(&client->dev,
1247 "Device with ID register %x is not a sgtl5000\n", reg);
9e13f345
FE		 1248 ret = -ENODEV;
1249 goto disable_clk;
b871f1ad
FE		 1250 }
1251
1252 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1253 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
252e91ff 1254 sgtl5000->revision = rev;
b871f1ad 1255
08dea16e
EN		 1256 /* reconfigure the clocks in case we're using the PLL */
1257 ret = regmap_write(sgtl5000->regmap,
1258 SGTL5000_CHIP_CLK_CTRL,
1259 SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1260 if (ret)
1261 dev_err(&client->dev,
1262 "Error %d initializing CHIP_CLK_CTRL\n", ret);
1263
940adb28 1264 /* Follow section 2.2.1.1 of AN3663 */
3d632cc8 1265 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
940adb28
EN		 1266 if (sgtl5000->num_supplies <= VDDD) {
1267 /* internal VDDD at 1.2V */
3d632cc8
EN		 1268 ret = regmap_update_bits(sgtl5000->regmap,
1269 SGTL5000_CHIP_LINREG_CTRL,
1270 SGTL5000_LINREG_VDDD_MASK,
1271 LINREG_VDDD);
1272 if (ret)
1273 dev_err(&client->dev,
1274 "Error %d setting LINREG_VDDD\n", ret);
1275
1276 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1277 dev_info(&client->dev,
1278 "Using internal LDO instead of VDDD: check ER1\n");
940adb28
EN		 1279 } else {
1280 /* using external LDO for VDDD
1281 * Clear startup powerup and simple powerup
1282 * bits to save power
1283 */
3d632cc8
EN		 1284 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1285 | SGTL5000_LINREG_SIMPLE_POWERUP);
940adb28
EN		 1286 dev_dbg(&client->dev, "Using external VDDD\n");
1287 }
3d632cc8
EN		 1288 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1289 if (ret)
1290 dev_err(&client->dev,
1291 "Error %d setting CHIP_ANA_POWER to %04x\n",
1292 ret, ana_pwr);
940adb28 1293
bd0593f5
JMH		 1294 if (np) {
1295 if (!of_property_read_u32(np,
1296 "micbias-resistor-k-ohms", &value)) {
1297 switch (value) {
1298 case SGTL5000_MICBIAS_OFF:
1299 sgtl5000->micbias_resistor = 0;
1300 break;
1301 case SGTL5000_MICBIAS_2K:
1302 sgtl5000->micbias_resistor = 1;
1303 break;
1304 case SGTL5000_MICBIAS_4K:
1305 sgtl5000->micbias_resistor = 2;
1306 break;
1307 case SGTL5000_MICBIAS_8K:
1308 sgtl5000->micbias_resistor = 3;
1309 break;
1310 default:
1311 sgtl5000->micbias_resistor = 2;
1312 dev_err(&client->dev,
1313 "Unsuitable MicBias resistor\n");
1314 }
1315 } else {
1316 /* default is 4Kohms */
1317 sgtl5000->micbias_resistor = 2;
1318 }
87357797
JMH		 1319 if (!of_property_read_u32(np,
1320 "micbias-voltage-m-volts", &value)) {
1321 /* 1250mV => 0 */
1322 /* steps of 250mV */
1323 if ((value >= 1250) && (value <= 3000))
1324 sgtl5000->micbias_voltage = (value / 250) - 5;
1325 else {
1326 sgtl5000->micbias_voltage = 0;
bd0593f5 1327 dev_err(&client->dev,
fb97d75b 1328 "Unsuitable MicBias voltage\n");
bd0593f5
JMH		 1329 }
1330 } else {
87357797 1331 sgtl5000->micbias_voltage = 0;
bd0593f5
JMH		 1332 }
1333 }
1334
af8ee112 1335 /* Ensure sgtl5000 will start with sane register values */
f219b169 1336 sgtl5000_fill_defaults(client);
af8ee112 1337
9b34e6cc
ZZ		 1338 ret = snd_soc_register_codec(&client->dev,
1339 &sgtl5000_driver, &sgtl5000_dai, 1);
9e13f345
FE		 1340 if (ret)
1341 goto disable_clk;
1342
1343 return 0;
1344
1345disable_clk:
1346 clk_disable_unprepare(sgtl5000->mclk);
940adb28
EN		 1347
1348disable_regs:
1349 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1350 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1351
512fa7c4 1352 return ret;
9b34e6cc
ZZ		 1353}
1354
7a79e94e 1355static int sgtl5000_i2c_remove(struct i2c_client *client)
9b34e6cc 1356{
7c647af4 1357 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc 1358
9e13f345
FE		 1359 snd_soc_unregister_codec(&client->dev);
1360 clk_disable_unprepare(sgtl5000->mclk);
940adb28
EN		 1361 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1362 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1363
9b34e6cc
ZZ		 1364 return 0;
1365}
1366
1367static const struct i2c_device_id sgtl5000_id[] = {
1368 {"sgtl5000", 0},
1369 {},
1370};
1371
1372MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1373
58e49424
SG		 1374static const struct of_device_id sgtl5000_dt_ids[] = {
1375 { .compatible = "fsl,sgtl5000", },
1376 { /* sentinel */ }
1377};
4c54c6de 1378MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1379
9b34e6cc
ZZ		 1380static struct i2c_driver sgtl5000_i2c_driver = {
1381 .driver = {
1382 .name = "sgtl5000",
58e49424 1383 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1384 },
1385 .probe = sgtl5000_i2c_probe,
7a79e94e 1386 .remove = sgtl5000_i2c_remove,
9b34e6cc
ZZ		 1387 .id_table = sgtl5000_id,
1388};
1389
67d45090 1390module_i2c_driver(sgtl5000_i2c_driver);
9b34e6cc
ZZ		 1391
1392MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
f7cb8a4b 1393MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
9b34e6cc 1394MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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