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Merge branch 'topic/fsl' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / sound / soc / codecs / sgtl5000.c
CommitLineData
9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
e5d80e82 19#include <linux/regmap.h>
9b34e6cc
ZZ		 20#include <linux/regulator/driver.h>
21#include <linux/regulator/machine.h>
22#include <linux/regulator/consumer.h>
58e49424 23#include <linux/of_device.h>
9b34e6cc
ZZ		 24#include <sound/core.h>
25#include <sound/tlv.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
9b34e6cc
ZZ		 31
32#include "sgtl5000.h"
33
34#define SGTL5000_DAP_REG_OFFSET 0x0100
35#define SGTL5000_MAX_REG_OFFSET 0x013A
36
151798f8 37/* default value of sgtl5000 registers */
e5d80e82
FE		 38static const struct reg_default sgtl5000_reg_defaults[] = {
39 { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
40 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
41 { SGTL5000_CHIP_SSS_CTRL, 0x0008 },
42 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
43 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
44 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
45 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
46 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
47 { SGTL5000_CHIP_ANA_POWER, 0x7060 },
48 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
49 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
50 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
51 { SGTL5000_DAP_SURROUND, 0x0040 },
52 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
53 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
54 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
55 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
56 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
57 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
58 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
59 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
60 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
61 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
9b34e6cc
ZZ		 62};
63
64/* regulator supplies for sgtl5000, VDDD is an optional external supply */
65enum sgtl5000_regulator_supplies {
66 VDDA,
67 VDDIO,
68 VDDD,
69 SGTL5000_SUPPLY_NUM
70};
71
72/* vddd is optional supply */
73static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
74 "VDDA",
75 "VDDIO",
76 "VDDD"
77};
78
79#define LDO_CONSUMER_NAME "VDDD_LDO"
80#define LDO_VOLTAGE 1200000
81
82static struct regulator_consumer_supply ldo_consumer[] = {
83 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
84};
85
61a142b7 86static struct regulator_init_data ldo_init_data = {
9b34e6cc 87 .constraints = {
cd041f64
FE		 88 .min_uV = 1200000,
89 .max_uV = 1200000,
9b34e6cc
ZZ		 90 .valid_modes_mask = REGULATOR_MODE_NORMAL,
91 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
92 },
93 .num_consumer_supplies = 1,
94 .consumer_supplies = &ldo_consumer[0],
95};
96
97/*
98 * sgtl5000 internal ldo regulator,
99 * enabled when VDDD not provided
100 */
101struct ldo_regulator {
102 struct regulator_desc desc;
103 struct regulator_dev *dev;
104 int voltage;
105 void *codec_data;
106 bool enabled;
107};
108
109/* sgtl5000 private structure in codec */
110struct sgtl5000_priv {
111 int sysclk; /* sysclk rate */
112 int master; /* i2s master or not */
113 int fmt; /* i2s data format */
114 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
115 struct ldo_regulator *ldo;
e5d80e82 116 struct regmap *regmap;
9b34e6cc
ZZ		 117};
118
119/*
120 * mic_bias power on/off share the same register bits with
121 * output impedance of mic bias, when power on mic bias, we
122 * need reclaim it to impedance value.
123 * 0x0 = Powered off
124 * 0x1 = 2Kohm
125 * 0x2 = 4Kohm
126 * 0x3 = 8Kohm
127 */
128static int mic_bias_event(struct snd_soc_dapm_widget *w,
129 struct snd_kcontrol *kcontrol, int event)
130{
131 switch (event) {
132 case SND_SOC_DAPM_POST_PMU:
133 /* change mic bias resistor to 4Kohm */
134 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8
AL		 135 SGTL5000_BIAS_R_MASK,
136 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 137 break;
138
139 case SND_SOC_DAPM_PRE_PMD:
9b34e6cc 140 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 141 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 142 break;
143 }
144 return 0;
145}
146
147/*
f0cdcf3a
ZZ		 148 * As manual described, ADC/DAC only works when VAG powerup,
149 * So enabled VAG before ADC/DAC up.
150 * In power down case, we need wait 400ms when vag fully ramped down.
9b34e6cc 151 */
f0cdcf3a 152static int power_vag_event(struct snd_soc_dapm_widget *w,
9b34e6cc
ZZ		 153 struct snd_kcontrol *kcontrol, int event)
154{
155 switch (event) {
dd4d2d6d 156 case SND_SOC_DAPM_POST_PMU:
9b34e6cc
ZZ		 157 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
158 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
159 break;
160
dd4d2d6d 161 case SND_SOC_DAPM_PRE_PMD:
9b34e6cc
ZZ		 162 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
163 SGTL5000_VAG_POWERUP, 0);
164 msleep(400);
165 break;
166 default:
167 break;
168 }
169
170 return 0;
171}
172
173/* input sources for ADC */
174static const char *adc_mux_text[] = {
175 "MIC_IN", "LINE_IN"
176};
177
178static const struct soc_enum adc_enum =
179SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
180
181static const struct snd_kcontrol_new adc_mux =
182SOC_DAPM_ENUM("Capture Mux", adc_enum);
183
184/* input sources for DAC */
185static const char *dac_mux_text[] = {
186 "DAC", "LINE_IN"
187};
188
189static const struct soc_enum dac_enum =
190SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
191
192static const struct snd_kcontrol_new dac_mux =
193SOC_DAPM_ENUM("Headphone Mux", dac_enum);
194
195static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
196 SND_SOC_DAPM_INPUT("LINE_IN"),
197 SND_SOC_DAPM_INPUT("MIC_IN"),
198
199 SND_SOC_DAPM_OUTPUT("HP_OUT"),
200 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
201
8fc8ec92
MB		 202 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
203 mic_bias_event,
204 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9b34e6cc 205
f0cdcf3a
ZZ		 206 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
207 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
9b34e6cc
ZZ		 208
209 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
210 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
211
212 /* aif for i2s input */
213 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
214 0, SGTL5000_CHIP_DIG_POWER,
215 0, 0),
216
217 /* aif for i2s output */
218 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
219 0, SGTL5000_CHIP_DIG_POWER,
220 1, 0),
221
f0cdcf3a 222 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
9b34e6cc 223 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
dd4d2d6d
MV		 224
225 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
226 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
9b34e6cc
ZZ		 227};
228
229/* routes for sgtl5000 */
89989637 230static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
9b34e6cc
ZZ		 231 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
232 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
233
234 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
235 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
236
237 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
238 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
239 {"LO", NULL, "DAC"}, /* dac --> line_out */
240
241 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
242 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
243
244 {"LINE_OUT", NULL, "LO"},
245 {"HP_OUT", NULL, "HP"},
246};
247
248/* custom function to fetch info of PCM playback volume */
249static int dac_info_volsw(struct snd_kcontrol *kcontrol,
250 struct snd_ctl_elem_info *uinfo)
251{
252 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
253 uinfo->count = 2;
254 uinfo->value.integer.min = 0;
255 uinfo->value.integer.max = 0xfc - 0x3c;
256 return 0;
257}
258
259/*
260 * custom function to get of PCM playback volume
261 *
262 * dac volume register
263 * 15-------------8-7--------------0
264 * | R channel vol | L channel vol |
265 * -------------------------------
266 *
267 * PCM volume with 0.5017 dB steps from 0 to -90 dB
268 *
269 * register values map to dB
270 * 0x3B and less = Reserved
271 * 0x3C = 0 dB
272 * 0x3D = -0.5 dB
273 * 0xF0 = -90 dB
274 * 0xFC and greater = Muted
275 *
276 * register value map to userspace value
277 *
278 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
279 * ------------------------------
280 * userspace value 0xc0 0
281 */
282static int dac_get_volsw(struct snd_kcontrol *kcontrol,
283 struct snd_ctl_elem_value *ucontrol)
284{
285 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
286 int reg;
287 int l;
288 int r;
289
290 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
291
292 /* get left channel volume */
293 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
294
295 /* get right channel volume */
296 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
297
298 /* make sure value fall in (0x3c,0xfc) */
299 l = clamp(l, 0x3c, 0xfc);
300 r = clamp(r, 0x3c, 0xfc);
301
302 /* invert it and map to userspace value */
303 l = 0xfc - l;
304 r = 0xfc - r;
305
306 ucontrol->value.integer.value[0] = l;
307 ucontrol->value.integer.value[1] = r;
308
309 return 0;
310}
311
312/*
313 * custom function to put of PCM playback volume
314 *
315 * dac volume register
316 * 15-------------8-7--------------0
317 * | R channel vol | L channel vol |
318 * -------------------------------
319 *
320 * PCM volume with 0.5017 dB steps from 0 to -90 dB
321 *
322 * register values map to dB
323 * 0x3B and less = Reserved
324 * 0x3C = 0 dB
325 * 0x3D = -0.5 dB
326 * 0xF0 = -90 dB
327 * 0xFC and greater = Muted
328 *
329 * userspace value map to register value
330 *
331 * userspace value 0xc0 0
332 * ------------------------------
333 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
334 */
335static int dac_put_volsw(struct snd_kcontrol *kcontrol,
336 struct snd_ctl_elem_value *ucontrol)
337{
338 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
339 int reg;
340 int l;
341 int r;
342
343 l = ucontrol->value.integer.value[0];
344 r = ucontrol->value.integer.value[1];
345
346 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
347 l = clamp(l, 0, 0xfc - 0x3c);
348 r = clamp(r, 0, 0xfc - 0x3c);
349
350 /* invert it, get the value can be set to register */
351 l = 0xfc - l;
352 r = 0xfc - r;
353
354 /* shift to get the register value */
355 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
356 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
357
358 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
359
360 return 0;
361}
362
363static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
364
365/* tlv for mic gain, 0db 20db 30db 40db */
366static const unsigned int mic_gain_tlv[] = {
740fb9d5 367 TLV_DB_RANGE_HEAD(2),
9b34e6cc
ZZ		 368 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
369 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
370};
371
372/* tlv for hp volume, -51.5db to 12.0db, step .5db */
373static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
374
375static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
376 /* SOC_DOUBLE_S8_TLV with invert */
377 {
378 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
379 .name = "PCM Playback Volume",
380 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
381 SNDRV_CTL_ELEM_ACCESS_READWRITE,
382 .info = dac_info_volsw,
383 .get = dac_get_volsw,
384 .put = dac_put_volsw,
385 },
386
387 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
388 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
389 SGTL5000_CHIP_ANA_ADC_CTRL,
390 8, 2, 0, capture_6db_attenuate),
391 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
392
393 SOC_DOUBLE_TLV("Headphone Playback Volume",
394 SGTL5000_CHIP_ANA_HP_CTRL,
395 0, 8,
396 0x7f, 1,
397 headphone_volume),
398 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
399 5, 1, 0),
400
401 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
b50684da 402 0, 3, 0, mic_gain_tlv),
9b34e6cc
ZZ		 403};
404
405/* mute the codec used by alsa core */
406static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
407{
408 struct snd_soc_codec *codec = codec_dai->codec;
409 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
410
411 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
412 adcdac_ctrl, mute ? adcdac_ctrl : 0);
413
414 return 0;
415}
416
417/* set codec format */
418static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
419{
420 struct snd_soc_codec *codec = codec_dai->codec;
421 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
422 u16 i2sctl = 0;
423
424 sgtl5000->master = 0;
425 /*
426 * i2s clock and frame master setting.
427 * ONLY support:
428 * - clock and frame slave,
429 * - clock and frame master
430 */
431 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
432 case SND_SOC_DAIFMT_CBS_CFS:
433 break;
434 case SND_SOC_DAIFMT_CBM_CFM:
435 i2sctl |= SGTL5000_I2S_MASTER;
436 sgtl5000->master = 1;
437 break;
438 default:
439 return -EINVAL;
440 }
441
442 /* setting i2s data format */
443 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
444 case SND_SOC_DAIFMT_DSP_A:
445 i2sctl |= SGTL5000_I2S_MODE_PCM;
446 break;
447 case SND_SOC_DAIFMT_DSP_B:
448 i2sctl |= SGTL5000_I2S_MODE_PCM;
449 i2sctl |= SGTL5000_I2S_LRALIGN;
450 break;
451 case SND_SOC_DAIFMT_I2S:
452 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
453 break;
454 case SND_SOC_DAIFMT_RIGHT_J:
455 i2sctl |= SGTL5000_I2S_MODE_RJ;
456 i2sctl |= SGTL5000_I2S_LRPOL;
457 break;
458 case SND_SOC_DAIFMT_LEFT_J:
459 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
460 i2sctl |= SGTL5000_I2S_LRALIGN;
461 break;
462 default:
463 return -EINVAL;
464 }
465
466 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
467
468 /* Clock inversion */
469 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
470 case SND_SOC_DAIFMT_NB_NF:
471 break;
472 case SND_SOC_DAIFMT_IB_NF:
473 i2sctl |= SGTL5000_I2S_SCLK_INV;
474 break;
475 default:
476 return -EINVAL;
477 }
478
479 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
480
481 return 0;
482}
483
484/* set codec sysclk */
485static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
486 int clk_id, unsigned int freq, int dir)
487{
488 struct snd_soc_codec *codec = codec_dai->codec;
489 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
490
491 switch (clk_id) {
492 case SGTL5000_SYSCLK:
493 sgtl5000->sysclk = freq;
494 break;
495 default:
496 return -EINVAL;
497 }
498
499 return 0;
500}
501
502/*
503 * set clock according to i2s frame clock,
504 * sgtl5000 provide 2 clock sources.
505 * 1. sys_mclk. sample freq can only configure to
506 * 1/256, 1/384, 1/512 of sys_mclk.
507 * 2. pll. can derive any audio clocks.
508 *
509 * clock setting rules:
510 * 1. in slave mode, only sys_mclk can use.
511 * 2. as constraint by sys_mclk, sample freq should
512 * set to 32k, 44.1k and above.
513 * 3. using sys_mclk prefer to pll to save power.
514 */
515static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
516{
517 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
518 int clk_ctl = 0;
519 int sys_fs; /* sample freq */
520
521 /*
522 * sample freq should be divided by frame clock,
523 * if frame clock lower than 44.1khz, sample feq should set to
524 * 32khz or 44.1khz.
525 */
526 switch (frame_rate) {
527 case 8000:
528 case 16000:
529 sys_fs = 32000;
530 break;
531 case 11025:
532 case 22050:
533 sys_fs = 44100;
534 break;
535 default:
536 sys_fs = frame_rate;
537 break;
538 }
539
540 /* set divided factor of frame clock */
541 switch (sys_fs / frame_rate) {
542 case 4:
543 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
544 break;
545 case 2:
546 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
547 break;
548 case 1:
549 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
550 break;
551 default:
552 return -EINVAL;
553 }
554
555 /* set the sys_fs according to frame rate */
556 switch (sys_fs) {
557 case 32000:
558 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
559 break;
560 case 44100:
561 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
562 break;
563 case 48000:
564 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
565 break;
566 case 96000:
567 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
568 break;
569 default:
570 dev_err(codec->dev, "frame rate %d not supported\n",
571 frame_rate);
572 return -EINVAL;
573 }
574
575 /*
576 * calculate the divider of mclk/sample_freq,
577 * factor of freq =96k can only be 256, since mclk in range (12m,27m)
578 */
579 switch (sgtl5000->sysclk / sys_fs) {
580 case 256:
581 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
582 SGTL5000_MCLK_FREQ_SHIFT;
583 break;
584 case 384:
585 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
586 SGTL5000_MCLK_FREQ_SHIFT;
587 break;
588 case 512:
589 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
590 SGTL5000_MCLK_FREQ_SHIFT;
591 break;
592 default:
593 /* if mclk not satisify the divider, use pll */
594 if (sgtl5000->master) {
595 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
596 SGTL5000_MCLK_FREQ_SHIFT;
597 } else {
598 dev_err(codec->dev,
599 "PLL not supported in slave mode\n");
600 return -EINVAL;
601 }
602 }
603
604 /* if using pll, please check manual 6.4.2 for detail */
605 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
606 u64 out, t;
607 int div2;
608 int pll_ctl;
609 unsigned int in, int_div, frac_div;
610
611 if (sgtl5000->sysclk > 17000000) {
612 div2 = 1;
613 in = sgtl5000->sysclk / 2;
614 } else {
615 div2 = 0;
616 in = sgtl5000->sysclk;
617 }
618 if (sys_fs == 44100)
619 out = 180633600;
620 else
621 out = 196608000;
622 t = do_div(out, in);
623 int_div = out;
624 t *= 2048;
625 do_div(t, in);
626 frac_div = t;
627 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
628 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
629
630 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
631 if (div2)
632 snd_soc_update_bits(codec,
633 SGTL5000_CHIP_CLK_TOP_CTRL,
634 SGTL5000_INPUT_FREQ_DIV2,
635 SGTL5000_INPUT_FREQ_DIV2);
636 else
637 snd_soc_update_bits(codec,
638 SGTL5000_CHIP_CLK_TOP_CTRL,
639 SGTL5000_INPUT_FREQ_DIV2,
640 0);
641
642 /* power up pll */
643 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
644 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
645 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
646 } else {
647 /* power down pll */
648 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
649 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
650 0);
651 }
652
653 /* if using pll, clk_ctrl must be set after pll power up */
654 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
655
656 return 0;
657}
658
659/*
660 * Set PCM DAI bit size and sample rate.
661 * input: params_rate, params_fmt
662 */
663static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
664 struct snd_pcm_hw_params *params,
665 struct snd_soc_dai *dai)
666{
e6968a17 667 struct snd_soc_codec *codec = dai->codec;
9b34e6cc
ZZ		 668 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
669 int channels = params_channels(params);
670 int i2s_ctl = 0;
671 int stereo;
672 int ret;
673
674 /* sysclk should already set */
675 if (!sgtl5000->sysclk) {
676 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
677 return -EFAULT;
678 }
679
680 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
681 stereo = SGTL5000_DAC_STEREO;
682 else
683 stereo = SGTL5000_ADC_STEREO;
684
685 /* set mono to save power */
686 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
687 channels == 1 ? 0 : stereo);
688
689 /* set codec clock base on lrclk */
690 ret = sgtl5000_set_clock(codec, params_rate(params));
691 if (ret)
692 return ret;
693
694 /* set i2s data format */
695 switch (params_format(params)) {
696 case SNDRV_PCM_FORMAT_S16_LE:
697 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
698 return -EINVAL;
699 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
700 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
701 SGTL5000_I2S_SCLKFREQ_SHIFT;
702 break;
703 case SNDRV_PCM_FORMAT_S20_3LE:
704 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
705 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
706 SGTL5000_I2S_SCLKFREQ_SHIFT;
707 break;
708 case SNDRV_PCM_FORMAT_S24_LE:
709 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
710 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
711 SGTL5000_I2S_SCLKFREQ_SHIFT;
712 break;
713 case SNDRV_PCM_FORMAT_S32_LE:
714 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
715 return -EINVAL;
716 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
717 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
718 SGTL5000_I2S_SCLKFREQ_SHIFT;
719 break;
720 default:
721 return -EINVAL;
722 }
723
33cb92cf
AL		 724 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
725 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
726 i2s_ctl);
9b34e6cc
ZZ		 727
728 return 0;
729}
730
333802e9 731#ifdef CONFIG_REGULATOR
9b34e6cc
ZZ		 732static int ldo_regulator_is_enabled(struct regulator_dev *dev)
733{
734 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
735
736 return ldo->enabled;
737}
738
739static int ldo_regulator_enable(struct regulator_dev *dev)
740{
741 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
742 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
743 int reg;
744
745 if (ldo_regulator_is_enabled(dev))
746 return 0;
747
748 /* set regulator value firstly */
749 reg = (1600 - ldo->voltage / 1000) / 50;
750 reg = clamp(reg, 0x0, 0xf);
751
752 /* amend the voltage value, unit: uV */
753 ldo->voltage = (1600 - reg * 50) * 1000;
754
755 /* set voltage to register */
756 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 757 SGTL5000_LINREG_VDDD_MASK, reg);
9b34e6cc
ZZ		 758
759 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
760 SGTL5000_LINEREG_D_POWERUP,
761 SGTL5000_LINEREG_D_POWERUP);
762
763 /* when internal ldo enabled, simple digital power can be disabled */
764 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
765 SGTL5000_LINREG_SIMPLE_POWERUP,
766 0);
767
768 ldo->enabled = 1;
769 return 0;
770}
771
772static int ldo_regulator_disable(struct regulator_dev *dev)
773{
774 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
775 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
776
777 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
778 SGTL5000_LINEREG_D_POWERUP,
779 0);
780
781 /* clear voltage info */
782 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 783 SGTL5000_LINREG_VDDD_MASK, 0);
9b34e6cc
ZZ		 784
785 ldo->enabled = 0;
786
787 return 0;
788}
789
790static int ldo_regulator_get_voltage(struct regulator_dev *dev)
791{
792 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
793
794 return ldo->voltage;
795}
796
797static struct regulator_ops ldo_regulator_ops = {
798 .is_enabled = ldo_regulator_is_enabled,
799 .enable = ldo_regulator_enable,
800 .disable = ldo_regulator_disable,
801 .get_voltage = ldo_regulator_get_voltage,
802};
803
804static int ldo_regulator_register(struct snd_soc_codec *codec,
805 struct regulator_init_data *init_data,
806 int voltage)
807{
808 struct ldo_regulator *ldo;
5b13de7a 809 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
c172708d 810 struct regulator_config config = { };
9b34e6cc
ZZ		 811
812 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
813
814 if (!ldo) {
815 dev_err(codec->dev, "failed to allocate ldo_regulator\n");
816 return -ENOMEM;
817 }
818
819 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
820 if (!ldo->desc.name) {
821 kfree(ldo);
822 dev_err(codec->dev, "failed to allocate decs name memory\n");
823 return -ENOMEM;
824 }
825
826 ldo->desc.type = REGULATOR_VOLTAGE;
827 ldo->desc.owner = THIS_MODULE;
828 ldo->desc.ops = &ldo_regulator_ops;
829 ldo->desc.n_voltages = 1;
830
831 ldo->codec_data = codec;
832 ldo->voltage = voltage;
833
c172708d
MB		 834 config.dev = codec->dev;
835 config.driver_data = ldo;
836 config.init_data = init_data;
837
838 ldo->dev = regulator_register(&ldo->desc, &config);
9b34e6cc 839 if (IS_ERR(ldo->dev)) {
62f75aaf
DC		 840 int ret = PTR_ERR(ldo->dev);
841
9b34e6cc
ZZ		 842 dev_err(codec->dev, "failed to register regulator\n");
843 kfree(ldo->desc.name);
844 kfree(ldo);
845
62f75aaf 846 return ret;
9b34e6cc 847 }
5b13de7a 848 sgtl5000->ldo = ldo;
9b34e6cc
ZZ		 849
850 return 0;
851}
852
853static int ldo_regulator_remove(struct snd_soc_codec *codec)
854{
855 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
856 struct ldo_regulator *ldo = sgtl5000->ldo;
857
858 if (!ldo)
859 return 0;
860
861 regulator_unregister(ldo->dev);
862 kfree(ldo->desc.name);
863 kfree(ldo);
864
865 return 0;
866}
333802e9
MB		 867#else
868static int ldo_regulator_register(struct snd_soc_codec *codec,
869 struct regulator_init_data *init_data,
870 int voltage)
871{
09bddc8e 872 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
333802e9
MB		 873 return -EINVAL;
874}
875
876static int ldo_regulator_remove(struct snd_soc_codec *codec)
877{
878 return 0;
879}
880#endif
9b34e6cc
ZZ		 881
882/*
883 * set dac bias
884 * common state changes:
885 * startup:
886 * off --> standby --> prepare --> on
887 * standby --> prepare --> on
888 *
889 * stop:
890 * on --> prepare --> standby
891 */
892static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
893 enum snd_soc_bias_level level)
894{
895 int ret;
896 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
897
898 switch (level) {
899 case SND_SOC_BIAS_ON:
900 case SND_SOC_BIAS_PREPARE:
901 break;
902 case SND_SOC_BIAS_STANDBY:
903 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
904 ret = regulator_bulk_enable(
905 ARRAY_SIZE(sgtl5000->supplies),
906 sgtl5000->supplies);
907 if (ret)
908 return ret;
909 udelay(10);
2bdc1bb2
MB		 910
911 regcache_cache_only(sgtl5000->regmap, false);
912
913 ret = regcache_sync(sgtl5000->regmap);
914 if (ret != 0) {
915 dev_err(codec->dev,
916 "Failed to restore cache: %d\n", ret);
917
918 regcache_cache_only(sgtl5000->regmap, true);
919 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
920 sgtl5000->supplies);
921
922 return ret;
923 }
9b34e6cc
ZZ		 924 }
925
926 break;
927 case SND_SOC_BIAS_OFF:
2bdc1bb2 928 regcache_cache_only(sgtl5000->regmap, true);
9b34e6cc
ZZ		 929 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
930 sgtl5000->supplies);
931 break;
932 }
933
934 codec->dapm.bias_level = level;
935 return 0;
936}
937
938#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
939 SNDRV_PCM_FMTBIT_S20_3LE |\
940 SNDRV_PCM_FMTBIT_S24_LE |\
941 SNDRV_PCM_FMTBIT_S32_LE)
942
85e7652d 943static const struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 944 .hw_params = sgtl5000_pcm_hw_params,
945 .digital_mute = sgtl5000_digital_mute,
946 .set_fmt = sgtl5000_set_dai_fmt,
947 .set_sysclk = sgtl5000_set_dai_sysclk,
948};
949
950static struct snd_soc_dai_driver sgtl5000_dai = {
951 .name = "sgtl5000",
952 .playback = {
953 .stream_name = "Playback",
954 .channels_min = 1,
955 .channels_max = 2,
956 /*
957 * only support 8~48K + 96K,
958 * TODO modify hw_param to support more
959 */
960 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
961 .formats = SGTL5000_FORMATS,
962 },
963 .capture = {
964 .stream_name = "Capture",
965 .channels_min = 1,
966 .channels_max = 2,
967 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
968 .formats = SGTL5000_FORMATS,
969 },
970 .ops = &sgtl5000_ops,
971 .symmetric_rates = 1,
972};
973
e5d80e82 974static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
9b34e6cc
ZZ		 975{
976 switch (reg) {
977 case SGTL5000_CHIP_ID:
978 case SGTL5000_CHIP_ADCDAC_CTRL:
979 case SGTL5000_CHIP_ANA_STATUS:
e5d80e82 980 return true;
9b34e6cc
ZZ		 981 }
982
e5d80e82
FE		 983 return false;
984}
985
986static bool sgtl5000_readable(struct device *dev, unsigned int reg)
987{
988 switch (reg) {
989 case SGTL5000_CHIP_ID:
990 case SGTL5000_CHIP_DIG_POWER:
991 case SGTL5000_CHIP_CLK_CTRL:
992 case SGTL5000_CHIP_I2S_CTRL:
993 case SGTL5000_CHIP_SSS_CTRL:
994 case SGTL5000_CHIP_ADCDAC_CTRL:
995 case SGTL5000_CHIP_DAC_VOL:
996 case SGTL5000_CHIP_PAD_STRENGTH:
997 case SGTL5000_CHIP_ANA_ADC_CTRL:
998 case SGTL5000_CHIP_ANA_HP_CTRL:
999 case SGTL5000_CHIP_ANA_CTRL:
1000 case SGTL5000_CHIP_LINREG_CTRL:
1001 case SGTL5000_CHIP_REF_CTRL:
1002 case SGTL5000_CHIP_MIC_CTRL:
1003 case SGTL5000_CHIP_LINE_OUT_CTRL:
1004 case SGTL5000_CHIP_LINE_OUT_VOL:
1005 case SGTL5000_CHIP_ANA_POWER:
1006 case SGTL5000_CHIP_PLL_CTRL:
1007 case SGTL5000_CHIP_CLK_TOP_CTRL:
1008 case SGTL5000_CHIP_ANA_STATUS:
1009 case SGTL5000_CHIP_SHORT_CTRL:
1010 case SGTL5000_CHIP_ANA_TEST2:
1011 case SGTL5000_DAP_CTRL:
1012 case SGTL5000_DAP_PEQ:
1013 case SGTL5000_DAP_BASS_ENHANCE:
1014 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1015 case SGTL5000_DAP_AUDIO_EQ:
1016 case SGTL5000_DAP_SURROUND:
1017 case SGTL5000_DAP_FLT_COEF_ACCESS:
1018 case SGTL5000_DAP_COEF_WR_B0_MSB:
1019 case SGTL5000_DAP_COEF_WR_B0_LSB:
1020 case SGTL5000_DAP_EQ_BASS_BAND0:
1021 case SGTL5000_DAP_EQ_BASS_BAND1:
1022 case SGTL5000_DAP_EQ_BASS_BAND2:
1023 case SGTL5000_DAP_EQ_BASS_BAND3:
1024 case SGTL5000_DAP_EQ_BASS_BAND4:
1025 case SGTL5000_DAP_MAIN_CHAN:
1026 case SGTL5000_DAP_MIX_CHAN:
1027 case SGTL5000_DAP_AVC_CTRL:
1028 case SGTL5000_DAP_AVC_THRESHOLD:
1029 case SGTL5000_DAP_AVC_ATTACK:
1030 case SGTL5000_DAP_AVC_DECAY:
1031 case SGTL5000_DAP_COEF_WR_B1_MSB:
1032 case SGTL5000_DAP_COEF_WR_B1_LSB:
1033 case SGTL5000_DAP_COEF_WR_B2_MSB:
1034 case SGTL5000_DAP_COEF_WR_B2_LSB:
1035 case SGTL5000_DAP_COEF_WR_A1_MSB:
1036 case SGTL5000_DAP_COEF_WR_A1_LSB:
1037 case SGTL5000_DAP_COEF_WR_A2_MSB:
1038 case SGTL5000_DAP_COEF_WR_A2_LSB:
1039 return true;
1040
1041 default:
1042 return false;
1043 }
9b34e6cc
ZZ		 1044}
1045
1046#ifdef CONFIG_SUSPEND
84b315ee 1047static int sgtl5000_suspend(struct snd_soc_codec *codec)
9b34e6cc
ZZ		 1048{
1049 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1050
1051 return 0;
1052}
1053
1054/*
1055 * restore all sgtl5000 registers,
1056 * since a big hole between dap and regular registers,
1057 * we will restore them respectively.
1058 */
1059static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
1060{
1061 u16 *cache = codec->reg_cache;
151798f8 1062 u16 reg;
9b34e6cc
ZZ		 1063
1064 /* restore regular registers */
151798f8 1065 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
9b34e6cc 1066
bb362e2e 1067 /* These regs should restore in particular order */
9b34e6cc
ZZ		 1068 if (reg == SGTL5000_CHIP_ANA_POWER ||
1069 reg == SGTL5000_CHIP_CLK_CTRL ||
1070 reg == SGTL5000_CHIP_LINREG_CTRL ||
1071 reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
bb362e2e 1072 reg == SGTL5000_CHIP_REF_CTRL)
9b34e6cc
ZZ		 1073 continue;
1074
151798f8 1075 snd_soc_write(codec, reg, cache[reg]);
9b34e6cc
ZZ		 1076 }
1077
1078 /* restore dap registers */
151798f8
WS		 1079 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
1080 snd_soc_write(codec, reg, cache[reg]);
9b34e6cc
ZZ		 1081
1082 /*
bb362e2e
ZZ		 1083 * restore these regs according to the power setting sequence in
1084 * sgtl5000_set_power_regs() and clock setting sequence in
1085 * sgtl5000_set_clock().
1086 *
1087 * The order of restore is:
1088 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
1089 * SGTL5000_CHIP_ANA_POWER PLL bits set
1090 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
1091 * SGTL5000_CHIP_ANA_POWER LINREG_D restored
1092 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
1093 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
9b34e6cc
ZZ		 1094 */
1095 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
151798f8 1096 cache[SGTL5000_CHIP_LINREG_CTRL]);
9b34e6cc
ZZ		 1097
1098 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
151798f8 1099 cache[SGTL5000_CHIP_ANA_POWER]);
9b34e6cc
ZZ		 1100
1101 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
151798f8 1102 cache[SGTL5000_CHIP_CLK_CTRL]);
9b34e6cc
ZZ		 1103
1104 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
151798f8 1105 cache[SGTL5000_CHIP_REF_CTRL]);
9b34e6cc
ZZ		 1106
1107 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
151798f8 1108 cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
9b34e6cc
ZZ		 1109 return 0;
1110}
1111
1112static int sgtl5000_resume(struct snd_soc_codec *codec)
1113{
1114 /* Bring the codec back up to standby to enable regulators */
1115 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1116
1117 /* Restore registers by cached in memory */
1118 sgtl5000_restore_regs(codec);
1119 return 0;
1120}
1121#else
1122#define sgtl5000_suspend NULL
1123#define sgtl5000_resume NULL
1124#endif /* CONFIG_SUSPEND */
1125
1126/*
1127 * sgtl5000 has 3 internal power supplies:
1128 * 1. VAG, normally set to vdda/2
1129 * 2. chargepump, set to different value
1130 * according to voltage of vdda and vddio
1131 * 3. line out VAG, normally set to vddio/2
1132 *
1133 * and should be set according to:
1134 * 1. vddd provided by external or not
1135 * 2. vdda and vddio voltage value. > 3.1v or not
1136 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1137 */
1138static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1139{
1140 int vddd;
1141 int vdda;
1142 int vddio;
1143 u16 ana_pwr;
1144 u16 lreg_ctrl;
1145 int vag;
1146 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1147
1148 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1149 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1150 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1151
1152 vdda = vdda / 1000;
1153 vddio = vddio / 1000;
1154 vddd = vddd / 1000;
1155
1156 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1157 dev_err(codec->dev, "regulator voltage not set correctly\n");
1158
1159 return -EINVAL;
1160 }
1161
1162 /* according to datasheet, maximum voltage of supplies */
1163 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1164 dev_err(codec->dev,
cf1ee98d 1165 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
9b34e6cc
ZZ		 1166 vdda, vddio, vddd);
1167
1168 return -EINVAL;
1169 }
1170
1171 /* reset value */
1172 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1173 ana_pwr |= SGTL5000_DAC_STEREO |
1174 SGTL5000_ADC_STEREO |
1175 SGTL5000_REFTOP_POWERUP;
1176 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1177
1178 if (vddio < 3100 && vdda < 3100) {
1179 /* enable internal oscillator used for charge pump */
1180 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1181 SGTL5000_INT_OSC_EN,
1182 SGTL5000_INT_OSC_EN);
1183 /* Enable VDDC charge pump */
1184 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1185 } else if (vddio >= 3100 && vdda >= 3100) {
1186 /*
1187 * if vddio and vddd > 3.1v,
1188 * charge pump should be clean before set ana_pwr
1189 */
1190 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1191 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1192
1193 /* VDDC use VDDIO rail */
1194 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1195 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1196 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1197 }
1198
1199 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1200
1201 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1202
1203 /* set voltage to register */
1204 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 1205 SGTL5000_LINREG_VDDD_MASK, 0x8);
9b34e6cc
ZZ		 1206
1207 /*
1208 * if vddd linear reg has been enabled,
1209 * simple digital supply should be clear to get
1210 * proper VDDD voltage.
1211 */
1212 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1213 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1214 SGTL5000_LINREG_SIMPLE_POWERUP,
1215 0);
1216 else
1217 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1218 SGTL5000_LINREG_SIMPLE_POWERUP |
1219 SGTL5000_STARTUP_POWERUP,
1220 0);
1221
1222 /*
1223 * set ADC/DAC VAG to vdda / 2,
1224 * should stay in range (0.8v, 1.575v)
1225 */
1226 vag = vdda / 2;
1227 if (vag <= SGTL5000_ANA_GND_BASE)
1228 vag = 0;
1229 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1230 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1231 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1232 else
1233 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1234
1235 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
33cb92cf 1236 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
9b34e6cc
ZZ		 1237
1238 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1239 vag = vddio / 2;
1240 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1241 vag = 0;
1242 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1243 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1244 vag = SGTL5000_LINE_OUT_GND_MAX;
1245 else
1246 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1247 SGTL5000_LINE_OUT_GND_STP;
1248
1249 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
33cb92cf
AL		 1250 SGTL5000_LINE_OUT_CURRENT_MASK |
1251 SGTL5000_LINE_OUT_GND_MASK,
9b34e6cc
ZZ		 1252 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1253 SGTL5000_LINE_OUT_CURRENT_360u <<
1254 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1255
1256 return 0;
1257}
1258
e94a4062
WS		 1259static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1260{
1261 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1262 int ret;
1263
1264 /* set internal ldo to 1.2v */
1265 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1266 if (ret) {
1267 dev_err(codec->dev,
1268 "Failed to register vddd internal supplies: %d\n", ret);
1269 return ret;
1270 }
1271
1272 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1273
1274 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1275 sgtl5000->supplies);
1276
1277 if (ret) {
1278 ldo_regulator_remove(codec);
1279 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1280 return ret;
1281 }
1282
1283 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1284 return 0;
1285}
1286
9b34e6cc
ZZ		 1287static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1288{
b871f1ad 1289 int reg;
9b34e6cc
ZZ		 1290 int ret;
1291 int rev;
1292 int i;
1293 int external_vddd = 0;
1294 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1295
1296 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1297 sgtl5000->supplies[i].supply = supply_names[i];
1298
1299 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1300 sgtl5000->supplies);
1301 if (!ret)
1302 external_vddd = 1;
1303 else {
e94a4062
WS		 1304 ret = sgtl5000_replace_vddd_with_ldo(codec);
1305 if (ret)
9b34e6cc 1306 return ret;
9b34e6cc
ZZ		 1307 }
1308
1309 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1310 sgtl5000->supplies);
1311 if (ret)
1312 goto err_regulator_free;
1313
1314 /* wait for all power rails bring up */
1315 udelay(10);
1316
9b34e6cc
ZZ		 1317 /*
1318 * workaround for revision 0x11 and later,
1319 * roll back to use internal LDO
1320 */
b871f1ad
FE		 1321
1322 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1323 if (ret)
1324 goto err_regulator_disable;
1325
1326 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1327
9b34e6cc 1328 if (external_vddd && rev >= 0x11) {
9b34e6cc
ZZ		 1329 /* disable all regulator first */
1330 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1331 sgtl5000->supplies);
1332 /* free VDDD regulator */
1333 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1334 sgtl5000->supplies);
1335
e94a4062 1336 ret = sgtl5000_replace_vddd_with_ldo(codec);
9b34e6cc
ZZ		 1337 if (ret)
1338 return ret;
1339
9b34e6cc
ZZ		 1340 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1341 sgtl5000->supplies);
1342 if (ret)
1343 goto err_regulator_free;
1344
1345 /* wait for all power rails bring up */
1346 udelay(10);
1347 }
1348
1349 return 0;
1350
1351err_regulator_disable:
1352 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1353 sgtl5000->supplies);
1354err_regulator_free:
1355 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1356 sgtl5000->supplies);
1357 if (external_vddd)
1358 ldo_regulator_remove(codec);
1359 return ret;
1360
1361}
1362
1363static int sgtl5000_probe(struct snd_soc_codec *codec)
1364{
1365 int ret;
1366 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1367
1368 /* setup i2c data ops */
e5d80e82
FE		 1369 codec->control_data = sgtl5000->regmap;
1370 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
9b34e6cc
ZZ		 1371 if (ret < 0) {
1372 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1373 return ret;
1374 }
1375
1376 ret = sgtl5000_enable_regulators(codec);
1377 if (ret)
1378 return ret;
1379
1380 /* power up sgtl5000 */
1381 ret = sgtl5000_set_power_regs(codec);
1382 if (ret)
1383 goto err;
1384
1385 /* enable small pop, introduce 400ms delay in turning off */
1386 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1387 SGTL5000_SMALL_POP,
1388 SGTL5000_SMALL_POP);
1389
1390 /* disable short cut detector */
1391 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1392
1393 /*
1394 * set i2s as default input of sound switch
1395 * TODO: add sound switch to control and dapm widge.
1396 */
1397 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1398 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1399 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1400 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1401
1402 /* enable dac volume ramp by default */
1403 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1404 SGTL5000_DAC_VOL_RAMP_EN |
1405 SGTL5000_DAC_MUTE_RIGHT |
1406 SGTL5000_DAC_MUTE_LEFT);
1407
1408 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1409
1410 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1411 SGTL5000_HP_ZCD_EN |
1412 SGTL5000_ADC_ZCD_EN);
1413
b50684da 1414 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2);
9b34e6cc
ZZ		 1415
1416 /*
1417 * disable DAP
1418 * TODO:
1419 * Enable DAP in kcontrol and dapm.
1420 */
1421 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1422
1423 /* leading to standby state */
1424 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1425 if (ret)
1426 goto err;
1427
9b34e6cc
ZZ		 1428 return 0;
1429
1430err:
1431 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1432 sgtl5000->supplies);
1433 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1434 sgtl5000->supplies);
1435 ldo_regulator_remove(codec);
1436
1437 return ret;
1438}
1439
1440static int sgtl5000_remove(struct snd_soc_codec *codec)
1441{
1442 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1443
1444 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1445
1446 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1447 sgtl5000->supplies);
1448 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1449 sgtl5000->supplies);
1450 ldo_regulator_remove(codec);
1451
1452 return 0;
1453}
1454
61a142b7 1455static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1456 .probe = sgtl5000_probe,
1457 .remove = sgtl5000_remove,
1458 .suspend = sgtl5000_suspend,
1459 .resume = sgtl5000_resume,
1460 .set_bias_level = sgtl5000_set_bias_level,
89989637
FE		 1461 .controls = sgtl5000_snd_controls,
1462 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
5e0ac527
MB		 1463 .dapm_widgets = sgtl5000_dapm_widgets,
1464 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1465 .dapm_routes = sgtl5000_dapm_routes,
1466 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
9b34e6cc
ZZ		 1467};
1468
e5d80e82
FE		 1469static const struct regmap_config sgtl5000_regmap = {
1470 .reg_bits = 16,
1471 .val_bits = 16,
1472
1473 .max_register = SGTL5000_MAX_REG_OFFSET,
1474 .volatile_reg = sgtl5000_volatile,
1475 .readable_reg = sgtl5000_readable,
1476
1477 .cache_type = REGCACHE_RBTREE,
1478 .reg_defaults = sgtl5000_reg_defaults,
1479 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1480};
1481
af8ee112
FE		 1482/*
1483 * Write all the default values from sgtl5000_reg_defaults[] array into the
1484 * sgtl5000 registers, to make sure we always start with the sane registers
1485 * values as stated in the datasheet.
1486 *
1487 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1488 * we follow this approach to guarantee we always start from the default values
1489 * and avoid problems like, not being able to probe after an audio playback
1490 * followed by a system reset or a 'reboot' command in Linux
1491 */
1492static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
1493{
1494 int i, ret, val, index;
1495
1496 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1497 val = sgtl5000_reg_defaults[i].def;
1498 index = sgtl5000_reg_defaults[i].reg;
1499 ret = regmap_write(sgtl5000->regmap, index, val);
1500 if (ret)
1501 return ret;
1502 }
1503
1504 return 0;
1505}
1506
7a79e94e
BP		 1507static int sgtl5000_i2c_probe(struct i2c_client *client,
1508 const struct i2c_device_id *id)
9b34e6cc
ZZ		 1509{
1510 struct sgtl5000_priv *sgtl5000;
b871f1ad 1511 int ret, reg, rev;
9b34e6cc 1512
512fa7c4
FE		 1513 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
1514 GFP_KERNEL);
9b34e6cc
ZZ		 1515 if (!sgtl5000)
1516 return -ENOMEM;
1517
e5d80e82
FE		 1518 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1519 if (IS_ERR(sgtl5000->regmap)) {
1520 ret = PTR_ERR(sgtl5000->regmap);
1521 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1522 return ret;
1523 }
1524
b871f1ad
FE		 1525 /* read chip information */
1526 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1527 if (ret)
1528 return ret;
1529
1530 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1531 SGTL5000_PARTID_PART_ID) {
1532 dev_err(&client->dev,
1533 "Device with ID register %x is not a sgtl5000\n", reg);
1534 return -ENODEV;
1535 }
1536
1537 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1538 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1539
9b34e6cc
ZZ		 1540 i2c_set_clientdata(client, sgtl5000);
1541
af8ee112
FE		 1542 /* Ensure sgtl5000 will start with sane register values */
1543 ret = sgtl5000_fill_defaults(sgtl5000);
1544 if (ret)
1545 return ret;
1546
9b34e6cc
ZZ		 1547 ret = snd_soc_register_codec(&client->dev,
1548 &sgtl5000_driver, &sgtl5000_dai, 1);
512fa7c4 1549 return ret;
9b34e6cc
ZZ		 1550}
1551
7a79e94e 1552static int sgtl5000_i2c_remove(struct i2c_client *client)
9b34e6cc 1553{
9b34e6cc
ZZ		 1554 snd_soc_unregister_codec(&client->dev);
1555
9b34e6cc
ZZ		 1556 return 0;
1557}
1558
1559static const struct i2c_device_id sgtl5000_id[] = {
1560 {"sgtl5000", 0},
1561 {},
1562};
1563
1564MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1565
58e49424
SG		 1566static const struct of_device_id sgtl5000_dt_ids[] = {
1567 { .compatible = "fsl,sgtl5000", },
1568 { /* sentinel */ }
1569};
4c54c6de 1570MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1571
9b34e6cc
ZZ		 1572static struct i2c_driver sgtl5000_i2c_driver = {
1573 .driver = {
1574 .name = "sgtl5000",
1575 .owner = THIS_MODULE,
58e49424 1576 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1577 },
1578 .probe = sgtl5000_i2c_probe,
7a79e94e 1579 .remove = sgtl5000_i2c_remove,
9b34e6cc
ZZ		 1580 .id_table = sgtl5000_id,
1581};
1582
67d45090 1583module_i2c_driver(sgtl5000_i2c_driver);
9b34e6cc
ZZ		 1584
1585MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
f7cb8a4b 1586MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
9b34e6cc 1587MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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