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ASoC: sgtl5000: Add MicBias resistor support in DT
[deliverable/linux.git] / sound / soc / codecs / sgtl5000.c
CommitLineData
9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
bd0593f5 19#include <linux/log2.h>
e5d80e82 20#include <linux/regmap.h>
9b34e6cc
ZZ		 21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/regulator/consumer.h>
58e49424 24#include <linux/of_device.h>
9b34e6cc
ZZ		 25#include <sound/core.h>
26#include <sound/tlv.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
9b34e6cc
ZZ		 32
33#include "sgtl5000.h"
34
35#define SGTL5000_DAP_REG_OFFSET 0x0100
36#define SGTL5000_MAX_REG_OFFSET 0x013A
37
151798f8 38/* default value of sgtl5000 registers */
e5d80e82 39static const struct reg_default sgtl5000_reg_defaults[] = {
29aa37cd 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
e5d80e82
FE		 41 { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
42 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
016fcab8 43 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
29aa37cd 44 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
e5d80e82
FE		 45 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
46 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
29aa37cd 47 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
e5d80e82
FE		 48 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
49 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
29aa37cd
FE		 50 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
51 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
52 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
53 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
e5d80e82
FE		 54 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
55 { SGTL5000_CHIP_ANA_POWER, 0x7060 },
56 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
29aa37cd
FE		 57 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
58 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
59 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
60 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
61 { SGTL5000_DAP_CTRL, 0x0000 },
62 { SGTL5000_DAP_PEQ, 0x0000 },
e5d80e82
FE		 63 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
64 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
29aa37cd 65 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
e5d80e82
FE		 66 { SGTL5000_DAP_SURROUND, 0x0040 },
67 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
69 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
70 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
71 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
72 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
29aa37cd 73 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
e5d80e82
FE		 74 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
75 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
76 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
77 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
9b34e6cc
ZZ		 78};
79
80/* regulator supplies for sgtl5000, VDDD is an optional external supply */
81enum sgtl5000_regulator_supplies {
82 VDDA,
83 VDDIO,
84 VDDD,
85 SGTL5000_SUPPLY_NUM
86};
87
88/* vddd is optional supply */
89static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
90 "VDDA",
91 "VDDIO",
92 "VDDD"
93};
94
95#define LDO_CONSUMER_NAME "VDDD_LDO"
96#define LDO_VOLTAGE 1200000
97
98static struct regulator_consumer_supply ldo_consumer[] = {
99 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
100};
101
61a142b7 102static struct regulator_init_data ldo_init_data = {
9b34e6cc 103 .constraints = {
cd041f64
FE		 104 .min_uV = 1200000,
105 .max_uV = 1200000,
9b34e6cc
ZZ		 106 .valid_modes_mask = REGULATOR_MODE_NORMAL,
107 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
108 },
109 .num_consumer_supplies = 1,
110 .consumer_supplies = &ldo_consumer[0],
111};
112
113/*
114 * sgtl5000 internal ldo regulator,
115 * enabled when VDDD not provided
116 */
117struct ldo_regulator {
118 struct regulator_desc desc;
119 struct regulator_dev *dev;
120 int voltage;
121 void *codec_data;
122 bool enabled;
123};
124
bd0593f5
JMH		 125enum sgtl5000_micbias_resistor {
126 SGTL5000_MICBIAS_OFF = 0,
127 SGTL5000_MICBIAS_2K = 2,
128 SGTL5000_MICBIAS_4K = 4,
129 SGTL5000_MICBIAS_8K = 8,
130};
131
9b34e6cc
ZZ		 132/* sgtl5000 private structure in codec */
133struct sgtl5000_priv {
134 int sysclk; /* sysclk rate */
135 int master; /* i2s master or not */
136 int fmt; /* i2s data format */
137 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
138 struct ldo_regulator *ldo;
e5d80e82 139 struct regmap *regmap;
9e13f345 140 struct clk *mclk;
252e91ff 141 int revision;
bd0593f5 142 u8 micbias_resistor;
9b34e6cc
ZZ		 143};
144
145/*
146 * mic_bias power on/off share the same register bits with
147 * output impedance of mic bias, when power on mic bias, we
148 * need reclaim it to impedance value.
149 * 0x0 = Powered off
150 * 0x1 = 2Kohm
151 * 0x2 = 4Kohm
152 * 0x3 = 8Kohm
153 */
154static int mic_bias_event(struct snd_soc_dapm_widget *w,
155 struct snd_kcontrol *kcontrol, int event)
156{
bd0593f5
JMH		 157 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(w->codec);
158
9b34e6cc
ZZ		 159 switch (event) {
160 case SND_SOC_DAPM_POST_PMU:
bd0593f5 161 /* change mic bias resistor */
9b34e6cc 162 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
bd0593f5
JMH		 163 SGTL5000_BIAS_R_MASK,
164 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 165 break;
166
167 case SND_SOC_DAPM_PRE_PMD:
9b34e6cc 168 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 169 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 170 break;
171 }
172 return 0;
173}
174
175/*
f0cdcf3a
ZZ		 176 * As manual described, ADC/DAC only works when VAG powerup,
177 * So enabled VAG before ADC/DAC up.
178 * In power down case, we need wait 400ms when vag fully ramped down.
9b34e6cc 179 */
f0cdcf3a 180static int power_vag_event(struct snd_soc_dapm_widget *w,
9b34e6cc
ZZ		 181 struct snd_kcontrol *kcontrol, int event)
182{
f091f3f0
LW		 183 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
184
9b34e6cc 185 switch (event) {
dd4d2d6d 186 case SND_SOC_DAPM_POST_PMU:
9b34e6cc
ZZ		 187 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
188 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
189 break;
190
dd4d2d6d 191 case SND_SOC_DAPM_PRE_PMD:
f091f3f0
LW		 192 /*
193 * Don't clear VAG_POWERUP, when both DAC and ADC are
194 * operational to prevent inadvertently starving the
195 * other one of them.
196 */
197 if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) &
198 mask) != mask) {
199 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
200 SGTL5000_VAG_POWERUP, 0);
201 msleep(400);
202 }
9b34e6cc
ZZ		 203 break;
204 default:
205 break;
206 }
207
208 return 0;
209}
210
211/* input sources for ADC */
212static const char *adc_mux_text[] = {
213 "MIC_IN", "LINE_IN"
214};
215
c8ed6504
TI		 216static SOC_ENUM_SINGLE_DECL(adc_enum,
217 SGTL5000_CHIP_ANA_CTRL, 2,
218 adc_mux_text);
9b34e6cc
ZZ		 219
220static const struct snd_kcontrol_new adc_mux =
221SOC_DAPM_ENUM("Capture Mux", adc_enum);
222
223/* input sources for DAC */
224static const char *dac_mux_text[] = {
225 "DAC", "LINE_IN"
226};
227
c8ed6504
TI		 228static SOC_ENUM_SINGLE_DECL(dac_enum,
229 SGTL5000_CHIP_ANA_CTRL, 6,
230 dac_mux_text);
9b34e6cc
ZZ		 231
232static const struct snd_kcontrol_new dac_mux =
233SOC_DAPM_ENUM("Headphone Mux", dac_enum);
234
235static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
236 SND_SOC_DAPM_INPUT("LINE_IN"),
237 SND_SOC_DAPM_INPUT("MIC_IN"),
238
239 SND_SOC_DAPM_OUTPUT("HP_OUT"),
240 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
241
8fc8ec92
MB		 242 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
243 mic_bias_event,
244 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9b34e6cc 245
f0cdcf3a
ZZ		 246 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
247 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
9b34e6cc
ZZ		 248
249 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
250 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
251
252 /* aif for i2s input */
253 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
254 0, SGTL5000_CHIP_DIG_POWER,
255 0, 0),
256
257 /* aif for i2s output */
258 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
259 0, SGTL5000_CHIP_DIG_POWER,
260 1, 0),
261
f0cdcf3a 262 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
9b34e6cc 263 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
dd4d2d6d
MV		 264
265 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
266 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
9b34e6cc
ZZ		 267};
268
269/* routes for sgtl5000 */
89989637 270static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
9b34e6cc
ZZ		 271 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
272 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
273
274 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
275 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
276
277 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
278 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
279 {"LO", NULL, "DAC"}, /* dac --> line_out */
280
281 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
282 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
283
284 {"LINE_OUT", NULL, "LO"},
285 {"HP_OUT", NULL, "HP"},
286};
287
288/* custom function to fetch info of PCM playback volume */
289static int dac_info_volsw(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_info *uinfo)
291{
292 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
293 uinfo->count = 2;
294 uinfo->value.integer.min = 0;
295 uinfo->value.integer.max = 0xfc - 0x3c;
296 return 0;
297}
298
299/*
300 * custom function to get of PCM playback volume
301 *
302 * dac volume register
303 * 15-------------8-7--------------0
304 * | R channel vol | L channel vol |
305 * -------------------------------
306 *
307 * PCM volume with 0.5017 dB steps from 0 to -90 dB
308 *
309 * register values map to dB
310 * 0x3B and less = Reserved
311 * 0x3C = 0 dB
312 * 0x3D = -0.5 dB
313 * 0xF0 = -90 dB
314 * 0xFC and greater = Muted
315 *
316 * register value map to userspace value
317 *
318 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
319 * ------------------------------
320 * userspace value 0xc0 0
321 */
322static int dac_get_volsw(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324{
ea53bf77 325 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 326 int reg;
327 int l;
328 int r;
329
330 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
331
332 /* get left channel volume */
333 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
334
335 /* get right channel volume */
336 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
337
338 /* make sure value fall in (0x3c,0xfc) */
339 l = clamp(l, 0x3c, 0xfc);
340 r = clamp(r, 0x3c, 0xfc);
341
342 /* invert it and map to userspace value */
343 l = 0xfc - l;
344 r = 0xfc - r;
345
346 ucontrol->value.integer.value[0] = l;
347 ucontrol->value.integer.value[1] = r;
348
349 return 0;
350}
351
352/*
353 * custom function to put of PCM playback volume
354 *
355 * dac volume register
356 * 15-------------8-7--------------0
357 * | R channel vol | L channel vol |
358 * -------------------------------
359 *
360 * PCM volume with 0.5017 dB steps from 0 to -90 dB
361 *
362 * register values map to dB
363 * 0x3B and less = Reserved
364 * 0x3C = 0 dB
365 * 0x3D = -0.5 dB
366 * 0xF0 = -90 dB
367 * 0xFC and greater = Muted
368 *
369 * userspace value map to register value
370 *
371 * userspace value 0xc0 0
372 * ------------------------------
373 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
374 */
375static int dac_put_volsw(struct snd_kcontrol *kcontrol,
376 struct snd_ctl_elem_value *ucontrol)
377{
ea53bf77 378 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 379 int reg;
380 int l;
381 int r;
382
383 l = ucontrol->value.integer.value[0];
384 r = ucontrol->value.integer.value[1];
385
386 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
387 l = clamp(l, 0, 0xfc - 0x3c);
388 r = clamp(r, 0, 0xfc - 0x3c);
389
390 /* invert it, get the value can be set to register */
391 l = 0xfc - l;
392 r = 0xfc - r;
393
394 /* shift to get the register value */
395 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
396 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
397
398 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
399
400 return 0;
401}
402
403static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
404
405/* tlv for mic gain, 0db 20db 30db 40db */
406static const unsigned int mic_gain_tlv[] = {
740fb9d5 407 TLV_DB_RANGE_HEAD(2),
9b34e6cc
ZZ		 408 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
409 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
410};
411
412/* tlv for hp volume, -51.5db to 12.0db, step .5db */
413static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
414
415static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
416 /* SOC_DOUBLE_S8_TLV with invert */
417 {
418 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
419 .name = "PCM Playback Volume",
420 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
421 SNDRV_CTL_ELEM_ACCESS_READWRITE,
422 .info = dac_info_volsw,
423 .get = dac_get_volsw,
424 .put = dac_put_volsw,
425 },
426
427 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
428 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
429 SGTL5000_CHIP_ANA_ADC_CTRL,
65f2b226 430 8, 1, 0, capture_6db_attenuate),
9b34e6cc
ZZ		 431 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
432
433 SOC_DOUBLE_TLV("Headphone Playback Volume",
434 SGTL5000_CHIP_ANA_HP_CTRL,
435 0, 8,
436 0x7f, 1,
437 headphone_volume),
438 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
439 5, 1, 0),
440
441 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
b50684da 442 0, 3, 0, mic_gain_tlv),
9b34e6cc
ZZ		 443};
444
445/* mute the codec used by alsa core */
446static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
447{
448 struct snd_soc_codec *codec = codec_dai->codec;
449 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
450
451 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
452 adcdac_ctrl, mute ? adcdac_ctrl : 0);
453
454 return 0;
455}
456
457/* set codec format */
458static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
459{
460 struct snd_soc_codec *codec = codec_dai->codec;
461 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
462 u16 i2sctl = 0;
463
464 sgtl5000->master = 0;
465 /*
466 * i2s clock and frame master setting.
467 * ONLY support:
468 * - clock and frame slave,
469 * - clock and frame master
470 */
471 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
472 case SND_SOC_DAIFMT_CBS_CFS:
473 break;
474 case SND_SOC_DAIFMT_CBM_CFM:
475 i2sctl |= SGTL5000_I2S_MASTER;
476 sgtl5000->master = 1;
477 break;
478 default:
479 return -EINVAL;
480 }
481
482 /* setting i2s data format */
483 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
484 case SND_SOC_DAIFMT_DSP_A:
485 i2sctl |= SGTL5000_I2S_MODE_PCM;
486 break;
487 case SND_SOC_DAIFMT_DSP_B:
488 i2sctl |= SGTL5000_I2S_MODE_PCM;
489 i2sctl |= SGTL5000_I2S_LRALIGN;
490 break;
491 case SND_SOC_DAIFMT_I2S:
492 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
493 break;
494 case SND_SOC_DAIFMT_RIGHT_J:
495 i2sctl |= SGTL5000_I2S_MODE_RJ;
496 i2sctl |= SGTL5000_I2S_LRPOL;
497 break;
498 case SND_SOC_DAIFMT_LEFT_J:
499 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
500 i2sctl |= SGTL5000_I2S_LRALIGN;
501 break;
502 default:
503 return -EINVAL;
504 }
505
506 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
507
508 /* Clock inversion */
509 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
510 case SND_SOC_DAIFMT_NB_NF:
511 break;
512 case SND_SOC_DAIFMT_IB_NF:
513 i2sctl |= SGTL5000_I2S_SCLK_INV;
514 break;
515 default:
516 return -EINVAL;
517 }
518
519 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
520
521 return 0;
522}
523
524/* set codec sysclk */
525static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
526 int clk_id, unsigned int freq, int dir)
527{
528 struct snd_soc_codec *codec = codec_dai->codec;
529 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
530
531 switch (clk_id) {
532 case SGTL5000_SYSCLK:
533 sgtl5000->sysclk = freq;
534 break;
535 default:
536 return -EINVAL;
537 }
538
539 return 0;
540}
541
542/*
543 * set clock according to i2s frame clock,
7f6d75d7
FE		 544 * sgtl5000 provides 2 clock sources:
545 * 1. sys_mclk: sample freq can only be configured to
9b34e6cc 546 * 1/256, 1/384, 1/512 of sys_mclk.
7f6d75d7 547 * 2. pll: can derive any audio clocks.
9b34e6cc
ZZ		 548 *
549 * clock setting rules:
7f6d75d7
FE		 550 * 1. in slave mode, only sys_mclk can be used
551 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
552 * and above.
553 * 3. usage of sys_mclk is preferred over pll to save power.
9b34e6cc
ZZ		 554 */
555static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
556{
557 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
558 int clk_ctl = 0;
559 int sys_fs; /* sample freq */
560
561 /*
562 * sample freq should be divided by frame clock,
7f6d75d7
FE		 563 * if frame clock is lower than 44.1 kHz, sample freq should be set to
564 * 32 kHz or 44.1 kHz.
9b34e6cc
ZZ		 565 */
566 switch (frame_rate) {
567 case 8000:
568 case 16000:
569 sys_fs = 32000;
570 break;
571 case 11025:
572 case 22050:
573 sys_fs = 44100;
574 break;
575 default:
576 sys_fs = frame_rate;
577 break;
578 }
579
580 /* set divided factor of frame clock */
581 switch (sys_fs / frame_rate) {
582 case 4:
583 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
584 break;
585 case 2:
586 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
587 break;
588 case 1:
589 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
590 break;
591 default:
592 return -EINVAL;
593 }
594
595 /* set the sys_fs according to frame rate */
596 switch (sys_fs) {
597 case 32000:
598 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
599 break;
600 case 44100:
601 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
602 break;
603 case 48000:
604 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
605 break;
606 case 96000:
607 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
608 break;
609 default:
610 dev_err(codec->dev, "frame rate %d not supported\n",
611 frame_rate);
612 return -EINVAL;
613 }
614
615 /*
616 * calculate the divider of mclk/sample_freq,
7f6d75d7
FE		 617 * factor of freq = 96 kHz can only be 256, since mclk is in the range
618 * of 8 MHz - 27 MHz
9b34e6cc
ZZ		 619 */
620 switch (sgtl5000->sysclk / sys_fs) {
621 case 256:
622 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
623 SGTL5000_MCLK_FREQ_SHIFT;
624 break;
625 case 384:
626 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
627 SGTL5000_MCLK_FREQ_SHIFT;
628 break;
629 case 512:
630 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
631 SGTL5000_MCLK_FREQ_SHIFT;
632 break;
633 default:
7f6d75d7 634 /* if mclk does not satisfy the divider, use pll */
9b34e6cc
ZZ		 635 if (sgtl5000->master) {
636 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
637 SGTL5000_MCLK_FREQ_SHIFT;
638 } else {
639 dev_err(codec->dev,
640 "PLL not supported in slave mode\n");
fa558d01
FE		 641 dev_err(codec->dev, "%d ratio is not supported. "
642 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
643 sgtl5000->sysclk / sys_fs);
9b34e6cc
ZZ		 644 return -EINVAL;
645 }
646 }
647
648 /* if using pll, please check manual 6.4.2 for detail */
649 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
650 u64 out, t;
651 int div2;
652 int pll_ctl;
653 unsigned int in, int_div, frac_div;
654
655 if (sgtl5000->sysclk > 17000000) {
656 div2 = 1;
657 in = sgtl5000->sysclk / 2;
658 } else {
659 div2 = 0;
660 in = sgtl5000->sysclk;
661 }
662 if (sys_fs == 44100)
663 out = 180633600;
664 else
665 out = 196608000;
666 t = do_div(out, in);
667 int_div = out;
668 t *= 2048;
669 do_div(t, in);
670 frac_div = t;
671 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
672 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
673
674 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
675 if (div2)
676 snd_soc_update_bits(codec,
677 SGTL5000_CHIP_CLK_TOP_CTRL,
678 SGTL5000_INPUT_FREQ_DIV2,
679 SGTL5000_INPUT_FREQ_DIV2);
680 else
681 snd_soc_update_bits(codec,
682 SGTL5000_CHIP_CLK_TOP_CTRL,
683 SGTL5000_INPUT_FREQ_DIV2,
684 0);
685
686 /* power up pll */
687 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
688 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
689 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
e06e4c2d
OS		 690
691 /* if using pll, clk_ctrl must be set after pll power up */
692 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
9b34e6cc 693 } else {
e06e4c2d
OS		 694 /* otherwise, clk_ctrl must be set before pll power down */
695 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
696
9b34e6cc
ZZ		 697 /* power down pll */
698 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
699 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
700 0);
701 }
702
9b34e6cc
ZZ		 703 return 0;
704}
705
706/*
707 * Set PCM DAI bit size and sample rate.
708 * input: params_rate, params_fmt
709 */
710static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
711 struct snd_pcm_hw_params *params,
712 struct snd_soc_dai *dai)
713{
e6968a17 714 struct snd_soc_codec *codec = dai->codec;
9b34e6cc
ZZ		 715 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
716 int channels = params_channels(params);
717 int i2s_ctl = 0;
718 int stereo;
719 int ret;
720
721 /* sysclk should already set */
722 if (!sgtl5000->sysclk) {
723 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
724 return -EFAULT;
725 }
726
727 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
728 stereo = SGTL5000_DAC_STEREO;
729 else
730 stereo = SGTL5000_ADC_STEREO;
731
732 /* set mono to save power */
733 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
734 channels == 1 ? 0 : stereo);
735
736 /* set codec clock base on lrclk */
737 ret = sgtl5000_set_clock(codec, params_rate(params));
738 if (ret)
739 return ret;
740
741 /* set i2s data format */
dacc2aef
MB		 742 switch (params_width(params)) {
743 case 16:
9b34e6cc
ZZ		 744 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
745 return -EINVAL;
746 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
747 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
748 SGTL5000_I2S_SCLKFREQ_SHIFT;
749 break;
dacc2aef 750 case 20:
9b34e6cc
ZZ		 751 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
752 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
753 SGTL5000_I2S_SCLKFREQ_SHIFT;
754 break;
dacc2aef 755 case 24:
9b34e6cc
ZZ		 756 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
757 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
758 SGTL5000_I2S_SCLKFREQ_SHIFT;
759 break;
dacc2aef 760 case 32:
9b34e6cc
ZZ		 761 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
762 return -EINVAL;
763 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
764 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
765 SGTL5000_I2S_SCLKFREQ_SHIFT;
766 break;
767 default:
768 return -EINVAL;
769 }
770
33cb92cf
AL		 771 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
772 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
773 i2s_ctl);
9b34e6cc
ZZ		 774
775 return 0;
776}
777
333802e9 778#ifdef CONFIG_REGULATOR
9b34e6cc
ZZ		 779static int ldo_regulator_is_enabled(struct regulator_dev *dev)
780{
781 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
782
783 return ldo->enabled;
784}
785
786static int ldo_regulator_enable(struct regulator_dev *dev)
787{
788 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
789 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
790 int reg;
791
792 if (ldo_regulator_is_enabled(dev))
793 return 0;
794
795 /* set regulator value firstly */
796 reg = (1600 - ldo->voltage / 1000) / 50;
797 reg = clamp(reg, 0x0, 0xf);
798
799 /* amend the voltage value, unit: uV */
800 ldo->voltage = (1600 - reg * 50) * 1000;
801
802 /* set voltage to register */
803 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 804 SGTL5000_LINREG_VDDD_MASK, reg);
9b34e6cc
ZZ		 805
806 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
807 SGTL5000_LINEREG_D_POWERUP,
808 SGTL5000_LINEREG_D_POWERUP);
809
7f6d75d7 810 /* when internal ldo is enabled, simple digital power can be disabled */
9b34e6cc
ZZ		 811 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
812 SGTL5000_LINREG_SIMPLE_POWERUP,
813 0);
814
815 ldo->enabled = 1;
816 return 0;
817}
818
819static int ldo_regulator_disable(struct regulator_dev *dev)
820{
821 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
822 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
823
824 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
825 SGTL5000_LINEREG_D_POWERUP,
826 0);
827
828 /* clear voltage info */
829 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 830 SGTL5000_LINREG_VDDD_MASK, 0);
9b34e6cc
ZZ		 831
832 ldo->enabled = 0;
833
834 return 0;
835}
836
837static int ldo_regulator_get_voltage(struct regulator_dev *dev)
838{
839 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
840
841 return ldo->voltage;
842}
843
844static struct regulator_ops ldo_regulator_ops = {
845 .is_enabled = ldo_regulator_is_enabled,
846 .enable = ldo_regulator_enable,
847 .disable = ldo_regulator_disable,
848 .get_voltage = ldo_regulator_get_voltage,
849};
850
851static int ldo_regulator_register(struct snd_soc_codec *codec,
852 struct regulator_init_data *init_data,
853 int voltage)
854{
855 struct ldo_regulator *ldo;
5b13de7a 856 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
c172708d 857 struct regulator_config config = { };
9b34e6cc
ZZ		 858
859 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
860
be813334 861 if (!ldo)
9b34e6cc 862 return -ENOMEM;
9b34e6cc
ZZ		 863
864 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
865 if (!ldo->desc.name) {
866 kfree(ldo);
867 dev_err(codec->dev, "failed to allocate decs name memory\n");
868 return -ENOMEM;
869 }
870
871 ldo->desc.type = REGULATOR_VOLTAGE;
872 ldo->desc.owner = THIS_MODULE;
873 ldo->desc.ops = &ldo_regulator_ops;
874 ldo->desc.n_voltages = 1;
875
876 ldo->codec_data = codec;
877 ldo->voltage = voltage;
878
c172708d
MB		 879 config.dev = codec->dev;
880 config.driver_data = ldo;
881 config.init_data = init_data;
882
883 ldo->dev = regulator_register(&ldo->desc, &config);
9b34e6cc 884 if (IS_ERR(ldo->dev)) {
62f75aaf
DC		 885 int ret = PTR_ERR(ldo->dev);
886
9b34e6cc
ZZ		 887 dev_err(codec->dev, "failed to register regulator\n");
888 kfree(ldo->desc.name);
889 kfree(ldo);
890
62f75aaf 891 return ret;
9b34e6cc 892 }
5b13de7a 893 sgtl5000->ldo = ldo;
9b34e6cc
ZZ		 894
895 return 0;
896}
897
898static int ldo_regulator_remove(struct snd_soc_codec *codec)
899{
900 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
901 struct ldo_regulator *ldo = sgtl5000->ldo;
902
903 if (!ldo)
904 return 0;
905
906 regulator_unregister(ldo->dev);
907 kfree(ldo->desc.name);
908 kfree(ldo);
909
910 return 0;
911}
333802e9
MB		 912#else
913static int ldo_regulator_register(struct snd_soc_codec *codec,
914 struct regulator_init_data *init_data,
915 int voltage)
916{
09bddc8e 917 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
333802e9
MB		 918 return -EINVAL;
919}
920
921static int ldo_regulator_remove(struct snd_soc_codec *codec)
922{
923 return 0;
924}
925#endif
9b34e6cc
ZZ		 926
927/*
928 * set dac bias
929 * common state changes:
930 * startup:
931 * off --> standby --> prepare --> on
932 * standby --> prepare --> on
933 *
934 * stop:
935 * on --> prepare --> standby
936 */
937static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
938 enum snd_soc_bias_level level)
939{
940 int ret;
941 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
942
943 switch (level) {
944 case SND_SOC_BIAS_ON:
945 case SND_SOC_BIAS_PREPARE:
946 break;
947 case SND_SOC_BIAS_STANDBY:
948 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
949 ret = regulator_bulk_enable(
950 ARRAY_SIZE(sgtl5000->supplies),
951 sgtl5000->supplies);
952 if (ret)
953 return ret;
954 udelay(10);
2bdc1bb2
MB		 955
956 regcache_cache_only(sgtl5000->regmap, false);
957
958 ret = regcache_sync(sgtl5000->regmap);
959 if (ret != 0) {
960 dev_err(codec->dev,
961 "Failed to restore cache: %d\n", ret);
962
963 regcache_cache_only(sgtl5000->regmap, true);
964 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
965 sgtl5000->supplies);
966
967 return ret;
968 }
9b34e6cc
ZZ		 969 }
970
971 break;
972 case SND_SOC_BIAS_OFF:
2bdc1bb2 973 regcache_cache_only(sgtl5000->regmap, true);
9b34e6cc
ZZ		 974 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
975 sgtl5000->supplies);
976 break;
977 }
978
979 codec->dapm.bias_level = level;
980 return 0;
981}
982
983#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
984 SNDRV_PCM_FMTBIT_S20_3LE |\
985 SNDRV_PCM_FMTBIT_S24_LE |\
986 SNDRV_PCM_FMTBIT_S32_LE)
987
85e7652d 988static const struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 989 .hw_params = sgtl5000_pcm_hw_params,
990 .digital_mute = sgtl5000_digital_mute,
991 .set_fmt = sgtl5000_set_dai_fmt,
992 .set_sysclk = sgtl5000_set_dai_sysclk,
993};
994
995static struct snd_soc_dai_driver sgtl5000_dai = {
996 .name = "sgtl5000",
997 .playback = {
998 .stream_name = "Playback",
999 .channels_min = 1,
1000 .channels_max = 2,
1001 /*
1002 * only support 8~48K + 96K,
1003 * TODO modify hw_param to support more
1004 */
1005 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1006 .formats = SGTL5000_FORMATS,
1007 },
1008 .capture = {
1009 .stream_name = "Capture",
1010 .channels_min = 1,
1011 .channels_max = 2,
1012 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1013 .formats = SGTL5000_FORMATS,
1014 },
1015 .ops = &sgtl5000_ops,
1016 .symmetric_rates = 1,
1017};
1018
e5d80e82 1019static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
9b34e6cc
ZZ		 1020{
1021 switch (reg) {
1022 case SGTL5000_CHIP_ID:
1023 case SGTL5000_CHIP_ADCDAC_CTRL:
1024 case SGTL5000_CHIP_ANA_STATUS:
e5d80e82 1025 return true;
9b34e6cc
ZZ		 1026 }
1027
e5d80e82
FE		 1028 return false;
1029}
1030
1031static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1032{
1033 switch (reg) {
1034 case SGTL5000_CHIP_ID:
1035 case SGTL5000_CHIP_DIG_POWER:
1036 case SGTL5000_CHIP_CLK_CTRL:
1037 case SGTL5000_CHIP_I2S_CTRL:
1038 case SGTL5000_CHIP_SSS_CTRL:
1039 case SGTL5000_CHIP_ADCDAC_CTRL:
1040 case SGTL5000_CHIP_DAC_VOL:
1041 case SGTL5000_CHIP_PAD_STRENGTH:
1042 case SGTL5000_CHIP_ANA_ADC_CTRL:
1043 case SGTL5000_CHIP_ANA_HP_CTRL:
1044 case SGTL5000_CHIP_ANA_CTRL:
1045 case SGTL5000_CHIP_LINREG_CTRL:
1046 case SGTL5000_CHIP_REF_CTRL:
1047 case SGTL5000_CHIP_MIC_CTRL:
1048 case SGTL5000_CHIP_LINE_OUT_CTRL:
1049 case SGTL5000_CHIP_LINE_OUT_VOL:
1050 case SGTL5000_CHIP_ANA_POWER:
1051 case SGTL5000_CHIP_PLL_CTRL:
1052 case SGTL5000_CHIP_CLK_TOP_CTRL:
1053 case SGTL5000_CHIP_ANA_STATUS:
1054 case SGTL5000_CHIP_SHORT_CTRL:
1055 case SGTL5000_CHIP_ANA_TEST2:
1056 case SGTL5000_DAP_CTRL:
1057 case SGTL5000_DAP_PEQ:
1058 case SGTL5000_DAP_BASS_ENHANCE:
1059 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1060 case SGTL5000_DAP_AUDIO_EQ:
1061 case SGTL5000_DAP_SURROUND:
1062 case SGTL5000_DAP_FLT_COEF_ACCESS:
1063 case SGTL5000_DAP_COEF_WR_B0_MSB:
1064 case SGTL5000_DAP_COEF_WR_B0_LSB:
1065 case SGTL5000_DAP_EQ_BASS_BAND0:
1066 case SGTL5000_DAP_EQ_BASS_BAND1:
1067 case SGTL5000_DAP_EQ_BASS_BAND2:
1068 case SGTL5000_DAP_EQ_BASS_BAND3:
1069 case SGTL5000_DAP_EQ_BASS_BAND4:
1070 case SGTL5000_DAP_MAIN_CHAN:
1071 case SGTL5000_DAP_MIX_CHAN:
1072 case SGTL5000_DAP_AVC_CTRL:
1073 case SGTL5000_DAP_AVC_THRESHOLD:
1074 case SGTL5000_DAP_AVC_ATTACK:
1075 case SGTL5000_DAP_AVC_DECAY:
1076 case SGTL5000_DAP_COEF_WR_B1_MSB:
1077 case SGTL5000_DAP_COEF_WR_B1_LSB:
1078 case SGTL5000_DAP_COEF_WR_B2_MSB:
1079 case SGTL5000_DAP_COEF_WR_B2_LSB:
1080 case SGTL5000_DAP_COEF_WR_A1_MSB:
1081 case SGTL5000_DAP_COEF_WR_A1_LSB:
1082 case SGTL5000_DAP_COEF_WR_A2_MSB:
1083 case SGTL5000_DAP_COEF_WR_A2_LSB:
1084 return true;
1085
1086 default:
1087 return false;
1088 }
9b34e6cc
ZZ		 1089}
1090
9b34e6cc
ZZ		 1091/*
1092 * sgtl5000 has 3 internal power supplies:
1093 * 1. VAG, normally set to vdda/2
7f6d75d7 1094 * 2. charge pump, set to different value
9b34e6cc
ZZ		 1095 * according to voltage of vdda and vddio
1096 * 3. line out VAG, normally set to vddio/2
1097 *
1098 * and should be set according to:
1099 * 1. vddd provided by external or not
1100 * 2. vdda and vddio voltage value. > 3.1v or not
1101 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1102 */
1103static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1104{
1105 int vddd;
1106 int vdda;
1107 int vddio;
1108 u16 ana_pwr;
1109 u16 lreg_ctrl;
1110 int vag;
1111 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1112
1113 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1114 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1115 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1116
1117 vdda = vdda / 1000;
1118 vddio = vddio / 1000;
1119 vddd = vddd / 1000;
1120
1121 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1122 dev_err(codec->dev, "regulator voltage not set correctly\n");
1123
1124 return -EINVAL;
1125 }
1126
1127 /* according to datasheet, maximum voltage of supplies */
1128 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1129 dev_err(codec->dev,
cf1ee98d 1130 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
9b34e6cc
ZZ		 1131 vdda, vddio, vddd);
1132
1133 return -EINVAL;
1134 }
1135
1136 /* reset value */
1137 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1138 ana_pwr |= SGTL5000_DAC_STEREO |
1139 SGTL5000_ADC_STEREO |
1140 SGTL5000_REFTOP_POWERUP;
1141 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1142
1143 if (vddio < 3100 && vdda < 3100) {
1144 /* enable internal oscillator used for charge pump */
1145 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1146 SGTL5000_INT_OSC_EN,
1147 SGTL5000_INT_OSC_EN);
1148 /* Enable VDDC charge pump */
1149 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1150 } else if (vddio >= 3100 && vdda >= 3100) {
1151 /*
1152 * if vddio and vddd > 3.1v,
1153 * charge pump should be clean before set ana_pwr
1154 */
1155 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1156 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1157
1158 /* VDDC use VDDIO rail */
1159 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1160 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1161 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1162 }
1163
1164 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1165
1166 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1167
1168 /* set voltage to register */
1169 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 1170 SGTL5000_LINREG_VDDD_MASK, 0x8);
9b34e6cc
ZZ		 1171
1172 /*
1173 * if vddd linear reg has been enabled,
1174 * simple digital supply should be clear to get
1175 * proper VDDD voltage.
1176 */
1177 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1178 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1179 SGTL5000_LINREG_SIMPLE_POWERUP,
1180 0);
1181 else
1182 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1183 SGTL5000_LINREG_SIMPLE_POWERUP |
1184 SGTL5000_STARTUP_POWERUP,
1185 0);
1186
1187 /*
1188 * set ADC/DAC VAG to vdda / 2,
1189 * should stay in range (0.8v, 1.575v)
1190 */
1191 vag = vdda / 2;
1192 if (vag <= SGTL5000_ANA_GND_BASE)
1193 vag = 0;
1194 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1195 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1196 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1197 else
1198 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1199
1200 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
33cb92cf 1201 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
9b34e6cc
ZZ		 1202
1203 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1204 vag = vddio / 2;
1205 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1206 vag = 0;
1207 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1208 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1209 vag = SGTL5000_LINE_OUT_GND_MAX;
1210 else
1211 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1212 SGTL5000_LINE_OUT_GND_STP;
1213
1214 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
33cb92cf
AL		 1215 SGTL5000_LINE_OUT_CURRENT_MASK |
1216 SGTL5000_LINE_OUT_GND_MASK,
9b34e6cc
ZZ		 1217 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1218 SGTL5000_LINE_OUT_CURRENT_360u <<
1219 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1220
1221 return 0;
1222}
1223
e94a4062
WS		 1224static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1225{
1226 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1227 int ret;
1228
1229 /* set internal ldo to 1.2v */
1230 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1231 if (ret) {
1232 dev_err(codec->dev,
1233 "Failed to register vddd internal supplies: %d\n", ret);
1234 return ret;
1235 }
1236
1237 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1238
e94a4062
WS		 1239 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1240 return 0;
1241}
1242
9b34e6cc
ZZ		 1243static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1244{
9b34e6cc 1245 int ret;
9b34e6cc
ZZ		 1246 int i;
1247 int external_vddd = 0;
1248 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
11db0da8 1249 struct regulator *vddd;
9b34e6cc
ZZ		 1250
1251 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1252 sgtl5000->supplies[i].supply = supply_names[i];
1253
11db0da8
SG		 1254 /* External VDDD only works before revision 0x11 */
1255 if (sgtl5000->revision < 0x11) {
1256 vddd = regulator_get_optional(codec->dev, "VDDD");
1257 if (IS_ERR(vddd)) {
1258 /* See if it's just not registered yet */
1259 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1260 return -EPROBE_DEFER;
1261 } else {
1262 external_vddd = 1;
1263 regulator_put(vddd);
1264 }
1265 }
1266
1267 if (!external_vddd) {
e94a4062
WS		 1268 ret = sgtl5000_replace_vddd_with_ldo(codec);
1269 if (ret)
9b34e6cc 1270 return ret;
9b34e6cc
ZZ		 1271 }
1272
e42be7e1 1273 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
11db0da8
SG		 1274 sgtl5000->supplies);
1275 if (ret)
1276 goto err_ldo_remove;
1277
9b34e6cc
ZZ		 1278 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1279 sgtl5000->supplies);
1280 if (ret)
e42be7e1 1281 goto err_regulator_free;
9b34e6cc
ZZ		 1282
1283 /* wait for all power rails bring up */
1284 udelay(10);
1285
9b34e6cc
ZZ		 1286 return 0;
1287
e42be7e1
FE		 1288err_regulator_free:
1289 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1290 sgtl5000->supplies);
11db0da8
SG		 1291err_ldo_remove:
1292 if (!external_vddd)
9b34e6cc
ZZ		 1293 ldo_regulator_remove(codec);
1294 return ret;
1295
1296}
1297
1298static int sgtl5000_probe(struct snd_soc_codec *codec)
1299{
1300 int ret;
1301 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1302
9b34e6cc
ZZ		 1303 ret = sgtl5000_enable_regulators(codec);
1304 if (ret)
1305 return ret;
1306
1307 /* power up sgtl5000 */
1308 ret = sgtl5000_set_power_regs(codec);
1309 if (ret)
1310 goto err;
1311
1312 /* enable small pop, introduce 400ms delay in turning off */
1313 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1314 SGTL5000_SMALL_POP,
1315 SGTL5000_SMALL_POP);
1316
1317 /* disable short cut detector */
1318 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1319
1320 /*
1321 * set i2s as default input of sound switch
1322 * TODO: add sound switch to control and dapm widge.
1323 */
1324 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1325 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1326 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1327 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1328
1329 /* enable dac volume ramp by default */
1330 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1331 SGTL5000_DAC_VOL_RAMP_EN |
1332 SGTL5000_DAC_MUTE_RIGHT |
1333 SGTL5000_DAC_MUTE_LEFT);
1334
1335 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1336
1337 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1338 SGTL5000_HP_ZCD_EN |
1339 SGTL5000_ADC_ZCD_EN);
1340
bd0593f5
JMH		 1341 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1342 SGTL5000_BIAS_R_MASK,
1343 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 1344
1345 /*
1346 * disable DAP
1347 * TODO:
1348 * Enable DAP in kcontrol and dapm.
1349 */
1350 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1351
9b34e6cc
ZZ		 1352 return 0;
1353
1354err:
1355 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1356 sgtl5000->supplies);
e42be7e1
FE		 1357 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1358 sgtl5000->supplies);
9b34e6cc
ZZ		 1359 ldo_regulator_remove(codec);
1360
1361 return ret;
1362}
1363
1364static int sgtl5000_remove(struct snd_soc_codec *codec)
1365{
1366 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1367
9b34e6cc
ZZ		 1368 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1369 sgtl5000->supplies);
e42be7e1
FE		 1370 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1371 sgtl5000->supplies);
9b34e6cc
ZZ		 1372 ldo_regulator_remove(codec);
1373
1374 return 0;
1375}
1376
61a142b7 1377static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1378 .probe = sgtl5000_probe,
1379 .remove = sgtl5000_remove,
9b34e6cc 1380 .set_bias_level = sgtl5000_set_bias_level,
e649057a 1381 .suspend_bias_off = true,
89989637
FE		 1382 .controls = sgtl5000_snd_controls,
1383 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
5e0ac527
MB		 1384 .dapm_widgets = sgtl5000_dapm_widgets,
1385 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1386 .dapm_routes = sgtl5000_dapm_routes,
1387 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
9b34e6cc
ZZ		 1388};
1389
e5d80e82
FE		 1390static const struct regmap_config sgtl5000_regmap = {
1391 .reg_bits = 16,
1392 .val_bits = 16,
cb23e852 1393 .reg_stride = 2,
e5d80e82
FE		 1394
1395 .max_register = SGTL5000_MAX_REG_OFFSET,
1396 .volatile_reg = sgtl5000_volatile,
1397 .readable_reg = sgtl5000_readable,
1398
1399 .cache_type = REGCACHE_RBTREE,
1400 .reg_defaults = sgtl5000_reg_defaults,
1401 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1402};
1403
af8ee112
FE		 1404/*
1405 * Write all the default values from sgtl5000_reg_defaults[] array into the
1406 * sgtl5000 registers, to make sure we always start with the sane registers
1407 * values as stated in the datasheet.
1408 *
1409 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1410 * we follow this approach to guarantee we always start from the default values
1411 * and avoid problems like, not being able to probe after an audio playback
1412 * followed by a system reset or a 'reboot' command in Linux
1413 */
1414static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
1415{
1416 int i, ret, val, index;
1417
1418 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1419 val = sgtl5000_reg_defaults[i].def;
1420 index = sgtl5000_reg_defaults[i].reg;
1421 ret = regmap_write(sgtl5000->regmap, index, val);
1422 if (ret)
1423 return ret;
1424 }
1425
1426 return 0;
1427}
1428
7a79e94e
BP		 1429static int sgtl5000_i2c_probe(struct i2c_client *client,
1430 const struct i2c_device_id *id)
9b34e6cc
ZZ		 1431{
1432 struct sgtl5000_priv *sgtl5000;
b871f1ad 1433 int ret, reg, rev;
6f4d2b31 1434 unsigned int mclk;
bd0593f5
JMH		 1435 struct device_node *np = client->dev.of_node;
1436 u32 value;
9b34e6cc 1437
512fa7c4
FE		 1438 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
1439 GFP_KERNEL);
9b34e6cc
ZZ		 1440 if (!sgtl5000)
1441 return -ENOMEM;
1442
e5d80e82
FE		 1443 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1444 if (IS_ERR(sgtl5000->regmap)) {
1445 ret = PTR_ERR(sgtl5000->regmap);
1446 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1447 return ret;
1448 }
1449
9e13f345
FE		 1450 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1451 if (IS_ERR(sgtl5000->mclk)) {
1452 ret = PTR_ERR(sgtl5000->mclk);
1453 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
46a5905e
SG		 1454 /* Defer the probe to see if the clk will be provided later */
1455 if (ret == -ENOENT)
1456 return -EPROBE_DEFER;
9e13f345
FE		 1457 return ret;
1458 }
1459
6f4d2b31
FE		 1460 /* SGTL5000 SYS_MCLK should be between 8 and 27 MHz */
1461 mclk = clk_get_rate(sgtl5000->mclk);
1462 if (mclk < 8000000 || mclk > 27000000) {
1463 dev_err(&client->dev, "Invalid SYS_CLK frequency: %u.%03uMHz\n",
1464 mclk / 1000000, mclk / 1000 % 1000);
1465 return -EINVAL;
1466 }
1467
9e13f345
FE		 1468 ret = clk_prepare_enable(sgtl5000->mclk);
1469 if (ret)
1470 return ret;
1471
b871f1ad
FE		 1472 /* read chip information */
1473 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1474 if (ret)
9e13f345 1475 goto disable_clk;
b871f1ad
FE		 1476
1477 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1478 SGTL5000_PARTID_PART_ID) {
1479 dev_err(&client->dev,
1480 "Device with ID register %x is not a sgtl5000\n", reg);
9e13f345
FE		 1481 ret = -ENODEV;
1482 goto disable_clk;
b871f1ad
FE		 1483 }
1484
1485 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1486 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
252e91ff 1487 sgtl5000->revision = rev;
b871f1ad 1488
bd0593f5
JMH		 1489 if (np) {
1490 if (!of_property_read_u32(np,
1491 "micbias-resistor-k-ohms", &value)) {
1492 switch (value) {
1493 case SGTL5000_MICBIAS_OFF:
1494 sgtl5000->micbias_resistor = 0;
1495 break;
1496 case SGTL5000_MICBIAS_2K:
1497 sgtl5000->micbias_resistor = 1;
1498 break;
1499 case SGTL5000_MICBIAS_4K:
1500 sgtl5000->micbias_resistor = 2;
1501 break;
1502 case SGTL5000_MICBIAS_8K:
1503 sgtl5000->micbias_resistor = 3;
1504 break;
1505 default:
1506 sgtl5000->micbias_resistor = 2;
1507 dev_err(&client->dev,
1508 "Unsuitable MicBias resistor\n");
1509 }
1510 } else {
1511 /* default is 4Kohms */
1512 sgtl5000->micbias_resistor = 2;
1513 }
1514 dev_err(&client->dev,
1515 "Unsuitable MicBias resistor\n");
1516 }
1517 } else {
1518 }
1519 }
1520
9b34e6cc
ZZ		 1521 i2c_set_clientdata(client, sgtl5000);
1522
af8ee112
FE		 1523 /* Ensure sgtl5000 will start with sane register values */
1524 ret = sgtl5000_fill_defaults(sgtl5000);
1525 if (ret)
9e13f345 1526 goto disable_clk;
af8ee112 1527
9b34e6cc
ZZ		 1528 ret = snd_soc_register_codec(&client->dev,
1529 &sgtl5000_driver, &sgtl5000_dai, 1);
9e13f345
FE		 1530 if (ret)
1531 goto disable_clk;
1532
1533 return 0;
1534
1535disable_clk:
1536 clk_disable_unprepare(sgtl5000->mclk);
512fa7c4 1537 return ret;
9b34e6cc
ZZ		 1538}
1539
7a79e94e 1540static int sgtl5000_i2c_remove(struct i2c_client *client)
9b34e6cc 1541{
7c647af4 1542 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc 1543
9e13f345
FE		 1544 snd_soc_unregister_codec(&client->dev);
1545 clk_disable_unprepare(sgtl5000->mclk);
9b34e6cc
ZZ		 1546 return 0;
1547}
1548
1549static const struct i2c_device_id sgtl5000_id[] = {
1550 {"sgtl5000", 0},
1551 {},
1552};
1553
1554MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1555
58e49424
SG		 1556static const struct of_device_id sgtl5000_dt_ids[] = {
1557 { .compatible = "fsl,sgtl5000", },
1558 { /* sentinel */ }
1559};
4c54c6de 1560MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1561
9b34e6cc
ZZ		 1562static struct i2c_driver sgtl5000_i2c_driver = {
1563 .driver = {
1564 .name = "sgtl5000",
1565 .owner = THIS_MODULE,
58e49424 1566 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1567 },
1568 .probe = sgtl5000_i2c_probe,
7a79e94e 1569 .remove = sgtl5000_i2c_remove,
9b34e6cc
ZZ		 1570 .id_table = sgtl5000_id,
1571};
1572
67d45090 1573module_i2c_driver(sgtl5000_i2c_driver);
9b34e6cc
ZZ		 1574
1575MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
f7cb8a4b 1576MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
9b34e6cc 1577MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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