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ASoC: sgtl5000: Write all default registers
[deliverable/linux.git] / sound / soc / codecs / sgtl5000.c
CommitLineData
9b34e6cc
ZZ		 1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
bd0593f5 19#include <linux/log2.h>
e5d80e82 20#include <linux/regmap.h>
9b34e6cc
ZZ		 21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/regulator/consumer.h>
58e49424 24#include <linux/of_device.h>
9b34e6cc
ZZ		 25#include <sound/core.h>
26#include <sound/tlv.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
9b34e6cc
ZZ		 32
33#include "sgtl5000.h"
34
35#define SGTL5000_DAP_REG_OFFSET 0x0100
36#define SGTL5000_MAX_REG_OFFSET 0x013A
37
151798f8 38/* default value of sgtl5000 registers */
e5d80e82 39static const struct reg_default sgtl5000_reg_defaults[] = {
29aa37cd 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
e5d80e82
FE		 41 { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
42 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
016fcab8 43 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
29aa37cd 44 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
e5d80e82
FE		 45 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
46 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
29aa37cd 47 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
e5d80e82
FE		 48 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
49 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
29aa37cd
FE		 50 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
51 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
52 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
53 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
e5d80e82
FE		 54 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
55 { SGTL5000_CHIP_ANA_POWER, 0x7060 },
56 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
29aa37cd
FE		 57 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
58 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
59 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
60 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
61 { SGTL5000_DAP_CTRL, 0x0000 },
62 { SGTL5000_DAP_PEQ, 0x0000 },
e5d80e82
FE		 63 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
64 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
29aa37cd 65 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
e5d80e82
FE		 66 { SGTL5000_DAP_SURROUND, 0x0040 },
67 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
69 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
70 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
71 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
72 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
29aa37cd 73 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
e5d80e82
FE		 74 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
75 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
76 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
77 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
9b34e6cc
ZZ		 78};
79
80/* regulator supplies for sgtl5000, VDDD is an optional external supply */
81enum sgtl5000_regulator_supplies {
82 VDDA,
83 VDDIO,
84 VDDD,
85 SGTL5000_SUPPLY_NUM
86};
87
88/* vddd is optional supply */
89static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
90 "VDDA",
91 "VDDIO",
92 "VDDD"
93};
94
9b34e6cc
ZZ		 95#define LDO_VOLTAGE 1200000
96
bd0593f5
JMH		 97enum sgtl5000_micbias_resistor {
98 SGTL5000_MICBIAS_OFF = 0,
99 SGTL5000_MICBIAS_2K = 2,
100 SGTL5000_MICBIAS_4K = 4,
101 SGTL5000_MICBIAS_8K = 8,
102};
103
9b34e6cc
ZZ		 104/* sgtl5000 private structure in codec */
105struct sgtl5000_priv {
106 int sysclk; /* sysclk rate */
107 int master; /* i2s master or not */
108 int fmt; /* i2s data format */
109 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
940adb28 110 int num_supplies;
e5d80e82 111 struct regmap *regmap;
9e13f345 112 struct clk *mclk;
252e91ff 113 int revision;
bd0593f5 114 u8 micbias_resistor;
87357797 115 u8 micbias_voltage;
9b34e6cc
ZZ		 116};
117
118/*
119 * mic_bias power on/off share the same register bits with
120 * output impedance of mic bias, when power on mic bias, we
121 * need reclaim it to impedance value.
122 * 0x0 = Powered off
123 * 0x1 = 2Kohm
124 * 0x2 = 4Kohm
125 * 0x3 = 8Kohm
126 */
127static int mic_bias_event(struct snd_soc_dapm_widget *w,
128 struct snd_kcontrol *kcontrol, int event)
129{
73bffd17
LPC		 130 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
131 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
bd0593f5 132
9b34e6cc
ZZ		 133 switch (event) {
134 case SND_SOC_DAPM_POST_PMU:
bd0593f5 135 /* change mic bias resistor */
73bffd17 136 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
bd0593f5
JMH		 137 SGTL5000_BIAS_R_MASK,
138 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc
ZZ		 139 break;
140
141 case SND_SOC_DAPM_PRE_PMD:
73bffd17 142 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
dc56c5a8 143 SGTL5000_BIAS_R_MASK, 0);
9b34e6cc
ZZ		 144 break;
145 }
146 return 0;
147}
148
149/*
f0cdcf3a
ZZ		 150 * As manual described, ADC/DAC only works when VAG powerup,
151 * So enabled VAG before ADC/DAC up.
152 * In power down case, we need wait 400ms when vag fully ramped down.
9b34e6cc 153 */
f0cdcf3a 154static int power_vag_event(struct snd_soc_dapm_widget *w,
9b34e6cc
ZZ		 155 struct snd_kcontrol *kcontrol, int event)
156{
73bffd17 157 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
f091f3f0
LW		 158 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
159
9b34e6cc 160 switch (event) {
dd4d2d6d 161 case SND_SOC_DAPM_POST_PMU:
73bffd17 162 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
9b34e6cc 163 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
c803cc2d 164 msleep(400);
9b34e6cc
ZZ		 165 break;
166
dd4d2d6d 167 case SND_SOC_DAPM_PRE_PMD:
f091f3f0
LW		 168 /*
169 * Don't clear VAG_POWERUP, when both DAC and ADC are
170 * operational to prevent inadvertently starving the
171 * other one of them.
172 */
73bffd17 173 if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) &
f091f3f0 174 mask) != mask) {
73bffd17 175 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
f091f3f0
LW		 176 SGTL5000_VAG_POWERUP, 0);
177 msleep(400);
178 }
9b34e6cc
ZZ		 179 break;
180 default:
181 break;
182 }
183
184 return 0;
185}
186
187/* input sources for ADC */
188static const char *adc_mux_text[] = {
189 "MIC_IN", "LINE_IN"
190};
191
c8ed6504
TI		 192static SOC_ENUM_SINGLE_DECL(adc_enum,
193 SGTL5000_CHIP_ANA_CTRL, 2,
194 adc_mux_text);
9b34e6cc
ZZ		 195
196static const struct snd_kcontrol_new adc_mux =
197SOC_DAPM_ENUM("Capture Mux", adc_enum);
198
199/* input sources for DAC */
200static const char *dac_mux_text[] = {
201 "DAC", "LINE_IN"
202};
203
c8ed6504
TI		 204static SOC_ENUM_SINGLE_DECL(dac_enum,
205 SGTL5000_CHIP_ANA_CTRL, 6,
206 dac_mux_text);
9b34e6cc
ZZ		 207
208static const struct snd_kcontrol_new dac_mux =
209SOC_DAPM_ENUM("Headphone Mux", dac_enum);
210
211static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
212 SND_SOC_DAPM_INPUT("LINE_IN"),
213 SND_SOC_DAPM_INPUT("MIC_IN"),
214
215 SND_SOC_DAPM_OUTPUT("HP_OUT"),
216 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
217
8fc8ec92
MB		 218 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
219 mic_bias_event,
220 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9b34e6cc 221
f0cdcf3a
ZZ		 222 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
223 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
9b34e6cc
ZZ		 224
225 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
226 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
227
228 /* aif for i2s input */
229 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
230 0, SGTL5000_CHIP_DIG_POWER,
231 0, 0),
232
233 /* aif for i2s output */
234 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
235 0, SGTL5000_CHIP_DIG_POWER,
236 1, 0),
237
f0cdcf3a 238 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
9b34e6cc 239 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
dd4d2d6d
MV		 240
241 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
242 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
9b34e6cc
ZZ		 243};
244
245/* routes for sgtl5000 */
89989637 246static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
9b34e6cc
ZZ		 247 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
248 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
249
250 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
251 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
252
253 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
254 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
255 {"LO", NULL, "DAC"}, /* dac --> line_out */
256
257 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
258 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
259
260 {"LINE_OUT", NULL, "LO"},
261 {"HP_OUT", NULL, "HP"},
262};
263
264/* custom function to fetch info of PCM playback volume */
265static int dac_info_volsw(struct snd_kcontrol *kcontrol,
266 struct snd_ctl_elem_info *uinfo)
267{
268 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
269 uinfo->count = 2;
270 uinfo->value.integer.min = 0;
271 uinfo->value.integer.max = 0xfc - 0x3c;
272 return 0;
273}
274
275/*
276 * custom function to get of PCM playback volume
277 *
278 * dac volume register
279 * 15-------------8-7--------------0
280 * | R channel vol | L channel vol |
281 * -------------------------------
282 *
283 * PCM volume with 0.5017 dB steps from 0 to -90 dB
284 *
285 * register values map to dB
286 * 0x3B and less = Reserved
287 * 0x3C = 0 dB
288 * 0x3D = -0.5 dB
289 * 0xF0 = -90 dB
290 * 0xFC and greater = Muted
291 *
292 * register value map to userspace value
293 *
294 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
295 * ------------------------------
296 * userspace value 0xc0 0
297 */
298static int dac_get_volsw(struct snd_kcontrol *kcontrol,
299 struct snd_ctl_elem_value *ucontrol)
300{
ea53bf77 301 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 302 int reg;
303 int l;
304 int r;
305
306 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
307
308 /* get left channel volume */
309 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
310
311 /* get right channel volume */
312 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
313
314 /* make sure value fall in (0x3c,0xfc) */
315 l = clamp(l, 0x3c, 0xfc);
316 r = clamp(r, 0x3c, 0xfc);
317
318 /* invert it and map to userspace value */
319 l = 0xfc - l;
320 r = 0xfc - r;
321
322 ucontrol->value.integer.value[0] = l;
323 ucontrol->value.integer.value[1] = r;
324
325 return 0;
326}
327
328/*
329 * custom function to put of PCM playback volume
330 *
331 * dac volume register
332 * 15-------------8-7--------------0
333 * | R channel vol | L channel vol |
334 * -------------------------------
335 *
336 * PCM volume with 0.5017 dB steps from 0 to -90 dB
337 *
338 * register values map to dB
339 * 0x3B and less = Reserved
340 * 0x3C = 0 dB
341 * 0x3D = -0.5 dB
342 * 0xF0 = -90 dB
343 * 0xFC and greater = Muted
344 *
345 * userspace value map to register value
346 *
347 * userspace value 0xc0 0
348 * ------------------------------
349 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
350 */
351static int dac_put_volsw(struct snd_kcontrol *kcontrol,
352 struct snd_ctl_elem_value *ucontrol)
353{
ea53bf77 354 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
9b34e6cc
ZZ		 355 int reg;
356 int l;
357 int r;
358
359 l = ucontrol->value.integer.value[0];
360 r = ucontrol->value.integer.value[1];
361
362 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
363 l = clamp(l, 0, 0xfc - 0x3c);
364 r = clamp(r, 0, 0xfc - 0x3c);
365
366 /* invert it, get the value can be set to register */
367 l = 0xfc - l;
368 r = 0xfc - r;
369
370 /* shift to get the register value */
371 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
372 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
373
374 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
375
376 return 0;
377}
378
379static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
380
381/* tlv for mic gain, 0db 20db 30db 40db */
53eb1ca3 382static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
9b34e6cc 383 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
53eb1ca3
LPC		 384 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
385);
9b34e6cc
ZZ		 386
387/* tlv for hp volume, -51.5db to 12.0db, step .5db */
388static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
389
390static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
391 /* SOC_DOUBLE_S8_TLV with invert */
392 {
393 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
394 .name = "PCM Playback Volume",
395 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
396 SNDRV_CTL_ELEM_ACCESS_READWRITE,
397 .info = dac_info_volsw,
398 .get = dac_get_volsw,
399 .put = dac_put_volsw,
400 },
401
402 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
403 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
404 SGTL5000_CHIP_ANA_ADC_CTRL,
65f2b226 405 8, 1, 0, capture_6db_attenuate),
9b34e6cc
ZZ		 406 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
407
408 SOC_DOUBLE_TLV("Headphone Playback Volume",
409 SGTL5000_CHIP_ANA_HP_CTRL,
410 0, 8,
411 0x7f, 1,
412 headphone_volume),
413 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
414 5, 1, 0),
415
416 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
b50684da 417 0, 3, 0, mic_gain_tlv),
9b34e6cc
ZZ		 418};
419
420/* mute the codec used by alsa core */
421static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
422{
423 struct snd_soc_codec *codec = codec_dai->codec;
424 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
425
426 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
427 adcdac_ctrl, mute ? adcdac_ctrl : 0);
428
429 return 0;
430}
431
432/* set codec format */
433static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
434{
435 struct snd_soc_codec *codec = codec_dai->codec;
436 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
437 u16 i2sctl = 0;
438
439 sgtl5000->master = 0;
440 /*
441 * i2s clock and frame master setting.
442 * ONLY support:
443 * - clock and frame slave,
444 * - clock and frame master
445 */
446 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
447 case SND_SOC_DAIFMT_CBS_CFS:
448 break;
449 case SND_SOC_DAIFMT_CBM_CFM:
450 i2sctl |= SGTL5000_I2S_MASTER;
451 sgtl5000->master = 1;
452 break;
453 default:
454 return -EINVAL;
455 }
456
457 /* setting i2s data format */
458 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
459 case SND_SOC_DAIFMT_DSP_A:
9ee802ec 460 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 461 break;
462 case SND_SOC_DAIFMT_DSP_B:
9ee802ec 463 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 464 i2sctl |= SGTL5000_I2S_LRALIGN;
465 break;
466 case SND_SOC_DAIFMT_I2S:
9ee802ec 467 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 468 break;
469 case SND_SOC_DAIFMT_RIGHT_J:
9ee802ec 470 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 471 i2sctl |= SGTL5000_I2S_LRPOL;
472 break;
473 case SND_SOC_DAIFMT_LEFT_J:
9ee802ec 474 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
9b34e6cc
ZZ		 475 i2sctl |= SGTL5000_I2S_LRALIGN;
476 break;
477 default:
478 return -EINVAL;
479 }
480
481 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
482
483 /* Clock inversion */
484 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
485 case SND_SOC_DAIFMT_NB_NF:
486 break;
487 case SND_SOC_DAIFMT_IB_NF:
488 i2sctl |= SGTL5000_I2S_SCLK_INV;
489 break;
490 default:
491 return -EINVAL;
492 }
493
494 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
495
496 return 0;
497}
498
499/* set codec sysclk */
500static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
501 int clk_id, unsigned int freq, int dir)
502{
503 struct snd_soc_codec *codec = codec_dai->codec;
504 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
505
506 switch (clk_id) {
507 case SGTL5000_SYSCLK:
508 sgtl5000->sysclk = freq;
509 break;
510 default:
511 return -EINVAL;
512 }
513
514 return 0;
515}
516
517/*
518 * set clock according to i2s frame clock,
7f6d75d7
FE		 519 * sgtl5000 provides 2 clock sources:
520 * 1. sys_mclk: sample freq can only be configured to
9b34e6cc 521 * 1/256, 1/384, 1/512 of sys_mclk.
7f6d75d7 522 * 2. pll: can derive any audio clocks.
9b34e6cc
ZZ		 523 *
524 * clock setting rules:
7f6d75d7
FE		 525 * 1. in slave mode, only sys_mclk can be used
526 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
527 * and above.
528 * 3. usage of sys_mclk is preferred over pll to save power.
9b34e6cc
ZZ		 529 */
530static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
531{
532 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
533 int clk_ctl = 0;
534 int sys_fs; /* sample freq */
535
536 /*
537 * sample freq should be divided by frame clock,
7f6d75d7
FE		 538 * if frame clock is lower than 44.1 kHz, sample freq should be set to
539 * 32 kHz or 44.1 kHz.
9b34e6cc
ZZ		 540 */
541 switch (frame_rate) {
542 case 8000:
543 case 16000:
544 sys_fs = 32000;
545 break;
546 case 11025:
547 case 22050:
548 sys_fs = 44100;
549 break;
550 default:
551 sys_fs = frame_rate;
552 break;
553 }
554
555 /* set divided factor of frame clock */
556 switch (sys_fs / frame_rate) {
557 case 4:
558 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
559 break;
560 case 2:
561 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
562 break;
563 case 1:
564 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
565 break;
566 default:
567 return -EINVAL;
568 }
569
570 /* set the sys_fs according to frame rate */
571 switch (sys_fs) {
572 case 32000:
573 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
574 break;
575 case 44100:
576 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
577 break;
578 case 48000:
579 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
580 break;
581 case 96000:
582 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
583 break;
584 default:
585 dev_err(codec->dev, "frame rate %d not supported\n",
586 frame_rate);
587 return -EINVAL;
588 }
589
590 /*
591 * calculate the divider of mclk/sample_freq,
7f6d75d7
FE		 592 * factor of freq = 96 kHz can only be 256, since mclk is in the range
593 * of 8 MHz - 27 MHz
9b34e6cc 594 */
2a4cfd10 595 switch (sgtl5000->sysclk / frame_rate) {
9b34e6cc
ZZ		 596 case 256:
597 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
598 SGTL5000_MCLK_FREQ_SHIFT;
599 break;
600 case 384:
601 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
602 SGTL5000_MCLK_FREQ_SHIFT;
603 break;
604 case 512:
605 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
606 SGTL5000_MCLK_FREQ_SHIFT;
607 break;
608 default:
7f6d75d7 609 /* if mclk does not satisfy the divider, use pll */
9b34e6cc
ZZ		 610 if (sgtl5000->master) {
611 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
612 SGTL5000_MCLK_FREQ_SHIFT;
613 } else {
614 dev_err(codec->dev,
615 "PLL not supported in slave mode\n");
fa558d01
FE		 616 dev_err(codec->dev, "%d ratio is not supported. "
617 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
2a4cfd10 618 sgtl5000->sysclk / frame_rate);
9b34e6cc
ZZ		 619 return -EINVAL;
620 }
621 }
622
623 /* if using pll, please check manual 6.4.2 for detail */
624 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
625 u64 out, t;
626 int div2;
627 int pll_ctl;
628 unsigned int in, int_div, frac_div;
629
630 if (sgtl5000->sysclk > 17000000) {
631 div2 = 1;
632 in = sgtl5000->sysclk / 2;
633 } else {
634 div2 = 0;
635 in = sgtl5000->sysclk;
636 }
637 if (sys_fs == 44100)
638 out = 180633600;
639 else
640 out = 196608000;
641 t = do_div(out, in);
642 int_div = out;
643 t *= 2048;
644 do_div(t, in);
645 frac_div = t;
646 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
647 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
648
649 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
650 if (div2)
651 snd_soc_update_bits(codec,
652 SGTL5000_CHIP_CLK_TOP_CTRL,
653 SGTL5000_INPUT_FREQ_DIV2,
654 SGTL5000_INPUT_FREQ_DIV2);
655 else
656 snd_soc_update_bits(codec,
657 SGTL5000_CHIP_CLK_TOP_CTRL,
658 SGTL5000_INPUT_FREQ_DIV2,
659 0);
660
661 /* power up pll */
662 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
663 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
664 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
e06e4c2d
OS		 665
666 /* if using pll, clk_ctrl must be set after pll power up */
667 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
9b34e6cc 668 } else {
e06e4c2d
OS		 669 /* otherwise, clk_ctrl must be set before pll power down */
670 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
671
9b34e6cc
ZZ		 672 /* power down pll */
673 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
674 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
675 0);
676 }
677
9b34e6cc
ZZ		 678 return 0;
679}
680
681/*
682 * Set PCM DAI bit size and sample rate.
683 * input: params_rate, params_fmt
684 */
685static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
686 struct snd_pcm_hw_params *params,
687 struct snd_soc_dai *dai)
688{
e6968a17 689 struct snd_soc_codec *codec = dai->codec;
9b34e6cc
ZZ		 690 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
691 int channels = params_channels(params);
692 int i2s_ctl = 0;
693 int stereo;
694 int ret;
695
696 /* sysclk should already set */
697 if (!sgtl5000->sysclk) {
698 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
699 return -EFAULT;
700 }
701
702 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
703 stereo = SGTL5000_DAC_STEREO;
704 else
705 stereo = SGTL5000_ADC_STEREO;
706
707 /* set mono to save power */
708 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
709 channels == 1 ? 0 : stereo);
710
711 /* set codec clock base on lrclk */
712 ret = sgtl5000_set_clock(codec, params_rate(params));
713 if (ret)
714 return ret;
715
716 /* set i2s data format */
dacc2aef
MB		 717 switch (params_width(params)) {
718 case 16:
9b34e6cc
ZZ		 719 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
720 return -EINVAL;
721 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
722 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
723 SGTL5000_I2S_SCLKFREQ_SHIFT;
724 break;
dacc2aef 725 case 20:
9b34e6cc
ZZ		 726 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
727 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
728 SGTL5000_I2S_SCLKFREQ_SHIFT;
729 break;
dacc2aef 730 case 24:
9b34e6cc
ZZ		 731 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
732 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
733 SGTL5000_I2S_SCLKFREQ_SHIFT;
734 break;
dacc2aef 735 case 32:
9b34e6cc
ZZ		 736 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
737 return -EINVAL;
738 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
739 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
740 SGTL5000_I2S_SCLKFREQ_SHIFT;
741 break;
742 default:
743 return -EINVAL;
744 }
745
33cb92cf
AL		 746 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
747 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
748 i2s_ctl);
9b34e6cc
ZZ		 749
750 return 0;
751}
752
9b34e6cc
ZZ		 753/*
754 * set dac bias
755 * common state changes:
756 * startup:
757 * off --> standby --> prepare --> on
758 * standby --> prepare --> on
759 *
760 * stop:
761 * on --> prepare --> standby
762 */
763static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
764 enum snd_soc_bias_level level)
765{
766 int ret;
767 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
768
769 switch (level) {
770 case SND_SOC_BIAS_ON:
771 case SND_SOC_BIAS_PREPARE:
772 break;
773 case SND_SOC_BIAS_STANDBY:
8533eb24 774 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
9b34e6cc 775 ret = regulator_bulk_enable(
940adb28 776 sgtl5000->num_supplies,
9b34e6cc
ZZ		 777 sgtl5000->supplies);
778 if (ret)
779 return ret;
780 udelay(10);
2bdc1bb2
MB		 781
782 regcache_cache_only(sgtl5000->regmap, false);
783
784 ret = regcache_sync(sgtl5000->regmap);
785 if (ret != 0) {
786 dev_err(codec->dev,
787 "Failed to restore cache: %d\n", ret);
788
789 regcache_cache_only(sgtl5000->regmap, true);
940adb28 790 regulator_bulk_disable(sgtl5000->num_supplies,
2bdc1bb2
MB		 791 sgtl5000->supplies);
792
793 return ret;
794 }
9b34e6cc
ZZ		 795 }
796
797 break;
798 case SND_SOC_BIAS_OFF:
2bdc1bb2 799 regcache_cache_only(sgtl5000->regmap, true);
940adb28
EN		 800 regulator_bulk_disable(sgtl5000->num_supplies,
801 sgtl5000->supplies);
9b34e6cc
ZZ		 802 break;
803 }
804
9b34e6cc
ZZ		 805 return 0;
806}
807
808#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
809 SNDRV_PCM_FMTBIT_S20_3LE |\
810 SNDRV_PCM_FMTBIT_S24_LE |\
811 SNDRV_PCM_FMTBIT_S32_LE)
812
85e7652d 813static const struct snd_soc_dai_ops sgtl5000_ops = {
9b34e6cc
ZZ		 814 .hw_params = sgtl5000_pcm_hw_params,
815 .digital_mute = sgtl5000_digital_mute,
816 .set_fmt = sgtl5000_set_dai_fmt,
817 .set_sysclk = sgtl5000_set_dai_sysclk,
818};
819
820static struct snd_soc_dai_driver sgtl5000_dai = {
821 .name = "sgtl5000",
822 .playback = {
823 .stream_name = "Playback",
824 .channels_min = 1,
825 .channels_max = 2,
826 /*
827 * only support 8~48K + 96K,
828 * TODO modify hw_param to support more
829 */
830 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
831 .formats = SGTL5000_FORMATS,
832 },
833 .capture = {
834 .stream_name = "Capture",
835 .channels_min = 1,
836 .channels_max = 2,
837 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
838 .formats = SGTL5000_FORMATS,
839 },
840 .ops = &sgtl5000_ops,
841 .symmetric_rates = 1,
842};
843
e5d80e82 844static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
9b34e6cc
ZZ		 845{
846 switch (reg) {
847 case SGTL5000_CHIP_ID:
848 case SGTL5000_CHIP_ADCDAC_CTRL:
849 case SGTL5000_CHIP_ANA_STATUS:
e5d80e82 850 return true;
9b34e6cc
ZZ		 851 }
852
e5d80e82
FE		 853 return false;
854}
855
856static bool sgtl5000_readable(struct device *dev, unsigned int reg)
857{
858 switch (reg) {
859 case SGTL5000_CHIP_ID:
860 case SGTL5000_CHIP_DIG_POWER:
861 case SGTL5000_CHIP_CLK_CTRL:
862 case SGTL5000_CHIP_I2S_CTRL:
863 case SGTL5000_CHIP_SSS_CTRL:
864 case SGTL5000_CHIP_ADCDAC_CTRL:
865 case SGTL5000_CHIP_DAC_VOL:
866 case SGTL5000_CHIP_PAD_STRENGTH:
867 case SGTL5000_CHIP_ANA_ADC_CTRL:
868 case SGTL5000_CHIP_ANA_HP_CTRL:
869 case SGTL5000_CHIP_ANA_CTRL:
870 case SGTL5000_CHIP_LINREG_CTRL:
871 case SGTL5000_CHIP_REF_CTRL:
872 case SGTL5000_CHIP_MIC_CTRL:
873 case SGTL5000_CHIP_LINE_OUT_CTRL:
874 case SGTL5000_CHIP_LINE_OUT_VOL:
875 case SGTL5000_CHIP_ANA_POWER:
876 case SGTL5000_CHIP_PLL_CTRL:
877 case SGTL5000_CHIP_CLK_TOP_CTRL:
878 case SGTL5000_CHIP_ANA_STATUS:
879 case SGTL5000_CHIP_SHORT_CTRL:
880 case SGTL5000_CHIP_ANA_TEST2:
881 case SGTL5000_DAP_CTRL:
882 case SGTL5000_DAP_PEQ:
883 case SGTL5000_DAP_BASS_ENHANCE:
884 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
885 case SGTL5000_DAP_AUDIO_EQ:
886 case SGTL5000_DAP_SURROUND:
887 case SGTL5000_DAP_FLT_COEF_ACCESS:
888 case SGTL5000_DAP_COEF_WR_B0_MSB:
889 case SGTL5000_DAP_COEF_WR_B0_LSB:
890 case SGTL5000_DAP_EQ_BASS_BAND0:
891 case SGTL5000_DAP_EQ_BASS_BAND1:
892 case SGTL5000_DAP_EQ_BASS_BAND2:
893 case SGTL5000_DAP_EQ_BASS_BAND3:
894 case SGTL5000_DAP_EQ_BASS_BAND4:
895 case SGTL5000_DAP_MAIN_CHAN:
896 case SGTL5000_DAP_MIX_CHAN:
897 case SGTL5000_DAP_AVC_CTRL:
898 case SGTL5000_DAP_AVC_THRESHOLD:
899 case SGTL5000_DAP_AVC_ATTACK:
900 case SGTL5000_DAP_AVC_DECAY:
901 case SGTL5000_DAP_COEF_WR_B1_MSB:
902 case SGTL5000_DAP_COEF_WR_B1_LSB:
903 case SGTL5000_DAP_COEF_WR_B2_MSB:
904 case SGTL5000_DAP_COEF_WR_B2_LSB:
905 case SGTL5000_DAP_COEF_WR_A1_MSB:
906 case SGTL5000_DAP_COEF_WR_A1_LSB:
907 case SGTL5000_DAP_COEF_WR_A2_MSB:
908 case SGTL5000_DAP_COEF_WR_A2_LSB:
909 return true;
910
911 default:
912 return false;
913 }
9b34e6cc
ZZ		 914}
915
1f39d939
AS		 916/*
917 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
918 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
919 * The calculatation was done for all possible register values which
920 * is the array index and the following formula: 10^((idx−15)/40) * 100
921 */
922static const u8 vol_quot_table[] = {
923 42, 45, 47, 50, 53, 56, 60, 63,
924 67, 71, 75, 79, 84, 89, 94, 100,
925 106, 112, 119, 126, 133, 141, 150, 158,
926 168, 178, 188, 200, 211, 224, 237, 251
927};
928
9b34e6cc
ZZ		 929/*
930 * sgtl5000 has 3 internal power supplies:
931 * 1. VAG, normally set to vdda/2
7f6d75d7 932 * 2. charge pump, set to different value
9b34e6cc
ZZ		 933 * according to voltage of vdda and vddio
934 * 3. line out VAG, normally set to vddio/2
935 *
936 * and should be set according to:
937 * 1. vddd provided by external or not
938 * 2. vdda and vddio voltage value. > 3.1v or not
9b34e6cc
ZZ		 939 */
940static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
941{
942 int vddd;
943 int vdda;
944 int vddio;
945 u16 ana_pwr;
946 u16 lreg_ctrl;
947 int vag;
d2b7c2aa 948 int lo_vag;
1f39d939
AS		 949 int vol_quot;
950 int lo_vol;
951 size_t i;
9b34e6cc
ZZ		 952 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
953
954 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
955 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
940adb28
EN		 956 vddd = (sgtl5000->num_supplies > VDDD)
957 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
958 : LDO_VOLTAGE;
9b34e6cc
ZZ		 959
960 vdda = vdda / 1000;
961 vddio = vddio / 1000;
962 vddd = vddd / 1000;
963
964 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
965 dev_err(codec->dev, "regulator voltage not set correctly\n");
966
967 return -EINVAL;
968 }
969
970 /* according to datasheet, maximum voltage of supplies */
971 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
972 dev_err(codec->dev,
cf1ee98d 973 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
9b34e6cc
ZZ		 974 vdda, vddio, vddd);
975
976 return -EINVAL;
977 }
978
979 /* reset value */
980 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
981 ana_pwr |= SGTL5000_DAC_STEREO |
982 SGTL5000_ADC_STEREO |
983 SGTL5000_REFTOP_POWERUP;
984 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
985
986 if (vddio < 3100 && vdda < 3100) {
987 /* enable internal oscillator used for charge pump */
988 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
989 SGTL5000_INT_OSC_EN,
990 SGTL5000_INT_OSC_EN);
991 /* Enable VDDC charge pump */
992 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
993 } else if (vddio >= 3100 && vdda >= 3100) {
c7d910b8 994 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
9b34e6cc
ZZ		 995 /* VDDC use VDDIO rail */
996 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
997 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
998 SGTL5000_VDDC_MAN_ASSN_SHIFT;
999 }
1000
1001 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1002
1003 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1004
1005 /* set voltage to register */
1006 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
064a4bce 1007 SGTL5000_LINREG_VDDD_MASK, 0x8);
9b34e6cc
ZZ		 1008
1009 /*
1010 * if vddd linear reg has been enabled,
1011 * simple digital supply should be clear to get
1012 * proper VDDD voltage.
1013 */
1014 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1015 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1016 SGTL5000_LINREG_SIMPLE_POWERUP,
1017 0);
1018 else
1019 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1020 SGTL5000_LINREG_SIMPLE_POWERUP |
1021 SGTL5000_STARTUP_POWERUP,
1022 0);
1023
1024 /*
1025 * set ADC/DAC VAG to vdda / 2,
1026 * should stay in range (0.8v, 1.575v)
1027 */
1028 vag = vdda / 2;
1029 if (vag <= SGTL5000_ANA_GND_BASE)
1030 vag = 0;
1031 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1032 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1033 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1034 else
1035 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1036
1037 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
33cb92cf 1038 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
9b34e6cc
ZZ		 1039
1040 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
d2b7c2aa
AS		 1041 lo_vag = vddio / 2;
1042 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1043 lo_vag = 0;
1044 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
9b34e6cc 1045 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
d2b7c2aa 1046 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
9b34e6cc 1047 else
d2b7c2aa 1048 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
9b34e6cc
ZZ		 1049 SGTL5000_LINE_OUT_GND_STP;
1050
1051 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
33cb92cf
AL		 1052 SGTL5000_LINE_OUT_CURRENT_MASK |
1053 SGTL5000_LINE_OUT_GND_MASK,
d2b7c2aa 1054 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
9b34e6cc
ZZ		 1055 SGTL5000_LINE_OUT_CURRENT_360u <<
1056 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1057
1f39d939
AS		 1058 /*
1059 * Set lineout output level in range (0..31)
1060 * the same value is used for right and left channel
1061 *
1062 * Searching for a suitable index solving this formula:
1063 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1064 */
1065 vol_quot = (vag * 100) / lo_vag;
1066 lo_vol = 0;
1067 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1068 if (vol_quot >= vol_quot_table[i])
1069 lo_vol = i;
1070 else
1071 break;
1072 }
1073
1074 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1075 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1076 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1077 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1078 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1079
9b34e6cc
ZZ		 1080 return 0;
1081}
1082
940adb28 1083static int sgtl5000_enable_regulators(struct i2c_client *client)
9b34e6cc 1084{
9b34e6cc 1085 int ret;
9b34e6cc
ZZ		 1086 int i;
1087 int external_vddd = 0;
11db0da8 1088 struct regulator *vddd;
940adb28 1089 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc
ZZ		 1090
1091 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1092 sgtl5000->supplies[i].supply = supply_names[i];
1093
940adb28
EN		 1094 vddd = regulator_get_optional(&client->dev, "VDDD");
1095 if (IS_ERR(vddd)) {
1096 /* See if it's just not registered yet */
1097 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1098 return -EPROBE_DEFER;
1099 } else {
1100 external_vddd = 1;
1101 regulator_put(vddd);
9b34e6cc
ZZ		 1102 }
1103
940adb28
EN		 1104 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1105 - 1 + external_vddd;
1106 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
11db0da8
SG		 1107 sgtl5000->supplies);
1108 if (ret)
940adb28 1109 return ret;
9b34e6cc 1110
940adb28
EN		 1111 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1112 sgtl5000->supplies);
1113 if (!ret)
1114 usleep_range(10, 20);
1115 else
1116 regulator_bulk_free(sgtl5000->num_supplies,
1117 sgtl5000->supplies);
9b34e6cc 1118
9b34e6cc 1119 return ret;
9b34e6cc
ZZ		 1120}
1121
1122static int sgtl5000_probe(struct snd_soc_codec *codec)
1123{
1124 int ret;
1125 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1126
9b34e6cc
ZZ		 1127 /* power up sgtl5000 */
1128 ret = sgtl5000_set_power_regs(codec);
1129 if (ret)
1130 goto err;
1131
1132 /* enable small pop, introduce 400ms delay in turning off */
1133 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
c251ea7b 1134 SGTL5000_SMALL_POP, 1);
9b34e6cc
ZZ		 1135
1136 /* disable short cut detector */
1137 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1138
1139 /*
1140 * set i2s as default input of sound switch
1141 * TODO: add sound switch to control and dapm widge.
1142 */
1143 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1144 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1145 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1146 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1147
1148 /* enable dac volume ramp by default */
1149 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1150 SGTL5000_DAC_VOL_RAMP_EN |
1151 SGTL5000_DAC_MUTE_RIGHT |
1152 SGTL5000_DAC_MUTE_LEFT);
1153
1154 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1155
1156 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1157 SGTL5000_HP_ZCD_EN |
1158 SGTL5000_ADC_ZCD_EN);
1159
bd0593f5
JMH		 1160 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1161 SGTL5000_BIAS_R_MASK,
1162 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
9b34e6cc 1163
87357797 1164 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
e256da84
GR		 1165 SGTL5000_BIAS_VOLT_MASK,
1166 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
9b34e6cc
ZZ		 1167 /*
1168 * disable DAP
1169 * TODO:
1170 * Enable DAP in kcontrol and dapm.
1171 */
1172 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1173
9b34e6cc
ZZ		 1174 return 0;
1175
1176err:
9b34e6cc
ZZ		 1177 return ret;
1178}
1179
1180static int sgtl5000_remove(struct snd_soc_codec *codec)
1181{
9b34e6cc
ZZ		 1182 return 0;
1183}
1184
61a142b7 1185static struct snd_soc_codec_driver sgtl5000_driver = {
9b34e6cc
ZZ		 1186 .probe = sgtl5000_probe,
1187 .remove = sgtl5000_remove,
9b34e6cc 1188 .set_bias_level = sgtl5000_set_bias_level,
e649057a 1189 .suspend_bias_off = true,
89989637
FE		 1190 .controls = sgtl5000_snd_controls,
1191 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
5e0ac527
MB		 1192 .dapm_widgets = sgtl5000_dapm_widgets,
1193 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1194 .dapm_routes = sgtl5000_dapm_routes,
1195 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
9b34e6cc
ZZ		 1196};
1197
e5d80e82
FE		 1198static const struct regmap_config sgtl5000_regmap = {
1199 .reg_bits = 16,
1200 .val_bits = 16,
cb23e852 1201 .reg_stride = 2,
e5d80e82
FE		 1202
1203 .max_register = SGTL5000_MAX_REG_OFFSET,
1204 .volatile_reg = sgtl5000_volatile,
1205 .readable_reg = sgtl5000_readable,
1206
1207 .cache_type = REGCACHE_RBTREE,
1208 .reg_defaults = sgtl5000_reg_defaults,
1209 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1210};
1211
af8ee112
FE		 1212/*
1213 * Write all the default values from sgtl5000_reg_defaults[] array into the
1214 * sgtl5000 registers, to make sure we always start with the sane registers
1215 * values as stated in the datasheet.
1216 *
1217 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1218 * we follow this approach to guarantee we always start from the default values
1219 * and avoid problems like, not being able to probe after an audio playback
1220 * followed by a system reset or a 'reboot' command in Linux
1221 */
f219b169 1222static void sgtl5000_fill_defaults(struct i2c_client *client)
af8ee112 1223{
f219b169 1224 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
af8ee112
FE		 1225 int i, ret, val, index;
1226
1227 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1228 val = sgtl5000_reg_defaults[i].def;
1229 index = sgtl5000_reg_defaults[i].reg;
1230 ret = regmap_write(sgtl5000->regmap, index, val);
1231 if (ret)
f219b169
EN		 1232 dev_err(&client->dev,
1233 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1234 __func__, ret, index, val);
af8ee112 1235 }
af8ee112
FE		 1236}
1237
7a79e94e
BP		 1238static int sgtl5000_i2c_probe(struct i2c_client *client,
1239 const struct i2c_device_id *id)
9b34e6cc
ZZ		 1240{
1241 struct sgtl5000_priv *sgtl5000;
b871f1ad 1242 int ret, reg, rev;
bd0593f5
JMH		 1243 struct device_node *np = client->dev.of_node;
1244 u32 value;
9b34e6cc 1245
3f7256fe 1246 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
9b34e6cc
ZZ		 1247 if (!sgtl5000)
1248 return -ENOMEM;
1249
940adb28
EN		 1250 i2c_set_clientdata(client, sgtl5000);
1251
1252 ret = sgtl5000_enable_regulators(client);
1253 if (ret)
1254 return ret;
1255
e5d80e82
FE		 1256 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1257 if (IS_ERR(sgtl5000->regmap)) {
1258 ret = PTR_ERR(sgtl5000->regmap);
1259 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
940adb28 1260 goto disable_regs;
e5d80e82
FE		 1261 }
1262
9e13f345
FE		 1263 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1264 if (IS_ERR(sgtl5000->mclk)) {
1265 ret = PTR_ERR(sgtl5000->mclk);
1266 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
46a5905e
SG		 1267 /* Defer the probe to see if the clk will be provided later */
1268 if (ret == -ENOENT)
940adb28
EN		 1269 ret = -EPROBE_DEFER;
1270 goto disable_regs;
9e13f345
FE		 1271 }
1272
1273 ret = clk_prepare_enable(sgtl5000->mclk);
940adb28
EN		 1274 if (ret) {
1275 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1276 goto disable_regs;
1277 }
9e13f345 1278
58cc9c9a
EN		 1279 /* Need 8 clocks before I2C accesses */
1280 udelay(1);
1281
b871f1ad
FE		 1282 /* read chip information */
1283 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
940adb28
EN		 1284 if (ret) {
1285 dev_err(&client->dev, "Error reading chip id %d\n", ret);
9e13f345 1286 goto disable_clk;
940adb28 1287 }
b871f1ad
FE		 1288
1289 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1290 SGTL5000_PARTID_PART_ID) {
1291 dev_err(&client->dev,
1292 "Device with ID register %x is not a sgtl5000\n", reg);
9e13f345
FE		 1293 ret = -ENODEV;
1294 goto disable_clk;
b871f1ad
FE		 1295 }
1296
1297 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1298 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
252e91ff 1299 sgtl5000->revision = rev;
b871f1ad 1300
940adb28
EN		 1301 /* Follow section 2.2.1.1 of AN3663 */
1302 if (sgtl5000->num_supplies <= VDDD) {
1303 /* internal VDDD at 1.2V */
1304 regmap_update_bits(sgtl5000->regmap,
1305 SGTL5000_CHIP_LINREG_CTRL,
1306 SGTL5000_LINREG_VDDD_MASK, 8);
1307 regmap_update_bits(sgtl5000->regmap,
1308 SGTL5000_CHIP_ANA_POWER,
1309 SGTL5000_LINEREG_D_POWERUP
1310 | SGTL5000_LINREG_SIMPLE_POWERUP,
1311 SGTL5000_LINEREG_D_POWERUP);
1312 dev_info(&client->dev, "Using internal LDO instead of VDDD: check ER1\n");
1313 } else {
1314 /* using external LDO for VDDD
1315 * Clear startup powerup and simple powerup
1316 * bits to save power
1317 */
1318 regmap_update_bits(sgtl5000->regmap,
1319 SGTL5000_CHIP_ANA_POWER,
1320 SGTL5000_STARTUP_POWERUP
1321 | SGTL5000_LINREG_SIMPLE_POWERUP,
1322 0);
1323 dev_dbg(&client->dev, "Using external VDDD\n");
1324 }
1325
bd0593f5
JMH		 1326 if (np) {
1327 if (!of_property_read_u32(np,
1328 "micbias-resistor-k-ohms", &value)) {
1329 switch (value) {
1330 case SGTL5000_MICBIAS_OFF:
1331 sgtl5000->micbias_resistor = 0;
1332 break;
1333 case SGTL5000_MICBIAS_2K:
1334 sgtl5000->micbias_resistor = 1;
1335 break;
1336 case SGTL5000_MICBIAS_4K:
1337 sgtl5000->micbias_resistor = 2;
1338 break;
1339 case SGTL5000_MICBIAS_8K:
1340 sgtl5000->micbias_resistor = 3;
1341 break;
1342 default:
1343 sgtl5000->micbias_resistor = 2;
1344 dev_err(&client->dev,
1345 "Unsuitable MicBias resistor\n");
1346 }
1347 } else {
1348 /* default is 4Kohms */
1349 sgtl5000->micbias_resistor = 2;
1350 }
87357797
JMH		 1351 if (!of_property_read_u32(np,
1352 "micbias-voltage-m-volts", &value)) {
1353 /* 1250mV => 0 */
1354 /* steps of 250mV */
1355 if ((value >= 1250) && (value <= 3000))
1356 sgtl5000->micbias_voltage = (value / 250) - 5;
1357 else {
1358 sgtl5000->micbias_voltage = 0;
bd0593f5 1359 dev_err(&client->dev,
fb97d75b 1360 "Unsuitable MicBias voltage\n");
bd0593f5
JMH		 1361 }
1362 } else {
87357797 1363 sgtl5000->micbias_voltage = 0;
bd0593f5
JMH		 1364 }
1365 }
1366
af8ee112 1367 /* Ensure sgtl5000 will start with sane register values */
f219b169 1368 sgtl5000_fill_defaults(client);
af8ee112 1369
9b34e6cc
ZZ		 1370 ret = snd_soc_register_codec(&client->dev,
1371 &sgtl5000_driver, &sgtl5000_dai, 1);
9e13f345
FE		 1372 if (ret)
1373 goto disable_clk;
1374
1375 return 0;
1376
1377disable_clk:
1378 clk_disable_unprepare(sgtl5000->mclk);
940adb28
EN		 1379
1380disable_regs:
1381 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1382 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1383
512fa7c4 1384 return ret;
9b34e6cc
ZZ		 1385}
1386
7a79e94e 1387static int sgtl5000_i2c_remove(struct i2c_client *client)
9b34e6cc 1388{
7c647af4 1389 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
9b34e6cc 1390
9e13f345
FE		 1391 snd_soc_unregister_codec(&client->dev);
1392 clk_disable_unprepare(sgtl5000->mclk);
940adb28
EN		 1393 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1394 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1395
9b34e6cc
ZZ		 1396 return 0;
1397}
1398
1399static const struct i2c_device_id sgtl5000_id[] = {
1400 {"sgtl5000", 0},
1401 {},
1402};
1403
1404MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1405
58e49424
SG		 1406static const struct of_device_id sgtl5000_dt_ids[] = {
1407 { .compatible = "fsl,sgtl5000", },
1408 { /* sentinel */ }
1409};
4c54c6de 1410MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
58e49424 1411
9b34e6cc
ZZ		 1412static struct i2c_driver sgtl5000_i2c_driver = {
1413 .driver = {
1414 .name = "sgtl5000",
58e49424 1415 .of_match_table = sgtl5000_dt_ids,
9b34e6cc
ZZ		 1416 },
1417 .probe = sgtl5000_i2c_probe,
7a79e94e 1418 .remove = sgtl5000_i2c_remove,
9b34e6cc
ZZ		 1419 .id_table = sgtl5000_id,
1420};
1421
67d45090 1422module_i2c_driver(sgtl5000_i2c_driver);
9b34e6cc
ZZ		 1423
1424MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
f7cb8a4b 1425MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
9b34e6cc 1426MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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