[deliverable/linux.git] / sound / soc / codecs / ssm4567.c

/*
 * SSM4567 amplifier audio driver
 *
 * Copyright 2014 Google Chromium project.
 *  Author: Anatol Pomozov <anatol@chromium.org>
 *
 * Based on code copyright/by:
 *   Copyright 2013 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>

#define SSM4567_REG_POWER_CTRL		0x00
#define SSM4567_REG_AMP_SNS_CTRL		0x01
#define SSM4567_REG_DAC_CTRL		0x02
#define SSM4567_REG_DAC_VOLUME		0x03
#define SSM4567_REG_SAI_CTRL_1		0x04
#define SSM4567_REG_SAI_CTRL_2		0x05
#define SSM4567_REG_SAI_PLACEMENT_1		0x06
#define SSM4567_REG_SAI_PLACEMENT_2		0x07
#define SSM4567_REG_SAI_PLACEMENT_3		0x08
#define SSM4567_REG_SAI_PLACEMENT_4		0x09
#define SSM4567_REG_SAI_PLACEMENT_5		0x0a
#define SSM4567_REG_SAI_PLACEMENT_6		0x0b
#define SSM4567_REG_BATTERY_V_OUT		0x0c
#define SSM4567_REG_LIMITER_CTRL_1		0x0d
#define SSM4567_REG_LIMITER_CTRL_2		0x0e
#define SSM4567_REG_LIMITER_CTRL_3		0x0f
#define SSM4567_REG_STATUS_1		0x10
#define SSM4567_REG_STATUS_2		0x11
#define SSM4567_REG_FAULT_CTRL		0x12
#define SSM4567_REG_PDM_CTRL		0x13
#define SSM4567_REG_MCLK_RATIO		0x14
#define SSM4567_REG_BOOST_CTRL_1		0x15
#define SSM4567_REG_BOOST_CTRL_2		0x16
#define SSM4567_REG_SOFT_RESET		0xff

/* POWER_CTRL */
#define SSM4567_POWER_APWDN_EN		BIT(7)
#define SSM4567_POWER_BSNS_PWDN		BIT(6)
#define SSM4567_POWER_VSNS_PWDN		BIT(5)
#define SSM4567_POWER_ISNS_PWDN		BIT(4)
#define SSM4567_POWER_BOOST_PWDN		BIT(3)
#define SSM4567_POWER_AMP_PWDN		BIT(2)
#define SSM4567_POWER_VBAT_ONLY		BIT(1)
#define SSM4567_POWER_SPWDN			BIT(0)

/* DAC_CTRL */
#define SSM4567_DAC_HV			BIT(7)
#define SSM4567_DAC_MUTE		BIT(6)
#define SSM4567_DAC_HPF			BIT(5)
#define SSM4567_DAC_LPM			BIT(4)
#define SSM4567_DAC_FS_MASK	0x7
#define SSM4567_DAC_FS_8000_12000	0x0
#define SSM4567_DAC_FS_16000_24000	0x1
#define SSM4567_DAC_FS_32000_48000	0x2
#define SSM4567_DAC_FS_64000_96000	0x3
#define SSM4567_DAC_FS_128000_192000	0x4

struct ssm4567 {
	struct regmap *regmap;
};

static const struct reg_default ssm4567_reg_defaults[] = {
	{ SSM4567_REG_POWER_CTRL,	0x81 },
	{ SSM4567_REG_AMP_SNS_CTRL, 0x09 },
	{ SSM4567_REG_DAC_CTRL, 0x32 },
	{ SSM4567_REG_DAC_VOLUME, 0x40 },
	{ SSM4567_REG_SAI_CTRL_1, 0x00 },
	{ SSM4567_REG_SAI_CTRL_2, 0x08 },
	{ SSM4567_REG_SAI_PLACEMENT_1, 0x01 },
	{ SSM4567_REG_SAI_PLACEMENT_2, 0x20 },
	{ SSM4567_REG_SAI_PLACEMENT_3, 0x32 },
	{ SSM4567_REG_SAI_PLACEMENT_4, 0x07 },
	{ SSM4567_REG_SAI_PLACEMENT_5, 0x07 },
	{ SSM4567_REG_SAI_PLACEMENT_6, 0x07 },
	{ SSM4567_REG_BATTERY_V_OUT, 0x00 },
	{ SSM4567_REG_LIMITER_CTRL_1, 0xa4 },
	{ SSM4567_REG_LIMITER_CTRL_2, 0x73 },
	{ SSM4567_REG_LIMITER_CTRL_3, 0x00 },
	{ SSM4567_REG_STATUS_1, 0x00 },
	{ SSM4567_REG_STATUS_2, 0x00 },
	{ SSM4567_REG_FAULT_CTRL, 0x30 },
	{ SSM4567_REG_PDM_CTRL, 0x40 },
	{ SSM4567_REG_MCLK_RATIO, 0x11 },
	{ SSM4567_REG_BOOST_CTRL_1, 0x03 },
	{ SSM4567_REG_BOOST_CTRL_2, 0x00 },
	{ SSM4567_REG_SOFT_RESET, 0x00 },
};


static bool ssm4567_readable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case SSM4567_REG_POWER_CTRL ... SSM4567_REG_BOOST_CTRL_2:
		return true;
	default:
		return false;
	}

}

static bool ssm4567_writeable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case SSM4567_REG_POWER_CTRL ... SSM4567_REG_SAI_PLACEMENT_6:
	case SSM4567_REG_LIMITER_CTRL_1 ... SSM4567_REG_LIMITER_CTRL_3:
	case SSM4567_REG_FAULT_CTRL ... SSM4567_REG_BOOST_CTRL_2:
	/* The datasheet states that soft reset register is read-only,
	 * but logically it is write-only. */
	case SSM4567_REG_SOFT_RESET:
		return true;
	default:
		return false;
	}
}

static bool ssm4567_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case SSM4567_REG_BATTERY_V_OUT:
	case SSM4567_REG_STATUS_1 ... SSM4567_REG_STATUS_2:
	case SSM4567_REG_SOFT_RESET:
		return true;
	default:
		return false;
	}
}

static const DECLARE_TLV_DB_MINMAX_MUTE(ssm4567_vol_tlv, -7125, 2400);

static const struct snd_kcontrol_new ssm4567_snd_controls[] = {
	SOC_SINGLE_TLV("Master Playback Volume", SSM4567_REG_DAC_VOLUME, 0,
		0xff, 1, ssm4567_vol_tlv),
	SOC_SINGLE("DAC Low Power Mode Switch", SSM4567_REG_DAC_CTRL, 4, 1, 0),
	SOC_SINGLE("DAC High Pass Filter Switch", SSM4567_REG_DAC_CTRL,
		5, 1, 0),
};

static const struct snd_soc_dapm_widget ssm4567_dapm_widgets[] = {
	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SSM4567_REG_POWER_CTRL, 2, 1),

	SND_SOC_DAPM_OUTPUT("OUT"),
};

static const struct snd_soc_dapm_route ssm4567_routes[] = {
	{ "OUT", NULL, "DAC" },
};

static int ssm4567_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct ssm4567 *ssm4567 = snd_soc_codec_get_drvdata(codec);
	unsigned int rate = params_rate(params);
	unsigned int dacfs;

	if (rate >= 8000 && rate <= 12000)
		dacfs = SSM4567_DAC_FS_8000_12000;
	else if (rate >= 16000 && rate <= 24000)
		dacfs = SSM4567_DAC_FS_16000_24000;
	else if (rate >= 32000 && rate <= 48000)
		dacfs = SSM4567_DAC_FS_32000_48000;
	else if (rate >= 64000 && rate <= 96000)
		dacfs = SSM4567_DAC_FS_64000_96000;
	else if (rate >= 128000 && rate <= 192000)
		dacfs = SSM4567_DAC_FS_128000_192000;
	else
		return -EINVAL;

	return regmap_update_bits(ssm4567->regmap, SSM4567_REG_DAC_CTRL,
				SSM4567_DAC_FS_MASK, dacfs);
}

static int ssm4567_mute(struct snd_soc_dai *dai, int mute)
{
	struct ssm4567 *ssm4567 = snd_soc_codec_get_drvdata(dai->codec);
	unsigned int val;

	val = mute ? SSM4567_DAC_MUTE : 0;
	return regmap_update_bits(ssm4567->regmap, SSM4567_REG_DAC_CTRL,
			SSM4567_DAC_MUTE, val);
}

static int ssm4567_set_power(struct ssm4567 *ssm4567, bool enable)
{
	int ret = 0;

	if (!enable) {
		ret = regmap_update_bits(ssm4567->regmap,
			SSM4567_REG_POWER_CTRL,
			SSM4567_POWER_SPWDN, SSM4567_POWER_SPWDN);
		regcache_mark_dirty(ssm4567->regmap);
	}

	regcache_cache_only(ssm4567->regmap, !enable);

	if (enable) {
		ret = regmap_update_bits(ssm4567->regmap,
			SSM4567_REG_POWER_CTRL,
			SSM4567_POWER_SPWDN, 0x00);
		regcache_sync(ssm4567->regmap);
	}

	return ret;
}

static int ssm4567_set_bias_level(struct snd_soc_codec *codec,
	enum snd_soc_bias_level level)
{
	struct ssm4567 *ssm4567 = snd_soc_codec_get_drvdata(codec);
	int ret = 0;

	switch (level) {
	case SND_SOC_BIAS_ON:
		break;
	case SND_SOC_BIAS_PREPARE:
		break;
	case SND_SOC_BIAS_STANDBY:
		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
			ret = ssm4567_set_power(ssm4567, true);
		break;
	case SND_SOC_BIAS_OFF:
		ret = ssm4567_set_power(ssm4567, false);
		break;
	}

	if (ret)
		return ret;

	codec->dapm.bias_level = level;

	return 0;
}

static const struct snd_soc_dai_ops ssm4567_dai_ops = {
	.hw_params	= ssm4567_hw_params,
	.digital_mute	= ssm4567_mute,
};

static struct snd_soc_dai_driver ssm4567_dai = {
	.name = "ssm4567-hifi",
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 1,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
			SNDRV_PCM_FMTBIT_S32,
	},
	.ops = &ssm4567_dai_ops,
};

static struct snd_soc_codec_driver ssm4567_codec_driver = {
	.set_bias_level = ssm4567_set_bias_level,
	.idle_bias_off = true,

	.controls = ssm4567_snd_controls,
	.num_controls = ARRAY_SIZE(ssm4567_snd_controls),
	.dapm_widgets = ssm4567_dapm_widgets,
	.num_dapm_widgets = ARRAY_SIZE(ssm4567_dapm_widgets),
	.dapm_routes = ssm4567_routes,
	.num_dapm_routes = ARRAY_SIZE(ssm4567_routes),
};

static const struct regmap_config ssm4567_regmap_config = {
	.val_bits = 8,
	.reg_bits = 8,

	.max_register = SSM4567_REG_SOFT_RESET,
	.readable_reg = ssm4567_readable_reg,
	.writeable_reg = ssm4567_writeable_reg,
	.volatile_reg = ssm4567_volatile_reg,

	.cache_type = REGCACHE_RBTREE,
	.reg_defaults = ssm4567_reg_defaults,
	.num_reg_defaults = ARRAY_SIZE(ssm4567_reg_defaults),
};

static int ssm4567_i2c_probe(struct i2c_client *i2c,
	const struct i2c_device_id *id)
{
	struct ssm4567 *ssm4567;
	int ret;

	ssm4567 = devm_kzalloc(&i2c->dev, sizeof(*ssm4567), GFP_KERNEL);
	if (ssm4567 == NULL)
		return -ENOMEM;

	i2c_set_clientdata(i2c, ssm4567);

	ssm4567->regmap = devm_regmap_init_i2c(i2c, &ssm4567_regmap_config);
	if (IS_ERR(ssm4567->regmap))
		return PTR_ERR(ssm4567->regmap);

	ret = regmap_write(ssm4567->regmap, SSM4567_REG_SOFT_RESET, 0x00);
	if (ret)
		return ret;

	ret = ssm4567_set_power(ssm4567, false);
	if (ret)
		return ret;

	return snd_soc_register_codec(&i2c->dev, &ssm4567_codec_driver,
			&ssm4567_dai, 1);
}

static int ssm4567_i2c_remove(struct i2c_client *client)
{
	snd_soc_unregister_codec(&client->dev);
	return 0;
}

static const struct i2c_device_id ssm4567_i2c_ids[] = {
	{ "ssm4567", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, ssm4567_i2c_ids);

static struct i2c_driver ssm4567_driver = {
	.driver = {
		.name = "ssm4567",
		.owner = THIS_MODULE,
	},
	.probe = ssm4567_i2c_probe,
	.remove = ssm4567_i2c_remove,
	.id_table = ssm4567_i2c_ids,
};
module_i2c_driver(ssm4567_driver);

MODULE_DESCRIPTION("ASoC SSM4567 driver");
MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
1ee44ce0 AP	1	/*
	2	* SSM4567 amplifier audio driver
	3	*
	4	* Copyright 2014 Google Chromium project.
	5	* Author: Anatol Pomozov <anatol@chromium.org>
	6	*
	7	* Based on code copyright/by:
	8	* Copyright 2013 Analog Devices Inc.
	9	*
	10	* Licensed under the GPL-2.
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/i2c.h>
	16	#include <linux/regmap.h>
	17	#include <linux/slab.h>
	18	#include <sound/core.h>
	19	#include <sound/pcm.h>
	20	#include <sound/pcm_params.h>
	21	#include <sound/soc.h>
	22	#include <sound/initval.h>
	23	#include <sound/tlv.h>
	24
	25	#define SSM4567_REG_POWER_CTRL 0x00
	26	#define SSM4567_REG_AMP_SNS_CTRL 0x01
	27	#define SSM4567_REG_DAC_CTRL 0x02
	28	#define SSM4567_REG_DAC_VOLUME 0x03
	29	#define SSM4567_REG_SAI_CTRL_1 0x04
	30	#define SSM4567_REG_SAI_CTRL_2 0x05
	31	#define SSM4567_REG_SAI_PLACEMENT_1 0x06
	32	#define SSM4567_REG_SAI_PLACEMENT_2 0x07
	33	#define SSM4567_REG_SAI_PLACEMENT_3 0x08
	34	#define SSM4567_REG_SAI_PLACEMENT_4 0x09
	35	#define SSM4567_REG_SAI_PLACEMENT_5 0x0a
	36	#define SSM4567_REG_SAI_PLACEMENT_6 0x0b
	37	#define SSM4567_REG_BATTERY_V_OUT 0x0c
	38	#define SSM4567_REG_LIMITER_CTRL_1 0x0d
	39	#define SSM4567_REG_LIMITER_CTRL_2 0x0e
	40	#define SSM4567_REG_LIMITER_CTRL_3 0x0f
	41	#define SSM4567_REG_STATUS_1 0x10
	42	#define SSM4567_REG_STATUS_2 0x11
	43	#define SSM4567_REG_FAULT_CTRL 0x12
	44	#define SSM4567_REG_PDM_CTRL 0x13
	45	#define SSM4567_REG_MCLK_RATIO 0x14
	46	#define SSM4567_REG_BOOST_CTRL_1 0x15
	47	#define SSM4567_REG_BOOST_CTRL_2 0x16
	48	#define SSM4567_REG_SOFT_RESET 0xff
	49
	50	/* POWER_CTRL */
	51	#define SSM4567_POWER_APWDN_EN BIT(7)
	52	#define SSM4567_POWER_BSNS_PWDN BIT(6)
	53	#define SSM4567_POWER_VSNS_PWDN BIT(5)
	54	#define SSM4567_POWER_ISNS_PWDN BIT(4)
	55	#define SSM4567_POWER_BOOST_PWDN BIT(3)
	56	#define SSM4567_POWER_AMP_PWDN BIT(2)
	57	#define SSM4567_POWER_VBAT_ONLY BIT(1)
	58	#define SSM4567_POWER_SPWDN BIT(0)
	59
	60	/* DAC_CTRL */
	61	#define SSM4567_DAC_HV BIT(7)
	62	#define SSM4567_DAC_MUTE BIT(6)
	63	#define SSM4567_DAC_HPF BIT(5)
	64	#define SSM4567_DAC_LPM BIT(4)
65	#define SSM4567_DAC_FS_MASK 0x7
66	#define SSM4567_DAC_FS_8000_12000 0x0
67	#define SSM4567_DAC_FS_16000_24000 0x1
68	#define SSM4567_DAC_FS_32000_48000 0x2
69	#define SSM4567_DAC_FS_64000_96000 0x3
70	#define SSM4567_DAC_FS_128000_192000 0x4
71
72	struct ssm4567 {
73	struct regmap *regmap;
74	};
75
76	static const struct reg_default ssm4567_reg_defaults[] = {
77	{ SSM4567_REG_POWER_CTRL, 0x81 },
78	{ SSM4567_REG_AMP_SNS_CTRL, 0x09 },
79	{ SSM4567_REG_DAC_CTRL, 0x32 },
80	{ SSM4567_REG_DAC_VOLUME, 0x40 },
81	{ SSM4567_REG_SAI_CTRL_1, 0x00 },
82	{ SSM4567_REG_SAI_CTRL_2, 0x08 },
83	{ SSM4567_REG_SAI_PLACEMENT_1, 0x01 },
84	{ SSM4567_REG_SAI_PLACEMENT_2, 0x20 },
85	{ SSM4567_REG_SAI_PLACEMENT_3, 0x32 },
86	{ SSM4567_REG_SAI_PLACEMENT_4, 0x07 },
87	{ SSM4567_REG_SAI_PLACEMENT_5, 0x07 },
88	{ SSM4567_REG_SAI_PLACEMENT_6, 0x07 },
89	{ SSM4567_REG_BATTERY_V_OUT, 0x00 },
90	{ SSM4567_REG_LIMITER_CTRL_1, 0xa4 },
91	{ SSM4567_REG_LIMITER_CTRL_2, 0x73 },
92	{ SSM4567_REG_LIMITER_CTRL_3, 0x00 },
93	{ SSM4567_REG_STATUS_1, 0x00 },
94	{ SSM4567_REG_STATUS_2, 0x00 },
95	{ SSM4567_REG_FAULT_CTRL, 0x30 },
96	{ SSM4567_REG_PDM_CTRL, 0x40 },
97	{ SSM4567_REG_MCLK_RATIO, 0x11 },
98	{ SSM4567_REG_BOOST_CTRL_1, 0x03 },
99	{ SSM4567_REG_BOOST_CTRL_2, 0x00 },
100	{ SSM4567_REG_SOFT_RESET, 0x00 },
101	};
102
103
104	static bool ssm4567_readable_reg(struct device *dev, unsigned int reg)
105	{
106	switch (reg) {
107	case SSM4567_REG_POWER_CTRL ... SSM4567_REG_BOOST_CTRL_2:
108	return true;
109	default:
110	return false;
111	}
112
113	}
114
115	static bool ssm4567_writeable_reg(struct device *dev, unsigned int reg)
116	{
117	switch (reg) {
118	case SSM4567_REG_POWER_CTRL ... SSM4567_REG_SAI_PLACEMENT_6:
119	case SSM4567_REG_LIMITER_CTRL_1 ... SSM4567_REG_LIMITER_CTRL_3:
120	case SSM4567_REG_FAULT_CTRL ... SSM4567_REG_BOOST_CTRL_2:
121	/* The datasheet states that soft reset register is read-only,
122	* but logically it is write-only. */
123	case SSM4567_REG_SOFT_RESET:
124	return true;
125	default:
126	return false;
127	}
128	}
129
130	static bool ssm4567_volatile_reg(struct device *dev, unsigned int reg)
131	{
132	switch (reg) {
133	case SSM4567_REG_BATTERY_V_OUT:
134	case SSM4567_REG_STATUS_1 ... SSM4567_REG_STATUS_2:
135	case SSM4567_REG_SOFT_RESET:
136	return true;
137	default:
138	return false;
139	}
140	}
141
142	static const DECLARE_TLV_DB_MINMAX_MUTE(ssm4567_vol_tlv, -7125, 2400);
143
144	static const struct snd_kcontrol_new ssm4567_snd_controls[] = {
145	SOC_SINGLE_TLV("Master Playback Volume", SSM4567_REG_DAC_VOLUME, 0,
146	0xff, 1, ssm4567_vol_tlv),
147	SOC_SINGLE("DAC Low Power Mode Switch", SSM4567_REG_DAC_CTRL, 4, 1, 0),
feec843d LPC	148	SOC_SINGLE("DAC High Pass Filter Switch", SSM4567_REG_DAC_CTRL,
feec843d LPC	149	5, 1, 0),
1ee44ce0 AP	150	};
	151
	152	static const struct snd_soc_dapm_widget ssm4567_dapm_widgets[] = {
	153	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SSM4567_REG_POWER_CTRL, 2, 1),
	154
	155	SND_SOC_DAPM_OUTPUT("OUT"),
	156	};
	157
	158	static const struct snd_soc_dapm_route ssm4567_routes[] = {
	159	{ "OUT", NULL, "DAC" },
	160	};
	161
	162	static int ssm4567_hw_params(struct snd_pcm_substream *substream,
	163	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
	164	{
	165	struct snd_soc_codec *codec = dai->codec;
	166	struct ssm4567 *ssm4567 = snd_soc_codec_get_drvdata(codec);
	167	unsigned int rate = params_rate(params);
	168	unsigned int dacfs;
	169
	170	if (rate >= 8000 && rate <= 12000)
	171	dacfs = SSM4567_DAC_FS_8000_12000;
	172	else if (rate >= 16000 && rate <= 24000)
	173	dacfs = SSM4567_DAC_FS_16000_24000;
	174	else if (rate >= 32000 && rate <= 48000)
	175	dacfs = SSM4567_DAC_FS_32000_48000;
	176	else if (rate >= 64000 && rate <= 96000)
	177	dacfs = SSM4567_DAC_FS_64000_96000;
1ee44ce0 AP	178	else if (rate >= 128000 && rate <= 192000)
	179	dacfs = SSM4567_DAC_FS_128000_192000;
	180	else
	181	return -EINVAL;
	182
	183	return regmap_update_bits(ssm4567->regmap, SSM4567_REG_DAC_CTRL,
	184	SSM4567_DAC_FS_MASK, dacfs);
	185	}
	186
	187	static int ssm4567_mute(struct snd_soc_dai *dai, int mute)
	188	{
	189	struct ssm4567 *ssm4567 = snd_soc_codec_get_drvdata(dai->codec);
	190	unsigned int val;
	191
	192	val = mute ? SSM4567_DAC_MUTE : 0;
	193	return regmap_update_bits(ssm4567->regmap, SSM4567_REG_DAC_CTRL,
	194	SSM4567_DAC_MUTE, val);
	195	}
	196
	197	static int ssm4567_set_power(struct ssm4567 *ssm4567, bool enable)
	198	{
	199	int ret = 0;
	200
	201	if (!enable) {
	202	ret = regmap_update_bits(ssm4567->regmap,
	203	SSM4567_REG_POWER_CTRL,
	204	SSM4567_POWER_SPWDN, SSM4567_POWER_SPWDN);
	205	regcache_mark_dirty(ssm4567->regmap);
	206	}
	207
	208	regcache_cache_only(ssm4567->regmap, !enable);
	209
	210	if (enable) {
	211	ret = regmap_update_bits(ssm4567->regmap,
	212	SSM4567_REG_POWER_CTRL,
	213	SSM4567_POWER_SPWDN, 0x00);
	214	regcache_sync(ssm4567->regmap);
	215	}
	216
	217	return ret;
	218	}
	219
	220	static int ssm4567_set_bias_level(struct snd_soc_codec *codec,
	221	enum snd_soc_bias_level level)
	222	{
	223	struct ssm4567 *ssm4567 = snd_soc_codec_get_drvdata(codec);
	224	int ret = 0;
	225
	226	switch (level) {
	227	case SND_SOC_BIAS_ON:
	228	break;
	229	case SND_SOC_BIAS_PREPARE:
	230	break;
	231	case SND_SOC_BIAS_STANDBY:
	232	if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
	233	ret = ssm4567_set_power(ssm4567, true);
	234	break;
	235	case SND_SOC_BIAS_OFF:
	236	ret = ssm4567_set_power(ssm4567, false);
	237	break;
	238	}
	239
	240	if (ret)
	241	return ret;
242
243	codec->dapm.bias_level = level;
244
245	return 0;
246	}
247
248	static const struct snd_soc_dai_ops ssm4567_dai_ops = {
249	.hw_params = ssm4567_hw_params,
250	.digital_mute = ssm4567_mute,
251	};
252
253	static struct snd_soc_dai_driver ssm4567_dai = {
254	.name = "ssm4567-hifi",
255	.playback = {
256	.stream_name = "Playback",
257	.channels_min = 1,
258	.channels_max = 1,
259	.rates = SNDRV_PCM_RATE_8000_192000,
260	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S24_LE \|
261	SNDRV_PCM_FMTBIT_S32,
262	},
263	.ops = &ssm4567_dai_ops,
264	};
265
266	static struct snd_soc_codec_driver ssm4567_codec_driver = {
267	.set_bias_level = ssm4567_set_bias_level,
268	.idle_bias_off = true,
269
270	.controls = ssm4567_snd_controls,
271	.num_controls = ARRAY_SIZE(ssm4567_snd_controls),
272	.dapm_widgets = ssm4567_dapm_widgets,
273	.num_dapm_widgets = ARRAY_SIZE(ssm4567_dapm_widgets),
274	.dapm_routes = ssm4567_routes,
275	.num_dapm_routes = ARRAY_SIZE(ssm4567_routes),
276	};
277
278	static const struct regmap_config ssm4567_regmap_config = {
279	.val_bits = 8,
280	.reg_bits = 8,
281
282	.max_register = SSM4567_REG_SOFT_RESET,
283	.readable_reg = ssm4567_readable_reg,
284	.writeable_reg = ssm4567_writeable_reg,
285	.volatile_reg = ssm4567_volatile_reg,
286
287	.cache_type = REGCACHE_RBTREE,
288	.reg_defaults = ssm4567_reg_defaults,
289	.num_reg_defaults = ARRAY_SIZE(ssm4567_reg_defaults),
290	};
291
292	static int ssm4567_i2c_probe(struct i2c_client *i2c,
293	const struct i2c_device_id *id)
294	{
295	struct ssm4567 *ssm4567;
296	int ret;
297
298	ssm4567 = devm_kzalloc(&i2c->dev, sizeof(*ssm4567), GFP_KERNEL);
299	if (ssm4567 == NULL)
300	return -ENOMEM;
301
302	i2c_set_clientdata(i2c, ssm4567);
303
304	ssm4567->regmap = devm_regmap_init_i2c(i2c, &ssm4567_regmap_config);
305	if (IS_ERR(ssm4567->regmap))
306	return PTR_ERR(ssm4567->regmap);
307
308	ret = regmap_write(ssm4567->regmap, SSM4567_REG_SOFT_RESET, 0x00);
309	if (ret)
310	return ret;
311
312	ret = ssm4567_set_power(ssm4567, false);
313	if (ret)
314	return ret;
315
316	return snd_soc_register_codec(&i2c->dev, &ssm4567_codec_driver,
317	&ssm4567_dai, 1);
318	}
319
320	static int ssm4567_i2c_remove(struct i2c_client *client)
321	{
322	snd_soc_unregister_codec(&client->dev);
323	return 0;
324	}
325
326	static const struct i2c_device_id ssm4567_i2c_ids[] = {
327	{ "ssm4567", 0 },
328	{ }
329	};
330	MODULE_DEVICE_TABLE(i2c, ssm4567_i2c_ids);
331
332	static struct i2c_driver ssm4567_driver = {
333	.driver = {
334	.name = "ssm4567",
335	.owner = THIS_MODULE,
336	},
337	.probe = ssm4567_i2c_probe,
338	.remove = ssm4567_i2c_remove,
339	.id_table = ssm4567_i2c_ids,
340	};
341	module_i2c_driver(ssm4567_driver);
342
343	MODULE_DESCRIPTION("ASoC SSM4567 driver");
344	MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
345	MODULE_LICENSE("GPL");