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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/wfg/writeback
[deliverable/linux.git] / sound / soc / codecs / sta32x.c
CommitLineData
c034abf6
JS		 1/*
2 * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
3 *
4 * Copyright: 2011 Raumfeld GmbH
5 * Author: Johannes Stezenbach <js@sig21.net>
6 *
7 * based on code from:
8 * Wolfson Microelectronics PLC.
9 * Mark Brown <broonie@opensource.wolfsonmicro.com>
10 * Freescale Semiconductor, Inc.
11 * Timur Tabi <timur@freescale.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
20
21#include <linux/module.h>
22#include <linux/moduleparam.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/pm.h>
26#include <linux/i2c.h>
27#include <linux/platform_device.h>
28#include <linux/regulator/consumer.h>
29#include <linux/slab.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
36#include <sound/tlv.h>
37
38#include "sta32x.h"
39
40#define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
41 SNDRV_PCM_RATE_44100 | \
42 SNDRV_PCM_RATE_48000 | \
43 SNDRV_PCM_RATE_88200 | \
44 SNDRV_PCM_RATE_96000 | \
45 SNDRV_PCM_RATE_176400 | \
46 SNDRV_PCM_RATE_192000)
47
48#define STA32X_FORMATS \
49 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
50 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
51 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
52 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \
53 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
54 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE)
55
56/* Power-up register defaults */
57static const u8 sta32x_regs[STA32X_REGISTER_COUNT] = {
58 0x63, 0x80, 0xc2, 0x40, 0xc2, 0x5c, 0x10, 0xff, 0x60, 0x60,
59 0x60, 0x80, 0x00, 0x00, 0x00, 0x40, 0x80, 0x77, 0x6a, 0x69,
60 0x6a, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
61 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2d,
62 0xc0, 0xf3, 0x33, 0x00, 0x0c,
63};
64
65/* regulator power supply names */
66static const char *sta32x_supply_names[] = {
67 "Vdda", /* analog supply, 3.3VV */
68 "Vdd3", /* digital supply, 3.3V */
69 "Vcc" /* power amp spply, 10V - 36V */
70};
71
72/* codec private data */
73struct sta32x_priv {
74 struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
75 struct snd_soc_codec *codec;
76
77 unsigned int mclk;
78 unsigned int format;
79};
80
81static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
82static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
83static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
84
85static const char *sta32x_drc_ac[] = {
86 "Anti-Clipping", "Dynamic Range Compression" };
87static const char *sta32x_auto_eq_mode[] = {
88 "User", "Preset", "Loudness" };
89static const char *sta32x_auto_gc_mode[] = {
90 "User", "AC no clipping", "AC limited clipping (10%)",
91 "DRC nighttime listening mode" };
92static const char *sta32x_auto_xo_mode[] = {
93 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
94 "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
95static const char *sta32x_preset_eq_mode[] = {
96 "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
97 "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
98 "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
99 "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
100 "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
101 "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
102static const char *sta32x_limiter_select[] = {
103 "Limiter Disabled", "Limiter #1", "Limiter #2" };
104static const char *sta32x_limiter_attack_rate[] = {
105 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
106 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
107 "0.0645", "0.0564", "0.0501", "0.0451" };
108static const char *sta32x_limiter_release_rate[] = {
109 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
110 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
111 "0.0134", "0.0117", "0.0110", "0.0104" };
112
113static const unsigned int sta32x_limiter_ac_attack_tlv[] = {
114 TLV_DB_RANGE_HEAD(2),
115 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
116 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
117};
118
119static const unsigned int sta32x_limiter_ac_release_tlv[] = {
120 TLV_DB_RANGE_HEAD(5),
121 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
122 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
123 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
124 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
125 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
126};
127
128static const unsigned int sta32x_limiter_drc_attack_tlv[] = {
129 TLV_DB_RANGE_HEAD(3),
130 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
131 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
132 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
133};
134
135static const unsigned int sta32x_limiter_drc_release_tlv[] = {
136 TLV_DB_RANGE_HEAD(5),
137 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
138 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
139 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
140 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
141 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
142};
143
144static const struct soc_enum sta32x_drc_ac_enum =
145 SOC_ENUM_SINGLE(STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
146 2, sta32x_drc_ac);
147static const struct soc_enum sta32x_auto_eq_enum =
148 SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
149 3, sta32x_auto_eq_mode);
150static const struct soc_enum sta32x_auto_gc_enum =
151 SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
152 4, sta32x_auto_gc_mode);
153static const struct soc_enum sta32x_auto_xo_enum =
154 SOC_ENUM_SINGLE(STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
155 16, sta32x_auto_xo_mode);
156static const struct soc_enum sta32x_preset_eq_enum =
157 SOC_ENUM_SINGLE(STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
158 32, sta32x_preset_eq_mode);
159static const struct soc_enum sta32x_limiter_ch1_enum =
160 SOC_ENUM_SINGLE(STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
161 3, sta32x_limiter_select);
162static const struct soc_enum sta32x_limiter_ch2_enum =
163 SOC_ENUM_SINGLE(STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
164 3, sta32x_limiter_select);
165static const struct soc_enum sta32x_limiter_ch3_enum =
166 SOC_ENUM_SINGLE(STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
167 3, sta32x_limiter_select);
168static const struct soc_enum sta32x_limiter1_attack_rate_enum =
169 SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxA_SHIFT,
170 16, sta32x_limiter_attack_rate);
171static const struct soc_enum sta32x_limiter2_attack_rate_enum =
172 SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxA_SHIFT,
173 16, sta32x_limiter_attack_rate);
174static const struct soc_enum sta32x_limiter1_release_rate_enum =
175 SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxR_SHIFT,
176 16, sta32x_limiter_release_rate);
177static const struct soc_enum sta32x_limiter2_release_rate_enum =
178 SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxR_SHIFT,
179 16, sta32x_limiter_release_rate);
79688439
JS		 180
181/* byte array controls for setting biquad, mixer, scaling coefficients;
182 * for biquads all five coefficients need to be set in one go,
183 * mixer and pre/postscale coefs can be set individually;
184 * each coef is 24bit, the bytes are ordered in the same way
185 * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0)
186 */
187
188static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
189 struct snd_ctl_elem_info *uinfo)
190{
191 int numcoef = kcontrol->private_value >> 16;
192 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
193 uinfo->count = 3 * numcoef;
194 return 0;
195}
196
197static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
198 struct snd_ctl_elem_value *ucontrol)
199{
200 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
201 int numcoef = kcontrol->private_value >> 16;
202 int index = kcontrol->private_value & 0xffff;
203 unsigned int cfud;
204 int i;
205
206 /* preserve reserved bits in STA32X_CFUD */
207 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
208 /* chip documentation does not say if the bits are self clearing,
209 * so do it explicitly */
210 snd_soc_write(codec, STA32X_CFUD, cfud);
211
212 snd_soc_write(codec, STA32X_CFADDR2, index);
213 if (numcoef == 1)
214 snd_soc_write(codec, STA32X_CFUD, cfud | 0x04);
215 else if (numcoef == 5)
216 snd_soc_write(codec, STA32X_CFUD, cfud | 0x08);
217 else
218 return -EINVAL;
219 for (i = 0; i < 3 * numcoef; i++)
220 ucontrol->value.bytes.data[i] =
221 snd_soc_read(codec, STA32X_B1CF1 + i);
222
223 return 0;
224}
225
226static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
227 struct snd_ctl_elem_value *ucontrol)
228{
229 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
230 int numcoef = kcontrol->private_value >> 16;
231 int index = kcontrol->private_value & 0xffff;
232 unsigned int cfud;
233 int i;
234
235 /* preserve reserved bits in STA32X_CFUD */
236 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
237 /* chip documentation does not say if the bits are self clearing,
238 * so do it explicitly */
239 snd_soc_write(codec, STA32X_CFUD, cfud);
240
241 snd_soc_write(codec, STA32X_CFADDR2, index);
242 for (i = 0; i < 3 * numcoef; i++)
243 snd_soc_write(codec, STA32X_B1CF1 + i,
244 ucontrol->value.bytes.data[i]);
245 if (numcoef == 1)
246 snd_soc_write(codec, STA32X_CFUD, cfud | 0x01);
247 else if (numcoef == 5)
248 snd_soc_write(codec, STA32X_CFUD, cfud | 0x02);
249 else
250 return -EINVAL;
251
252 return 0;
253}
254
255#define SINGLE_COEF(xname, index) \
256{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
257 .info = sta32x_coefficient_info, \
258 .get = sta32x_coefficient_get,\
259 .put = sta32x_coefficient_put, \
260 .private_value = index | (1 << 16) }
261
262#define BIQUAD_COEFS(xname, index) \
263{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
264 .info = sta32x_coefficient_info, \
265 .get = sta32x_coefficient_get,\
266 .put = sta32x_coefficient_put, \
267 .private_value = index | (5 << 16) }
268
c034abf6
JS		 269static const struct snd_kcontrol_new sta32x_snd_controls[] = {
270SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
271SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
272SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
273SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
274SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
275SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
276SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
277SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
278SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
279SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
280SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
281SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
282SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
283SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
284SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
285SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
286SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
287SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
288SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
289SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
290SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
291SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
292SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
293SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
294SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
295SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
296SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
297SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
298SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
299SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
300SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
301SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
302SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
303SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
304
305/* depending on mode, the attack/release thresholds have
306 * two different enum definitions; provide both
307 */
308SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
309 16, 0, sta32x_limiter_ac_attack_tlv),
310SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
311 16, 0, sta32x_limiter_ac_attack_tlv),
312SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
313 16, 0, sta32x_limiter_ac_release_tlv),
314SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
315 16, 0, sta32x_limiter_ac_release_tlv),
316SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
317 16, 0, sta32x_limiter_drc_attack_tlv),
318SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
319 16, 0, sta32x_limiter_drc_attack_tlv),
320SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
321 16, 0, sta32x_limiter_drc_release_tlv),
322SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
323 16, 0, sta32x_limiter_drc_release_tlv),
79688439
JS		 324
325BIQUAD_COEFS("Ch1 - Biquad 1", 0),
326BIQUAD_COEFS("Ch1 - Biquad 2", 5),
327BIQUAD_COEFS("Ch1 - Biquad 3", 10),
328BIQUAD_COEFS("Ch1 - Biquad 4", 15),
329BIQUAD_COEFS("Ch2 - Biquad 1", 20),
330BIQUAD_COEFS("Ch2 - Biquad 2", 25),
331BIQUAD_COEFS("Ch2 - Biquad 3", 30),
332BIQUAD_COEFS("Ch2 - Biquad 4", 35),
333BIQUAD_COEFS("High-pass", 40),
334BIQUAD_COEFS("Low-pass", 45),
335SINGLE_COEF("Ch1 - Prescale", 50),
336SINGLE_COEF("Ch2 - Prescale", 51),
337SINGLE_COEF("Ch1 - Postscale", 52),
338SINGLE_COEF("Ch2 - Postscale", 53),
339SINGLE_COEF("Ch3 - Postscale", 54),
340SINGLE_COEF("Thermal warning - Postscale", 55),
341SINGLE_COEF("Ch1 - Mix 1", 56),
342SINGLE_COEF("Ch1 - Mix 2", 57),
343SINGLE_COEF("Ch2 - Mix 1", 58),
344SINGLE_COEF("Ch2 - Mix 2", 59),
345SINGLE_COEF("Ch3 - Mix 1", 60),
346SINGLE_COEF("Ch3 - Mix 2", 61),
c034abf6
JS		 347};
348
349static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
350SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
351SND_SOC_DAPM_OUTPUT("LEFT"),
352SND_SOC_DAPM_OUTPUT("RIGHT"),
353SND_SOC_DAPM_OUTPUT("SUB"),
354};
355
356static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
357 { "LEFT", NULL, "DAC" },
358 { "RIGHT", NULL, "DAC" },
359 { "SUB", NULL, "DAC" },
360};
361
362/* MCLK interpolation ratio per fs */
363static struct {
364 int fs;
365 int ir;
366} interpolation_ratios[] = {
367 { 32000, 0 },
368 { 44100, 0 },
369 { 48000, 0 },
370 { 88200, 1 },
371 { 96000, 1 },
372 { 176400, 2 },
373 { 192000, 2 },
374};
375
376/* MCLK to fs clock ratios */
377static struct {
378 int ratio;
379 int mcs;
380} mclk_ratios[3][7] = {
381 { { 768, 0 }, { 512, 1 }, { 384, 2 }, { 256, 3 },
382 { 128, 4 }, { 576, 5 }, { 0, 0 } },
383 { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } },
384 { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } },
385};
386
387
388/**
389 * sta32x_set_dai_sysclk - configure MCLK
390 * @codec_dai: the codec DAI
391 * @clk_id: the clock ID (ignored)
392 * @freq: the MCLK input frequency
393 * @dir: the clock direction (ignored)
394 *
395 * The value of MCLK is used to determine which sample rates are supported
396 * by the STA32X, based on the mclk_ratios table.
397 *
398 * This function must be called by the machine driver's 'startup' function,
399 * otherwise the list of supported sample rates will not be available in
400 * time for ALSA.
401 *
402 * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
403 * theoretically possible sample rates to be enabled. Call it again with a
404 * proper value set one the external clock is set (most probably you would do
405 * that from a machine's driver 'hw_param' hook.
406 */
407static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
408 int clk_id, unsigned int freq, int dir)
409{
410 struct snd_soc_codec *codec = codec_dai->codec;
411 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
412 int i, j, ir, fs;
413 unsigned int rates = 0;
414 unsigned int rate_min = -1;
415 unsigned int rate_max = 0;
416
417 pr_debug("mclk=%u\n", freq);
418 sta32x->mclk = freq;
419
420 if (sta32x->mclk) {
421 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
422 ir = interpolation_ratios[i].ir;
423 fs = interpolation_ratios[i].fs;
424 for (j = 0; mclk_ratios[ir][j].ratio; j++) {
425 if (mclk_ratios[ir][j].ratio * fs == freq) {
426 rates |= snd_pcm_rate_to_rate_bit(fs);
427 if (fs < rate_min)
428 rate_min = fs;
429 if (fs > rate_max)
430 rate_max = fs;
431 }
432 }
433 }
434 /* FIXME: soc should support a rate list */
435 rates &= ~SNDRV_PCM_RATE_KNOT;
436
437 if (!rates) {
438 dev_err(codec->dev, "could not find a valid sample rate\n");
439 return -EINVAL;
440 }
441 } else {
442 /* enable all possible rates */
443 rates = STA32X_RATES;
444 rate_min = 32000;
445 rate_max = 192000;
446 }
447
448 codec_dai->driver->playback.rates = rates;
449 codec_dai->driver->playback.rate_min = rate_min;
450 codec_dai->driver->playback.rate_max = rate_max;
451 return 0;
452}
453
454/**
455 * sta32x_set_dai_fmt - configure the codec for the selected audio format
456 * @codec_dai: the codec DAI
457 * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
458 *
459 * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
460 * codec accordingly.
461 */
462static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
463 unsigned int fmt)
464{
465 struct snd_soc_codec *codec = codec_dai->codec;
466 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
467 u8 confb = snd_soc_read(codec, STA32X_CONFB);
468
469 pr_debug("\n");
470 confb &= ~(STA32X_CONFB_C1IM | STA32X_CONFB_C2IM);
471
472 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
473 case SND_SOC_DAIFMT_CBS_CFS:
474 break;
475 default:
476 return -EINVAL;
477 }
478
479 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
480 case SND_SOC_DAIFMT_I2S:
481 case SND_SOC_DAIFMT_RIGHT_J:
482 case SND_SOC_DAIFMT_LEFT_J:
483 sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
484 break;
485 default:
486 return -EINVAL;
487 }
488
489 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
490 case SND_SOC_DAIFMT_NB_NF:
491 confb |= STA32X_CONFB_C2IM;
492 break;
493 case SND_SOC_DAIFMT_NB_IF:
494 confb |= STA32X_CONFB_C1IM;
495 break;
496 default:
497 return -EINVAL;
498 }
499
500 snd_soc_write(codec, STA32X_CONFB, confb);
501 return 0;
502}
503
504/**
505 * sta32x_hw_params - program the STA32X with the given hardware parameters.
506 * @substream: the audio stream
507 * @params: the hardware parameters to set
508 * @dai: the SOC DAI (ignored)
509 *
510 * This function programs the hardware with the values provided.
511 * Specifically, the sample rate and the data format.
512 */
513static int sta32x_hw_params(struct snd_pcm_substream *substream,
514 struct snd_pcm_hw_params *params,
515 struct snd_soc_dai *dai)
516{
517 struct snd_soc_pcm_runtime *rtd = substream->private_data;
518 struct snd_soc_codec *codec = rtd->codec;
519 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
520 unsigned int rate;
521 int i, mcs = -1, ir = -1;
522 u8 confa, confb;
523
524 rate = params_rate(params);
525 pr_debug("rate: %u\n", rate);
526 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++)
527 if (interpolation_ratios[i].fs == rate)
528 ir = interpolation_ratios[i].ir;
529 if (ir < 0)
530 return -EINVAL;
531 for (i = 0; mclk_ratios[ir][i].ratio; i++)
532 if (mclk_ratios[ir][i].ratio * rate == sta32x->mclk)
533 mcs = mclk_ratios[ir][i].mcs;
534 if (mcs < 0)
535 return -EINVAL;
536
537 confa = snd_soc_read(codec, STA32X_CONFA);
538 confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK);
539 confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT);
540
541 confb = snd_soc_read(codec, STA32X_CONFB);
542 confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB);
543 switch (params_format(params)) {
544 case SNDRV_PCM_FORMAT_S24_LE:
545 case SNDRV_PCM_FORMAT_S24_BE:
546 case SNDRV_PCM_FORMAT_S24_3LE:
547 case SNDRV_PCM_FORMAT_S24_3BE:
548 pr_debug("24bit\n");
549 /* fall through */
550 case SNDRV_PCM_FORMAT_S32_LE:
551 case SNDRV_PCM_FORMAT_S32_BE:
552 pr_debug("24bit or 32bit\n");
553 switch (sta32x->format) {
554 case SND_SOC_DAIFMT_I2S:
555 confb |= 0x0;
556 break;
557 case SND_SOC_DAIFMT_LEFT_J:
558 confb |= 0x1;
559 break;
560 case SND_SOC_DAIFMT_RIGHT_J:
561 confb |= 0x2;
562 break;
563 }
564
565 break;
566 case SNDRV_PCM_FORMAT_S20_3LE:
567 case SNDRV_PCM_FORMAT_S20_3BE:
568 pr_debug("20bit\n");
569 switch (sta32x->format) {
570 case SND_SOC_DAIFMT_I2S:
571 confb |= 0x4;
572 break;
573 case SND_SOC_DAIFMT_LEFT_J:
574 confb |= 0x5;
575 break;
576 case SND_SOC_DAIFMT_RIGHT_J:
577 confb |= 0x6;
578 break;
579 }
580
581 break;
582 case SNDRV_PCM_FORMAT_S18_3LE:
583 case SNDRV_PCM_FORMAT_S18_3BE:
584 pr_debug("18bit\n");
585 switch (sta32x->format) {
586 case SND_SOC_DAIFMT_I2S:
587 confb |= 0x8;
588 break;
589 case SND_SOC_DAIFMT_LEFT_J:
590 confb |= 0x9;
591 break;
592 case SND_SOC_DAIFMT_RIGHT_J:
593 confb |= 0xa;
594 break;
595 }
596
597 break;
598 case SNDRV_PCM_FORMAT_S16_LE:
599 case SNDRV_PCM_FORMAT_S16_BE:
600 pr_debug("16bit\n");
601 switch (sta32x->format) {
602 case SND_SOC_DAIFMT_I2S:
603 confb |= 0x0;
604 break;
605 case SND_SOC_DAIFMT_LEFT_J:
606 confb |= 0xd;
607 break;
608 case SND_SOC_DAIFMT_RIGHT_J:
609 confb |= 0xe;
610 break;
611 }
612
613 break;
614 default:
615 return -EINVAL;
616 }
617
618 snd_soc_write(codec, STA32X_CONFA, confa);
619 snd_soc_write(codec, STA32X_CONFB, confb);
620 return 0;
621}
622
623/**
624 * sta32x_set_bias_level - DAPM callback
625 * @codec: the codec device
626 * @level: DAPM power level
627 *
628 * This is called by ALSA to put the codec into low power mode
629 * or to wake it up. If the codec is powered off completely
630 * all registers must be restored after power on.
631 */
632static int sta32x_set_bias_level(struct snd_soc_codec *codec,
633 enum snd_soc_bias_level level)
634{
635 int ret;
636 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
637
638 pr_debug("level = %d\n", level);
639 switch (level) {
640 case SND_SOC_BIAS_ON:
641 break;
642
643 case SND_SOC_BIAS_PREPARE:
644 /* Full power on */
645 snd_soc_update_bits(codec, STA32X_CONFF,
646 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
647 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
648 break;
649
650 case SND_SOC_BIAS_STANDBY:
651 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
652 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
653 sta32x->supplies);
654 if (ret != 0) {
655 dev_err(codec->dev,
656 "Failed to enable supplies: %d\n", ret);
657 return ret;
658 }
659
660 snd_soc_cache_sync(codec);
661 }
662
663 /* Power up to mute */
664 /* FIXME */
665 snd_soc_update_bits(codec, STA32X_CONFF,
666 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
667 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
668
669 break;
670
671 case SND_SOC_BIAS_OFF:
672 /* The chip runs through the power down sequence for us. */
673 snd_soc_update_bits(codec, STA32X_CONFF,
674 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
675 STA32X_CONFF_PWDN);
676 msleep(300);
677
678 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
679 sta32x->supplies);
680 break;
681 }
682 codec->dapm.bias_level = level;
683 return 0;
684}
685
686static struct snd_soc_dai_ops sta32x_dai_ops = {
687 .hw_params = sta32x_hw_params,
688 .set_sysclk = sta32x_set_dai_sysclk,
689 .set_fmt = sta32x_set_dai_fmt,
690};
691
692static struct snd_soc_dai_driver sta32x_dai = {
693 .name = "STA32X",
694 .playback = {
695 .stream_name = "Playback",
696 .channels_min = 2,
697 .channels_max = 2,
698 .rates = STA32X_RATES,
699 .formats = STA32X_FORMATS,
700 },
701 .ops = &sta32x_dai_ops,
702};
703
704#ifdef CONFIG_PM
705static int sta32x_suspend(struct snd_soc_codec *codec, pm_message_t state)
706{
707 sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF);
708 return 0;
709}
710
711static int sta32x_resume(struct snd_soc_codec *codec)
712{
713 sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
714 return 0;
715}
716#else
717#define sta32x_suspend NULL
718#define sta32x_resume NULL
719#endif
720
721static int sta32x_probe(struct snd_soc_codec *codec)
722{
723 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
724 int i, ret = 0;
725
726 sta32x->codec = codec;
727
728 /* regulators */
729 for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
730 sta32x->supplies[i].supply = sta32x_supply_names[i];
731
732 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sta32x->supplies),
733 sta32x->supplies);
734 if (ret != 0) {
735 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
736 goto err;
737 }
738
739 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
740 sta32x->supplies);
741 if (ret != 0) {
742 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
743 goto err_get;
744 }
745
746 /* Tell ASoC what kind of I/O to use to read the registers. ASoC will
747 * then do the I2C transactions itself.
748 */
749 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
750 if (ret < 0) {
751 dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret);
752 return ret;
753 }
754
755 /* read reg reset values into cache */
756 for (i = 0; i < STA32X_REGISTER_COUNT; i++)
757 snd_soc_cache_write(codec, i, sta32x_regs[i]);
758
889ebae5
JS		 759 /* preserve reset values of reserved register bits */
760 snd_soc_cache_write(codec, STA32X_CONFC,
761 codec->hw_read(codec, STA32X_CONFC));
762 snd_soc_cache_write(codec, STA32X_CONFE,
763 codec->hw_read(codec, STA32X_CONFE));
764 snd_soc_cache_write(codec, STA32X_CONFF,
765 codec->hw_read(codec, STA32X_CONFF));
766 snd_soc_cache_write(codec, STA32X_MMUTE,
767 codec->hw_read(codec, STA32X_MMUTE));
768 snd_soc_cache_write(codec, STA32X_AUTO1,
769 codec->hw_read(codec, STA32X_AUTO1));
770 snd_soc_cache_write(codec, STA32X_AUTO3,
771 codec->hw_read(codec, STA32X_AUTO3));
772 snd_soc_cache_write(codec, STA32X_C3CFG,
773 codec->hw_read(codec, STA32X_C3CFG));
774
c034abf6
JS		 775 /* FIXME enable thermal warning adjustment and recovery */
776 snd_soc_update_bits(codec, STA32X_CONFA,
777 STA32X_CONFA_TWAB | STA32X_CONFA_TWRB, 0);
778
779 /* FIXME select 2.1 mode */
780 snd_soc_update_bits(codec, STA32X_CONFF,
781 STA32X_CONFF_OCFG_MASK,
782 1 << STA32X_CONFF_OCFG_SHIFT);
783
784 /* FIXME channel to output mapping */
785 snd_soc_update_bits(codec, STA32X_C1CFG,
786 STA32X_CxCFG_OM_MASK,
787 0 << STA32X_CxCFG_OM_SHIFT);
788 snd_soc_update_bits(codec, STA32X_C2CFG,
789 STA32X_CxCFG_OM_MASK,
790 1 << STA32X_CxCFG_OM_SHIFT);
791 snd_soc_update_bits(codec, STA32X_C3CFG,
792 STA32X_CxCFG_OM_MASK,
793 2 << STA32X_CxCFG_OM_SHIFT);
794
795 sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
796 /* Bias level configuration will have done an extra enable */
797 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
798
799 return 0;
800
801err_get:
802 regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
803err:
804 return ret;
805}
806
807static int sta32x_remove(struct snd_soc_codec *codec)
808{
809 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
810
811 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
812 regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
813
814 return 0;
815}
816
79688439
JS		 817static int sta32x_reg_is_volatile(struct snd_soc_codec *codec,
818 unsigned int reg)
819{
820 switch (reg) {
821 case STA32X_CONFA ... STA32X_L2ATRT:
822 case STA32X_MPCC1 ... STA32X_FDRC2:
823 return 0;
824 }
825 return 1;
826}
827
c034abf6
JS		 828static const struct snd_soc_codec_driver sta32x_codec = {
829 .probe = sta32x_probe,
830 .remove = sta32x_remove,
831 .suspend = sta32x_suspend,
832 .resume = sta32x_resume,
833 .reg_cache_size = STA32X_REGISTER_COUNT,
834 .reg_word_size = sizeof(u8),
79688439 835 .volatile_register = sta32x_reg_is_volatile,
c034abf6
JS		 836 .set_bias_level = sta32x_set_bias_level,
837 .controls = sta32x_snd_controls,
838 .num_controls = ARRAY_SIZE(sta32x_snd_controls),
839 .dapm_widgets = sta32x_dapm_widgets,
840 .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets),
841 .dapm_routes = sta32x_dapm_routes,
842 .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes),
843};
844
845static __devinit int sta32x_i2c_probe(struct i2c_client *i2c,
846 const struct i2c_device_id *id)
847{
848 struct sta32x_priv *sta32x;
849 int ret;
850
851 sta32x = kzalloc(sizeof(struct sta32x_priv), GFP_KERNEL);
852 if (!sta32x)
853 return -ENOMEM;
854
855 i2c_set_clientdata(i2c, sta32x);
856
857 ret = snd_soc_register_codec(&i2c->dev, &sta32x_codec, &sta32x_dai, 1);
858 if (ret != 0) {
859 dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret);
860 return ret;
861 }
862
863 return 0;
864}
865
866static __devexit int sta32x_i2c_remove(struct i2c_client *client)
867{
868 struct sta32x_priv *sta32x = i2c_get_clientdata(client);
869 struct snd_soc_codec *codec = sta32x->codec;
870
871 if (codec)
872 sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF);
873
874 regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
875
876 if (codec) {
877 snd_soc_unregister_codec(&client->dev);
878 snd_soc_codec_set_drvdata(codec, NULL);
879 }
880
881 kfree(sta32x);
882 return 0;
883}
884
885static const struct i2c_device_id sta32x_i2c_id[] = {
886 { "sta326", 0 },
887 { "sta328", 0 },
888 { "sta329", 0 },
889 { }
890};
891MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
892
893static struct i2c_driver sta32x_i2c_driver = {
894 .driver = {
895 .name = "sta32x",
896 .owner = THIS_MODULE,
897 },
898 .probe = sta32x_i2c_probe,
899 .remove = __devexit_p(sta32x_i2c_remove),
900 .id_table = sta32x_i2c_id,
901};
902
903static int __init sta32x_init(void)
904{
905 return i2c_add_driver(&sta32x_i2c_driver);
906}
907module_init(sta32x_init);
908
909static void __exit sta32x_exit(void)
910{
911 i2c_del_driver(&sta32x_i2c_driver);
912}
913module_exit(sta32x_exit);
914
915MODULE_DESCRIPTION("ASoC STA32X driver");
916MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>");
917MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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