Commit | Line | Data |
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c034abf6 JS |
1 | /* |
2 | * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system | |
3 | * | |
4 | * Copyright: 2011 Raumfeld GmbH | |
5 | * Author: Johannes Stezenbach <js@sig21.net> | |
6 | * | |
7 | * based on code from: | |
8 | * Wolfson Microelectronics PLC. | |
9 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | |
10 | * Freescale Semiconductor, Inc. | |
11 | * Timur Tabi <timur@freescale.com> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
19 | #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/moduleparam.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/pm.h> | |
26 | #include <linux/i2c.h> | |
f04b1e76 TN |
27 | #include <linux/of_device.h> |
28 | #include <linux/of_gpio.h> | |
29fdf4fb | 29 | #include <linux/regmap.h> |
c034abf6 | 30 | #include <linux/regulator/consumer.h> |
b66a2980 | 31 | #include <linux/gpio/consumer.h> |
c034abf6 | 32 | #include <linux/slab.h> |
3fb5eac5 | 33 | #include <linux/workqueue.h> |
c034abf6 JS |
34 | #include <sound/core.h> |
35 | #include <sound/pcm.h> | |
36 | #include <sound/pcm_params.h> | |
37 | #include <sound/soc.h> | |
38 | #include <sound/soc-dapm.h> | |
39 | #include <sound/initval.h> | |
40 | #include <sound/tlv.h> | |
41 | ||
e012ba24 | 42 | #include <sound/sta32x.h> |
c034abf6 JS |
43 | #include "sta32x.h" |
44 | ||
45 | #define STA32X_RATES (SNDRV_PCM_RATE_32000 | \ | |
46 | SNDRV_PCM_RATE_44100 | \ | |
47 | SNDRV_PCM_RATE_48000 | \ | |
48 | SNDRV_PCM_RATE_88200 | \ | |
49 | SNDRV_PCM_RATE_96000 | \ | |
50 | SNDRV_PCM_RATE_176400 | \ | |
51 | SNDRV_PCM_RATE_192000) | |
52 | ||
53 | #define STA32X_FORMATS \ | |
54 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \ | |
55 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \ | |
56 | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
57 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \ | |
58 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \ | |
59 | SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE) | |
60 | ||
61 | /* Power-up register defaults */ | |
29fdf4fb MB |
62 | static const struct reg_default sta32x_regs[] = { |
63 | { 0x0, 0x63 }, | |
64 | { 0x1, 0x80 }, | |
65 | { 0x2, 0xc2 }, | |
66 | { 0x3, 0x40 }, | |
67 | { 0x4, 0xc2 }, | |
68 | { 0x5, 0x5c }, | |
69 | { 0x6, 0x10 }, | |
70 | { 0x7, 0xff }, | |
71 | { 0x8, 0x60 }, | |
72 | { 0x9, 0x60 }, | |
73 | { 0xa, 0x60 }, | |
74 | { 0xb, 0x80 }, | |
75 | { 0xc, 0x00 }, | |
76 | { 0xd, 0x00 }, | |
77 | { 0xe, 0x00 }, | |
78 | { 0xf, 0x40 }, | |
79 | { 0x10, 0x80 }, | |
80 | { 0x11, 0x77 }, | |
81 | { 0x12, 0x6a }, | |
82 | { 0x13, 0x69 }, | |
83 | { 0x14, 0x6a }, | |
84 | { 0x15, 0x69 }, | |
85 | { 0x16, 0x00 }, | |
86 | { 0x17, 0x00 }, | |
87 | { 0x18, 0x00 }, | |
88 | { 0x19, 0x00 }, | |
89 | { 0x1a, 0x00 }, | |
90 | { 0x1b, 0x00 }, | |
91 | { 0x1c, 0x00 }, | |
92 | { 0x1d, 0x00 }, | |
93 | { 0x1e, 0x00 }, | |
94 | { 0x1f, 0x00 }, | |
95 | { 0x20, 0x00 }, | |
96 | { 0x21, 0x00 }, | |
97 | { 0x22, 0x00 }, | |
98 | { 0x23, 0x00 }, | |
99 | { 0x24, 0x00 }, | |
100 | { 0x25, 0x00 }, | |
101 | { 0x26, 0x00 }, | |
102 | { 0x27, 0x2d }, | |
103 | { 0x28, 0xc0 }, | |
104 | { 0x2b, 0x00 }, | |
105 | { 0x2c, 0x0c }, | |
c034abf6 JS |
106 | }; |
107 | ||
a1be4cea | 108 | static const struct regmap_range sta32x_write_regs_range[] = { |
148388f3 | 109 | regmap_reg_range(STA32X_CONFA, STA32X_FDRC2), |
a1be4cea TN |
110 | }; |
111 | ||
112 | static const struct regmap_range sta32x_read_regs_range[] = { | |
148388f3 | 113 | regmap_reg_range(STA32X_CONFA, STA32X_FDRC2), |
a1be4cea TN |
114 | }; |
115 | ||
116 | static const struct regmap_range sta32x_volatile_regs_range[] = { | |
117 | regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD), | |
118 | }; | |
119 | ||
120 | static const struct regmap_access_table sta32x_write_regs = { | |
121 | .yes_ranges = sta32x_write_regs_range, | |
122 | .n_yes_ranges = ARRAY_SIZE(sta32x_write_regs_range), | |
123 | }; | |
124 | ||
125 | static const struct regmap_access_table sta32x_read_regs = { | |
126 | .yes_ranges = sta32x_read_regs_range, | |
127 | .n_yes_ranges = ARRAY_SIZE(sta32x_read_regs_range), | |
128 | }; | |
129 | ||
130 | static const struct regmap_access_table sta32x_volatile_regs = { | |
131 | .yes_ranges = sta32x_volatile_regs_range, | |
132 | .n_yes_ranges = ARRAY_SIZE(sta32x_volatile_regs_range), | |
133 | }; | |
134 | ||
c034abf6 JS |
135 | /* regulator power supply names */ |
136 | static const char *sta32x_supply_names[] = { | |
137 | "Vdda", /* analog supply, 3.3VV */ | |
138 | "Vdd3", /* digital supply, 3.3V */ | |
139 | "Vcc" /* power amp spply, 10V - 36V */ | |
140 | }; | |
141 | ||
142 | /* codec private data */ | |
143 | struct sta32x_priv { | |
29fdf4fb | 144 | struct regmap *regmap; |
c034abf6 JS |
145 | struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)]; |
146 | struct snd_soc_codec *codec; | |
e012ba24 | 147 | struct sta32x_platform_data *pdata; |
c034abf6 JS |
148 | |
149 | unsigned int mclk; | |
150 | unsigned int format; | |
54dc6cab JS |
151 | |
152 | u32 coef_shadow[STA32X_COEF_COUNT]; | |
3fb5eac5 JS |
153 | struct delayed_work watchdog_work; |
154 | int shutdown; | |
b66a2980 | 155 | struct gpio_desc *gpiod_nreset; |
a1be4cea | 156 | struct mutex coeff_lock; |
c034abf6 JS |
157 | }; |
158 | ||
159 | static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1); | |
160 | static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1); | |
161 | static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0); | |
162 | ||
163 | static const char *sta32x_drc_ac[] = { | |
164 | "Anti-Clipping", "Dynamic Range Compression" }; | |
165 | static const char *sta32x_auto_eq_mode[] = { | |
166 | "User", "Preset", "Loudness" }; | |
167 | static const char *sta32x_auto_gc_mode[] = { | |
168 | "User", "AC no clipping", "AC limited clipping (10%)", | |
169 | "DRC nighttime listening mode" }; | |
170 | static const char *sta32x_auto_xo_mode[] = { | |
171 | "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz", | |
172 | "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" }; | |
173 | static const char *sta32x_preset_eq_mode[] = { | |
174 | "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft", | |
175 | "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1", | |
176 | "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2", | |
177 | "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7", | |
178 | "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12", | |
179 | "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" }; | |
180 | static const char *sta32x_limiter_select[] = { | |
181 | "Limiter Disabled", "Limiter #1", "Limiter #2" }; | |
182 | static const char *sta32x_limiter_attack_rate[] = { | |
183 | "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024", | |
184 | "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752", | |
185 | "0.0645", "0.0564", "0.0501", "0.0451" }; | |
186 | static const char *sta32x_limiter_release_rate[] = { | |
187 | "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299", | |
188 | "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137", | |
189 | "0.0134", "0.0117", "0.0110", "0.0104" }; | |
88483f59 | 190 | static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_attack_tlv, |
c034abf6 JS |
191 | 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0), |
192 | 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0), | |
88483f59 | 193 | ); |
c034abf6 | 194 | |
88483f59 | 195 | static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_release_tlv, |
c034abf6 JS |
196 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), |
197 | 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0), | |
198 | 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0), | |
199 | 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0), | |
200 | 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0), | |
88483f59 | 201 | ); |
c034abf6 | 202 | |
88483f59 | 203 | static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_attack_tlv, |
c034abf6 JS |
204 | 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0), |
205 | 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0), | |
206 | 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0), | |
88483f59 | 207 | ); |
c034abf6 | 208 | |
88483f59 | 209 | static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_release_tlv, |
c034abf6 JS |
210 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), |
211 | 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0), | |
212 | 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0), | |
213 | 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0), | |
214 | 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0), | |
88483f59 | 215 | ); |
c034abf6 | 216 | |
025c3fa9 TI |
217 | static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum, |
218 | STA32X_CONFD, STA32X_CONFD_DRC_SHIFT, | |
219 | sta32x_drc_ac); | |
220 | static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum, | |
221 | STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT, | |
222 | sta32x_auto_eq_mode); | |
223 | static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum, | |
224 | STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT, | |
225 | sta32x_auto_gc_mode); | |
226 | static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum, | |
227 | STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT, | |
228 | sta32x_auto_xo_mode); | |
229 | static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum, | |
230 | STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT, | |
231 | sta32x_preset_eq_mode); | |
232 | static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum, | |
233 | STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT, | |
234 | sta32x_limiter_select); | |
235 | static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum, | |
236 | STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT, | |
237 | sta32x_limiter_select); | |
238 | static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum, | |
239 | STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT, | |
240 | sta32x_limiter_select); | |
241 | static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum, | |
242 | STA32X_L1AR, STA32X_LxA_SHIFT, | |
243 | sta32x_limiter_attack_rate); | |
244 | static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum, | |
245 | STA32X_L2AR, STA32X_LxA_SHIFT, | |
246 | sta32x_limiter_attack_rate); | |
247 | static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum, | |
248 | STA32X_L1AR, STA32X_LxR_SHIFT, | |
249 | sta32x_limiter_release_rate); | |
250 | static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum, | |
251 | STA32X_L2AR, STA32X_LxR_SHIFT, | |
252 | sta32x_limiter_release_rate); | |
79688439 JS |
253 | |
254 | /* byte array controls for setting biquad, mixer, scaling coefficients; | |
255 | * for biquads all five coefficients need to be set in one go, | |
256 | * mixer and pre/postscale coefs can be set individually; | |
257 | * each coef is 24bit, the bytes are ordered in the same way | |
258 | * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0) | |
259 | */ | |
260 | ||
261 | static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol, | |
262 | struct snd_ctl_elem_info *uinfo) | |
263 | { | |
264 | int numcoef = kcontrol->private_value >> 16; | |
265 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; | |
266 | uinfo->count = 3 * numcoef; | |
267 | return 0; | |
268 | } | |
269 | ||
270 | static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol, | |
271 | struct snd_ctl_elem_value *ucontrol) | |
272 | { | |
ea53bf77 | 273 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
a1be4cea | 274 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
79688439 JS |
275 | int numcoef = kcontrol->private_value >> 16; |
276 | int index = kcontrol->private_value & 0xffff; | |
a1be4cea TN |
277 | unsigned int cfud, val; |
278 | int i, ret = 0; | |
279 | ||
280 | mutex_lock(&sta32x->coeff_lock); | |
79688439 JS |
281 | |
282 | /* preserve reserved bits in STA32X_CFUD */ | |
a1be4cea TN |
283 | regmap_read(sta32x->regmap, STA32X_CFUD, &cfud); |
284 | cfud &= 0xf0; | |
285 | /* | |
286 | * chip documentation does not say if the bits are self clearing, | |
287 | * so do it explicitly | |
288 | */ | |
289 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud); | |
79688439 | 290 | |
a1be4cea TN |
291 | regmap_write(sta32x->regmap, STA32X_CFADDR2, index); |
292 | if (numcoef == 1) { | |
293 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04); | |
294 | } else if (numcoef == 5) { | |
295 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08); | |
296 | } else { | |
297 | ret = -EINVAL; | |
298 | goto exit_unlock; | |
299 | } | |
79688439 | 300 | |
a1be4cea TN |
301 | for (i = 0; i < 3 * numcoef; i++) { |
302 | regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val); | |
303 | ucontrol->value.bytes.data[i] = val; | |
304 | } | |
305 | ||
306 | exit_unlock: | |
307 | mutex_unlock(&sta32x->coeff_lock); | |
308 | ||
309 | return ret; | |
79688439 JS |
310 | } |
311 | ||
312 | static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol, | |
313 | struct snd_ctl_elem_value *ucontrol) | |
314 | { | |
ea53bf77 | 315 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
54dc6cab | 316 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
79688439 JS |
317 | int numcoef = kcontrol->private_value >> 16; |
318 | int index = kcontrol->private_value & 0xffff; | |
319 | unsigned int cfud; | |
320 | int i; | |
321 | ||
322 | /* preserve reserved bits in STA32X_CFUD */ | |
a1be4cea TN |
323 | regmap_read(sta32x->regmap, STA32X_CFUD, &cfud); |
324 | cfud &= 0xf0; | |
325 | /* | |
326 | * chip documentation does not say if the bits are self clearing, | |
327 | * so do it explicitly | |
328 | */ | |
329 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud); | |
79688439 | 330 | |
a1be4cea | 331 | regmap_write(sta32x->regmap, STA32X_CFADDR2, index); |
54dc6cab JS |
332 | for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++) |
333 | sta32x->coef_shadow[index + i] = | |
334 | (ucontrol->value.bytes.data[3 * i] << 16) | |
335 | | (ucontrol->value.bytes.data[3 * i + 1] << 8) | |
336 | | (ucontrol->value.bytes.data[3 * i + 2]); | |
79688439 | 337 | for (i = 0; i < 3 * numcoef; i++) |
a1be4cea TN |
338 | regmap_write(sta32x->regmap, STA32X_B1CF1 + i, |
339 | ucontrol->value.bytes.data[i]); | |
79688439 | 340 | if (numcoef == 1) |
a1be4cea | 341 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01); |
79688439 | 342 | else if (numcoef == 5) |
a1be4cea | 343 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02); |
79688439 JS |
344 | else |
345 | return -EINVAL; | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
878042d1 | 350 | static int sta32x_sync_coef_shadow(struct snd_soc_codec *codec) |
54dc6cab JS |
351 | { |
352 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
353 | unsigned int cfud; | |
354 | int i; | |
355 | ||
356 | /* preserve reserved bits in STA32X_CFUD */ | |
a1be4cea TN |
357 | regmap_read(sta32x->regmap, STA32X_CFUD, &cfud); |
358 | cfud &= 0xf0; | |
54dc6cab JS |
359 | |
360 | for (i = 0; i < STA32X_COEF_COUNT; i++) { | |
a1be4cea TN |
361 | regmap_write(sta32x->regmap, STA32X_CFADDR2, i); |
362 | regmap_write(sta32x->regmap, STA32X_B1CF1, | |
363 | (sta32x->coef_shadow[i] >> 16) & 0xff); | |
364 | regmap_write(sta32x->regmap, STA32X_B1CF2, | |
365 | (sta32x->coef_shadow[i] >> 8) & 0xff); | |
366 | regmap_write(sta32x->regmap, STA32X_B1CF3, | |
367 | (sta32x->coef_shadow[i]) & 0xff); | |
368 | /* | |
369 | * chip documentation does not say if the bits are | |
370 | * self-clearing, so do it explicitly | |
371 | */ | |
372 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud); | |
373 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01); | |
54dc6cab JS |
374 | } |
375 | return 0; | |
376 | } | |
377 | ||
878042d1 | 378 | static int sta32x_cache_sync(struct snd_soc_codec *codec) |
54dc6cab | 379 | { |
70ff00f8 | 380 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
54dc6cab JS |
381 | unsigned int mute; |
382 | int rc; | |
383 | ||
54dc6cab | 384 | /* mute during register sync */ |
a1be4cea TN |
385 | regmap_read(sta32x->regmap, STA32X_MMUTE, &mute); |
386 | regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE); | |
54dc6cab | 387 | sta32x_sync_coef_shadow(codec); |
29fdf4fb | 388 | rc = regcache_sync(sta32x->regmap); |
a1be4cea | 389 | regmap_write(sta32x->regmap, STA32X_MMUTE, mute); |
54dc6cab JS |
390 | return rc; |
391 | } | |
392 | ||
3fb5eac5 JS |
393 | /* work around ESD issue where sta32x resets and loses all configuration */ |
394 | static void sta32x_watchdog(struct work_struct *work) | |
395 | { | |
396 | struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv, | |
397 | watchdog_work.work); | |
398 | struct snd_soc_codec *codec = sta32x->codec; | |
399 | unsigned int confa, confa_cached; | |
400 | ||
401 | /* check if sta32x has reset itself */ | |
402 | confa_cached = snd_soc_read(codec, STA32X_CONFA); | |
29fdf4fb | 403 | regcache_cache_bypass(sta32x->regmap, true); |
3fb5eac5 | 404 | confa = snd_soc_read(codec, STA32X_CONFA); |
29fdf4fb | 405 | regcache_cache_bypass(sta32x->regmap, false); |
3fb5eac5 | 406 | if (confa != confa_cached) { |
29fdf4fb | 407 | regcache_mark_dirty(sta32x->regmap); |
3fb5eac5 JS |
408 | sta32x_cache_sync(codec); |
409 | } | |
410 | ||
411 | if (!sta32x->shutdown) | |
a14d9829 MB |
412 | queue_delayed_work(system_power_efficient_wq, |
413 | &sta32x->watchdog_work, | |
414 | round_jiffies_relative(HZ)); | |
3fb5eac5 JS |
415 | } |
416 | ||
417 | static void sta32x_watchdog_start(struct sta32x_priv *sta32x) | |
418 | { | |
419 | if (sta32x->pdata->needs_esd_watchdog) { | |
420 | sta32x->shutdown = 0; | |
a14d9829 MB |
421 | queue_delayed_work(system_power_efficient_wq, |
422 | &sta32x->watchdog_work, | |
423 | round_jiffies_relative(HZ)); | |
3fb5eac5 JS |
424 | } |
425 | } | |
426 | ||
427 | static void sta32x_watchdog_stop(struct sta32x_priv *sta32x) | |
428 | { | |
429 | if (sta32x->pdata->needs_esd_watchdog) { | |
430 | sta32x->shutdown = 1; | |
431 | cancel_delayed_work_sync(&sta32x->watchdog_work); | |
432 | } | |
433 | } | |
434 | ||
79688439 JS |
435 | #define SINGLE_COEF(xname, index) \ |
436 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
437 | .info = sta32x_coefficient_info, \ | |
438 | .get = sta32x_coefficient_get,\ | |
439 | .put = sta32x_coefficient_put, \ | |
440 | .private_value = index | (1 << 16) } | |
441 | ||
442 | #define BIQUAD_COEFS(xname, index) \ | |
443 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
444 | .info = sta32x_coefficient_info, \ | |
445 | .get = sta32x_coefficient_get,\ | |
446 | .put = sta32x_coefficient_put, \ | |
447 | .private_value = index | (5 << 16) } | |
448 | ||
c034abf6 JS |
449 | static const struct snd_kcontrol_new sta32x_snd_controls[] = { |
450 | SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv), | |
451 | SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1), | |
452 | SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1), | |
453 | SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1), | |
454 | SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1), | |
455 | SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv), | |
456 | SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv), | |
457 | SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv), | |
458 | SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0), | |
459 | SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum), | |
460 | SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0), | |
461 | SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0), | |
462 | SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0), | |
463 | SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0), | |
464 | SOC_ENUM("Automode EQ", sta32x_auto_eq_enum), | |
465 | SOC_ENUM("Automode GC", sta32x_auto_gc_enum), | |
466 | SOC_ENUM("Automode XO", sta32x_auto_xo_enum), | |
467 | SOC_ENUM("Preset EQ", sta32x_preset_eq_enum), | |
468 | SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), | |
469 | SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), | |
470 | SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), | |
471 | SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), | |
472 | SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), | |
473 | SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), | |
474 | SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), | |
475 | SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum), | |
476 | SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum), | |
477 | SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum), | |
478 | SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv), | |
479 | SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv), | |
480 | SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum), | |
481 | SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum), | |
482 | SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum), | |
b3619b28 | 483 | SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum), |
c034abf6 JS |
484 | |
485 | /* depending on mode, the attack/release thresholds have | |
486 | * two different enum definitions; provide both | |
487 | */ | |
488 | SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, | |
489 | 16, 0, sta32x_limiter_ac_attack_tlv), | |
490 | SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, | |
491 | 16, 0, sta32x_limiter_ac_attack_tlv), | |
492 | SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, | |
493 | 16, 0, sta32x_limiter_ac_release_tlv), | |
494 | SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, | |
495 | 16, 0, sta32x_limiter_ac_release_tlv), | |
496 | SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, | |
497 | 16, 0, sta32x_limiter_drc_attack_tlv), | |
498 | SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, | |
499 | 16, 0, sta32x_limiter_drc_attack_tlv), | |
500 | SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, | |
501 | 16, 0, sta32x_limiter_drc_release_tlv), | |
502 | SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, | |
503 | 16, 0, sta32x_limiter_drc_release_tlv), | |
79688439 JS |
504 | |
505 | BIQUAD_COEFS("Ch1 - Biquad 1", 0), | |
506 | BIQUAD_COEFS("Ch1 - Biquad 2", 5), | |
507 | BIQUAD_COEFS("Ch1 - Biquad 3", 10), | |
508 | BIQUAD_COEFS("Ch1 - Biquad 4", 15), | |
509 | BIQUAD_COEFS("Ch2 - Biquad 1", 20), | |
510 | BIQUAD_COEFS("Ch2 - Biquad 2", 25), | |
511 | BIQUAD_COEFS("Ch2 - Biquad 3", 30), | |
512 | BIQUAD_COEFS("Ch2 - Biquad 4", 35), | |
513 | BIQUAD_COEFS("High-pass", 40), | |
514 | BIQUAD_COEFS("Low-pass", 45), | |
515 | SINGLE_COEF("Ch1 - Prescale", 50), | |
516 | SINGLE_COEF("Ch2 - Prescale", 51), | |
517 | SINGLE_COEF("Ch1 - Postscale", 52), | |
518 | SINGLE_COEF("Ch2 - Postscale", 53), | |
519 | SINGLE_COEF("Ch3 - Postscale", 54), | |
520 | SINGLE_COEF("Thermal warning - Postscale", 55), | |
521 | SINGLE_COEF("Ch1 - Mix 1", 56), | |
522 | SINGLE_COEF("Ch1 - Mix 2", 57), | |
523 | SINGLE_COEF("Ch2 - Mix 1", 58), | |
524 | SINGLE_COEF("Ch2 - Mix 2", 59), | |
525 | SINGLE_COEF("Ch3 - Mix 1", 60), | |
526 | SINGLE_COEF("Ch3 - Mix 2", 61), | |
c034abf6 JS |
527 | }; |
528 | ||
529 | static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = { | |
530 | SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0), | |
531 | SND_SOC_DAPM_OUTPUT("LEFT"), | |
532 | SND_SOC_DAPM_OUTPUT("RIGHT"), | |
533 | SND_SOC_DAPM_OUTPUT("SUB"), | |
534 | }; | |
535 | ||
536 | static const struct snd_soc_dapm_route sta32x_dapm_routes[] = { | |
537 | { "LEFT", NULL, "DAC" }, | |
538 | { "RIGHT", NULL, "DAC" }, | |
539 | { "SUB", NULL, "DAC" }, | |
540 | }; | |
541 | ||
542 | /* MCLK interpolation ratio per fs */ | |
543 | static struct { | |
544 | int fs; | |
545 | int ir; | |
546 | } interpolation_ratios[] = { | |
547 | { 32000, 0 }, | |
548 | { 44100, 0 }, | |
549 | { 48000, 0 }, | |
550 | { 88200, 1 }, | |
551 | { 96000, 1 }, | |
552 | { 176400, 2 }, | |
553 | { 192000, 2 }, | |
554 | }; | |
555 | ||
556 | /* MCLK to fs clock ratios */ | |
1c34c876 TN |
557 | static int mcs_ratio_table[3][7] = { |
558 | { 768, 512, 384, 256, 128, 576, 0 }, | |
559 | { 384, 256, 192, 128, 64, 0 }, | |
560 | { 384, 256, 192, 128, 64, 0 }, | |
c034abf6 JS |
561 | }; |
562 | ||
c034abf6 JS |
563 | /** |
564 | * sta32x_set_dai_sysclk - configure MCLK | |
565 | * @codec_dai: the codec DAI | |
566 | * @clk_id: the clock ID (ignored) | |
567 | * @freq: the MCLK input frequency | |
568 | * @dir: the clock direction (ignored) | |
569 | * | |
570 | * The value of MCLK is used to determine which sample rates are supported | |
571 | * by the STA32X, based on the mclk_ratios table. | |
572 | * | |
573 | * This function must be called by the machine driver's 'startup' function, | |
574 | * otherwise the list of supported sample rates will not be available in | |
575 | * time for ALSA. | |
576 | * | |
577 | * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause | |
578 | * theoretically possible sample rates to be enabled. Call it again with a | |
579 | * proper value set one the external clock is set (most probably you would do | |
580 | * that from a machine's driver 'hw_param' hook. | |
581 | */ | |
582 | static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
583 | int clk_id, unsigned int freq, int dir) | |
584 | { | |
585 | struct snd_soc_codec *codec = codec_dai->codec; | |
586 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
c034abf6 | 587 | |
1c34c876 | 588 | dev_dbg(codec->dev, "mclk=%u\n", freq); |
c034abf6 JS |
589 | sta32x->mclk = freq; |
590 | ||
c034abf6 JS |
591 | return 0; |
592 | } | |
593 | ||
594 | /** | |
595 | * sta32x_set_dai_fmt - configure the codec for the selected audio format | |
596 | * @codec_dai: the codec DAI | |
597 | * @fmt: a SND_SOC_DAIFMT_x value indicating the data format | |
598 | * | |
599 | * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the | |
600 | * codec accordingly. | |
601 | */ | |
602 | static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
603 | unsigned int fmt) | |
604 | { | |
605 | struct snd_soc_codec *codec = codec_dai->codec; | |
606 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
a1be4cea | 607 | u8 confb = 0; |
c034abf6 JS |
608 | |
609 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
610 | case SND_SOC_DAIFMT_CBS_CFS: | |
611 | break; | |
612 | default: | |
613 | return -EINVAL; | |
614 | } | |
615 | ||
616 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
617 | case SND_SOC_DAIFMT_I2S: | |
618 | case SND_SOC_DAIFMT_RIGHT_J: | |
619 | case SND_SOC_DAIFMT_LEFT_J: | |
620 | sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
621 | break; | |
622 | default: | |
623 | return -EINVAL; | |
624 | } | |
625 | ||
626 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
627 | case SND_SOC_DAIFMT_NB_NF: | |
628 | confb |= STA32X_CONFB_C2IM; | |
629 | break; | |
630 | case SND_SOC_DAIFMT_NB_IF: | |
631 | confb |= STA32X_CONFB_C1IM; | |
632 | break; | |
633 | default: | |
634 | return -EINVAL; | |
635 | } | |
636 | ||
a1be4cea TN |
637 | return regmap_update_bits(sta32x->regmap, STA32X_CONFB, |
638 | STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb); | |
c034abf6 JS |
639 | } |
640 | ||
641 | /** | |
642 | * sta32x_hw_params - program the STA32X with the given hardware parameters. | |
643 | * @substream: the audio stream | |
644 | * @params: the hardware parameters to set | |
645 | * @dai: the SOC DAI (ignored) | |
646 | * | |
647 | * This function programs the hardware with the values provided. | |
648 | * Specifically, the sample rate and the data format. | |
649 | */ | |
650 | static int sta32x_hw_params(struct snd_pcm_substream *substream, | |
651 | struct snd_pcm_hw_params *params, | |
652 | struct snd_soc_dai *dai) | |
653 | { | |
e6968a17 | 654 | struct snd_soc_codec *codec = dai->codec; |
c034abf6 | 655 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
1c34c876 | 656 | int i, mcs = -EINVAL, ir = -EINVAL; |
a1be4cea | 657 | unsigned int confa, confb; |
1c34c876 TN |
658 | unsigned int rate, ratio; |
659 | int ret; | |
660 | ||
661 | if (!sta32x->mclk) { | |
662 | dev_err(codec->dev, | |
663 | "sta32x->mclk is unset. Unable to determine ratio\n"); | |
664 | return -EIO; | |
665 | } | |
c034abf6 JS |
666 | |
667 | rate = params_rate(params); | |
1c34c876 TN |
668 | ratio = sta32x->mclk / rate; |
669 | dev_dbg(codec->dev, "rate: %u, ratio: %u\n", rate, ratio); | |
670 | ||
671 | for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) { | |
a595238b | 672 | if (interpolation_ratios[i].fs == rate) { |
c034abf6 | 673 | ir = interpolation_ratios[i].ir; |
a595238b AL |
674 | break; |
675 | } | |
1c34c876 TN |
676 | } |
677 | ||
678 | if (ir < 0) { | |
679 | dev_err(codec->dev, "Unsupported samplerate: %u\n", rate); | |
c034abf6 | 680 | return -EINVAL; |
1c34c876 TN |
681 | } |
682 | ||
683 | for (i = 0; i < 6; i++) { | |
684 | if (mcs_ratio_table[ir][i] == ratio) { | |
685 | mcs = i; | |
a595238b AL |
686 | break; |
687 | } | |
1c34c876 TN |
688 | } |
689 | ||
690 | if (mcs < 0) { | |
691 | dev_err(codec->dev, "Unresolvable ratio: %u\n", ratio); | |
c034abf6 | 692 | return -EINVAL; |
1c34c876 | 693 | } |
c034abf6 | 694 | |
a1be4cea TN |
695 | confa = (ir << STA32X_CONFA_IR_SHIFT) | |
696 | (mcs << STA32X_CONFA_MCS_SHIFT); | |
697 | confb = 0; | |
c034abf6 | 698 | |
737e0f89 MB |
699 | switch (params_width(params)) { |
700 | case 24: | |
30374d5d | 701 | dev_dbg(codec->dev, "24bit\n"); |
c034abf6 | 702 | /* fall through */ |
737e0f89 | 703 | case 32: |
30374d5d | 704 | dev_dbg(codec->dev, "24bit or 32bit\n"); |
c034abf6 JS |
705 | switch (sta32x->format) { |
706 | case SND_SOC_DAIFMT_I2S: | |
707 | confb |= 0x0; | |
708 | break; | |
709 | case SND_SOC_DAIFMT_LEFT_J: | |
710 | confb |= 0x1; | |
711 | break; | |
712 | case SND_SOC_DAIFMT_RIGHT_J: | |
713 | confb |= 0x2; | |
714 | break; | |
715 | } | |
716 | ||
717 | break; | |
737e0f89 | 718 | case 20: |
30374d5d | 719 | dev_dbg(codec->dev, "20bit\n"); |
c034abf6 JS |
720 | switch (sta32x->format) { |
721 | case SND_SOC_DAIFMT_I2S: | |
722 | confb |= 0x4; | |
723 | break; | |
724 | case SND_SOC_DAIFMT_LEFT_J: | |
725 | confb |= 0x5; | |
726 | break; | |
727 | case SND_SOC_DAIFMT_RIGHT_J: | |
728 | confb |= 0x6; | |
729 | break; | |
730 | } | |
731 | ||
732 | break; | |
737e0f89 | 733 | case 18: |
30374d5d | 734 | dev_dbg(codec->dev, "18bit\n"); |
c034abf6 JS |
735 | switch (sta32x->format) { |
736 | case SND_SOC_DAIFMT_I2S: | |
737 | confb |= 0x8; | |
738 | break; | |
739 | case SND_SOC_DAIFMT_LEFT_J: | |
740 | confb |= 0x9; | |
741 | break; | |
742 | case SND_SOC_DAIFMT_RIGHT_J: | |
743 | confb |= 0xa; | |
744 | break; | |
745 | } | |
746 | ||
747 | break; | |
737e0f89 | 748 | case 16: |
30374d5d | 749 | dev_dbg(codec->dev, "16bit\n"); |
c034abf6 JS |
750 | switch (sta32x->format) { |
751 | case SND_SOC_DAIFMT_I2S: | |
752 | confb |= 0x0; | |
753 | break; | |
754 | case SND_SOC_DAIFMT_LEFT_J: | |
755 | confb |= 0xd; | |
756 | break; | |
757 | case SND_SOC_DAIFMT_RIGHT_J: | |
758 | confb |= 0xe; | |
759 | break; | |
760 | } | |
761 | ||
762 | break; | |
763 | default: | |
764 | return -EINVAL; | |
765 | } | |
766 | ||
a1be4cea TN |
767 | ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA, |
768 | STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK, | |
769 | confa); | |
770 | if (ret < 0) | |
771 | return ret; | |
772 | ||
773 | ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB, | |
774 | STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB, | |
775 | confb); | |
776 | if (ret < 0) | |
777 | return ret; | |
778 | ||
779 | return 0; | |
780 | } | |
b66a2980 TN |
781 | |
782 | static int sta32x_startup_sequence(struct sta32x_priv *sta32x) | |
783 | { | |
784 | if (sta32x->gpiod_nreset) { | |
785 | gpiod_set_value(sta32x->gpiod_nreset, 0); | |
786 | mdelay(1); | |
787 | gpiod_set_value(sta32x->gpiod_nreset, 1); | |
788 | mdelay(1); | |
789 | } | |
790 | ||
c034abf6 JS |
791 | return 0; |
792 | } | |
793 | ||
794 | /** | |
795 | * sta32x_set_bias_level - DAPM callback | |
796 | * @codec: the codec device | |
797 | * @level: DAPM power level | |
798 | * | |
799 | * This is called by ALSA to put the codec into low power mode | |
800 | * or to wake it up. If the codec is powered off completely | |
801 | * all registers must be restored after power on. | |
802 | */ | |
803 | static int sta32x_set_bias_level(struct snd_soc_codec *codec, | |
804 | enum snd_soc_bias_level level) | |
805 | { | |
806 | int ret; | |
807 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
808 | ||
30374d5d | 809 | dev_dbg(codec->dev, "level = %d\n", level); |
c034abf6 JS |
810 | switch (level) { |
811 | case SND_SOC_BIAS_ON: | |
812 | break; | |
813 | ||
814 | case SND_SOC_BIAS_PREPARE: | |
815 | /* Full power on */ | |
a1be4cea | 816 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, |
c034abf6 JS |
817 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, |
818 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); | |
819 | break; | |
820 | ||
821 | case SND_SOC_BIAS_STANDBY: | |
cc740ec8 | 822 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { |
c034abf6 JS |
823 | ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), |
824 | sta32x->supplies); | |
825 | if (ret != 0) { | |
826 | dev_err(codec->dev, | |
827 | "Failed to enable supplies: %d\n", ret); | |
828 | return ret; | |
829 | } | |
830 | ||
b66a2980 | 831 | sta32x_startup_sequence(sta32x); |
54dc6cab | 832 | sta32x_cache_sync(codec); |
3fb5eac5 | 833 | sta32x_watchdog_start(sta32x); |
c034abf6 JS |
834 | } |
835 | ||
a1be4cea TN |
836 | /* Power down */ |
837 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, | |
838 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | |
839 | 0); | |
c034abf6 JS |
840 | |
841 | break; | |
842 | ||
843 | case SND_SOC_BIAS_OFF: | |
844 | /* The chip runs through the power down sequence for us. */ | |
a1be4cea TN |
845 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, |
846 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0); | |
c034abf6 | 847 | msleep(300); |
3fb5eac5 | 848 | sta32x_watchdog_stop(sta32x); |
b66a2980 TN |
849 | |
850 | if (sta32x->gpiod_nreset) | |
851 | gpiod_set_value(sta32x->gpiod_nreset, 0); | |
852 | ||
c034abf6 JS |
853 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), |
854 | sta32x->supplies); | |
855 | break; | |
856 | } | |
c034abf6 JS |
857 | return 0; |
858 | } | |
859 | ||
85e7652d | 860 | static const struct snd_soc_dai_ops sta32x_dai_ops = { |
c034abf6 JS |
861 | .hw_params = sta32x_hw_params, |
862 | .set_sysclk = sta32x_set_dai_sysclk, | |
863 | .set_fmt = sta32x_set_dai_fmt, | |
864 | }; | |
865 | ||
866 | static struct snd_soc_dai_driver sta32x_dai = { | |
3c9390ad | 867 | .name = "sta32x-hifi", |
c034abf6 JS |
868 | .playback = { |
869 | .stream_name = "Playback", | |
870 | .channels_min = 2, | |
871 | .channels_max = 2, | |
872 | .rates = STA32X_RATES, | |
873 | .formats = STA32X_FORMATS, | |
874 | }, | |
875 | .ops = &sta32x_dai_ops, | |
876 | }; | |
877 | ||
c034abf6 JS |
878 | static int sta32x_probe(struct snd_soc_codec *codec) |
879 | { | |
880 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
a1be4cea | 881 | struct sta32x_platform_data *pdata = sta32x->pdata; |
e012ba24 | 882 | int i, ret = 0, thermal = 0; |
c034abf6 JS |
883 | ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), |
884 | sta32x->supplies); | |
885 | if (ret != 0) { | |
886 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
aff041af | 887 | return ret; |
c034abf6 JS |
888 | } |
889 | ||
b66a2980 TN |
890 | ret = sta32x_startup_sequence(sta32x); |
891 | if (ret < 0) { | |
892 | dev_err(codec->dev, "Failed to startup device\n"); | |
893 | return ret; | |
894 | } | |
f04b1e76 TN |
895 | |
896 | /* CONFA */ | |
a1be4cea | 897 | if (!pdata->thermal_warning_recovery) |
e012ba24 | 898 | thermal |= STA32X_CONFA_TWAB; |
a1be4cea | 899 | if (!pdata->thermal_warning_adjustment) |
e012ba24 | 900 | thermal |= STA32X_CONFA_TWRB; |
f04b1e76 TN |
901 | if (!pdata->fault_detect_recovery) |
902 | thermal |= STA32X_CONFA_FDRB; | |
a1be4cea | 903 | regmap_update_bits(sta32x->regmap, STA32X_CONFA, |
f04b1e76 TN |
904 | STA32X_CONFA_TWAB | STA32X_CONFA_TWRB | |
905 | STA32X_CONFA_FDRB, | |
a1be4cea | 906 | thermal); |
c034abf6 | 907 | |
f04b1e76 TN |
908 | /* CONFC */ |
909 | regmap_update_bits(sta32x->regmap, STA32X_CONFC, | |
910 | STA32X_CONFC_CSZ_MASK, | |
911 | pdata->drop_compensation_ns | |
912 | << STA32X_CONFC_CSZ_SHIFT); | |
913 | ||
914 | /* CONFE */ | |
915 | regmap_update_bits(sta32x->regmap, STA32X_CONFE, | |
916 | STA32X_CONFE_MPCV, | |
917 | pdata->max_power_use_mpcc ? | |
918 | STA32X_CONFE_MPCV : 0); | |
919 | regmap_update_bits(sta32x->regmap, STA32X_CONFE, | |
920 | STA32X_CONFE_MPC, | |
921 | pdata->max_power_correction ? | |
922 | STA32X_CONFE_MPC : 0); | |
923 | regmap_update_bits(sta32x->regmap, STA32X_CONFE, | |
924 | STA32X_CONFE_AME, | |
925 | pdata->am_reduction_mode ? | |
926 | STA32X_CONFE_AME : 0); | |
927 | regmap_update_bits(sta32x->regmap, STA32X_CONFE, | |
928 | STA32X_CONFE_PWMS, | |
929 | pdata->odd_pwm_speed_mode ? | |
930 | STA32X_CONFE_PWMS : 0); | |
931 | ||
932 | /* CONFF */ | |
933 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, | |
934 | STA32X_CONFF_IDE, | |
935 | pdata->invalid_input_detect_mute ? | |
936 | STA32X_CONFF_IDE : 0); | |
937 | ||
e012ba24 | 938 | /* select output configuration */ |
a1be4cea TN |
939 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, |
940 | STA32X_CONFF_OCFG_MASK, | |
941 | pdata->output_conf | |
942 | << STA32X_CONFF_OCFG_SHIFT); | |
c034abf6 | 943 | |
e012ba24 | 944 | /* channel to output mapping */ |
a1be4cea TN |
945 | regmap_update_bits(sta32x->regmap, STA32X_C1CFG, |
946 | STA32X_CxCFG_OM_MASK, | |
947 | pdata->ch1_output_mapping | |
948 | << STA32X_CxCFG_OM_SHIFT); | |
949 | regmap_update_bits(sta32x->regmap, STA32X_C2CFG, | |
950 | STA32X_CxCFG_OM_MASK, | |
951 | pdata->ch2_output_mapping | |
952 | << STA32X_CxCFG_OM_SHIFT); | |
953 | regmap_update_bits(sta32x->regmap, STA32X_C3CFG, | |
954 | STA32X_CxCFG_OM_MASK, | |
955 | pdata->ch3_output_mapping | |
956 | << STA32X_CxCFG_OM_SHIFT); | |
c034abf6 | 957 | |
54dc6cab JS |
958 | /* initialize coefficient shadow RAM with reset values */ |
959 | for (i = 4; i <= 49; i += 5) | |
960 | sta32x->coef_shadow[i] = 0x400000; | |
961 | for (i = 50; i <= 54; i++) | |
962 | sta32x->coef_shadow[i] = 0x7fffff; | |
963 | sta32x->coef_shadow[55] = 0x5a9df7; | |
964 | sta32x->coef_shadow[56] = 0x7fffff; | |
965 | sta32x->coef_shadow[59] = 0x7fffff; | |
966 | sta32x->coef_shadow[60] = 0x400000; | |
967 | sta32x->coef_shadow[61] = 0x400000; | |
968 | ||
3fb5eac5 JS |
969 | if (sta32x->pdata->needs_esd_watchdog) |
970 | INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog); | |
971 | ||
bd1204cb | 972 | snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY); |
c034abf6 JS |
973 | /* Bias level configuration will have done an extra enable */ |
974 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); | |
975 | ||
976 | return 0; | |
c034abf6 JS |
977 | } |
978 | ||
979 | static int sta32x_remove(struct snd_soc_codec *codec) | |
980 | { | |
981 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
982 | ||
3fb5eac5 | 983 | sta32x_watchdog_stop(sta32x); |
c034abf6 | 984 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); |
c034abf6 JS |
985 | |
986 | return 0; | |
987 | } | |
988 | ||
989 | static const struct snd_soc_codec_driver sta32x_codec = { | |
990 | .probe = sta32x_probe, | |
991 | .remove = sta32x_remove, | |
c034abf6 | 992 | .set_bias_level = sta32x_set_bias_level, |
815b776c | 993 | .suspend_bias_off = true, |
c034abf6 JS |
994 | .controls = sta32x_snd_controls, |
995 | .num_controls = ARRAY_SIZE(sta32x_snd_controls), | |
996 | .dapm_widgets = sta32x_dapm_widgets, | |
997 | .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets), | |
998 | .dapm_routes = sta32x_dapm_routes, | |
999 | .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes), | |
1000 | }; | |
1001 | ||
29fdf4fb MB |
1002 | static const struct regmap_config sta32x_regmap = { |
1003 | .reg_bits = 8, | |
1004 | .val_bits = 8, | |
1005 | .max_register = STA32X_FDRC2, | |
1006 | .reg_defaults = sta32x_regs, | |
1007 | .num_reg_defaults = ARRAY_SIZE(sta32x_regs), | |
1008 | .cache_type = REGCACHE_RBTREE, | |
a1be4cea TN |
1009 | .wr_table = &sta32x_write_regs, |
1010 | .rd_table = &sta32x_read_regs, | |
1011 | .volatile_table = &sta32x_volatile_regs, | |
1012 | }; | |
f04b1e76 TN |
1013 | |
1014 | #ifdef CONFIG_OF | |
1015 | static const struct of_device_id st32x_dt_ids[] = { | |
1016 | { .compatible = "st,sta32x", }, | |
1017 | { } | |
29fdf4fb | 1018 | }; |
f04b1e76 TN |
1019 | MODULE_DEVICE_TABLE(of, st32x_dt_ids); |
1020 | ||
1021 | static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x) | |
1022 | { | |
1023 | struct device_node *np = dev->of_node; | |
1024 | struct sta32x_platform_data *pdata; | |
1025 | u16 tmp; | |
1026 | ||
1027 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
1028 | if (!pdata) | |
1029 | return -ENOMEM; | |
1030 | ||
1031 | of_property_read_u8(np, "st,output-conf", | |
1032 | &pdata->output_conf); | |
1033 | of_property_read_u8(np, "st,ch1-output-mapping", | |
1034 | &pdata->ch1_output_mapping); | |
1035 | of_property_read_u8(np, "st,ch2-output-mapping", | |
1036 | &pdata->ch2_output_mapping); | |
1037 | of_property_read_u8(np, "st,ch3-output-mapping", | |
1038 | &pdata->ch3_output_mapping); | |
1039 | ||
1040 | if (of_get_property(np, "st,thermal-warning-recovery", NULL)) | |
1041 | pdata->thermal_warning_recovery = 1; | |
1042 | if (of_get_property(np, "st,thermal-warning-adjustment", NULL)) | |
1043 | pdata->thermal_warning_adjustment = 1; | |
1044 | if (of_get_property(np, "st,needs_esd_watchdog", NULL)) | |
1045 | pdata->needs_esd_watchdog = 1; | |
1046 | ||
1047 | tmp = 140; | |
1048 | of_property_read_u16(np, "st,drop-compensation-ns", &tmp); | |
1049 | pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20; | |
1050 | ||
1051 | /* CONFE */ | |
1052 | if (of_get_property(np, "st,max-power-use-mpcc", NULL)) | |
1053 | pdata->max_power_use_mpcc = 1; | |
1054 | ||
1055 | if (of_get_property(np, "st,max-power-correction", NULL)) | |
1056 | pdata->max_power_correction = 1; | |
1057 | ||
1058 | if (of_get_property(np, "st,am-reduction-mode", NULL)) | |
1059 | pdata->am_reduction_mode = 1; | |
1060 | ||
1061 | if (of_get_property(np, "st,odd-pwm-speed-mode", NULL)) | |
1062 | pdata->odd_pwm_speed_mode = 1; | |
1063 | ||
1064 | /* CONFF */ | |
1065 | if (of_get_property(np, "st,invalid-input-detect-mute", NULL)) | |
1066 | pdata->invalid_input_detect_mute = 1; | |
1067 | ||
1068 | sta32x->pdata = pdata; | |
1069 | ||
1070 | return 0; | |
1071 | } | |
1072 | #endif | |
29fdf4fb | 1073 | |
7a79e94e BP |
1074 | static int sta32x_i2c_probe(struct i2c_client *i2c, |
1075 | const struct i2c_device_id *id) | |
c034abf6 | 1076 | { |
a1be4cea | 1077 | struct device *dev = &i2c->dev; |
c034abf6 | 1078 | struct sta32x_priv *sta32x; |
aff041af | 1079 | int ret, i; |
c034abf6 | 1080 | |
d999c021 AL |
1081 | sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv), |
1082 | GFP_KERNEL); | |
c034abf6 JS |
1083 | if (!sta32x) |
1084 | return -ENOMEM; | |
1085 | ||
a1be4cea TN |
1086 | mutex_init(&sta32x->coeff_lock); |
1087 | sta32x->pdata = dev_get_platdata(dev); | |
b66a2980 | 1088 | |
f04b1e76 TN |
1089 | #ifdef CONFIG_OF |
1090 | if (dev->of_node) { | |
1091 | ret = sta32x_probe_dt(dev, sta32x); | |
1092 | if (ret < 0) | |
1093 | return ret; | |
1094 | } | |
1095 | #endif | |
1096 | ||
b66a2980 | 1097 | /* GPIOs */ |
1137e580 UKK |
1098 | sta32x->gpiod_nreset = devm_gpiod_get_optional(dev, "reset", |
1099 | GPIOD_OUT_LOW); | |
1100 | if (IS_ERR(sta32x->gpiod_nreset)) | |
1101 | return PTR_ERR(sta32x->gpiod_nreset); | |
b66a2980 | 1102 | |
aff041af MB |
1103 | /* regulators */ |
1104 | for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++) | |
1105 | sta32x->supplies[i].supply = sta32x_supply_names[i]; | |
1106 | ||
1107 | ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies), | |
1108 | sta32x->supplies); | |
1109 | if (ret != 0) { | |
1110 | dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); | |
1111 | return ret; | |
1112 | } | |
1113 | ||
29fdf4fb MB |
1114 | sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap); |
1115 | if (IS_ERR(sta32x->regmap)) { | |
1116 | ret = PTR_ERR(sta32x->regmap); | |
a1be4cea | 1117 | dev_err(dev, "Failed to init regmap: %d\n", ret); |
29fdf4fb MB |
1118 | return ret; |
1119 | } | |
1120 | ||
c034abf6 JS |
1121 | i2c_set_clientdata(i2c, sta32x); |
1122 | ||
a1be4cea TN |
1123 | ret = snd_soc_register_codec(dev, &sta32x_codec, &sta32x_dai, 1); |
1124 | if (ret < 0) | |
1125 | dev_err(dev, "Failed to register codec (%d)\n", ret); | |
c034abf6 | 1126 | |
d999c021 | 1127 | return ret; |
c034abf6 JS |
1128 | } |
1129 | ||
7a79e94e | 1130 | static int sta32x_i2c_remove(struct i2c_client *client) |
c034abf6 | 1131 | { |
e3d73c1b | 1132 | snd_soc_unregister_codec(&client->dev); |
c034abf6 JS |
1133 | return 0; |
1134 | } | |
1135 | ||
1136 | static const struct i2c_device_id sta32x_i2c_id[] = { | |
1137 | { "sta326", 0 }, | |
1138 | { "sta328", 0 }, | |
1139 | { "sta329", 0 }, | |
1140 | { } | |
1141 | }; | |
1142 | MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id); | |
1143 | ||
1144 | static struct i2c_driver sta32x_i2c_driver = { | |
1145 | .driver = { | |
1146 | .name = "sta32x", | |
1147 | .owner = THIS_MODULE, | |
f04b1e76 | 1148 | .of_match_table = of_match_ptr(st32x_dt_ids), |
c034abf6 JS |
1149 | }, |
1150 | .probe = sta32x_i2c_probe, | |
7a79e94e | 1151 | .remove = sta32x_i2c_remove, |
c034abf6 JS |
1152 | .id_table = sta32x_i2c_id, |
1153 | }; | |
1154 | ||
0ead1136 | 1155 | module_i2c_driver(sta32x_i2c_driver); |
c034abf6 JS |
1156 | |
1157 | MODULE_DESCRIPTION("ASoC STA32X driver"); | |
1158 | MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>"); | |
1159 | MODULE_LICENSE("GPL"); |