Commit | Line | Data |
---|---|---|
c034abf6 JS |
1 | /* |
2 | * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system | |
3 | * | |
4 | * Copyright: 2011 Raumfeld GmbH | |
5 | * Author: Johannes Stezenbach <js@sig21.net> | |
6 | * | |
7 | * based on code from: | |
8 | * Wolfson Microelectronics PLC. | |
9 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | |
10 | * Freescale Semiconductor, Inc. | |
11 | * Timur Tabi <timur@freescale.com> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | ||
19 | #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/moduleparam.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/pm.h> | |
26 | #include <linux/i2c.h> | |
c034abf6 JS |
27 | #include <linux/regulator/consumer.h> |
28 | #include <linux/slab.h> | |
3fb5eac5 | 29 | #include <linux/workqueue.h> |
c034abf6 JS |
30 | #include <sound/core.h> |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/soc-dapm.h> | |
35 | #include <sound/initval.h> | |
36 | #include <sound/tlv.h> | |
37 | ||
e012ba24 | 38 | #include <sound/sta32x.h> |
c034abf6 JS |
39 | #include "sta32x.h" |
40 | ||
41 | #define STA32X_RATES (SNDRV_PCM_RATE_32000 | \ | |
42 | SNDRV_PCM_RATE_44100 | \ | |
43 | SNDRV_PCM_RATE_48000 | \ | |
44 | SNDRV_PCM_RATE_88200 | \ | |
45 | SNDRV_PCM_RATE_96000 | \ | |
46 | SNDRV_PCM_RATE_176400 | \ | |
47 | SNDRV_PCM_RATE_192000) | |
48 | ||
49 | #define STA32X_FORMATS \ | |
50 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \ | |
51 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \ | |
52 | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
53 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \ | |
54 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \ | |
55 | SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE) | |
56 | ||
57 | /* Power-up register defaults */ | |
58 | static const u8 sta32x_regs[STA32X_REGISTER_COUNT] = { | |
59 | 0x63, 0x80, 0xc2, 0x40, 0xc2, 0x5c, 0x10, 0xff, 0x60, 0x60, | |
60 | 0x60, 0x80, 0x00, 0x00, 0x00, 0x40, 0x80, 0x77, 0x6a, 0x69, | |
61 | 0x6a, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
62 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2d, | |
63 | 0xc0, 0xf3, 0x33, 0x00, 0x0c, | |
64 | }; | |
65 | ||
66 | /* regulator power supply names */ | |
67 | static const char *sta32x_supply_names[] = { | |
68 | "Vdda", /* analog supply, 3.3VV */ | |
69 | "Vdd3", /* digital supply, 3.3V */ | |
70 | "Vcc" /* power amp spply, 10V - 36V */ | |
71 | }; | |
72 | ||
73 | /* codec private data */ | |
74 | struct sta32x_priv { | |
75 | struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)]; | |
76 | struct snd_soc_codec *codec; | |
e012ba24 | 77 | struct sta32x_platform_data *pdata; |
c034abf6 JS |
78 | |
79 | unsigned int mclk; | |
80 | unsigned int format; | |
54dc6cab JS |
81 | |
82 | u32 coef_shadow[STA32X_COEF_COUNT]; | |
3fb5eac5 JS |
83 | struct delayed_work watchdog_work; |
84 | int shutdown; | |
c034abf6 JS |
85 | }; |
86 | ||
87 | static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1); | |
88 | static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1); | |
89 | static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0); | |
90 | ||
91 | static const char *sta32x_drc_ac[] = { | |
92 | "Anti-Clipping", "Dynamic Range Compression" }; | |
93 | static const char *sta32x_auto_eq_mode[] = { | |
94 | "User", "Preset", "Loudness" }; | |
95 | static const char *sta32x_auto_gc_mode[] = { | |
96 | "User", "AC no clipping", "AC limited clipping (10%)", | |
97 | "DRC nighttime listening mode" }; | |
98 | static const char *sta32x_auto_xo_mode[] = { | |
99 | "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz", | |
100 | "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" }; | |
101 | static const char *sta32x_preset_eq_mode[] = { | |
102 | "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft", | |
103 | "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1", | |
104 | "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2", | |
105 | "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7", | |
106 | "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12", | |
107 | "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" }; | |
108 | static const char *sta32x_limiter_select[] = { | |
109 | "Limiter Disabled", "Limiter #1", "Limiter #2" }; | |
110 | static const char *sta32x_limiter_attack_rate[] = { | |
111 | "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024", | |
112 | "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752", | |
113 | "0.0645", "0.0564", "0.0501", "0.0451" }; | |
114 | static const char *sta32x_limiter_release_rate[] = { | |
115 | "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299", | |
116 | "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137", | |
117 | "0.0134", "0.0117", "0.0110", "0.0104" }; | |
118 | ||
119 | static const unsigned int sta32x_limiter_ac_attack_tlv[] = { | |
120 | TLV_DB_RANGE_HEAD(2), | |
121 | 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0), | |
122 | 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0), | |
123 | }; | |
124 | ||
125 | static const unsigned int sta32x_limiter_ac_release_tlv[] = { | |
126 | TLV_DB_RANGE_HEAD(5), | |
127 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), | |
128 | 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0), | |
129 | 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0), | |
130 | 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0), | |
131 | 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0), | |
132 | }; | |
133 | ||
134 | static const unsigned int sta32x_limiter_drc_attack_tlv[] = { | |
135 | TLV_DB_RANGE_HEAD(3), | |
136 | 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0), | |
137 | 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0), | |
138 | 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0), | |
139 | }; | |
140 | ||
141 | static const unsigned int sta32x_limiter_drc_release_tlv[] = { | |
142 | TLV_DB_RANGE_HEAD(5), | |
143 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), | |
144 | 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0), | |
145 | 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0), | |
146 | 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0), | |
147 | 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0), | |
148 | }; | |
149 | ||
150 | static const struct soc_enum sta32x_drc_ac_enum = | |
151 | SOC_ENUM_SINGLE(STA32X_CONFD, STA32X_CONFD_DRC_SHIFT, | |
152 | 2, sta32x_drc_ac); | |
153 | static const struct soc_enum sta32x_auto_eq_enum = | |
154 | SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT, | |
155 | 3, sta32x_auto_eq_mode); | |
156 | static const struct soc_enum sta32x_auto_gc_enum = | |
157 | SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT, | |
158 | 4, sta32x_auto_gc_mode); | |
159 | static const struct soc_enum sta32x_auto_xo_enum = | |
160 | SOC_ENUM_SINGLE(STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT, | |
161 | 16, sta32x_auto_xo_mode); | |
162 | static const struct soc_enum sta32x_preset_eq_enum = | |
163 | SOC_ENUM_SINGLE(STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT, | |
164 | 32, sta32x_preset_eq_mode); | |
165 | static const struct soc_enum sta32x_limiter_ch1_enum = | |
166 | SOC_ENUM_SINGLE(STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT, | |
167 | 3, sta32x_limiter_select); | |
168 | static const struct soc_enum sta32x_limiter_ch2_enum = | |
169 | SOC_ENUM_SINGLE(STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT, | |
170 | 3, sta32x_limiter_select); | |
171 | static const struct soc_enum sta32x_limiter_ch3_enum = | |
172 | SOC_ENUM_SINGLE(STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT, | |
173 | 3, sta32x_limiter_select); | |
174 | static const struct soc_enum sta32x_limiter1_attack_rate_enum = | |
175 | SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxA_SHIFT, | |
176 | 16, sta32x_limiter_attack_rate); | |
177 | static const struct soc_enum sta32x_limiter2_attack_rate_enum = | |
178 | SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxA_SHIFT, | |
179 | 16, sta32x_limiter_attack_rate); | |
180 | static const struct soc_enum sta32x_limiter1_release_rate_enum = | |
181 | SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxR_SHIFT, | |
182 | 16, sta32x_limiter_release_rate); | |
183 | static const struct soc_enum sta32x_limiter2_release_rate_enum = | |
184 | SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxR_SHIFT, | |
185 | 16, sta32x_limiter_release_rate); | |
79688439 JS |
186 | |
187 | /* byte array controls for setting biquad, mixer, scaling coefficients; | |
188 | * for biquads all five coefficients need to be set in one go, | |
189 | * mixer and pre/postscale coefs can be set individually; | |
190 | * each coef is 24bit, the bytes are ordered in the same way | |
191 | * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0) | |
192 | */ | |
193 | ||
194 | static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol, | |
195 | struct snd_ctl_elem_info *uinfo) | |
196 | { | |
197 | int numcoef = kcontrol->private_value >> 16; | |
198 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; | |
199 | uinfo->count = 3 * numcoef; | |
200 | return 0; | |
201 | } | |
202 | ||
203 | static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol, | |
204 | struct snd_ctl_elem_value *ucontrol) | |
205 | { | |
206 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
207 | int numcoef = kcontrol->private_value >> 16; | |
208 | int index = kcontrol->private_value & 0xffff; | |
209 | unsigned int cfud; | |
210 | int i; | |
211 | ||
212 | /* preserve reserved bits in STA32X_CFUD */ | |
213 | cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; | |
214 | /* chip documentation does not say if the bits are self clearing, | |
215 | * so do it explicitly */ | |
216 | snd_soc_write(codec, STA32X_CFUD, cfud); | |
217 | ||
218 | snd_soc_write(codec, STA32X_CFADDR2, index); | |
219 | if (numcoef == 1) | |
220 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x04); | |
221 | else if (numcoef == 5) | |
222 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x08); | |
223 | else | |
224 | return -EINVAL; | |
225 | for (i = 0; i < 3 * numcoef; i++) | |
226 | ucontrol->value.bytes.data[i] = | |
227 | snd_soc_read(codec, STA32X_B1CF1 + i); | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
232 | static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol, | |
233 | struct snd_ctl_elem_value *ucontrol) | |
234 | { | |
235 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
54dc6cab | 236 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
79688439 JS |
237 | int numcoef = kcontrol->private_value >> 16; |
238 | int index = kcontrol->private_value & 0xffff; | |
239 | unsigned int cfud; | |
240 | int i; | |
241 | ||
242 | /* preserve reserved bits in STA32X_CFUD */ | |
243 | cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; | |
244 | /* chip documentation does not say if the bits are self clearing, | |
245 | * so do it explicitly */ | |
246 | snd_soc_write(codec, STA32X_CFUD, cfud); | |
247 | ||
248 | snd_soc_write(codec, STA32X_CFADDR2, index); | |
54dc6cab JS |
249 | for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++) |
250 | sta32x->coef_shadow[index + i] = | |
251 | (ucontrol->value.bytes.data[3 * i] << 16) | |
252 | | (ucontrol->value.bytes.data[3 * i + 1] << 8) | |
253 | | (ucontrol->value.bytes.data[3 * i + 2]); | |
79688439 JS |
254 | for (i = 0; i < 3 * numcoef; i++) |
255 | snd_soc_write(codec, STA32X_B1CF1 + i, | |
256 | ucontrol->value.bytes.data[i]); | |
257 | if (numcoef == 1) | |
258 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x01); | |
259 | else if (numcoef == 5) | |
260 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x02); | |
261 | else | |
262 | return -EINVAL; | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
878042d1 | 267 | static int sta32x_sync_coef_shadow(struct snd_soc_codec *codec) |
54dc6cab JS |
268 | { |
269 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
270 | unsigned int cfud; | |
271 | int i; | |
272 | ||
273 | /* preserve reserved bits in STA32X_CFUD */ | |
274 | cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; | |
275 | ||
276 | for (i = 0; i < STA32X_COEF_COUNT; i++) { | |
277 | snd_soc_write(codec, STA32X_CFADDR2, i); | |
278 | snd_soc_write(codec, STA32X_B1CF1, | |
279 | (sta32x->coef_shadow[i] >> 16) & 0xff); | |
280 | snd_soc_write(codec, STA32X_B1CF2, | |
281 | (sta32x->coef_shadow[i] >> 8) & 0xff); | |
282 | snd_soc_write(codec, STA32X_B1CF3, | |
283 | (sta32x->coef_shadow[i]) & 0xff); | |
284 | /* chip documentation does not say if the bits are | |
285 | * self-clearing, so do it explicitly */ | |
286 | snd_soc_write(codec, STA32X_CFUD, cfud); | |
287 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x01); | |
288 | } | |
289 | return 0; | |
290 | } | |
291 | ||
878042d1 | 292 | static int sta32x_cache_sync(struct snd_soc_codec *codec) |
54dc6cab JS |
293 | { |
294 | unsigned int mute; | |
295 | int rc; | |
296 | ||
297 | if (!codec->cache_sync) | |
298 | return 0; | |
299 | ||
300 | /* mute during register sync */ | |
301 | mute = snd_soc_read(codec, STA32X_MMUTE); | |
302 | snd_soc_write(codec, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE); | |
303 | sta32x_sync_coef_shadow(codec); | |
304 | rc = snd_soc_cache_sync(codec); | |
305 | snd_soc_write(codec, STA32X_MMUTE, mute); | |
306 | return rc; | |
307 | } | |
308 | ||
3fb5eac5 JS |
309 | /* work around ESD issue where sta32x resets and loses all configuration */ |
310 | static void sta32x_watchdog(struct work_struct *work) | |
311 | { | |
312 | struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv, | |
313 | watchdog_work.work); | |
314 | struct snd_soc_codec *codec = sta32x->codec; | |
315 | unsigned int confa, confa_cached; | |
316 | ||
317 | /* check if sta32x has reset itself */ | |
318 | confa_cached = snd_soc_read(codec, STA32X_CONFA); | |
319 | codec->cache_bypass = 1; | |
320 | confa = snd_soc_read(codec, STA32X_CONFA); | |
321 | codec->cache_bypass = 0; | |
322 | if (confa != confa_cached) { | |
323 | codec->cache_sync = 1; | |
324 | sta32x_cache_sync(codec); | |
325 | } | |
326 | ||
327 | if (!sta32x->shutdown) | |
328 | schedule_delayed_work(&sta32x->watchdog_work, | |
329 | round_jiffies_relative(HZ)); | |
330 | } | |
331 | ||
332 | static void sta32x_watchdog_start(struct sta32x_priv *sta32x) | |
333 | { | |
334 | if (sta32x->pdata->needs_esd_watchdog) { | |
335 | sta32x->shutdown = 0; | |
336 | schedule_delayed_work(&sta32x->watchdog_work, | |
337 | round_jiffies_relative(HZ)); | |
338 | } | |
339 | } | |
340 | ||
341 | static void sta32x_watchdog_stop(struct sta32x_priv *sta32x) | |
342 | { | |
343 | if (sta32x->pdata->needs_esd_watchdog) { | |
344 | sta32x->shutdown = 1; | |
345 | cancel_delayed_work_sync(&sta32x->watchdog_work); | |
346 | } | |
347 | } | |
348 | ||
79688439 JS |
349 | #define SINGLE_COEF(xname, index) \ |
350 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
351 | .info = sta32x_coefficient_info, \ | |
352 | .get = sta32x_coefficient_get,\ | |
353 | .put = sta32x_coefficient_put, \ | |
354 | .private_value = index | (1 << 16) } | |
355 | ||
356 | #define BIQUAD_COEFS(xname, index) \ | |
357 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
358 | .info = sta32x_coefficient_info, \ | |
359 | .get = sta32x_coefficient_get,\ | |
360 | .put = sta32x_coefficient_put, \ | |
361 | .private_value = index | (5 << 16) } | |
362 | ||
c034abf6 JS |
363 | static const struct snd_kcontrol_new sta32x_snd_controls[] = { |
364 | SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv), | |
365 | SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1), | |
366 | SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1), | |
367 | SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1), | |
368 | SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1), | |
369 | SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv), | |
370 | SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv), | |
371 | SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv), | |
372 | SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0), | |
373 | SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum), | |
374 | SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0), | |
375 | SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0), | |
376 | SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0), | |
377 | SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0), | |
378 | SOC_ENUM("Automode EQ", sta32x_auto_eq_enum), | |
379 | SOC_ENUM("Automode GC", sta32x_auto_gc_enum), | |
380 | SOC_ENUM("Automode XO", sta32x_auto_xo_enum), | |
381 | SOC_ENUM("Preset EQ", sta32x_preset_eq_enum), | |
382 | SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), | |
383 | SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), | |
384 | SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), | |
385 | SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), | |
386 | SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), | |
387 | SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), | |
388 | SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), | |
389 | SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum), | |
390 | SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum), | |
391 | SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum), | |
392 | SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv), | |
393 | SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv), | |
394 | SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum), | |
395 | SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum), | |
396 | SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum), | |
397 | SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum), | |
398 | ||
399 | /* depending on mode, the attack/release thresholds have | |
400 | * two different enum definitions; provide both | |
401 | */ | |
402 | SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, | |
403 | 16, 0, sta32x_limiter_ac_attack_tlv), | |
404 | SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, | |
405 | 16, 0, sta32x_limiter_ac_attack_tlv), | |
406 | SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, | |
407 | 16, 0, sta32x_limiter_ac_release_tlv), | |
408 | SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, | |
409 | 16, 0, sta32x_limiter_ac_release_tlv), | |
410 | SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, | |
411 | 16, 0, sta32x_limiter_drc_attack_tlv), | |
412 | SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, | |
413 | 16, 0, sta32x_limiter_drc_attack_tlv), | |
414 | SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, | |
415 | 16, 0, sta32x_limiter_drc_release_tlv), | |
416 | SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, | |
417 | 16, 0, sta32x_limiter_drc_release_tlv), | |
79688439 JS |
418 | |
419 | BIQUAD_COEFS("Ch1 - Biquad 1", 0), | |
420 | BIQUAD_COEFS("Ch1 - Biquad 2", 5), | |
421 | BIQUAD_COEFS("Ch1 - Biquad 3", 10), | |
422 | BIQUAD_COEFS("Ch1 - Biquad 4", 15), | |
423 | BIQUAD_COEFS("Ch2 - Biquad 1", 20), | |
424 | BIQUAD_COEFS("Ch2 - Biquad 2", 25), | |
425 | BIQUAD_COEFS("Ch2 - Biquad 3", 30), | |
426 | BIQUAD_COEFS("Ch2 - Biquad 4", 35), | |
427 | BIQUAD_COEFS("High-pass", 40), | |
428 | BIQUAD_COEFS("Low-pass", 45), | |
429 | SINGLE_COEF("Ch1 - Prescale", 50), | |
430 | SINGLE_COEF("Ch2 - Prescale", 51), | |
431 | SINGLE_COEF("Ch1 - Postscale", 52), | |
432 | SINGLE_COEF("Ch2 - Postscale", 53), | |
433 | SINGLE_COEF("Ch3 - Postscale", 54), | |
434 | SINGLE_COEF("Thermal warning - Postscale", 55), | |
435 | SINGLE_COEF("Ch1 - Mix 1", 56), | |
436 | SINGLE_COEF("Ch1 - Mix 2", 57), | |
437 | SINGLE_COEF("Ch2 - Mix 1", 58), | |
438 | SINGLE_COEF("Ch2 - Mix 2", 59), | |
439 | SINGLE_COEF("Ch3 - Mix 1", 60), | |
440 | SINGLE_COEF("Ch3 - Mix 2", 61), | |
c034abf6 JS |
441 | }; |
442 | ||
443 | static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = { | |
444 | SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0), | |
445 | SND_SOC_DAPM_OUTPUT("LEFT"), | |
446 | SND_SOC_DAPM_OUTPUT("RIGHT"), | |
447 | SND_SOC_DAPM_OUTPUT("SUB"), | |
448 | }; | |
449 | ||
450 | static const struct snd_soc_dapm_route sta32x_dapm_routes[] = { | |
451 | { "LEFT", NULL, "DAC" }, | |
452 | { "RIGHT", NULL, "DAC" }, | |
453 | { "SUB", NULL, "DAC" }, | |
454 | }; | |
455 | ||
456 | /* MCLK interpolation ratio per fs */ | |
457 | static struct { | |
458 | int fs; | |
459 | int ir; | |
460 | } interpolation_ratios[] = { | |
461 | { 32000, 0 }, | |
462 | { 44100, 0 }, | |
463 | { 48000, 0 }, | |
464 | { 88200, 1 }, | |
465 | { 96000, 1 }, | |
466 | { 176400, 2 }, | |
467 | { 192000, 2 }, | |
468 | }; | |
469 | ||
470 | /* MCLK to fs clock ratios */ | |
471 | static struct { | |
472 | int ratio; | |
473 | int mcs; | |
474 | } mclk_ratios[3][7] = { | |
475 | { { 768, 0 }, { 512, 1 }, { 384, 2 }, { 256, 3 }, | |
476 | { 128, 4 }, { 576, 5 }, { 0, 0 } }, | |
477 | { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } }, | |
478 | { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } }, | |
479 | }; | |
480 | ||
481 | ||
482 | /** | |
483 | * sta32x_set_dai_sysclk - configure MCLK | |
484 | * @codec_dai: the codec DAI | |
485 | * @clk_id: the clock ID (ignored) | |
486 | * @freq: the MCLK input frequency | |
487 | * @dir: the clock direction (ignored) | |
488 | * | |
489 | * The value of MCLK is used to determine which sample rates are supported | |
490 | * by the STA32X, based on the mclk_ratios table. | |
491 | * | |
492 | * This function must be called by the machine driver's 'startup' function, | |
493 | * otherwise the list of supported sample rates will not be available in | |
494 | * time for ALSA. | |
495 | * | |
496 | * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause | |
497 | * theoretically possible sample rates to be enabled. Call it again with a | |
498 | * proper value set one the external clock is set (most probably you would do | |
499 | * that from a machine's driver 'hw_param' hook. | |
500 | */ | |
501 | static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
502 | int clk_id, unsigned int freq, int dir) | |
503 | { | |
504 | struct snd_soc_codec *codec = codec_dai->codec; | |
505 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
506 | int i, j, ir, fs; | |
507 | unsigned int rates = 0; | |
508 | unsigned int rate_min = -1; | |
509 | unsigned int rate_max = 0; | |
510 | ||
511 | pr_debug("mclk=%u\n", freq); | |
512 | sta32x->mclk = freq; | |
513 | ||
514 | if (sta32x->mclk) { | |
515 | for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) { | |
516 | ir = interpolation_ratios[i].ir; | |
517 | fs = interpolation_ratios[i].fs; | |
518 | for (j = 0; mclk_ratios[ir][j].ratio; j++) { | |
519 | if (mclk_ratios[ir][j].ratio * fs == freq) { | |
520 | rates |= snd_pcm_rate_to_rate_bit(fs); | |
521 | if (fs < rate_min) | |
522 | rate_min = fs; | |
523 | if (fs > rate_max) | |
524 | rate_max = fs; | |
7a748e43 | 525 | break; |
c034abf6 JS |
526 | } |
527 | } | |
528 | } | |
529 | /* FIXME: soc should support a rate list */ | |
530 | rates &= ~SNDRV_PCM_RATE_KNOT; | |
531 | ||
532 | if (!rates) { | |
533 | dev_err(codec->dev, "could not find a valid sample rate\n"); | |
534 | return -EINVAL; | |
535 | } | |
536 | } else { | |
537 | /* enable all possible rates */ | |
538 | rates = STA32X_RATES; | |
539 | rate_min = 32000; | |
540 | rate_max = 192000; | |
541 | } | |
542 | ||
543 | codec_dai->driver->playback.rates = rates; | |
544 | codec_dai->driver->playback.rate_min = rate_min; | |
545 | codec_dai->driver->playback.rate_max = rate_max; | |
546 | return 0; | |
547 | } | |
548 | ||
549 | /** | |
550 | * sta32x_set_dai_fmt - configure the codec for the selected audio format | |
551 | * @codec_dai: the codec DAI | |
552 | * @fmt: a SND_SOC_DAIFMT_x value indicating the data format | |
553 | * | |
554 | * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the | |
555 | * codec accordingly. | |
556 | */ | |
557 | static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
558 | unsigned int fmt) | |
559 | { | |
560 | struct snd_soc_codec *codec = codec_dai->codec; | |
561 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
562 | u8 confb = snd_soc_read(codec, STA32X_CONFB); | |
563 | ||
564 | pr_debug("\n"); | |
565 | confb &= ~(STA32X_CONFB_C1IM | STA32X_CONFB_C2IM); | |
566 | ||
567 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
568 | case SND_SOC_DAIFMT_CBS_CFS: | |
569 | break; | |
570 | default: | |
571 | return -EINVAL; | |
572 | } | |
573 | ||
574 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
575 | case SND_SOC_DAIFMT_I2S: | |
576 | case SND_SOC_DAIFMT_RIGHT_J: | |
577 | case SND_SOC_DAIFMT_LEFT_J: | |
578 | sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
579 | break; | |
580 | default: | |
581 | return -EINVAL; | |
582 | } | |
583 | ||
584 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
585 | case SND_SOC_DAIFMT_NB_NF: | |
586 | confb |= STA32X_CONFB_C2IM; | |
587 | break; | |
588 | case SND_SOC_DAIFMT_NB_IF: | |
589 | confb |= STA32X_CONFB_C1IM; | |
590 | break; | |
591 | default: | |
592 | return -EINVAL; | |
593 | } | |
594 | ||
595 | snd_soc_write(codec, STA32X_CONFB, confb); | |
596 | return 0; | |
597 | } | |
598 | ||
599 | /** | |
600 | * sta32x_hw_params - program the STA32X with the given hardware parameters. | |
601 | * @substream: the audio stream | |
602 | * @params: the hardware parameters to set | |
603 | * @dai: the SOC DAI (ignored) | |
604 | * | |
605 | * This function programs the hardware with the values provided. | |
606 | * Specifically, the sample rate and the data format. | |
607 | */ | |
608 | static int sta32x_hw_params(struct snd_pcm_substream *substream, | |
609 | struct snd_pcm_hw_params *params, | |
610 | struct snd_soc_dai *dai) | |
611 | { | |
e6968a17 | 612 | struct snd_soc_codec *codec = dai->codec; |
c034abf6 JS |
613 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
614 | unsigned int rate; | |
615 | int i, mcs = -1, ir = -1; | |
616 | u8 confa, confb; | |
617 | ||
618 | rate = params_rate(params); | |
619 | pr_debug("rate: %u\n", rate); | |
620 | for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) | |
a595238b | 621 | if (interpolation_ratios[i].fs == rate) { |
c034abf6 | 622 | ir = interpolation_ratios[i].ir; |
a595238b AL |
623 | break; |
624 | } | |
c034abf6 JS |
625 | if (ir < 0) |
626 | return -EINVAL; | |
627 | for (i = 0; mclk_ratios[ir][i].ratio; i++) | |
a595238b | 628 | if (mclk_ratios[ir][i].ratio * rate == sta32x->mclk) { |
c034abf6 | 629 | mcs = mclk_ratios[ir][i].mcs; |
a595238b AL |
630 | break; |
631 | } | |
c034abf6 JS |
632 | if (mcs < 0) |
633 | return -EINVAL; | |
634 | ||
635 | confa = snd_soc_read(codec, STA32X_CONFA); | |
636 | confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK); | |
637 | confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT); | |
638 | ||
639 | confb = snd_soc_read(codec, STA32X_CONFB); | |
640 | confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB); | |
641 | switch (params_format(params)) { | |
642 | case SNDRV_PCM_FORMAT_S24_LE: | |
643 | case SNDRV_PCM_FORMAT_S24_BE: | |
644 | case SNDRV_PCM_FORMAT_S24_3LE: | |
645 | case SNDRV_PCM_FORMAT_S24_3BE: | |
646 | pr_debug("24bit\n"); | |
647 | /* fall through */ | |
648 | case SNDRV_PCM_FORMAT_S32_LE: | |
649 | case SNDRV_PCM_FORMAT_S32_BE: | |
650 | pr_debug("24bit or 32bit\n"); | |
651 | switch (sta32x->format) { | |
652 | case SND_SOC_DAIFMT_I2S: | |
653 | confb |= 0x0; | |
654 | break; | |
655 | case SND_SOC_DAIFMT_LEFT_J: | |
656 | confb |= 0x1; | |
657 | break; | |
658 | case SND_SOC_DAIFMT_RIGHT_J: | |
659 | confb |= 0x2; | |
660 | break; | |
661 | } | |
662 | ||
663 | break; | |
664 | case SNDRV_PCM_FORMAT_S20_3LE: | |
665 | case SNDRV_PCM_FORMAT_S20_3BE: | |
666 | pr_debug("20bit\n"); | |
667 | switch (sta32x->format) { | |
668 | case SND_SOC_DAIFMT_I2S: | |
669 | confb |= 0x4; | |
670 | break; | |
671 | case SND_SOC_DAIFMT_LEFT_J: | |
672 | confb |= 0x5; | |
673 | break; | |
674 | case SND_SOC_DAIFMT_RIGHT_J: | |
675 | confb |= 0x6; | |
676 | break; | |
677 | } | |
678 | ||
679 | break; | |
680 | case SNDRV_PCM_FORMAT_S18_3LE: | |
681 | case SNDRV_PCM_FORMAT_S18_3BE: | |
682 | pr_debug("18bit\n"); | |
683 | switch (sta32x->format) { | |
684 | case SND_SOC_DAIFMT_I2S: | |
685 | confb |= 0x8; | |
686 | break; | |
687 | case SND_SOC_DAIFMT_LEFT_J: | |
688 | confb |= 0x9; | |
689 | break; | |
690 | case SND_SOC_DAIFMT_RIGHT_J: | |
691 | confb |= 0xa; | |
692 | break; | |
693 | } | |
694 | ||
695 | break; | |
696 | case SNDRV_PCM_FORMAT_S16_LE: | |
697 | case SNDRV_PCM_FORMAT_S16_BE: | |
698 | pr_debug("16bit\n"); | |
699 | switch (sta32x->format) { | |
700 | case SND_SOC_DAIFMT_I2S: | |
701 | confb |= 0x0; | |
702 | break; | |
703 | case SND_SOC_DAIFMT_LEFT_J: | |
704 | confb |= 0xd; | |
705 | break; | |
706 | case SND_SOC_DAIFMT_RIGHT_J: | |
707 | confb |= 0xe; | |
708 | break; | |
709 | } | |
710 | ||
711 | break; | |
712 | default: | |
713 | return -EINVAL; | |
714 | } | |
715 | ||
716 | snd_soc_write(codec, STA32X_CONFA, confa); | |
717 | snd_soc_write(codec, STA32X_CONFB, confb); | |
718 | return 0; | |
719 | } | |
720 | ||
721 | /** | |
722 | * sta32x_set_bias_level - DAPM callback | |
723 | * @codec: the codec device | |
724 | * @level: DAPM power level | |
725 | * | |
726 | * This is called by ALSA to put the codec into low power mode | |
727 | * or to wake it up. If the codec is powered off completely | |
728 | * all registers must be restored after power on. | |
729 | */ | |
730 | static int sta32x_set_bias_level(struct snd_soc_codec *codec, | |
731 | enum snd_soc_bias_level level) | |
732 | { | |
733 | int ret; | |
734 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
735 | ||
736 | pr_debug("level = %d\n", level); | |
737 | switch (level) { | |
738 | case SND_SOC_BIAS_ON: | |
739 | break; | |
740 | ||
741 | case SND_SOC_BIAS_PREPARE: | |
742 | /* Full power on */ | |
743 | snd_soc_update_bits(codec, STA32X_CONFF, | |
744 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | |
745 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); | |
746 | break; | |
747 | ||
748 | case SND_SOC_BIAS_STANDBY: | |
749 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
750 | ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), | |
751 | sta32x->supplies); | |
752 | if (ret != 0) { | |
753 | dev_err(codec->dev, | |
754 | "Failed to enable supplies: %d\n", ret); | |
755 | return ret; | |
756 | } | |
757 | ||
54dc6cab | 758 | sta32x_cache_sync(codec); |
3fb5eac5 | 759 | sta32x_watchdog_start(sta32x); |
c034abf6 JS |
760 | } |
761 | ||
762 | /* Power up to mute */ | |
763 | /* FIXME */ | |
764 | snd_soc_update_bits(codec, STA32X_CONFF, | |
765 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | |
766 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); | |
767 | ||
768 | break; | |
769 | ||
770 | case SND_SOC_BIAS_OFF: | |
771 | /* The chip runs through the power down sequence for us. */ | |
772 | snd_soc_update_bits(codec, STA32X_CONFF, | |
773 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | |
774 | STA32X_CONFF_PWDN); | |
775 | msleep(300); | |
3fb5eac5 | 776 | sta32x_watchdog_stop(sta32x); |
c034abf6 JS |
777 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), |
778 | sta32x->supplies); | |
779 | break; | |
780 | } | |
781 | codec->dapm.bias_level = level; | |
782 | return 0; | |
783 | } | |
784 | ||
85e7652d | 785 | static const struct snd_soc_dai_ops sta32x_dai_ops = { |
c034abf6 JS |
786 | .hw_params = sta32x_hw_params, |
787 | .set_sysclk = sta32x_set_dai_sysclk, | |
788 | .set_fmt = sta32x_set_dai_fmt, | |
789 | }; | |
790 | ||
791 | static struct snd_soc_dai_driver sta32x_dai = { | |
792 | .name = "STA32X", | |
793 | .playback = { | |
794 | .stream_name = "Playback", | |
795 | .channels_min = 2, | |
796 | .channels_max = 2, | |
797 | .rates = STA32X_RATES, | |
798 | .formats = STA32X_FORMATS, | |
799 | }, | |
800 | .ops = &sta32x_dai_ops, | |
801 | }; | |
802 | ||
803 | #ifdef CONFIG_PM | |
84b315ee | 804 | static int sta32x_suspend(struct snd_soc_codec *codec) |
c034abf6 JS |
805 | { |
806 | sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
807 | return 0; | |
808 | } | |
809 | ||
810 | static int sta32x_resume(struct snd_soc_codec *codec) | |
811 | { | |
812 | sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
813 | return 0; | |
814 | } | |
815 | #else | |
816 | #define sta32x_suspend NULL | |
817 | #define sta32x_resume NULL | |
818 | #endif | |
819 | ||
820 | static int sta32x_probe(struct snd_soc_codec *codec) | |
821 | { | |
822 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
e012ba24 | 823 | int i, ret = 0, thermal = 0; |
c034abf6 JS |
824 | |
825 | sta32x->codec = codec; | |
e012ba24 | 826 | sta32x->pdata = dev_get_platdata(codec->dev); |
c034abf6 JS |
827 | |
828 | /* regulators */ | |
829 | for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++) | |
830 | sta32x->supplies[i].supply = sta32x_supply_names[i]; | |
831 | ||
832 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sta32x->supplies), | |
833 | sta32x->supplies); | |
834 | if (ret != 0) { | |
835 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
836 | goto err; | |
837 | } | |
838 | ||
839 | ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), | |
840 | sta32x->supplies); | |
841 | if (ret != 0) { | |
842 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
843 | goto err_get; | |
844 | } | |
845 | ||
846 | /* Tell ASoC what kind of I/O to use to read the registers. ASoC will | |
847 | * then do the I2C transactions itself. | |
848 | */ | |
849 | ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); | |
850 | if (ret < 0) { | |
851 | dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret); | |
852 | return ret; | |
853 | } | |
854 | ||
edf413f6 AL |
855 | /* Chip documentation explicitly requires that the reset values |
856 | * of reserved register bits are left untouched. | |
857 | * Write the register default value to cache for reserved registers, | |
858 | * so the write to the these registers are suppressed by the cache | |
859 | * restore code when it skips writes of default registers. | |
860 | */ | |
861 | snd_soc_cache_write(codec, STA32X_CONFC, 0xc2); | |
862 | snd_soc_cache_write(codec, STA32X_CONFE, 0xc2); | |
863 | snd_soc_cache_write(codec, STA32X_CONFF, 0x5c); | |
864 | snd_soc_cache_write(codec, STA32X_MMUTE, 0x10); | |
865 | snd_soc_cache_write(codec, STA32X_AUTO1, 0x60); | |
866 | snd_soc_cache_write(codec, STA32X_AUTO3, 0x00); | |
867 | snd_soc_cache_write(codec, STA32X_C3CFG, 0x40); | |
889ebae5 | 868 | |
e012ba24 JS |
869 | /* set thermal warning adjustment and recovery */ |
870 | if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_ADJUSTMENT_ENABLE)) | |
871 | thermal |= STA32X_CONFA_TWAB; | |
872 | if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_RECOVERY_ENABLE)) | |
873 | thermal |= STA32X_CONFA_TWRB; | |
c034abf6 | 874 | snd_soc_update_bits(codec, STA32X_CONFA, |
e012ba24 JS |
875 | STA32X_CONFA_TWAB | STA32X_CONFA_TWRB, |
876 | thermal); | |
c034abf6 | 877 | |
e012ba24 | 878 | /* select output configuration */ |
c034abf6 JS |
879 | snd_soc_update_bits(codec, STA32X_CONFF, |
880 | STA32X_CONFF_OCFG_MASK, | |
e012ba24 JS |
881 | sta32x->pdata->output_conf |
882 | << STA32X_CONFF_OCFG_SHIFT); | |
c034abf6 | 883 | |
e012ba24 | 884 | /* channel to output mapping */ |
c034abf6 JS |
885 | snd_soc_update_bits(codec, STA32X_C1CFG, |
886 | STA32X_CxCFG_OM_MASK, | |
e012ba24 JS |
887 | sta32x->pdata->ch1_output_mapping |
888 | << STA32X_CxCFG_OM_SHIFT); | |
c034abf6 JS |
889 | snd_soc_update_bits(codec, STA32X_C2CFG, |
890 | STA32X_CxCFG_OM_MASK, | |
e012ba24 JS |
891 | sta32x->pdata->ch2_output_mapping |
892 | << STA32X_CxCFG_OM_SHIFT); | |
c034abf6 JS |
893 | snd_soc_update_bits(codec, STA32X_C3CFG, |
894 | STA32X_CxCFG_OM_MASK, | |
e012ba24 JS |
895 | sta32x->pdata->ch3_output_mapping |
896 | << STA32X_CxCFG_OM_SHIFT); | |
c034abf6 | 897 | |
54dc6cab JS |
898 | /* initialize coefficient shadow RAM with reset values */ |
899 | for (i = 4; i <= 49; i += 5) | |
900 | sta32x->coef_shadow[i] = 0x400000; | |
901 | for (i = 50; i <= 54; i++) | |
902 | sta32x->coef_shadow[i] = 0x7fffff; | |
903 | sta32x->coef_shadow[55] = 0x5a9df7; | |
904 | sta32x->coef_shadow[56] = 0x7fffff; | |
905 | sta32x->coef_shadow[59] = 0x7fffff; | |
906 | sta32x->coef_shadow[60] = 0x400000; | |
907 | sta32x->coef_shadow[61] = 0x400000; | |
908 | ||
3fb5eac5 JS |
909 | if (sta32x->pdata->needs_esd_watchdog) |
910 | INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog); | |
911 | ||
c034abf6 JS |
912 | sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
913 | /* Bias level configuration will have done an extra enable */ | |
914 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); | |
915 | ||
916 | return 0; | |
917 | ||
918 | err_get: | |
919 | regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); | |
920 | err: | |
921 | return ret; | |
922 | } | |
923 | ||
924 | static int sta32x_remove(struct snd_soc_codec *codec) | |
925 | { | |
926 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | |
927 | ||
3fb5eac5 | 928 | sta32x_watchdog_stop(sta32x); |
e3d73c1b | 929 | sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF); |
c034abf6 JS |
930 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); |
931 | regulator_bulk_free(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
79688439 JS |
936 | static int sta32x_reg_is_volatile(struct snd_soc_codec *codec, |
937 | unsigned int reg) | |
938 | { | |
939 | switch (reg) { | |
940 | case STA32X_CONFA ... STA32X_L2ATRT: | |
941 | case STA32X_MPCC1 ... STA32X_FDRC2: | |
942 | return 0; | |
943 | } | |
944 | return 1; | |
945 | } | |
946 | ||
c034abf6 JS |
947 | static const struct snd_soc_codec_driver sta32x_codec = { |
948 | .probe = sta32x_probe, | |
949 | .remove = sta32x_remove, | |
950 | .suspend = sta32x_suspend, | |
951 | .resume = sta32x_resume, | |
952 | .reg_cache_size = STA32X_REGISTER_COUNT, | |
953 | .reg_word_size = sizeof(u8), | |
f0bbc2b5 | 954 | .reg_cache_default = sta32x_regs, |
79688439 | 955 | .volatile_register = sta32x_reg_is_volatile, |
c034abf6 JS |
956 | .set_bias_level = sta32x_set_bias_level, |
957 | .controls = sta32x_snd_controls, | |
958 | .num_controls = ARRAY_SIZE(sta32x_snd_controls), | |
959 | .dapm_widgets = sta32x_dapm_widgets, | |
960 | .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets), | |
961 | .dapm_routes = sta32x_dapm_routes, | |
962 | .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes), | |
963 | }; | |
964 | ||
965 | static __devinit int sta32x_i2c_probe(struct i2c_client *i2c, | |
966 | const struct i2c_device_id *id) | |
967 | { | |
968 | struct sta32x_priv *sta32x; | |
969 | int ret; | |
970 | ||
d999c021 AL |
971 | sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv), |
972 | GFP_KERNEL); | |
c034abf6 JS |
973 | if (!sta32x) |
974 | return -ENOMEM; | |
975 | ||
976 | i2c_set_clientdata(i2c, sta32x); | |
977 | ||
978 | ret = snd_soc_register_codec(&i2c->dev, &sta32x_codec, &sta32x_dai, 1); | |
d999c021 | 979 | if (ret != 0) |
c034abf6 | 980 | dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret); |
c034abf6 | 981 | |
d999c021 | 982 | return ret; |
c034abf6 JS |
983 | } |
984 | ||
985 | static __devexit int sta32x_i2c_remove(struct i2c_client *client) | |
986 | { | |
e3d73c1b | 987 | snd_soc_unregister_codec(&client->dev); |
c034abf6 JS |
988 | return 0; |
989 | } | |
990 | ||
991 | static const struct i2c_device_id sta32x_i2c_id[] = { | |
992 | { "sta326", 0 }, | |
993 | { "sta328", 0 }, | |
994 | { "sta329", 0 }, | |
995 | { } | |
996 | }; | |
997 | MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id); | |
998 | ||
999 | static struct i2c_driver sta32x_i2c_driver = { | |
1000 | .driver = { | |
1001 | .name = "sta32x", | |
1002 | .owner = THIS_MODULE, | |
1003 | }, | |
1004 | .probe = sta32x_i2c_probe, | |
1005 | .remove = __devexit_p(sta32x_i2c_remove), | |
1006 | .id_table = sta32x_i2c_id, | |
1007 | }; | |
1008 | ||
0ead1136 | 1009 | module_i2c_driver(sta32x_i2c_driver); |
c034abf6 JS |
1010 | |
1011 | MODULE_DESCRIPTION("ASoC STA32X driver"); | |
1012 | MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>"); | |
1013 | MODULE_LICENSE("GPL"); |