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Linux 3.18-rc1
[deliverable/linux.git] / sound / soc / codecs / sta32x.c
CommitLineData
c034abf6
JS		 1/*
2 * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
3 *
4 * Copyright: 2011 Raumfeld GmbH
5 * Author: Johannes Stezenbach <js@sig21.net>
6 *
7 * based on code from:
8 * Wolfson Microelectronics PLC.
9 * Mark Brown <broonie@opensource.wolfsonmicro.com>
10 * Freescale Semiconductor, Inc.
11 * Timur Tabi <timur@freescale.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
20
21#include <linux/module.h>
22#include <linux/moduleparam.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/pm.h>
26#include <linux/i2c.h>
29fdf4fb 27#include <linux/regmap.h>
c034abf6
JS		 28#include <linux/regulator/consumer.h>
29#include <linux/slab.h>
3fb5eac5 30#include <linux/workqueue.h>
c034abf6
JS		 31#include <sound/core.h>
32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/soc.h>
35#include <sound/soc-dapm.h>
36#include <sound/initval.h>
37#include <sound/tlv.h>
38
e012ba24 39#include <sound/sta32x.h>
c034abf6
JS		 40#include "sta32x.h"
41
42#define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
43 SNDRV_PCM_RATE_44100 | \
44 SNDRV_PCM_RATE_48000 | \
45 SNDRV_PCM_RATE_88200 | \
46 SNDRV_PCM_RATE_96000 | \
47 SNDRV_PCM_RATE_176400 | \
48 SNDRV_PCM_RATE_192000)
49
50#define STA32X_FORMATS \
51 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
52 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
53 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
54 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \
55 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
56 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE)
57
58/* Power-up register defaults */
29fdf4fb
MB		 59static const struct reg_default sta32x_regs[] = {
60 { 0x0, 0x63 },
61 { 0x1, 0x80 },
62 { 0x2, 0xc2 },
63 { 0x3, 0x40 },
64 { 0x4, 0xc2 },
65 { 0x5, 0x5c },
66 { 0x6, 0x10 },
67 { 0x7, 0xff },
68 { 0x8, 0x60 },
69 { 0x9, 0x60 },
70 { 0xa, 0x60 },
71 { 0xb, 0x80 },
72 { 0xc, 0x00 },
73 { 0xd, 0x00 },
74 { 0xe, 0x00 },
75 { 0xf, 0x40 },
76 { 0x10, 0x80 },
77 { 0x11, 0x77 },
78 { 0x12, 0x6a },
79 { 0x13, 0x69 },
80 { 0x14, 0x6a },
81 { 0x15, 0x69 },
82 { 0x16, 0x00 },
83 { 0x17, 0x00 },
84 { 0x18, 0x00 },
85 { 0x19, 0x00 },
86 { 0x1a, 0x00 },
87 { 0x1b, 0x00 },
88 { 0x1c, 0x00 },
89 { 0x1d, 0x00 },
90 { 0x1e, 0x00 },
91 { 0x1f, 0x00 },
92 { 0x20, 0x00 },
93 { 0x21, 0x00 },
94 { 0x22, 0x00 },
95 { 0x23, 0x00 },
96 { 0x24, 0x00 },
97 { 0x25, 0x00 },
98 { 0x26, 0x00 },
99 { 0x27, 0x2d },
100 { 0x28, 0xc0 },
101 { 0x2b, 0x00 },
102 { 0x2c, 0x0c },
c034abf6
JS		 103};
104
105/* regulator power supply names */
106static const char *sta32x_supply_names[] = {
107 "Vdda", /* analog supply, 3.3VV */
108 "Vdd3", /* digital supply, 3.3V */
109 "Vcc" /* power amp spply, 10V - 36V */
110};
111
112/* codec private data */
113struct sta32x_priv {
29fdf4fb 114 struct regmap *regmap;
c034abf6
JS		 115 struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
116 struct snd_soc_codec *codec;
e012ba24 117 struct sta32x_platform_data *pdata;
c034abf6
JS		 118
119 unsigned int mclk;
120 unsigned int format;
54dc6cab
JS		 121
122 u32 coef_shadow[STA32X_COEF_COUNT];
3fb5eac5
JS		 123 struct delayed_work watchdog_work;
124 int shutdown;
c034abf6
JS		 125};
126
127static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
128static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
129static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
130
131static const char *sta32x_drc_ac[] = {
132 "Anti-Clipping", "Dynamic Range Compression" };
133static const char *sta32x_auto_eq_mode[] = {
134 "User", "Preset", "Loudness" };
135static const char *sta32x_auto_gc_mode[] = {
136 "User", "AC no clipping", "AC limited clipping (10%)",
137 "DRC nighttime listening mode" };
138static const char *sta32x_auto_xo_mode[] = {
139 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
140 "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
141static const char *sta32x_preset_eq_mode[] = {
142 "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
143 "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
144 "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
145 "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
146 "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
147 "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
148static const char *sta32x_limiter_select[] = {
149 "Limiter Disabled", "Limiter #1", "Limiter #2" };
150static const char *sta32x_limiter_attack_rate[] = {
151 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
152 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
153 "0.0645", "0.0564", "0.0501", "0.0451" };
154static const char *sta32x_limiter_release_rate[] = {
155 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
156 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
157 "0.0134", "0.0117", "0.0110", "0.0104" };
158
159static const unsigned int sta32x_limiter_ac_attack_tlv[] = {
160 TLV_DB_RANGE_HEAD(2),
161 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
162 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
163};
164
165static const unsigned int sta32x_limiter_ac_release_tlv[] = {
166 TLV_DB_RANGE_HEAD(5),
167 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
168 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
169 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
170 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
171 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
172};
173
174static const unsigned int sta32x_limiter_drc_attack_tlv[] = {
175 TLV_DB_RANGE_HEAD(3),
176 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
177 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
178 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
179};
180
181static const unsigned int sta32x_limiter_drc_release_tlv[] = {
182 TLV_DB_RANGE_HEAD(5),
183 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
184 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
185 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
186 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
187 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
188};
189
025c3fa9
TI		 190static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum,
191 STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
192 sta32x_drc_ac);
193static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum,
194 STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
195 sta32x_auto_eq_mode);
196static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum,
197 STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
198 sta32x_auto_gc_mode);
199static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum,
200 STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
201 sta32x_auto_xo_mode);
202static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum,
203 STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
204 sta32x_preset_eq_mode);
205static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum,
206 STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
207 sta32x_limiter_select);
208static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum,
209 STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
210 sta32x_limiter_select);
211static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum,
212 STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
213 sta32x_limiter_select);
214static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum,
215 STA32X_L1AR, STA32X_LxA_SHIFT,
216 sta32x_limiter_attack_rate);
217static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum,
218 STA32X_L2AR, STA32X_LxA_SHIFT,
219 sta32x_limiter_attack_rate);
220static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum,
221 STA32X_L1AR, STA32X_LxR_SHIFT,
222 sta32x_limiter_release_rate);
223static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum,
224 STA32X_L2AR, STA32X_LxR_SHIFT,
225 sta32x_limiter_release_rate);
79688439
JS		 226
227/* byte array controls for setting biquad, mixer, scaling coefficients;
228 * for biquads all five coefficients need to be set in one go,
229 * mixer and pre/postscale coefs can be set individually;
230 * each coef is 24bit, the bytes are ordered in the same way
231 * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0)
232 */
233
234static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
235 struct snd_ctl_elem_info *uinfo)
236{
237 int numcoef = kcontrol->private_value >> 16;
238 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
239 uinfo->count = 3 * numcoef;
240 return 0;
241}
242
243static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
244 struct snd_ctl_elem_value *ucontrol)
245{
ea53bf77 246 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
79688439
JS		 247 int numcoef = kcontrol->private_value >> 16;
248 int index = kcontrol->private_value & 0xffff;
249 unsigned int cfud;
250 int i;
251
252 /* preserve reserved bits in STA32X_CFUD */
253 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
254 /* chip documentation does not say if the bits are self clearing,
255 * so do it explicitly */
256 snd_soc_write(codec, STA32X_CFUD, cfud);
257
258 snd_soc_write(codec, STA32X_CFADDR2, index);
259 if (numcoef == 1)
260 snd_soc_write(codec, STA32X_CFUD, cfud | 0x04);
261 else if (numcoef == 5)
262 snd_soc_write(codec, STA32X_CFUD, cfud | 0x08);
263 else
264 return -EINVAL;
265 for (i = 0; i < 3 * numcoef; i++)
266 ucontrol->value.bytes.data[i] =
267 snd_soc_read(codec, STA32X_B1CF1 + i);
268
269 return 0;
270}
271
272static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
273 struct snd_ctl_elem_value *ucontrol)
274{
ea53bf77 275 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
54dc6cab 276 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
79688439
JS		 277 int numcoef = kcontrol->private_value >> 16;
278 int index = kcontrol->private_value & 0xffff;
279 unsigned int cfud;
280 int i;
281
282 /* preserve reserved bits in STA32X_CFUD */
283 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
284 /* chip documentation does not say if the bits are self clearing,
285 * so do it explicitly */
286 snd_soc_write(codec, STA32X_CFUD, cfud);
287
288 snd_soc_write(codec, STA32X_CFADDR2, index);
54dc6cab
JS		 289 for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
290 sta32x->coef_shadow[index + i] =
291 (ucontrol->value.bytes.data[3 * i] << 16)
292 | (ucontrol->value.bytes.data[3 * i + 1] << 8)
293 | (ucontrol->value.bytes.data[3 * i + 2]);
79688439
JS		 294 for (i = 0; i < 3 * numcoef; i++)
295 snd_soc_write(codec, STA32X_B1CF1 + i,
296 ucontrol->value.bytes.data[i]);
297 if (numcoef == 1)
298 snd_soc_write(codec, STA32X_CFUD, cfud | 0x01);
299 else if (numcoef == 5)
300 snd_soc_write(codec, STA32X_CFUD, cfud | 0x02);
301 else
302 return -EINVAL;
303
304 return 0;
305}
306
878042d1 307static int sta32x_sync_coef_shadow(struct snd_soc_codec *codec)
54dc6cab
JS		 308{
309 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
310 unsigned int cfud;
311 int i;
312
313 /* preserve reserved bits in STA32X_CFUD */
314 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
315
316 for (i = 0; i < STA32X_COEF_COUNT; i++) {
317 snd_soc_write(codec, STA32X_CFADDR2, i);
318 snd_soc_write(codec, STA32X_B1CF1,
319 (sta32x->coef_shadow[i] >> 16) & 0xff);
320 snd_soc_write(codec, STA32X_B1CF2,
321 (sta32x->coef_shadow[i] >> 8) & 0xff);
322 snd_soc_write(codec, STA32X_B1CF3,
323 (sta32x->coef_shadow[i]) & 0xff);
324 /* chip documentation does not say if the bits are
325 * self-clearing, so do it explicitly */
326 snd_soc_write(codec, STA32X_CFUD, cfud);
327 snd_soc_write(codec, STA32X_CFUD, cfud | 0x01);
328 }
329 return 0;
330}
331
878042d1 332static int sta32x_cache_sync(struct snd_soc_codec *codec)
54dc6cab 333{
70ff00f8 334 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
54dc6cab
JS		 335 unsigned int mute;
336 int rc;
337
54dc6cab
JS		 338 /* mute during register sync */
339 mute = snd_soc_read(codec, STA32X_MMUTE);
340 snd_soc_write(codec, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
341 sta32x_sync_coef_shadow(codec);
29fdf4fb 342 rc = regcache_sync(sta32x->regmap);
54dc6cab
JS		 343 snd_soc_write(codec, STA32X_MMUTE, mute);
344 return rc;
345}
346
3fb5eac5
JS		 347/* work around ESD issue where sta32x resets and loses all configuration */
348static void sta32x_watchdog(struct work_struct *work)
349{
350 struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv,
351 watchdog_work.work);
352 struct snd_soc_codec *codec = sta32x->codec;
353 unsigned int confa, confa_cached;
354
355 /* check if sta32x has reset itself */
356 confa_cached = snd_soc_read(codec, STA32X_CONFA);
29fdf4fb 357 regcache_cache_bypass(sta32x->regmap, true);
3fb5eac5 358 confa = snd_soc_read(codec, STA32X_CONFA);
29fdf4fb 359 regcache_cache_bypass(sta32x->regmap, false);
3fb5eac5 360 if (confa != confa_cached) {
29fdf4fb 361 regcache_mark_dirty(sta32x->regmap);
3fb5eac5
JS		 362 sta32x_cache_sync(codec);
363 }
364
365 if (!sta32x->shutdown)
a14d9829
MB		 366 queue_delayed_work(system_power_efficient_wq,
367 &sta32x->watchdog_work,
368 round_jiffies_relative(HZ));
3fb5eac5
JS		 369}
370
371static void sta32x_watchdog_start(struct sta32x_priv *sta32x)
372{
373 if (sta32x->pdata->needs_esd_watchdog) {
374 sta32x->shutdown = 0;
a14d9829
MB		 375 queue_delayed_work(system_power_efficient_wq,
376 &sta32x->watchdog_work,
377 round_jiffies_relative(HZ));
3fb5eac5
JS		 378 }
379}
380
381static void sta32x_watchdog_stop(struct sta32x_priv *sta32x)
382{
383 if (sta32x->pdata->needs_esd_watchdog) {
384 sta32x->shutdown = 1;
385 cancel_delayed_work_sync(&sta32x->watchdog_work);
386 }
387}
388
79688439
JS		 389#define SINGLE_COEF(xname, index) \
390{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
391 .info = sta32x_coefficient_info, \
392 .get = sta32x_coefficient_get,\
393 .put = sta32x_coefficient_put, \
394 .private_value = index | (1 << 16) }
395
396#define BIQUAD_COEFS(xname, index) \
397{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
398 .info = sta32x_coefficient_info, \
399 .get = sta32x_coefficient_get,\
400 .put = sta32x_coefficient_put, \
401 .private_value = index | (5 << 16) }
402
c034abf6
JS		 403static const struct snd_kcontrol_new sta32x_snd_controls[] = {
404SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
405SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
406SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
407SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
408SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
409SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
410SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
411SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
412SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
413SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
414SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
415SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
416SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
417SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
418SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
419SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
420SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
421SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
422SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
423SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
424SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
425SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
426SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
427SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
428SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
429SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
430SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
431SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
432SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
433SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
434SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
435SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
436SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
b3619b28 437SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum),
c034abf6
JS		 438
439/* depending on mode, the attack/release thresholds have
440 * two different enum definitions; provide both
441 */
442SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
443 16, 0, sta32x_limiter_ac_attack_tlv),
444SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
445 16, 0, sta32x_limiter_ac_attack_tlv),
446SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
447 16, 0, sta32x_limiter_ac_release_tlv),
448SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
449 16, 0, sta32x_limiter_ac_release_tlv),
450SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
451 16, 0, sta32x_limiter_drc_attack_tlv),
452SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
453 16, 0, sta32x_limiter_drc_attack_tlv),
454SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
455 16, 0, sta32x_limiter_drc_release_tlv),
456SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
457 16, 0, sta32x_limiter_drc_release_tlv),
79688439
JS		 458
459BIQUAD_COEFS("Ch1 - Biquad 1", 0),
460BIQUAD_COEFS("Ch1 - Biquad 2", 5),
461BIQUAD_COEFS("Ch1 - Biquad 3", 10),
462BIQUAD_COEFS("Ch1 - Biquad 4", 15),
463BIQUAD_COEFS("Ch2 - Biquad 1", 20),
464BIQUAD_COEFS("Ch2 - Biquad 2", 25),
465BIQUAD_COEFS("Ch2 - Biquad 3", 30),
466BIQUAD_COEFS("Ch2 - Biquad 4", 35),
467BIQUAD_COEFS("High-pass", 40),
468BIQUAD_COEFS("Low-pass", 45),
469SINGLE_COEF("Ch1 - Prescale", 50),
470SINGLE_COEF("Ch2 - Prescale", 51),
471SINGLE_COEF("Ch1 - Postscale", 52),
472SINGLE_COEF("Ch2 - Postscale", 53),
473SINGLE_COEF("Ch3 - Postscale", 54),
474SINGLE_COEF("Thermal warning - Postscale", 55),
475SINGLE_COEF("Ch1 - Mix 1", 56),
476SINGLE_COEF("Ch1 - Mix 2", 57),
477SINGLE_COEF("Ch2 - Mix 1", 58),
478SINGLE_COEF("Ch2 - Mix 2", 59),
479SINGLE_COEF("Ch3 - Mix 1", 60),
480SINGLE_COEF("Ch3 - Mix 2", 61),
c034abf6
JS		 481};
482
483static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
484SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
485SND_SOC_DAPM_OUTPUT("LEFT"),
486SND_SOC_DAPM_OUTPUT("RIGHT"),
487SND_SOC_DAPM_OUTPUT("SUB"),
488};
489
490static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
491 { "LEFT", NULL, "DAC" },
492 { "RIGHT", NULL, "DAC" },
493 { "SUB", NULL, "DAC" },
494};
495
496/* MCLK interpolation ratio per fs */
497static struct {
498 int fs;
499 int ir;
500} interpolation_ratios[] = {
501 { 32000, 0 },
502 { 44100, 0 },
503 { 48000, 0 },
504 { 88200, 1 },
505 { 96000, 1 },
506 { 176400, 2 },
507 { 192000, 2 },
508};
509
510/* MCLK to fs clock ratios */
511static struct {
512 int ratio;
513 int mcs;
514} mclk_ratios[3][7] = {
515 { { 768, 0 }, { 512, 1 }, { 384, 2 }, { 256, 3 },
516 { 128, 4 }, { 576, 5 }, { 0, 0 } },
517 { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } },
518 { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } },
519};
520
521
522/**
523 * sta32x_set_dai_sysclk - configure MCLK
524 * @codec_dai: the codec DAI
525 * @clk_id: the clock ID (ignored)
526 * @freq: the MCLK input frequency
527 * @dir: the clock direction (ignored)
528 *
529 * The value of MCLK is used to determine which sample rates are supported
530 * by the STA32X, based on the mclk_ratios table.
531 *
532 * This function must be called by the machine driver's 'startup' function,
533 * otherwise the list of supported sample rates will not be available in
534 * time for ALSA.
535 *
536 * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
537 * theoretically possible sample rates to be enabled. Call it again with a
538 * proper value set one the external clock is set (most probably you would do
539 * that from a machine's driver 'hw_param' hook.
540 */
541static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
542 int clk_id, unsigned int freq, int dir)
543{
544 struct snd_soc_codec *codec = codec_dai->codec;
545 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
546 int i, j, ir, fs;
547 unsigned int rates = 0;
548 unsigned int rate_min = -1;
549 unsigned int rate_max = 0;
550
551 pr_debug("mclk=%u\n", freq);
552 sta32x->mclk = freq;
553
554 if (sta32x->mclk) {
555 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
556 ir = interpolation_ratios[i].ir;
557 fs = interpolation_ratios[i].fs;
558 for (j = 0; mclk_ratios[ir][j].ratio; j++) {
559 if (mclk_ratios[ir][j].ratio * fs == freq) {
560 rates |= snd_pcm_rate_to_rate_bit(fs);
561 if (fs < rate_min)
562 rate_min = fs;
563 if (fs > rate_max)
564 rate_max = fs;
7a748e43 565 break;
c034abf6
JS		 566 }
567 }
568 }
569 /* FIXME: soc should support a rate list */
570 rates &= ~SNDRV_PCM_RATE_KNOT;
571
572 if (!rates) {
573 dev_err(codec->dev, "could not find a valid sample rate\n");
574 return -EINVAL;
575 }
576 } else {
577 /* enable all possible rates */
578 rates = STA32X_RATES;
579 rate_min = 32000;
580 rate_max = 192000;
581 }
582
583 codec_dai->driver->playback.rates = rates;
584 codec_dai->driver->playback.rate_min = rate_min;
585 codec_dai->driver->playback.rate_max = rate_max;
586 return 0;
587}
588
589/**
590 * sta32x_set_dai_fmt - configure the codec for the selected audio format
591 * @codec_dai: the codec DAI
592 * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
593 *
594 * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
595 * codec accordingly.
596 */
597static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
598 unsigned int fmt)
599{
600 struct snd_soc_codec *codec = codec_dai->codec;
601 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
602 u8 confb = snd_soc_read(codec, STA32X_CONFB);
603
604 pr_debug("\n");
605 confb &= ~(STA32X_CONFB_C1IM | STA32X_CONFB_C2IM);
606
607 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
608 case SND_SOC_DAIFMT_CBS_CFS:
609 break;
610 default:
611 return -EINVAL;
612 }
613
614 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
615 case SND_SOC_DAIFMT_I2S:
616 case SND_SOC_DAIFMT_RIGHT_J:
617 case SND_SOC_DAIFMT_LEFT_J:
618 sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
619 break;
620 default:
621 return -EINVAL;
622 }
623
624 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
625 case SND_SOC_DAIFMT_NB_NF:
626 confb |= STA32X_CONFB_C2IM;
627 break;
628 case SND_SOC_DAIFMT_NB_IF:
629 confb |= STA32X_CONFB_C1IM;
630 break;
631 default:
632 return -EINVAL;
633 }
634
635 snd_soc_write(codec, STA32X_CONFB, confb);
636 return 0;
637}
638
639/**
640 * sta32x_hw_params - program the STA32X with the given hardware parameters.
641 * @substream: the audio stream
642 * @params: the hardware parameters to set
643 * @dai: the SOC DAI (ignored)
644 *
645 * This function programs the hardware with the values provided.
646 * Specifically, the sample rate and the data format.
647 */
648static int sta32x_hw_params(struct snd_pcm_substream *substream,
649 struct snd_pcm_hw_params *params,
650 struct snd_soc_dai *dai)
651{
e6968a17 652 struct snd_soc_codec *codec = dai->codec;
c034abf6
JS		 653 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
654 unsigned int rate;
655 int i, mcs = -1, ir = -1;
656 u8 confa, confb;
657
658 rate = params_rate(params);
659 pr_debug("rate: %u\n", rate);
660 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++)
a595238b 661 if (interpolation_ratios[i].fs == rate) {
c034abf6 662 ir = interpolation_ratios[i].ir;
a595238b
AL		 663 break;
664 }
c034abf6
JS		 665 if (ir < 0)
666 return -EINVAL;
667 for (i = 0; mclk_ratios[ir][i].ratio; i++)
a595238b 668 if (mclk_ratios[ir][i].ratio * rate == sta32x->mclk) {
c034abf6 669 mcs = mclk_ratios[ir][i].mcs;
a595238b
AL		 670 break;
671 }
c034abf6
JS		 672 if (mcs < 0)
673 return -EINVAL;
674
675 confa = snd_soc_read(codec, STA32X_CONFA);
676 confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK);
677 confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT);
678
679 confb = snd_soc_read(codec, STA32X_CONFB);
680 confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB);
737e0f89
MB		 681 switch (params_width(params)) {
682 case 24:
c034abf6
JS		 683 pr_debug("24bit\n");
684 /* fall through */
737e0f89 685 case 32:
c034abf6
JS		 686 pr_debug("24bit or 32bit\n");
687 switch (sta32x->format) {
688 case SND_SOC_DAIFMT_I2S:
689 confb |= 0x0;
690 break;
691 case SND_SOC_DAIFMT_LEFT_J:
692 confb |= 0x1;
693 break;
694 case SND_SOC_DAIFMT_RIGHT_J:
695 confb |= 0x2;
696 break;
697 }
698
699 break;
737e0f89 700 case 20:
c034abf6
JS		 701 pr_debug("20bit\n");
702 switch (sta32x->format) {
703 case SND_SOC_DAIFMT_I2S:
704 confb |= 0x4;
705 break;
706 case SND_SOC_DAIFMT_LEFT_J:
707 confb |= 0x5;
708 break;
709 case SND_SOC_DAIFMT_RIGHT_J:
710 confb |= 0x6;
711 break;
712 }
713
714 break;
737e0f89 715 case 18:
c034abf6
JS		 716 pr_debug("18bit\n");
717 switch (sta32x->format) {
718 case SND_SOC_DAIFMT_I2S:
719 confb |= 0x8;
720 break;
721 case SND_SOC_DAIFMT_LEFT_J:
722 confb |= 0x9;
723 break;
724 case SND_SOC_DAIFMT_RIGHT_J:
725 confb |= 0xa;
726 break;
727 }
728
729 break;
737e0f89 730 case 16:
c034abf6
JS		 731 pr_debug("16bit\n");
732 switch (sta32x->format) {
733 case SND_SOC_DAIFMT_I2S:
734 confb |= 0x0;
735 break;
736 case SND_SOC_DAIFMT_LEFT_J:
737 confb |= 0xd;
738 break;
739 case SND_SOC_DAIFMT_RIGHT_J:
740 confb |= 0xe;
741 break;
742 }
743
744 break;
745 default:
746 return -EINVAL;
747 }
748
749 snd_soc_write(codec, STA32X_CONFA, confa);
750 snd_soc_write(codec, STA32X_CONFB, confb);
751 return 0;
752}
753
754/**
755 * sta32x_set_bias_level - DAPM callback
756 * @codec: the codec device
757 * @level: DAPM power level
758 *
759 * This is called by ALSA to put the codec into low power mode
760 * or to wake it up. If the codec is powered off completely
761 * all registers must be restored after power on.
762 */
763static int sta32x_set_bias_level(struct snd_soc_codec *codec,
764 enum snd_soc_bias_level level)
765{
766 int ret;
767 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
768
769 pr_debug("level = %d\n", level);
770 switch (level) {
771 case SND_SOC_BIAS_ON:
772 break;
773
774 case SND_SOC_BIAS_PREPARE:
775 /* Full power on */
776 snd_soc_update_bits(codec, STA32X_CONFF,
777 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
778 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
779 break;
780
781 case SND_SOC_BIAS_STANDBY:
782 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
783 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
784 sta32x->supplies);
785 if (ret != 0) {
786 dev_err(codec->dev,
787 "Failed to enable supplies: %d\n", ret);
788 return ret;
789 }
790
54dc6cab 791 sta32x_cache_sync(codec);
3fb5eac5 792 sta32x_watchdog_start(sta32x);
c034abf6
JS		 793 }
794
795 /* Power up to mute */
796 /* FIXME */
797 snd_soc_update_bits(codec, STA32X_CONFF,
798 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
799 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
800
801 break;
802
803 case SND_SOC_BIAS_OFF:
804 /* The chip runs through the power down sequence for us. */
805 snd_soc_update_bits(codec, STA32X_CONFF,
806 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
807 STA32X_CONFF_PWDN);
808 msleep(300);
3fb5eac5 809 sta32x_watchdog_stop(sta32x);
c034abf6
JS		 810 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
811 sta32x->supplies);
812 break;
813 }
814 codec->dapm.bias_level = level;
815 return 0;
816}
817
85e7652d 818static const struct snd_soc_dai_ops sta32x_dai_ops = {
c034abf6
JS		 819 .hw_params = sta32x_hw_params,
820 .set_sysclk = sta32x_set_dai_sysclk,
821 .set_fmt = sta32x_set_dai_fmt,
822};
823
824static struct snd_soc_dai_driver sta32x_dai = {
825 .name = "STA32X",
826 .playback = {
827 .stream_name = "Playback",
828 .channels_min = 2,
829 .channels_max = 2,
830 .rates = STA32X_RATES,
831 .formats = STA32X_FORMATS,
832 },
833 .ops = &sta32x_dai_ops,
834};
835
836#ifdef CONFIG_PM
84b315ee 837static int sta32x_suspend(struct snd_soc_codec *codec)
c034abf6
JS		 838{
839 sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF);
840 return 0;
841}
842
843static int sta32x_resume(struct snd_soc_codec *codec)
844{
845 sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
846 return 0;
847}
848#else
849#define sta32x_suspend NULL
850#define sta32x_resume NULL
851#endif
852
853static int sta32x_probe(struct snd_soc_codec *codec)
854{
855 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
e012ba24 856 int i, ret = 0, thermal = 0;
c034abf6
JS		 857
858 sta32x->codec = codec;
e012ba24 859 sta32x->pdata = dev_get_platdata(codec->dev);
c034abf6 860
c034abf6
JS		 861 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
862 sta32x->supplies);
863 if (ret != 0) {
864 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
aff041af 865 return ret;
c034abf6
JS		 866 }
867
edf413f6
AL		 868 /* Chip documentation explicitly requires that the reset values
869 * of reserved register bits are left untouched.
870 * Write the register default value to cache for reserved registers,
871 * so the write to the these registers are suppressed by the cache
872 * restore code when it skips writes of default registers.
873 */
29fdf4fb
MB		 874 regcache_cache_only(sta32x->regmap, true);
875 snd_soc_write(codec, STA32X_CONFC, 0xc2);
876 snd_soc_write(codec, STA32X_CONFE, 0xc2);
877 snd_soc_write(codec, STA32X_CONFF, 0x5c);
878 snd_soc_write(codec, STA32X_MMUTE, 0x10);
879 snd_soc_write(codec, STA32X_AUTO1, 0x60);
880 snd_soc_write(codec, STA32X_AUTO3, 0x00);
881 snd_soc_write(codec, STA32X_C3CFG, 0x40);
882 regcache_cache_only(sta32x->regmap, false);
889ebae5 883
e012ba24
JS		 884 /* set thermal warning adjustment and recovery */
885 if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_ADJUSTMENT_ENABLE))
886 thermal |= STA32X_CONFA_TWAB;
887 if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_RECOVERY_ENABLE))
888 thermal |= STA32X_CONFA_TWRB;
c034abf6 889 snd_soc_update_bits(codec, STA32X_CONFA,
e012ba24
JS		 890 STA32X_CONFA_TWAB | STA32X_CONFA_TWRB,
891 thermal);
c034abf6 892
e012ba24 893 /* select output configuration */
c034abf6
JS		 894 snd_soc_update_bits(codec, STA32X_CONFF,
895 STA32X_CONFF_OCFG_MASK,
e012ba24
JS		 896 sta32x->pdata->output_conf
897 << STA32X_CONFF_OCFG_SHIFT);
c034abf6 898
e012ba24 899 /* channel to output mapping */
c034abf6
JS		 900 snd_soc_update_bits(codec, STA32X_C1CFG,
901 STA32X_CxCFG_OM_MASK,
e012ba24
JS		 902 sta32x->pdata->ch1_output_mapping
903 << STA32X_CxCFG_OM_SHIFT);
c034abf6
JS		 904 snd_soc_update_bits(codec, STA32X_C2CFG,
905 STA32X_CxCFG_OM_MASK,
e012ba24
JS		 906 sta32x->pdata->ch2_output_mapping
907 << STA32X_CxCFG_OM_SHIFT);
c034abf6
JS		 908 snd_soc_update_bits(codec, STA32X_C3CFG,
909 STA32X_CxCFG_OM_MASK,
e012ba24
JS		 910 sta32x->pdata->ch3_output_mapping
911 << STA32X_CxCFG_OM_SHIFT);
c034abf6 912
54dc6cab
JS		 913 /* initialize coefficient shadow RAM with reset values */
914 for (i = 4; i <= 49; i += 5)
915 sta32x->coef_shadow[i] = 0x400000;
916 for (i = 50; i <= 54; i++)
917 sta32x->coef_shadow[i] = 0x7fffff;
918 sta32x->coef_shadow[55] = 0x5a9df7;
919 sta32x->coef_shadow[56] = 0x7fffff;
920 sta32x->coef_shadow[59] = 0x7fffff;
921 sta32x->coef_shadow[60] = 0x400000;
922 sta32x->coef_shadow[61] = 0x400000;
923
3fb5eac5
JS		 924 if (sta32x->pdata->needs_esd_watchdog)
925 INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog);
926
c034abf6
JS		 927 sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
928 /* Bias level configuration will have done an extra enable */
929 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
930
931 return 0;
c034abf6
JS		 932}
933
934static int sta32x_remove(struct snd_soc_codec *codec)
935{
936 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
937
3fb5eac5 938 sta32x_watchdog_stop(sta32x);
e3d73c1b 939 sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF);
c034abf6 940 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
c034abf6
JS		 941
942 return 0;
943}
944
29fdf4fb 945static bool sta32x_reg_is_volatile(struct device *dev, unsigned int reg)
79688439
JS		 946{
947 switch (reg) {
948 case STA32X_CONFA ... STA32X_L2ATRT:
949 case STA32X_MPCC1 ... STA32X_FDRC2:
950 return 0;
951 }
952 return 1;
953}
954
c034abf6
JS		 955static const struct snd_soc_codec_driver sta32x_codec = {
956 .probe = sta32x_probe,
957 .remove = sta32x_remove,
958 .suspend = sta32x_suspend,
959 .resume = sta32x_resume,
c034abf6
JS		 960 .set_bias_level = sta32x_set_bias_level,
961 .controls = sta32x_snd_controls,
962 .num_controls = ARRAY_SIZE(sta32x_snd_controls),
963 .dapm_widgets = sta32x_dapm_widgets,
964 .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets),
965 .dapm_routes = sta32x_dapm_routes,
966 .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes),
967};
968
29fdf4fb
MB		 969static const struct regmap_config sta32x_regmap = {
970 .reg_bits = 8,
971 .val_bits = 8,
972 .max_register = STA32X_FDRC2,
973 .reg_defaults = sta32x_regs,
974 .num_reg_defaults = ARRAY_SIZE(sta32x_regs),
975 .cache_type = REGCACHE_RBTREE,
976 .volatile_reg = sta32x_reg_is_volatile,
977};
978
7a79e94e
BP		 979static int sta32x_i2c_probe(struct i2c_client *i2c,
980 const struct i2c_device_id *id)
c034abf6
JS		 981{
982 struct sta32x_priv *sta32x;
aff041af 983 int ret, i;
c034abf6 984
d999c021
AL		 985 sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv),
986 GFP_KERNEL);
c034abf6
JS		 987 if (!sta32x)
988 return -ENOMEM;
989
aff041af
MB		 990 /* regulators */
991 for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
992 sta32x->supplies[i].supply = sta32x_supply_names[i];
993
994 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies),
995 sta32x->supplies);
996 if (ret != 0) {
997 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
998 return ret;
999 }
1000
29fdf4fb
MB		 1001 sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap);
1002 if (IS_ERR(sta32x->regmap)) {
1003 ret = PTR_ERR(sta32x->regmap);
1004 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
1005 return ret;
1006 }
1007
c034abf6
JS		 1008 i2c_set_clientdata(i2c, sta32x);
1009
1010 ret = snd_soc_register_codec(&i2c->dev, &sta32x_codec, &sta32x_dai, 1);
d999c021 1011 if (ret != 0)
c034abf6 1012 dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret);
c034abf6 1013
d999c021 1014 return ret;
c034abf6
JS		 1015}
1016
7a79e94e 1017static int sta32x_i2c_remove(struct i2c_client *client)
c034abf6 1018{
e3d73c1b 1019 snd_soc_unregister_codec(&client->dev);
c034abf6
JS		 1020 return 0;
1021}
1022
1023static const struct i2c_device_id sta32x_i2c_id[] = {
1024 { "sta326", 0 },
1025 { "sta328", 0 },
1026 { "sta329", 0 },
1027 { }
1028};
1029MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
1030
1031static struct i2c_driver sta32x_i2c_driver = {
1032 .driver = {
1033 .name = "sta32x",
1034 .owner = THIS_MODULE,
1035 },
1036 .probe = sta32x_i2c_probe,
7a79e94e 1037 .remove = sta32x_i2c_remove,
c034abf6
JS		 1038 .id_table = sta32x_i2c_id,
1039};
1040
0ead1136 1041module_i2c_driver(sta32x_i2c_driver);
c034abf6
JS		 1042
1043MODULE_DESCRIPTION("ASoC STA32X driver");
1044MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>");
1045MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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