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4fa89346 DM |
1 | /* |
2 | * TAS5086 ASoC codec driver | |
3 | * | |
4 | * Copyright (c) 2013 Daniel Mack <zonque@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * TODO: | |
17 | * - implement DAPM and input muxing | |
18 | * - implement modulation limit | |
19 | * - implement non-default PWM start | |
20 | * | |
21 | * Note that this chip has a very unusual register layout, specifically | |
22 | * because the registers are of unequal size, and multi-byte registers | |
23 | * require bulk writes to take effect. Regmap does not support that kind | |
24 | * of devices. | |
25 | * | |
26 | * Currently, the driver does not touch any of the registers >= 0x20, so | |
27 | * it doesn't matter because the entire map can be accessed as 8-bit | |
28 | * array. In case more features will be added in the future | |
29 | * that require access to higher registers, the entire regmap H/W I/O | |
30 | * routines have to be open-coded. | |
31 | */ | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/gpio.h> | |
37 | #include <linux/i2c.h> | |
38 | #include <linux/regmap.h> | |
39 | #include <linux/spi/spi.h> | |
40 | #include <linux/of_device.h> | |
41 | #include <linux/of_gpio.h> | |
42 | #include <sound/pcm.h> | |
43 | #include <sound/pcm_params.h> | |
44 | #include <sound/soc.h> | |
45 | #include <sound/tlv.h> | |
46 | #include <sound/tas5086.h> | |
47 | ||
48 | #define TAS5086_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ | |
49 | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
50 | SNDRV_PCM_FMTBIT_S24_3LE) | |
51 | ||
52 | #define TAS5086_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ | |
53 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \ | |
54 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \ | |
55 | SNDRV_PCM_RATE_192000) | |
56 | ||
57 | /* | |
58 | * TAS5086 registers | |
59 | */ | |
60 | #define TAS5086_CLOCK_CONTROL 0x00 /* Clock control register */ | |
61 | #define TAS5086_CLOCK_RATE(val) (val << 5) | |
62 | #define TAS5086_CLOCK_RATE_MASK (0x7 << 5) | |
63 | #define TAS5086_CLOCK_RATIO(val) (val << 2) | |
64 | #define TAS5086_CLOCK_RATIO_MASK (0x7 << 2) | |
65 | #define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1) | |
66 | #define TAS5086_CLOCK_VALID (1 << 0) | |
67 | ||
68 | #define TAS5086_DEEMPH_MASK 0x03 | |
69 | #define TAS5086_SOFT_MUTE_ALL 0x3f | |
70 | ||
71 | #define TAS5086_DEV_ID 0x01 /* Device ID register */ | |
72 | #define TAS5086_ERROR_STATUS 0x02 /* Error status register */ | |
73 | #define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */ | |
74 | #define TAS5086_SERIAL_DATA_IF 0x04 /* Serial data interface register */ | |
75 | #define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */ | |
76 | #define TAS5086_SOFT_MUTE 0x06 /* Soft mute register */ | |
77 | #define TAS5086_MASTER_VOL 0x07 /* Master volume */ | |
78 | #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */ | |
79 | #define TAS5086_VOLUME_CONTROL 0x09 /* Volume control register */ | |
80 | #define TAS5086_MOD_LIMIT 0x10 /* Modulation limit register */ | |
81 | #define TAS5086_PWM_START 0x18 /* PWM start register */ | |
82 | #define TAS5086_SURROUND 0x19 /* Surround register */ | |
83 | #define TAS5086_SPLIT_CAP_CHARGE 0x1a /* Split cap charge period register */ | |
84 | #define TAS5086_OSC_TRIM 0x1b /* Oscillator trim register */ | |
85 | #define TAS5086_BKNDERR 0x1c | |
8892d479 DM |
86 | #define TAS5086_INPUT_MUX 0x20 |
87 | #define TAS5086_PWM_OUTPUT_MUX 0x25 | |
88 | ||
89 | #define TAS5086_MAX_REGISTER TAS5086_PWM_OUTPUT_MUX | |
4fa89346 | 90 | |
79b23b56 DM |
91 | #define TAS5086_PWM_START_MIDZ_FOR_START_1 (1 << 7) |
92 | #define TAS5086_PWM_START_MIDZ_FOR_START_2 (1 << 6) | |
93 | #define TAS5086_PWM_START_CHANNEL_MASK (0x3f) | |
94 | ||
4fa89346 DM |
95 | /* |
96 | * Default TAS5086 power-up configuration | |
97 | */ | |
98 | static const struct reg_default tas5086_reg_defaults[] = { | |
99 | { 0x00, 0x6c }, | |
100 | { 0x01, 0x03 }, | |
101 | { 0x02, 0x00 }, | |
102 | { 0x03, 0xa0 }, | |
103 | { 0x04, 0x05 }, | |
104 | { 0x05, 0x60 }, | |
105 | { 0x06, 0x00 }, | |
106 | { 0x07, 0xff }, | |
107 | { 0x08, 0x30 }, | |
108 | { 0x09, 0x30 }, | |
109 | { 0x0a, 0x30 }, | |
110 | { 0x0b, 0x30 }, | |
111 | { 0x0c, 0x30 }, | |
112 | { 0x0d, 0x30 }, | |
113 | { 0x0e, 0xb1 }, | |
114 | { 0x0f, 0x00 }, | |
115 | { 0x10, 0x02 }, | |
116 | { 0x11, 0x00 }, | |
117 | { 0x12, 0x00 }, | |
118 | { 0x13, 0x00 }, | |
119 | { 0x14, 0x00 }, | |
120 | { 0x15, 0x00 }, | |
121 | { 0x16, 0x00 }, | |
122 | { 0x17, 0x00 }, | |
123 | { 0x18, 0x3f }, | |
124 | { 0x19, 0x00 }, | |
125 | { 0x1a, 0x18 }, | |
126 | { 0x1b, 0x82 }, | |
127 | { 0x1c, 0x05 }, | |
128 | }; | |
129 | ||
6b36d370 DM |
130 | static int tas5086_register_size(struct device *dev, unsigned int reg) |
131 | { | |
132 | switch (reg) { | |
9f24dc87 | 133 | case TAS5086_CLOCK_CONTROL ... TAS5086_BKNDERR: |
6b36d370 | 134 | return 1; |
8892d479 DM |
135 | case TAS5086_INPUT_MUX: |
136 | case TAS5086_PWM_OUTPUT_MUX: | |
137 | return 4; | |
6b36d370 DM |
138 | } |
139 | ||
140 | dev_err(dev, "Unsupported register address: %d\n", reg); | |
141 | return 0; | |
142 | } | |
143 | ||
4fa89346 DM |
144 | static bool tas5086_accessible_reg(struct device *dev, unsigned int reg) |
145 | { | |
8892d479 DM |
146 | switch (reg) { |
147 | case 0x0f: | |
148 | case 0x11 ... 0x17: | |
149 | case 0x1d ... 0x1f: | |
150 | return false; | |
151 | default: | |
152 | return true; | |
153 | } | |
4fa89346 DM |
154 | } |
155 | ||
156 | static bool tas5086_volatile_reg(struct device *dev, unsigned int reg) | |
157 | { | |
158 | switch (reg) { | |
159 | case TAS5086_DEV_ID: | |
160 | case TAS5086_ERROR_STATUS: | |
161 | return true; | |
162 | } | |
163 | ||
164 | return false; | |
165 | } | |
166 | ||
167 | static bool tas5086_writeable_reg(struct device *dev, unsigned int reg) | |
168 | { | |
169 | return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID); | |
170 | } | |
171 | ||
6b36d370 DM |
172 | static int tas5086_reg_write(void *context, unsigned int reg, |
173 | unsigned int value) | |
174 | { | |
175 | struct i2c_client *client = context; | |
176 | unsigned int i, size; | |
177 | uint8_t buf[5]; | |
178 | int ret; | |
179 | ||
180 | size = tas5086_register_size(&client->dev, reg); | |
181 | if (size == 0) | |
182 | return -EINVAL; | |
183 | ||
184 | buf[0] = reg; | |
185 | ||
186 | for (i = size; i >= 1; --i) { | |
187 | buf[i] = value; | |
188 | value >>= 8; | |
189 | } | |
190 | ||
191 | ret = i2c_master_send(client, buf, size + 1); | |
192 | if (ret == size + 1) | |
193 | return 0; | |
194 | else if (ret < 0) | |
195 | return ret; | |
196 | else | |
197 | return -EIO; | |
198 | } | |
199 | ||
200 | static int tas5086_reg_read(void *context, unsigned int reg, | |
201 | unsigned int *value) | |
202 | { | |
203 | struct i2c_client *client = context; | |
204 | uint8_t send_buf, recv_buf[4]; | |
205 | struct i2c_msg msgs[2]; | |
206 | unsigned int size; | |
207 | unsigned int i; | |
208 | int ret; | |
209 | ||
210 | size = tas5086_register_size(&client->dev, reg); | |
211 | if (size == 0) | |
212 | return -EINVAL; | |
213 | ||
214 | send_buf = reg; | |
215 | ||
216 | msgs[0].addr = client->addr; | |
217 | msgs[0].len = sizeof(send_buf); | |
218 | msgs[0].buf = &send_buf; | |
219 | msgs[0].flags = 0; | |
220 | ||
221 | msgs[1].addr = client->addr; | |
222 | msgs[1].len = size; | |
223 | msgs[1].buf = recv_buf; | |
224 | msgs[1].flags = I2C_M_RD; | |
225 | ||
226 | ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); | |
227 | if (ret < 0) | |
228 | return ret; | |
229 | else if (ret != ARRAY_SIZE(msgs)) | |
230 | return -EIO; | |
231 | ||
232 | *value = 0; | |
233 | ||
234 | for (i = 0; i < size; i++) { | |
235 | *value <<= 8; | |
236 | *value |= recv_buf[i]; | |
237 | } | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
4fa89346 DM |
242 | struct tas5086_private { |
243 | struct regmap *regmap; | |
244 | unsigned int mclk, sclk; | |
245 | unsigned int format; | |
246 | bool deemph; | |
648c5382 DM |
247 | unsigned int charge_period; |
248 | unsigned int pwm_start_mid_z; | |
4fa89346 DM |
249 | /* Current sample rate for de-emphasis control */ |
250 | int rate; | |
251 | /* GPIO driving Reset pin, if any */ | |
252 | int gpio_nreset; | |
253 | }; | |
254 | ||
255 | static int tas5086_deemph[] = { 0, 32000, 44100, 48000 }; | |
256 | ||
257 | static int tas5086_set_deemph(struct snd_soc_codec *codec) | |
258 | { | |
259 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
260 | int i, val = 0; | |
261 | ||
262 | if (priv->deemph) | |
263 | for (i = 0; i < ARRAY_SIZE(tas5086_deemph); i++) | |
264 | if (tas5086_deemph[i] == priv->rate) | |
265 | val = i; | |
266 | ||
267 | return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1, | |
268 | TAS5086_DEEMPH_MASK, val); | |
269 | } | |
270 | ||
271 | static int tas5086_get_deemph(struct snd_kcontrol *kcontrol, | |
272 | struct snd_ctl_elem_value *ucontrol) | |
273 | { | |
274 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
275 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
276 | ||
277 | ucontrol->value.enumerated.item[0] = priv->deemph; | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | static int tas5086_put_deemph(struct snd_kcontrol *kcontrol, | |
283 | struct snd_ctl_elem_value *ucontrol) | |
284 | { | |
285 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
286 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
287 | ||
288 | priv->deemph = ucontrol->value.enumerated.item[0]; | |
289 | ||
290 | return tas5086_set_deemph(codec); | |
291 | } | |
292 | ||
293 | ||
294 | static int tas5086_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
295 | int clk_id, unsigned int freq, int dir) | |
296 | { | |
297 | struct snd_soc_codec *codec = codec_dai->codec; | |
298 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
299 | ||
300 | switch (clk_id) { | |
301 | case TAS5086_CLK_IDX_MCLK: | |
302 | priv->mclk = freq; | |
303 | break; | |
304 | case TAS5086_CLK_IDX_SCLK: | |
305 | priv->sclk = freq; | |
306 | break; | |
307 | } | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static int tas5086_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
313 | unsigned int format) | |
314 | { | |
315 | struct snd_soc_codec *codec = codec_dai->codec; | |
316 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
317 | ||
318 | /* The TAS5086 can only be slave to all clocks */ | |
319 | if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) { | |
320 | dev_err(codec->dev, "Invalid clocking mode\n"); | |
321 | return -EINVAL; | |
322 | } | |
323 | ||
324 | /* we need to refer to the data format from hw_params() */ | |
325 | priv->format = format; | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
330 | static const int tas5086_sample_rates[] = { | |
331 | 32000, 38000, 44100, 48000, 88200, 96000, 176400, 192000 | |
332 | }; | |
333 | ||
334 | static const int tas5086_ratios[] = { | |
335 | 64, 128, 192, 256, 384, 512 | |
336 | }; | |
337 | ||
338 | static int index_in_array(const int *array, int len, int needle) | |
339 | { | |
340 | int i; | |
341 | ||
342 | for (i = 0; i < len; i++) | |
343 | if (array[i] == needle) | |
344 | return i; | |
345 | ||
346 | return -ENOENT; | |
347 | } | |
348 | ||
349 | static int tas5086_hw_params(struct snd_pcm_substream *substream, | |
350 | struct snd_pcm_hw_params *params, | |
351 | struct snd_soc_dai *dai) | |
352 | { | |
353 | struct snd_soc_codec *codec = dai->codec; | |
354 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
28dbd161 | 355 | int val; |
4fa89346 DM |
356 | int ret; |
357 | ||
358 | priv->rate = params_rate(params); | |
359 | ||
360 | /* Look up the sample rate and refer to the offset in the list */ | |
361 | val = index_in_array(tas5086_sample_rates, | |
362 | ARRAY_SIZE(tas5086_sample_rates), priv->rate); | |
363 | ||
364 | if (val < 0) { | |
365 | dev_err(codec->dev, "Invalid sample rate\n"); | |
366 | return -EINVAL; | |
367 | } | |
368 | ||
369 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, | |
370 | TAS5086_CLOCK_RATE_MASK, | |
371 | TAS5086_CLOCK_RATE(val)); | |
372 | if (ret < 0) | |
373 | return ret; | |
374 | ||
375 | /* MCLK / Fs ratio */ | |
376 | val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios), | |
377 | priv->mclk / priv->rate); | |
378 | if (val < 0) { | |
379 | dev_err(codec->dev, "Inavlid MCLK / Fs ratio\n"); | |
380 | return -EINVAL; | |
381 | } | |
382 | ||
383 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, | |
384 | TAS5086_CLOCK_RATIO_MASK, | |
385 | TAS5086_CLOCK_RATIO(val)); | |
386 | if (ret < 0) | |
387 | return ret; | |
388 | ||
389 | ||
390 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, | |
391 | TAS5086_CLOCK_SCLK_RATIO_48, | |
392 | (priv->sclk == 48 * priv->rate) ? | |
393 | TAS5086_CLOCK_SCLK_RATIO_48 : 0); | |
394 | if (ret < 0) | |
395 | return ret; | |
396 | ||
397 | /* | |
398 | * The chip has a very unituitive register mapping and muxes information | |
399 | * about data format and sample depth into the same register, but not on | |
400 | * a logical bit-boundary. Hence, we have to refer to the format passed | |
401 | * in the set_dai_fmt() callback and set up everything from here. | |
402 | * | |
403 | * First, determine the 'base' value, using the format ... | |
404 | */ | |
405 | switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) { | |
406 | case SND_SOC_DAIFMT_RIGHT_J: | |
407 | val = 0x00; | |
408 | break; | |
409 | case SND_SOC_DAIFMT_I2S: | |
410 | val = 0x03; | |
411 | break; | |
412 | case SND_SOC_DAIFMT_LEFT_J: | |
413 | val = 0x06; | |
414 | break; | |
415 | default: | |
416 | dev_err(codec->dev, "Invalid DAI format\n"); | |
417 | return -EINVAL; | |
418 | } | |
419 | ||
420 | /* ... then add the offset for the sample bit depth. */ | |
421 | switch (params_format(params)) { | |
422 | case SNDRV_PCM_FORMAT_S16_LE: | |
423 | val += 0; | |
424 | break; | |
425 | case SNDRV_PCM_FORMAT_S20_3LE: | |
426 | val += 1; | |
427 | break; | |
428 | case SNDRV_PCM_FORMAT_S24_3LE: | |
429 | val += 2; | |
430 | break; | |
431 | default: | |
432 | dev_err(codec->dev, "Invalid bit width\n"); | |
433 | return -EINVAL; | |
434 | }; | |
435 | ||
436 | ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val); | |
437 | if (ret < 0) | |
438 | return ret; | |
439 | ||
440 | /* clock is considered valid now */ | |
441 | ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, | |
442 | TAS5086_CLOCK_VALID, TAS5086_CLOCK_VALID); | |
443 | if (ret < 0) | |
444 | return ret; | |
445 | ||
446 | return tas5086_set_deemph(codec); | |
447 | } | |
448 | ||
449 | static int tas5086_mute_stream(struct snd_soc_dai *dai, int mute, int stream) | |
450 | { | |
451 | struct snd_soc_codec *codec = dai->codec; | |
452 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
453 | unsigned int val = 0; | |
454 | ||
455 | if (mute) | |
456 | val = TAS5086_SOFT_MUTE_ALL; | |
457 | ||
458 | return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val); | |
459 | } | |
460 | ||
d5fd3ccc DM |
461 | static void tas5086_reset(struct tas5086_private *priv) |
462 | { | |
463 | if (gpio_is_valid(priv->gpio_nreset)) { | |
464 | /* Reset codec - minimum assertion time is 400ns */ | |
465 | gpio_direction_output(priv->gpio_nreset, 0); | |
466 | udelay(1); | |
467 | gpio_set_value(priv->gpio_nreset, 1); | |
468 | ||
469 | /* Codec needs ~15ms to wake up */ | |
470 | msleep(15); | |
471 | } | |
472 | } | |
473 | ||
474 | /* charge period values in microseconds */ | |
475 | static const int tas5086_charge_period[] = { | |
476 | 13000, 16900, 23400, 31200, 41600, 54600, 72800, 96200, | |
477 | 130000, 156000, 234000, 312000, 416000, 546000, 728000, 962000, | |
478 | 1300000, 169000, 2340000, 3120000, 4160000, 5460000, 7280000, 9620000, | |
479 | }; | |
480 | ||
481 | static int tas5086_init(struct device *dev, struct tas5086_private *priv) | |
482 | { | |
483 | int ret, i; | |
484 | ||
485 | /* | |
486 | * If any of the channels is configured to start in Mid-Z mode, | |
487 | * configure 'part 1' of the PWM starts to use Mid-Z, and tell | |
488 | * all configured mid-z channels to start start under 'part 1'. | |
489 | */ | |
490 | if (priv->pwm_start_mid_z) | |
491 | regmap_write(priv->regmap, TAS5086_PWM_START, | |
492 | TAS5086_PWM_START_MIDZ_FOR_START_1 | | |
493 | priv->pwm_start_mid_z); | |
494 | ||
495 | /* lookup and set split-capacitor charge period */ | |
496 | if (priv->charge_period == 0) { | |
497 | regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0); | |
498 | } else { | |
499 | i = index_in_array(tas5086_charge_period, | |
500 | ARRAY_SIZE(tas5086_charge_period), | |
501 | priv->charge_period); | |
502 | if (i >= 0) | |
503 | regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, | |
504 | i + 0x08); | |
505 | else | |
506 | dev_warn(dev, | |
507 | "Invalid split-cap charge period of %d ns.\n", | |
508 | priv->charge_period); | |
509 | } | |
510 | ||
511 | /* enable factory trim */ | |
512 | ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00); | |
513 | if (ret < 0) | |
514 | return ret; | |
515 | ||
516 | /* start all channels */ | |
517 | ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20); | |
518 | if (ret < 0) | |
519 | return ret; | |
520 | ||
521 | /* mute all channels for now */ | |
522 | ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE, | |
523 | TAS5086_SOFT_MUTE_ALL); | |
524 | if (ret < 0) | |
525 | return ret; | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
4fa89346 DM |
530 | /* TAS5086 controls */ |
531 | static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1); | |
532 | ||
533 | static const struct snd_kcontrol_new tas5086_controls[] = { | |
534 | SOC_SINGLE_TLV("Master Playback Volume", TAS5086_MASTER_VOL, | |
535 | 0, 0xff, 1, tas5086_dac_tlv), | |
536 | SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume", | |
537 | TAS5086_CHANNEL_VOL(0), TAS5086_CHANNEL_VOL(1), | |
538 | 0, 0xff, 1, tas5086_dac_tlv), | |
539 | SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume", | |
540 | TAS5086_CHANNEL_VOL(2), TAS5086_CHANNEL_VOL(3), | |
541 | 0, 0xff, 1, tas5086_dac_tlv), | |
542 | SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume", | |
543 | TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5), | |
544 | 0, 0xff, 1, tas5086_dac_tlv), | |
545 | SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, | |
546 | tas5086_get_deemph, tas5086_put_deemph), | |
547 | }; | |
548 | ||
18710acd DM |
549 | /* Input mux controls */ |
550 | static const char *tas5086_dapm_sdin_texts[] = | |
551 | { | |
552 | "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R", | |
553 | "SDIN3-L", "SDIN3-R", "Ground (0)", "nc" | |
554 | }; | |
555 | ||
556 | static const struct soc_enum tas5086_dapm_input_mux_enum[] = { | |
557 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts), | |
558 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts), | |
559 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts), | |
560 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8, 8, tas5086_dapm_sdin_texts), | |
561 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts), | |
562 | SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0, 8, tas5086_dapm_sdin_texts), | |
563 | }; | |
564 | ||
565 | static const struct snd_kcontrol_new tas5086_dapm_input_mux_controls[] = { | |
566 | SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]), | |
567 | SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]), | |
568 | SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]), | |
569 | SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]), | |
570 | SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]), | |
571 | SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]), | |
572 | }; | |
573 | ||
574 | /* Output mux controls */ | |
575 | static const char *tas5086_dapm_channel_texts[] = | |
576 | { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux", | |
577 | "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" }; | |
578 | ||
579 | static const struct soc_enum tas5086_dapm_output_mux_enum[] = { | |
580 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 20, 6, tas5086_dapm_channel_texts), | |
581 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 16, 6, tas5086_dapm_channel_texts), | |
582 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 12, 6, tas5086_dapm_channel_texts), | |
583 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8, 6, tas5086_dapm_channel_texts), | |
584 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4, 6, tas5086_dapm_channel_texts), | |
585 | SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 0, 6, tas5086_dapm_channel_texts), | |
586 | }; | |
587 | ||
588 | static const struct snd_kcontrol_new tas5086_dapm_output_mux_controls[] = { | |
589 | SOC_DAPM_ENUM("PWM1 Output", tas5086_dapm_output_mux_enum[0]), | |
590 | SOC_DAPM_ENUM("PWM2 Output", tas5086_dapm_output_mux_enum[1]), | |
591 | SOC_DAPM_ENUM("PWM3 Output", tas5086_dapm_output_mux_enum[2]), | |
592 | SOC_DAPM_ENUM("PWM4 Output", tas5086_dapm_output_mux_enum[3]), | |
593 | SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]), | |
594 | SOC_DAPM_ENUM("PWM6 Output", tas5086_dapm_output_mux_enum[5]), | |
595 | }; | |
596 | ||
597 | static const struct snd_soc_dapm_widget tas5086_dapm_widgets[] = { | |
598 | SND_SOC_DAPM_INPUT("SDIN1-L"), | |
599 | SND_SOC_DAPM_INPUT("SDIN1-R"), | |
600 | SND_SOC_DAPM_INPUT("SDIN2-L"), | |
601 | SND_SOC_DAPM_INPUT("SDIN2-R"), | |
602 | SND_SOC_DAPM_INPUT("SDIN3-L"), | |
603 | SND_SOC_DAPM_INPUT("SDIN3-R"), | |
604 | SND_SOC_DAPM_INPUT("SDIN4-L"), | |
605 | SND_SOC_DAPM_INPUT("SDIN4-R"), | |
606 | ||
607 | SND_SOC_DAPM_OUTPUT("PWM1"), | |
608 | SND_SOC_DAPM_OUTPUT("PWM2"), | |
609 | SND_SOC_DAPM_OUTPUT("PWM3"), | |
610 | SND_SOC_DAPM_OUTPUT("PWM4"), | |
611 | SND_SOC_DAPM_OUTPUT("PWM5"), | |
612 | SND_SOC_DAPM_OUTPUT("PWM6"), | |
613 | ||
614 | SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0, | |
615 | &tas5086_dapm_input_mux_controls[0]), | |
616 | SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0, | |
617 | &tas5086_dapm_input_mux_controls[1]), | |
618 | SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0, | |
619 | &tas5086_dapm_input_mux_controls[2]), | |
620 | SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0, | |
621 | &tas5086_dapm_input_mux_controls[3]), | |
622 | SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0, | |
623 | &tas5086_dapm_input_mux_controls[4]), | |
624 | SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0, | |
625 | &tas5086_dapm_input_mux_controls[5]), | |
626 | ||
627 | SND_SOC_DAPM_MUX("PWM1 Mux", SND_SOC_NOPM, 0, 0, | |
628 | &tas5086_dapm_output_mux_controls[0]), | |
629 | SND_SOC_DAPM_MUX("PWM2 Mux", SND_SOC_NOPM, 0, 0, | |
630 | &tas5086_dapm_output_mux_controls[1]), | |
631 | SND_SOC_DAPM_MUX("PWM3 Mux", SND_SOC_NOPM, 0, 0, | |
632 | &tas5086_dapm_output_mux_controls[2]), | |
633 | SND_SOC_DAPM_MUX("PWM4 Mux", SND_SOC_NOPM, 0, 0, | |
634 | &tas5086_dapm_output_mux_controls[3]), | |
635 | SND_SOC_DAPM_MUX("PWM5 Mux", SND_SOC_NOPM, 0, 0, | |
636 | &tas5086_dapm_output_mux_controls[4]), | |
637 | SND_SOC_DAPM_MUX("PWM6 Mux", SND_SOC_NOPM, 0, 0, | |
638 | &tas5086_dapm_output_mux_controls[5]), | |
639 | }; | |
640 | ||
641 | static const struct snd_soc_dapm_route tas5086_dapm_routes[] = { | |
642 | /* SDIN inputs -> channel muxes */ | |
643 | { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" }, | |
644 | { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" }, | |
645 | { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" }, | |
646 | { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" }, | |
647 | { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" }, | |
648 | { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" }, | |
649 | ||
650 | { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" }, | |
651 | { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" }, | |
652 | { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" }, | |
653 | { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" }, | |
654 | { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" }, | |
655 | { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" }, | |
656 | ||
657 | { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" }, | |
658 | { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" }, | |
659 | { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" }, | |
660 | { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" }, | |
661 | { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" }, | |
662 | { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" }, | |
663 | ||
664 | { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" }, | |
665 | { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" }, | |
666 | { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" }, | |
667 | { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" }, | |
668 | { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" }, | |
669 | { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" }, | |
670 | ||
671 | { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" }, | |
672 | { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" }, | |
673 | { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" }, | |
674 | { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" }, | |
675 | { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" }, | |
676 | { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" }, | |
677 | ||
678 | { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" }, | |
679 | { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" }, | |
680 | { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" }, | |
681 | { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" }, | |
682 | { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" }, | |
683 | { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" }, | |
684 | ||
685 | { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" }, | |
686 | { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" }, | |
687 | { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" }, | |
688 | { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" }, | |
689 | { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" }, | |
690 | { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" }, | |
691 | ||
692 | /* Channel muxes -> PWM muxes */ | |
693 | { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" }, | |
694 | { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" }, | |
695 | { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" }, | |
696 | { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" }, | |
697 | { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" }, | |
698 | { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" }, | |
699 | ||
700 | { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" }, | |
701 | { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" }, | |
702 | { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" }, | |
703 | { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" }, | |
704 | { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" }, | |
705 | { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" }, | |
706 | ||
707 | { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" }, | |
708 | { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" }, | |
709 | { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" }, | |
710 | { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" }, | |
711 | { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" }, | |
712 | { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" }, | |
713 | ||
714 | { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" }, | |
715 | { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" }, | |
716 | { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" }, | |
717 | { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" }, | |
718 | { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" }, | |
719 | { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" }, | |
720 | ||
721 | { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" }, | |
722 | { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" }, | |
723 | { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" }, | |
724 | { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" }, | |
725 | { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" }, | |
726 | { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" }, | |
727 | ||
728 | { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" }, | |
729 | { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" }, | |
730 | { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" }, | |
731 | { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" }, | |
732 | { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" }, | |
733 | { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" }, | |
734 | ||
735 | /* The PWM muxes are directly connected to the PWM outputs */ | |
736 | { "PWM1", NULL, "PWM1 Mux" }, | |
737 | { "PWM2", NULL, "PWM2 Mux" }, | |
738 | { "PWM3", NULL, "PWM3 Mux" }, | |
739 | { "PWM4", NULL, "PWM4 Mux" }, | |
740 | { "PWM5", NULL, "PWM5 Mux" }, | |
741 | { "PWM6", NULL, "PWM6 Mux" }, | |
742 | ||
743 | }; | |
744 | ||
4fa89346 DM |
745 | static const struct snd_soc_dai_ops tas5086_dai_ops = { |
746 | .hw_params = tas5086_hw_params, | |
747 | .set_sysclk = tas5086_set_dai_sysclk, | |
748 | .set_fmt = tas5086_set_dai_fmt, | |
749 | .mute_stream = tas5086_mute_stream, | |
750 | }; | |
751 | ||
752 | static struct snd_soc_dai_driver tas5086_dai = { | |
753 | .name = "tas5086-hifi", | |
754 | .playback = { | |
755 | .stream_name = "Playback", | |
756 | .channels_min = 2, | |
757 | .channels_max = 6, | |
758 | .rates = TAS5086_PCM_RATES, | |
759 | .formats = TAS5086_PCM_FORMATS, | |
760 | }, | |
761 | .ops = &tas5086_dai_ops, | |
762 | }; | |
763 | ||
764 | #ifdef CONFIG_PM | |
765 | static int tas5086_soc_resume(struct snd_soc_codec *codec) | |
766 | { | |
767 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
768 | ||
769 | /* Restore codec state */ | |
770 | return regcache_sync(priv->regmap); | |
771 | } | |
772 | #else | |
773 | #define tas5086_soc_resume NULL | |
774 | #endif /* CONFIG_PM */ | |
775 | ||
776 | #ifdef CONFIG_OF | |
777 | static const struct of_device_id tas5086_dt_ids[] = { | |
778 | { .compatible = "ti,tas5086", }, | |
779 | { } | |
780 | }; | |
781 | MODULE_DEVICE_TABLE(of, tas5086_dt_ids); | |
782 | #endif | |
783 | ||
4fa89346 DM |
784 | static int tas5086_probe(struct snd_soc_codec *codec) |
785 | { | |
786 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
4fa89346 DM |
787 | int i, ret; |
788 | ||
648c5382 DM |
789 | priv->pwm_start_mid_z = 0; |
790 | priv->charge_period = 1300000; /* hardware default is 1300 ms */ | |
791 | ||
4fa89346 DM |
792 | if (of_match_device(of_match_ptr(tas5086_dt_ids), codec->dev)) { |
793 | struct device_node *of_node = codec->dev->of_node; | |
d5fd3ccc | 794 | |
648c5382 DM |
795 | of_property_read_u32(of_node, "ti,charge-period", |
796 | &priv->charge_period); | |
79b23b56 DM |
797 | |
798 | for (i = 0; i < 6; i++) { | |
799 | char name[25]; | |
800 | ||
801 | snprintf(name, sizeof(name), | |
802 | "ti,mid-z-channel-%d", i + 1); | |
803 | ||
804 | if (of_get_property(of_node, name, NULL) != NULL) | |
648c5382 | 805 | priv->pwm_start_mid_z |= 1 << i; |
79b23b56 | 806 | } |
4fa89346 DM |
807 | } |
808 | ||
d5fd3ccc | 809 | ret = tas5086_init(codec->dev, priv); |
4fa89346 DM |
810 | if (ret < 0) |
811 | return ret; | |
812 | ||
813 | /* set master volume to 0 dB */ | |
814 | ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30); | |
815 | if (ret < 0) | |
816 | return ret; | |
817 | ||
4fa89346 DM |
818 | return 0; |
819 | } | |
820 | ||
821 | static int tas5086_remove(struct snd_soc_codec *codec) | |
822 | { | |
823 | struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); | |
824 | ||
825 | if (gpio_is_valid(priv->gpio_nreset)) | |
826 | /* Set codec to the reset state */ | |
827 | gpio_set_value(priv->gpio_nreset, 0); | |
828 | ||
829 | return 0; | |
830 | }; | |
831 | ||
832 | static struct snd_soc_codec_driver soc_codec_dev_tas5086 = { | |
833 | .probe = tas5086_probe, | |
834 | .remove = tas5086_remove, | |
835 | .resume = tas5086_soc_resume, | |
836 | .controls = tas5086_controls, | |
837 | .num_controls = ARRAY_SIZE(tas5086_controls), | |
18710acd DM |
838 | .dapm_widgets = tas5086_dapm_widgets, |
839 | .num_dapm_widgets = ARRAY_SIZE(tas5086_dapm_widgets), | |
840 | .dapm_routes = tas5086_dapm_routes, | |
841 | .num_dapm_routes = ARRAY_SIZE(tas5086_dapm_routes), | |
4fa89346 DM |
842 | }; |
843 | ||
844 | static const struct i2c_device_id tas5086_i2c_id[] = { | |
845 | { "tas5086", 0 }, | |
846 | { } | |
847 | }; | |
848 | MODULE_DEVICE_TABLE(i2c, tas5086_i2c_id); | |
849 | ||
850 | static const struct regmap_config tas5086_regmap = { | |
851 | .reg_bits = 8, | |
8892d479 DM |
852 | .val_bits = 32, |
853 | .max_register = TAS5086_MAX_REGISTER, | |
4fa89346 DM |
854 | .reg_defaults = tas5086_reg_defaults, |
855 | .num_reg_defaults = ARRAY_SIZE(tas5086_reg_defaults), | |
856 | .cache_type = REGCACHE_RBTREE, | |
857 | .volatile_reg = tas5086_volatile_reg, | |
858 | .writeable_reg = tas5086_writeable_reg, | |
859 | .readable_reg = tas5086_accessible_reg, | |
6b36d370 DM |
860 | .reg_read = tas5086_reg_read, |
861 | .reg_write = tas5086_reg_write, | |
4fa89346 DM |
862 | }; |
863 | ||
864 | static int tas5086_i2c_probe(struct i2c_client *i2c, | |
865 | const struct i2c_device_id *id) | |
866 | { | |
867 | struct tas5086_private *priv; | |
868 | struct device *dev = &i2c->dev; | |
869 | int gpio_nreset = -EINVAL; | |
870 | int i, ret; | |
871 | ||
872 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
873 | if (!priv) | |
874 | return -ENOMEM; | |
875 | ||
6b36d370 | 876 | priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap); |
4fa89346 DM |
877 | if (IS_ERR(priv->regmap)) { |
878 | ret = PTR_ERR(priv->regmap); | |
879 | dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret); | |
880 | return ret; | |
881 | } | |
882 | ||
883 | i2c_set_clientdata(i2c, priv); | |
884 | ||
885 | if (of_match_device(of_match_ptr(tas5086_dt_ids), dev)) { | |
886 | struct device_node *of_node = dev->of_node; | |
887 | gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0); | |
888 | } | |
889 | ||
890 | if (gpio_is_valid(gpio_nreset)) | |
891 | if (devm_gpio_request(dev, gpio_nreset, "TAS5086 Reset")) | |
892 | gpio_nreset = -EINVAL; | |
893 | ||
4fa89346 | 894 | priv->gpio_nreset = gpio_nreset; |
d5fd3ccc | 895 | tas5086_reset(priv); |
4fa89346 DM |
896 | |
897 | /* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */ | |
898 | ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i); | |
899 | if (ret < 0) | |
900 | return ret; | |
901 | ||
902 | if (i != 0x3) { | |
903 | dev_err(dev, | |
904 | "Failed to identify TAS5086 codec (got %02x)\n", i); | |
905 | return -ENODEV; | |
906 | } | |
907 | ||
908 | return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tas5086, | |
909 | &tas5086_dai, 1); | |
910 | } | |
911 | ||
912 | static int tas5086_i2c_remove(struct i2c_client *i2c) | |
913 | { | |
914 | snd_soc_unregister_codec(&i2c->dev); | |
915 | return 0; | |
916 | } | |
917 | ||
918 | static struct i2c_driver tas5086_i2c_driver = { | |
919 | .driver = { | |
920 | .name = "tas5086", | |
921 | .owner = THIS_MODULE, | |
922 | .of_match_table = of_match_ptr(tas5086_dt_ids), | |
923 | }, | |
924 | .id_table = tas5086_i2c_id, | |
925 | .probe = tas5086_i2c_probe, | |
926 | .remove = tas5086_i2c_remove, | |
927 | }; | |
928 | ||
c300d6de | 929 | module_i2c_driver(tas5086_i2c_driver); |
4fa89346 DM |
930 | |
931 | MODULE_AUTHOR("Daniel Mack <zonque@gmail.com>"); | |
932 | MODULE_DESCRIPTION("Texas Instruments TAS5086 ALSA SoC Codec Driver"); | |
933 | MODULE_LICENSE("GPL"); |