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ASoC: pcm1681: Fix wrong value references for boolean kctl
[deliverable/linux.git] / sound / soc / codecs / tas5086.c
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4fa89346
DM		 1/*
2 * TAS5086 ASoC codec driver
3 *
4 * Copyright (c) 2013 Daniel Mack <zonque@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * TODO:
17 * - implement DAPM and input muxing
18 * - implement modulation limit
19 * - implement non-default PWM start
20 *
21 * Note that this chip has a very unusual register layout, specifically
22 * because the registers are of unequal size, and multi-byte registers
23 * require bulk writes to take effect. Regmap does not support that kind
24 * of devices.
25 *
26 * Currently, the driver does not touch any of the registers >= 0x20, so
27 * it doesn't matter because the entire map can be accessed as 8-bit
28 * array. In case more features will be added in the future
29 * that require access to higher registers, the entire regmap H/W I/O
30 * routines have to be open-coded.
31 */
32
33#include <linux/module.h>
34#include <linux/slab.h>
35#include <linux/delay.h>
36#include <linux/gpio.h>
37#include <linux/i2c.h>
38#include <linux/regmap.h>
c46af312 39#include <linux/regulator/consumer.h>
4fa89346 40#include <linux/spi/spi.h>
285d00c1 41#include <linux/of.h>
4fa89346
DM		 42#include <linux/of_device.h>
43#include <linux/of_gpio.h>
44#include <sound/pcm.h>
45#include <sound/pcm_params.h>
46#include <sound/soc.h>
47#include <sound/tlv.h>
48#include <sound/tas5086.h>
49
50#define TAS5086_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
51 SNDRV_PCM_FMTBIT_S20_3LE | \
52 SNDRV_PCM_FMTBIT_S24_3LE)
53
54#define TAS5086_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
55 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \
56 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
57 SNDRV_PCM_RATE_192000)
58
59/*
60 * TAS5086 registers
61 */
62#define TAS5086_CLOCK_CONTROL 0x00 /* Clock control register */
63#define TAS5086_CLOCK_RATE(val) (val << 5)
64#define TAS5086_CLOCK_RATE_MASK (0x7 << 5)
65#define TAS5086_CLOCK_RATIO(val) (val << 2)
66#define TAS5086_CLOCK_RATIO_MASK (0x7 << 2)
67#define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1)
68#define TAS5086_CLOCK_VALID (1 << 0)
69
70#define TAS5086_DEEMPH_MASK 0x03
71#define TAS5086_SOFT_MUTE_ALL 0x3f
72
73#define TAS5086_DEV_ID 0x01 /* Device ID register */
74#define TAS5086_ERROR_STATUS 0x02 /* Error status register */
75#define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */
76#define TAS5086_SERIAL_DATA_IF 0x04 /* Serial data interface register */
77#define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */
78#define TAS5086_SOFT_MUTE 0x06 /* Soft mute register */
79#define TAS5086_MASTER_VOL 0x07 /* Master volume */
80#define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
81#define TAS5086_VOLUME_CONTROL 0x09 /* Volume control register */
82#define TAS5086_MOD_LIMIT 0x10 /* Modulation limit register */
83#define TAS5086_PWM_START 0x18 /* PWM start register */
84#define TAS5086_SURROUND 0x19 /* Surround register */
85#define TAS5086_SPLIT_CAP_CHARGE 0x1a /* Split cap charge period register */
86#define TAS5086_OSC_TRIM 0x1b /* Oscillator trim register */
87#define TAS5086_BKNDERR 0x1c
8892d479
DM		 88#define TAS5086_INPUT_MUX 0x20
89#define TAS5086_PWM_OUTPUT_MUX 0x25
90
91#define TAS5086_MAX_REGISTER TAS5086_PWM_OUTPUT_MUX
4fa89346 92
79b23b56
DM		 93#define TAS5086_PWM_START_MIDZ_FOR_START_1 (1 << 7)
94#define TAS5086_PWM_START_MIDZ_FOR_START_2 (1 << 6)
95#define TAS5086_PWM_START_CHANNEL_MASK (0x3f)
96
4fa89346
DM		 97/*
98 * Default TAS5086 power-up configuration
99 */
100static const struct reg_default tas5086_reg_defaults[] = {
101 { 0x00, 0x6c },
102 { 0x01, 0x03 },
103 { 0x02, 0x00 },
104 { 0x03, 0xa0 },
105 { 0x04, 0x05 },
106 { 0x05, 0x60 },
107 { 0x06, 0x00 },
108 { 0x07, 0xff },
109 { 0x08, 0x30 },
110 { 0x09, 0x30 },
111 { 0x0a, 0x30 },
112 { 0x0b, 0x30 },
113 { 0x0c, 0x30 },
114 { 0x0d, 0x30 },
115 { 0x0e, 0xb1 },
116 { 0x0f, 0x00 },
117 { 0x10, 0x02 },
118 { 0x11, 0x00 },
119 { 0x12, 0x00 },
120 { 0x13, 0x00 },
121 { 0x14, 0x00 },
122 { 0x15, 0x00 },
123 { 0x16, 0x00 },
124 { 0x17, 0x00 },
125 { 0x18, 0x3f },
126 { 0x19, 0x00 },
127 { 0x1a, 0x18 },
128 { 0x1b, 0x82 },
129 { 0x1c, 0x05 },
130};
131
6b36d370
DM		 132static int tas5086_register_size(struct device *dev, unsigned int reg)
133{
134 switch (reg) {
9f24dc87 135 case TAS5086_CLOCK_CONTROL ... TAS5086_BKNDERR:
6b36d370 136 return 1;
8892d479
DM		 137 case TAS5086_INPUT_MUX:
138 case TAS5086_PWM_OUTPUT_MUX:
139 return 4;
6b36d370
DM		 140 }
141
142 dev_err(dev, "Unsupported register address: %d\n", reg);
143 return 0;
144}
145
4fa89346
DM		 146static bool tas5086_accessible_reg(struct device *dev, unsigned int reg)
147{
8892d479
DM		 148 switch (reg) {
149 case 0x0f:
150 case 0x11 ... 0x17:
151 case 0x1d ... 0x1f:
152 return false;
153 default:
154 return true;
155 }
4fa89346
DM		 156}
157
158static bool tas5086_volatile_reg(struct device *dev, unsigned int reg)
159{
160 switch (reg) {
161 case TAS5086_DEV_ID:
162 case TAS5086_ERROR_STATUS:
163 return true;
164 }
165
166 return false;
167}
168
169static bool tas5086_writeable_reg(struct device *dev, unsigned int reg)
170{
171 return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID);
172}
173
6b36d370
DM		 174static int tas5086_reg_write(void *context, unsigned int reg,
175 unsigned int value)
176{
177 struct i2c_client *client = context;
178 unsigned int i, size;
179 uint8_t buf[5];
180 int ret;
181
182 size = tas5086_register_size(&client->dev, reg);
183 if (size == 0)
184 return -EINVAL;
185
186 buf[0] = reg;
187
188 for (i = size; i >= 1; --i) {
189 buf[i] = value;
190 value >>= 8;
191 }
192
193 ret = i2c_master_send(client, buf, size + 1);
194 if (ret == size + 1)
195 return 0;
196 else if (ret < 0)
197 return ret;
198 else
199 return -EIO;
200}
201
202static int tas5086_reg_read(void *context, unsigned int reg,
203 unsigned int *value)
204{
205 struct i2c_client *client = context;
206 uint8_t send_buf, recv_buf[4];
207 struct i2c_msg msgs[2];
208 unsigned int size;
209 unsigned int i;
210 int ret;
211
212 size = tas5086_register_size(&client->dev, reg);
213 if (size == 0)
214 return -EINVAL;
215
216 send_buf = reg;
217
218 msgs[0].addr = client->addr;
219 msgs[0].len = sizeof(send_buf);
220 msgs[0].buf = &send_buf;
221 msgs[0].flags = 0;
222
223 msgs[1].addr = client->addr;
224 msgs[1].len = size;
225 msgs[1].buf = recv_buf;
226 msgs[1].flags = I2C_M_RD;
227
228 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
229 if (ret < 0)
230 return ret;
231 else if (ret != ARRAY_SIZE(msgs))
232 return -EIO;
233
234 *value = 0;
235
236 for (i = 0; i < size; i++) {
237 *value <<= 8;
238 *value |= recv_buf[i];
239 }
240
241 return 0;
242}
243
c46af312
DM		 244static const char * const supply_names[] = {
245 "dvdd", "avdd"
246};
247
4fa89346
DM		 248struct tas5086_private {
249 struct regmap *regmap;
250 unsigned int mclk, sclk;
251 unsigned int format;
252 bool deemph;
648c5382
DM		 253 unsigned int charge_period;
254 unsigned int pwm_start_mid_z;
4fa89346
DM		 255 /* Current sample rate for de-emphasis control */
256 int rate;
257 /* GPIO driving Reset pin, if any */
258 int gpio_nreset;
c46af312 259 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
4fa89346
DM		 260};
261
262static int tas5086_deemph[] = { 0, 32000, 44100, 48000 };
263
264static int tas5086_set_deemph(struct snd_soc_codec *codec)
265{
266 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
267 int i, val = 0;
268
269 if (priv->deemph)
270 for (i = 0; i < ARRAY_SIZE(tas5086_deemph); i++)
271 if (tas5086_deemph[i] == priv->rate)
272 val = i;
273
274 return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1,
275 TAS5086_DEEMPH_MASK, val);
276}
277
278static int tas5086_get_deemph(struct snd_kcontrol *kcontrol,
279 struct snd_ctl_elem_value *ucontrol)
280{
ea53bf77 281 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
4fa89346
DM		 282 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
283
284 ucontrol->value.enumerated.item[0] = priv->deemph;
285
286 return 0;
287}
288
289static int tas5086_put_deemph(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_value *ucontrol)
291{
ea53bf77 292 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
4fa89346
DM		 293 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
294
295 priv->deemph = ucontrol->value.enumerated.item[0];
296
297 return tas5086_set_deemph(codec);
298}
299
300
301static int tas5086_set_dai_sysclk(struct snd_soc_dai *codec_dai,
302 int clk_id, unsigned int freq, int dir)
303{
304 struct snd_soc_codec *codec = codec_dai->codec;
305 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
306
307 switch (clk_id) {
308 case TAS5086_CLK_IDX_MCLK:
309 priv->mclk = freq;
310 break;
311 case TAS5086_CLK_IDX_SCLK:
312 priv->sclk = freq;
313 break;
314 }
315
316 return 0;
317}
318
319static int tas5086_set_dai_fmt(struct snd_soc_dai *codec_dai,
320 unsigned int format)
321{
322 struct snd_soc_codec *codec = codec_dai->codec;
323 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
324
325 /* The TAS5086 can only be slave to all clocks */
326 if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
327 dev_err(codec->dev, "Invalid clocking mode\n");
328 return -EINVAL;
329 }
330
331 /* we need to refer to the data format from hw_params() */
332 priv->format = format;
333
334 return 0;
335}
336
337static const int tas5086_sample_rates[] = {
338 32000, 38000, 44100, 48000, 88200, 96000, 176400, 192000
339};
340
341static const int tas5086_ratios[] = {
342 64, 128, 192, 256, 384, 512
343};
344
345static int index_in_array(const int *array, int len, int needle)
346{
347 int i;
348
349 for (i = 0; i < len; i++)
350 if (array[i] == needle)
351 return i;
352
353 return -ENOENT;
354}
355
356static int tas5086_hw_params(struct snd_pcm_substream *substream,
357 struct snd_pcm_hw_params *params,
358 struct snd_soc_dai *dai)
359{
360 struct snd_soc_codec *codec = dai->codec;
361 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
28dbd161 362 int val;
4fa89346
DM		 363 int ret;
364
365 priv->rate = params_rate(params);
366
367 /* Look up the sample rate and refer to the offset in the list */
368 val = index_in_array(tas5086_sample_rates,
369 ARRAY_SIZE(tas5086_sample_rates), priv->rate);
370
371 if (val < 0) {
372 dev_err(codec->dev, "Invalid sample rate\n");
373 return -EINVAL;
374 }
375
376 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
377 TAS5086_CLOCK_RATE_MASK,
378 TAS5086_CLOCK_RATE(val));
379 if (ret < 0)
380 return ret;
381
382 /* MCLK / Fs ratio */
383 val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios),
384 priv->mclk / priv->rate);
385 if (val < 0) {
386 dev_err(codec->dev, "Inavlid MCLK / Fs ratio\n");
387 return -EINVAL;
388 }
389
390 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
391 TAS5086_CLOCK_RATIO_MASK,
392 TAS5086_CLOCK_RATIO(val));
393 if (ret < 0)
394 return ret;
395
396
397 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
398 TAS5086_CLOCK_SCLK_RATIO_48,
399 (priv->sclk == 48 * priv->rate) ?
400 TAS5086_CLOCK_SCLK_RATIO_48 : 0);
401 if (ret < 0)
402 return ret;
403
404 /*
405 * The chip has a very unituitive register mapping and muxes information
406 * about data format and sample depth into the same register, but not on
407 * a logical bit-boundary. Hence, we have to refer to the format passed
408 * in the set_dai_fmt() callback and set up everything from here.
409 *
410 * First, determine the 'base' value, using the format ...
411 */
412 switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
413 case SND_SOC_DAIFMT_RIGHT_J:
414 val = 0x00;
415 break;
416 case SND_SOC_DAIFMT_I2S:
417 val = 0x03;
418 break;
419 case SND_SOC_DAIFMT_LEFT_J:
420 val = 0x06;
421 break;
422 default:
423 dev_err(codec->dev, "Invalid DAI format\n");
424 return -EINVAL;
425 }
426
427 /* ... then add the offset for the sample bit depth. */
c665330c
MB		 428 switch (params_width(params)) {
429 case 16:
4fa89346
DM		 430 val += 0;
431 break;
c665330c 432 case 20:
4fa89346
DM		 433 val += 1;
434 break;
c665330c 435 case 24:
4fa89346
DM		 436 val += 2;
437 break;
438 default:
439 dev_err(codec->dev, "Invalid bit width\n");
440 return -EINVAL;
1d198f26 441 }
4fa89346
DM		 442
443 ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val);
444 if (ret < 0)
445 return ret;
446
447 /* clock is considered valid now */
448 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL,
449 TAS5086_CLOCK_VALID, TAS5086_CLOCK_VALID);
450 if (ret < 0)
451 return ret;
452
453 return tas5086_set_deemph(codec);
454}
455
456static int tas5086_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
457{
458 struct snd_soc_codec *codec = dai->codec;
459 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
460 unsigned int val = 0;
461
462 if (mute)
463 val = TAS5086_SOFT_MUTE_ALL;
464
465 return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val);
466}
467
d5fd3ccc
DM		 468static void tas5086_reset(struct tas5086_private *priv)
469{
470 if (gpio_is_valid(priv->gpio_nreset)) {
471 /* Reset codec - minimum assertion time is 400ns */
472 gpio_direction_output(priv->gpio_nreset, 0);
473 udelay(1);
474 gpio_set_value(priv->gpio_nreset, 1);
475
476 /* Codec needs ~15ms to wake up */
477 msleep(15);
478 }
479}
480
481/* charge period values in microseconds */
482static const int tas5086_charge_period[] = {
483 13000, 16900, 23400, 31200, 41600, 54600, 72800, 96200,
484 130000, 156000, 234000, 312000, 416000, 546000, 728000, 962000,
485 1300000, 169000, 2340000, 3120000, 4160000, 5460000, 7280000, 9620000,
486};
487
488static int tas5086_init(struct device *dev, struct tas5086_private *priv)
489{
490 int ret, i;
491
492 /*
493 * If any of the channels is configured to start in Mid-Z mode,
494 * configure 'part 1' of the PWM starts to use Mid-Z, and tell
495 * all configured mid-z channels to start start under 'part 1'.
496 */
497 if (priv->pwm_start_mid_z)
498 regmap_write(priv->regmap, TAS5086_PWM_START,
499 TAS5086_PWM_START_MIDZ_FOR_START_1 |
500 priv->pwm_start_mid_z);
501
502 /* lookup and set split-capacitor charge period */
503 if (priv->charge_period == 0) {
504 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0);
505 } else {
506 i = index_in_array(tas5086_charge_period,
507 ARRAY_SIZE(tas5086_charge_period),
508 priv->charge_period);
509 if (i >= 0)
510 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE,
511 i + 0x08);
512 else
513 dev_warn(dev,
514 "Invalid split-cap charge period of %d ns.\n",
515 priv->charge_period);
516 }
517
518 /* enable factory trim */
519 ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00);
520 if (ret < 0)
521 return ret;
522
523 /* start all channels */
524 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20);
525 if (ret < 0)
526 return ret;
527
528 /* mute all channels for now */
529 ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE,
530 TAS5086_SOFT_MUTE_ALL);
531 if (ret < 0)
532 return ret;
533
534 return 0;
535}
536
4fa89346
DM		 537/* TAS5086 controls */
538static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1);
539
540static const struct snd_kcontrol_new tas5086_controls[] = {
541 SOC_SINGLE_TLV("Master Playback Volume", TAS5086_MASTER_VOL,
542 0, 0xff, 1, tas5086_dac_tlv),
543 SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
544 TAS5086_CHANNEL_VOL(0), TAS5086_CHANNEL_VOL(1),
545 0, 0xff, 1, tas5086_dac_tlv),
546 SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
547 TAS5086_CHANNEL_VOL(2), TAS5086_CHANNEL_VOL(3),
548 0, 0xff, 1, tas5086_dac_tlv),
549 SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
550 TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5),
551 0, 0xff, 1, tas5086_dac_tlv),
552 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
553 tas5086_get_deemph, tas5086_put_deemph),
554};
555
18710acd
DM		 556/* Input mux controls */
557static const char *tas5086_dapm_sdin_texts[] =
558{
559 "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R",
560 "SDIN3-L", "SDIN3-R", "Ground (0)", "nc"
561};
562
563static const struct soc_enum tas5086_dapm_input_mux_enum[] = {
564 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts),
565 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts),
566 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts),
567 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8, 8, tas5086_dapm_sdin_texts),
568 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts),
569 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0, 8, tas5086_dapm_sdin_texts),
570};
571
572static const struct snd_kcontrol_new tas5086_dapm_input_mux_controls[] = {
573 SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
574 SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
575 SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
576 SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
577 SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
578 SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]),
579};
580
581/* Output mux controls */
582static const char *tas5086_dapm_channel_texts[] =
583 { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux",
584 "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" };
585
586static const struct soc_enum tas5086_dapm_output_mux_enum[] = {
587 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 20, 6, tas5086_dapm_channel_texts),
588 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 16, 6, tas5086_dapm_channel_texts),
589 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 12, 6, tas5086_dapm_channel_texts),
590 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8, 6, tas5086_dapm_channel_texts),
591 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4, 6, tas5086_dapm_channel_texts),
592 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 0, 6, tas5086_dapm_channel_texts),
593};
594
595static const struct snd_kcontrol_new tas5086_dapm_output_mux_controls[] = {
596 SOC_DAPM_ENUM("PWM1 Output", tas5086_dapm_output_mux_enum[0]),
597 SOC_DAPM_ENUM("PWM2 Output", tas5086_dapm_output_mux_enum[1]),
598 SOC_DAPM_ENUM("PWM3 Output", tas5086_dapm_output_mux_enum[2]),
599 SOC_DAPM_ENUM("PWM4 Output", tas5086_dapm_output_mux_enum[3]),
600 SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]),
601 SOC_DAPM_ENUM("PWM6 Output", tas5086_dapm_output_mux_enum[5]),
602};
603
604static const struct snd_soc_dapm_widget tas5086_dapm_widgets[] = {
605 SND_SOC_DAPM_INPUT("SDIN1-L"),
606 SND_SOC_DAPM_INPUT("SDIN1-R"),
607 SND_SOC_DAPM_INPUT("SDIN2-L"),
608 SND_SOC_DAPM_INPUT("SDIN2-R"),
609 SND_SOC_DAPM_INPUT("SDIN3-L"),
610 SND_SOC_DAPM_INPUT("SDIN3-R"),
611 SND_SOC_DAPM_INPUT("SDIN4-L"),
612 SND_SOC_DAPM_INPUT("SDIN4-R"),
613
614 SND_SOC_DAPM_OUTPUT("PWM1"),
615 SND_SOC_DAPM_OUTPUT("PWM2"),
616 SND_SOC_DAPM_OUTPUT("PWM3"),
617 SND_SOC_DAPM_OUTPUT("PWM4"),
618 SND_SOC_DAPM_OUTPUT("PWM5"),
619 SND_SOC_DAPM_OUTPUT("PWM6"),
620
621 SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0,
622 &tas5086_dapm_input_mux_controls[0]),
623 SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0,
624 &tas5086_dapm_input_mux_controls[1]),
625 SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0,
626 &tas5086_dapm_input_mux_controls[2]),
627 SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0,
628 &tas5086_dapm_input_mux_controls[3]),
629 SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0,
630 &tas5086_dapm_input_mux_controls[4]),
631 SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0,
632 &tas5086_dapm_input_mux_controls[5]),
633
634 SND_SOC_DAPM_MUX("PWM1 Mux", SND_SOC_NOPM, 0, 0,
635 &tas5086_dapm_output_mux_controls[0]),
636 SND_SOC_DAPM_MUX("PWM2 Mux", SND_SOC_NOPM, 0, 0,
637 &tas5086_dapm_output_mux_controls[1]),
638 SND_SOC_DAPM_MUX("PWM3 Mux", SND_SOC_NOPM, 0, 0,
639 &tas5086_dapm_output_mux_controls[2]),
640 SND_SOC_DAPM_MUX("PWM4 Mux", SND_SOC_NOPM, 0, 0,
641 &tas5086_dapm_output_mux_controls[3]),
642 SND_SOC_DAPM_MUX("PWM5 Mux", SND_SOC_NOPM, 0, 0,
643 &tas5086_dapm_output_mux_controls[4]),
644 SND_SOC_DAPM_MUX("PWM6 Mux", SND_SOC_NOPM, 0, 0,
645 &tas5086_dapm_output_mux_controls[5]),
646};
647
648static const struct snd_soc_dapm_route tas5086_dapm_routes[] = {
649 /* SDIN inputs -> channel muxes */
650 { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" },
651 { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" },
652 { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" },
653 { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" },
654 { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" },
655 { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" },
656
657 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
658 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
659 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
660 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
661 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
662 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
663
664 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
665 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
666 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
667 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
668 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
669 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
670
671 { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" },
672 { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" },
673 { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" },
674 { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" },
675 { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" },
676 { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" },
677
678 { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" },
679 { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" },
680 { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" },
681 { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" },
682 { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" },
683 { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" },
684
685 { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" },
686 { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" },
687 { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" },
688 { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" },
689 { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" },
690 { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" },
691
692 { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" },
693 { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" },
694 { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" },
695 { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" },
696 { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" },
697 { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" },
698
699 /* Channel muxes -> PWM muxes */
700 { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" },
701 { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" },
702 { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" },
703 { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" },
704 { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" },
705 { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" },
706
707 { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" },
708 { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" },
709 { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" },
710 { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" },
711 { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" },
712 { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" },
713
714 { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" },
715 { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" },
716 { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" },
717 { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" },
718 { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" },
719 { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" },
720
721 { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" },
722 { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" },
723 { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" },
724 { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" },
725 { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" },
726 { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" },
727
728 { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" },
729 { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" },
730 { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" },
731 { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" },
732 { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" },
733 { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" },
734
735 { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" },
736 { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" },
737 { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" },
738 { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" },
739 { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" },
740 { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" },
741
742 /* The PWM muxes are directly connected to the PWM outputs */
743 { "PWM1", NULL, "PWM1 Mux" },
744 { "PWM2", NULL, "PWM2 Mux" },
745 { "PWM3", NULL, "PWM3 Mux" },
746 { "PWM4", NULL, "PWM4 Mux" },
747 { "PWM5", NULL, "PWM5 Mux" },
748 { "PWM6", NULL, "PWM6 Mux" },
749
750};
751
4fa89346
DM		 752static const struct snd_soc_dai_ops tas5086_dai_ops = {
753 .hw_params = tas5086_hw_params,
754 .set_sysclk = tas5086_set_dai_sysclk,
755 .set_fmt = tas5086_set_dai_fmt,
756 .mute_stream = tas5086_mute_stream,
757};
758
759static struct snd_soc_dai_driver tas5086_dai = {
760 .name = "tas5086-hifi",
761 .playback = {
762 .stream_name = "Playback",
763 .channels_min = 2,
764 .channels_max = 6,
765 .rates = TAS5086_PCM_RATES,
766 .formats = TAS5086_PCM_FORMATS,
767 },
768 .ops = &tas5086_dai_ops,
769};
770
771#ifdef CONFIG_PM
25c84cc1
DM		 772static int tas5086_soc_suspend(struct snd_soc_codec *codec)
773{
774 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
775 int ret;
776
777 /* Shut down all channels */
778 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x60);
779 if (ret < 0)
780 return ret;
781
c46af312
DM		 782 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
783
25c84cc1
DM		 784 return 0;
785}
786
4fa89346
DM		 787static int tas5086_soc_resume(struct snd_soc_codec *codec)
788{
789 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
25c84cc1
DM		 790 int ret;
791
c46af312
DM		 792 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
793 if (ret < 0)
794 return ret;
795
25c84cc1
DM		 796 tas5086_reset(priv);
797 regcache_mark_dirty(priv->regmap);
798
799 ret = tas5086_init(codec->dev, priv);
800 if (ret < 0)
801 return ret;
4fa89346 802
25c84cc1
DM		 803 ret = regcache_sync(priv->regmap);
804 if (ret < 0)
805 return ret;
4fa89346 806
25c84cc1 807 return 0;
4fa89346
DM		 808}
809#else
25c84cc1 810#define tas5086_soc_suspend NULL
4fa89346
DM		 811#define tas5086_soc_resume NULL
812#endif /* CONFIG_PM */
813
814#ifdef CONFIG_OF
815static const struct of_device_id tas5086_dt_ids[] = {
816 { .compatible = "ti,tas5086", },
817 { }
818};
819MODULE_DEVICE_TABLE(of, tas5086_dt_ids);
820#endif
821
4fa89346
DM		 822static int tas5086_probe(struct snd_soc_codec *codec)
823{
824 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
4fa89346
DM		 825 int i, ret;
826
c46af312
DM		 827 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
828 if (ret < 0) {
829 dev_err(codec->dev, "Failed to enable regulators: %d\n", ret);
830 return ret;
831 }
832
648c5382
DM		 833 priv->pwm_start_mid_z = 0;
834 priv->charge_period = 1300000; /* hardware default is 1300 ms */
835
4fa89346
DM		 836 if (of_match_device(of_match_ptr(tas5086_dt_ids), codec->dev)) {
837 struct device_node *of_node = codec->dev->of_node;
d5fd3ccc 838
648c5382
DM		 839 of_property_read_u32(of_node, "ti,charge-period",
840 &priv->charge_period);
79b23b56
DM		 841
842 for (i = 0; i < 6; i++) {
843 char name[25];
844
845 snprintf(name, sizeof(name),
846 "ti,mid-z-channel-%d", i + 1);
847
848 if (of_get_property(of_node, name, NULL) != NULL)
648c5382 849 priv->pwm_start_mid_z |= 1 << i;
79b23b56 850 }
4fa89346
DM		 851 }
852
c46af312 853 tas5086_reset(priv);
d5fd3ccc 854 ret = tas5086_init(codec->dev, priv);
4fa89346 855 if (ret < 0)
c46af312 856 goto exit_disable_regulators;
4fa89346
DM		 857
858 /* set master volume to 0 dB */
859 ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30);
860 if (ret < 0)
c46af312 861 goto exit_disable_regulators;
4fa89346 862
4fa89346 863 return 0;
c46af312
DM		 864
865exit_disable_regulators:
866 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
867
868 return ret;
4fa89346
DM		 869}
870
871static int tas5086_remove(struct snd_soc_codec *codec)
872{
873 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
874
875 if (gpio_is_valid(priv->gpio_nreset))
876 /* Set codec to the reset state */
877 gpio_set_value(priv->gpio_nreset, 0);
878
c46af312
DM		 879 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
880
4fa89346
DM		 881 return 0;
882};
883
884static struct snd_soc_codec_driver soc_codec_dev_tas5086 = {
885 .probe = tas5086_probe,
886 .remove = tas5086_remove,
25c84cc1 887 .suspend = tas5086_soc_suspend,
4fa89346
DM		 888 .resume = tas5086_soc_resume,
889 .controls = tas5086_controls,
890 .num_controls = ARRAY_SIZE(tas5086_controls),
18710acd
DM		 891 .dapm_widgets = tas5086_dapm_widgets,
892 .num_dapm_widgets = ARRAY_SIZE(tas5086_dapm_widgets),
893 .dapm_routes = tas5086_dapm_routes,
894 .num_dapm_routes = ARRAY_SIZE(tas5086_dapm_routes),
4fa89346
DM		 895};
896
897static const struct i2c_device_id tas5086_i2c_id[] = {
898 { "tas5086", 0 },
899 { }
900};
901MODULE_DEVICE_TABLE(i2c, tas5086_i2c_id);
902
903static const struct regmap_config tas5086_regmap = {
904 .reg_bits = 8,
8892d479
DM		 905 .val_bits = 32,
906 .max_register = TAS5086_MAX_REGISTER,
4fa89346
DM		 907 .reg_defaults = tas5086_reg_defaults,
908 .num_reg_defaults = ARRAY_SIZE(tas5086_reg_defaults),
909 .cache_type = REGCACHE_RBTREE,
910 .volatile_reg = tas5086_volatile_reg,
911 .writeable_reg = tas5086_writeable_reg,
912 .readable_reg = tas5086_accessible_reg,
6b36d370
DM		 913 .reg_read = tas5086_reg_read,
914 .reg_write = tas5086_reg_write,
4fa89346
DM		 915};
916
917static int tas5086_i2c_probe(struct i2c_client *i2c,
918 const struct i2c_device_id *id)
919{
920 struct tas5086_private *priv;
921 struct device *dev = &i2c->dev;
922 int gpio_nreset = -EINVAL;
923 int i, ret;
924
925 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
926 if (!priv)
927 return -ENOMEM;
928
c46af312
DM		 929 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
930 priv->supplies[i].supply = supply_names[i];
931
932 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
933 priv->supplies);
934 if (ret < 0) {
935 dev_err(dev, "Failed to get regulators: %d\n", ret);
936 return ret;
937 }
938
6b36d370 939 priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap);
4fa89346
DM		 940 if (IS_ERR(priv->regmap)) {
941 ret = PTR_ERR(priv->regmap);
942 dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret);
943 return ret;
944 }
945
946 i2c_set_clientdata(i2c, priv);
947
948 if (of_match_device(of_match_ptr(tas5086_dt_ids), dev)) {
949 struct device_node *of_node = dev->of_node;
950 gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0);
951 }
952
953 if (gpio_is_valid(gpio_nreset))
954 if (devm_gpio_request(dev, gpio_nreset, "TAS5086 Reset"))
955 gpio_nreset = -EINVAL;
956
4fa89346 957 priv->gpio_nreset = gpio_nreset;
c46af312
DM		 958
959 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
960 if (ret < 0) {
961 dev_err(dev, "Failed to enable regulators: %d\n", ret);
962 return ret;
963 }
964
d5fd3ccc 965 tas5086_reset(priv);
4fa89346
DM		 966
967 /* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */
968 ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i);
c46af312 969 if (ret == 0 && i != 0x3) {
4fa89346
DM		 970 dev_err(dev,
971 "Failed to identify TAS5086 codec (got %02x)\n", i);
c46af312 972 ret = -ENODEV;
4fa89346
DM		 973 }
974
c46af312
DM		 975 /*
976 * The chip has been identified, so we can turn off the power
977 * again until the dai link is set up.
978 */
979 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
980
981 if (ret == 0)
982 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tas5086,
983 &tas5086_dai, 1);
984
985 return ret;
4fa89346
DM		 986}
987
988static int tas5086_i2c_remove(struct i2c_client *i2c)
989{
990 snd_soc_unregister_codec(&i2c->dev);
991 return 0;
992}
993
994static struct i2c_driver tas5086_i2c_driver = {
995 .driver = {
996 .name = "tas5086",
997 .owner = THIS_MODULE,
998 .of_match_table = of_match_ptr(tas5086_dt_ids),
999 },
1000 .id_table = tas5086_i2c_id,
1001 .probe = tas5086_i2c_probe,
1002 .remove = tas5086_i2c_remove,
1003};
1004
c300d6de 1005module_i2c_driver(tas5086_i2c_driver);
4fa89346
DM		 1006
1007MODULE_AUTHOR("Daniel Mack <zonque@gmail.com>");
1008MODULE_DESCRIPTION("Texas Instruments TAS5086 ALSA SoC Codec Driver");
1009MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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