Commit | Line | Data |
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d8e3bb73 GL |
1 | /* |
2 | * Texas Instruments TLV320AIC26 low power audio CODEC | |
3 | * ALSA SoC CODEC driver | |
4 | * | |
5 | * Copyright (C) 2008 Secret Lab Technologies Ltd. | |
6 | */ | |
7 | ||
8 | #include <linux/module.h> | |
9 | #include <linux/moduleparam.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/pm.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/sysfs.h> | |
15 | #include <linux/spi/spi.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
d8e3bb73 GL |
17 | #include <sound/core.h> |
18 | #include <sound/pcm.h> | |
19 | #include <sound/pcm_params.h> | |
20 | #include <sound/soc.h> | |
d8e3bb73 GL |
21 | #include <sound/initval.h> |
22 | ||
23 | #include "tlv320aic26.h" | |
24 | ||
25 | MODULE_DESCRIPTION("ASoC TLV320AIC26 codec driver"); | |
26 | MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); | |
27 | MODULE_LICENSE("GPL"); | |
28 | ||
29 | /* AIC26 driver private data */ | |
30 | struct aic26 { | |
31 | struct spi_device *spi; | |
32 | struct snd_soc_codec codec; | |
d8e3bb73 GL |
33 | int master; |
34 | int datfm; | |
35 | int mclk; | |
36 | ||
37 | /* Keyclick parameters */ | |
38 | int keyclick_amplitude; | |
39 | int keyclick_freq; | |
40 | int keyclick_len; | |
41 | }; | |
42 | ||
43 | /* --------------------------------------------------------------------- | |
44 | * Register access routines | |
45 | */ | |
46 | static unsigned int aic26_reg_read(struct snd_soc_codec *codec, | |
47 | unsigned int reg) | |
48 | { | |
d4a8ca24 | 49 | struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec); |
d8e3bb73 GL |
50 | u16 *cache = codec->reg_cache; |
51 | u16 cmd, value; | |
52 | u8 buffer[2]; | |
53 | int rc; | |
54 | ||
55 | if (reg >= AIC26_NUM_REGS) { | |
56 | WARN_ON_ONCE(1); | |
57 | return 0; | |
58 | } | |
59 | ||
60 | /* Do SPI transfer; first 16bits are command; remaining is | |
61 | * register contents */ | |
62 | cmd = AIC26_READ_COMMAND_WORD(reg); | |
63 | buffer[0] = (cmd >> 8) & 0xff; | |
64 | buffer[1] = cmd & 0xff; | |
65 | rc = spi_write_then_read(aic26->spi, buffer, 2, buffer, 2); | |
66 | if (rc) { | |
67 | dev_err(&aic26->spi->dev, "AIC26 reg read error\n"); | |
68 | return -EIO; | |
69 | } | |
70 | value = (buffer[0] << 8) | buffer[1]; | |
71 | ||
72 | /* Update the cache before returning with the value */ | |
73 | cache[reg] = value; | |
74 | return value; | |
75 | } | |
76 | ||
77 | static unsigned int aic26_reg_read_cache(struct snd_soc_codec *codec, | |
78 | unsigned int reg) | |
79 | { | |
80 | u16 *cache = codec->reg_cache; | |
81 | ||
82 | if (reg >= AIC26_NUM_REGS) { | |
83 | WARN_ON_ONCE(1); | |
84 | return 0; | |
85 | } | |
86 | ||
87 | return cache[reg]; | |
88 | } | |
89 | ||
90 | static int aic26_reg_write(struct snd_soc_codec *codec, unsigned int reg, | |
91 | unsigned int value) | |
92 | { | |
d4a8ca24 | 93 | struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec); |
d8e3bb73 GL |
94 | u16 *cache = codec->reg_cache; |
95 | u16 cmd; | |
96 | u8 buffer[4]; | |
97 | int rc; | |
98 | ||
99 | if (reg >= AIC26_NUM_REGS) { | |
100 | WARN_ON_ONCE(1); | |
101 | return -EINVAL; | |
102 | } | |
103 | ||
104 | /* Do SPI transfer; first 16bits are command; remaining is data | |
105 | * to write into register */ | |
106 | cmd = AIC26_WRITE_COMMAND_WORD(reg); | |
107 | buffer[0] = (cmd >> 8) & 0xff; | |
108 | buffer[1] = cmd & 0xff; | |
109 | buffer[2] = value >> 8; | |
110 | buffer[3] = value; | |
111 | rc = spi_write(aic26->spi, buffer, 4); | |
112 | if (rc) { | |
113 | dev_err(&aic26->spi->dev, "AIC26 reg read error\n"); | |
114 | return -EIO; | |
115 | } | |
116 | ||
117 | /* update cache before returning */ | |
118 | cache[reg] = value; | |
119 | return 0; | |
120 | } | |
121 | ||
122 | /* --------------------------------------------------------------------- | |
123 | * Digital Audio Interface Operations | |
124 | */ | |
125 | static int aic26_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
126 | struct snd_pcm_hw_params *params, |
127 | struct snd_soc_dai *dai) | |
d8e3bb73 GL |
128 | { |
129 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 130 | struct snd_soc_codec *codec = rtd->codec; |
d4a8ca24 | 131 | struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec); |
d8e3bb73 GL |
132 | int fsref, divisor, wlen, pval, jval, dval, qval; |
133 | u16 reg; | |
134 | ||
135 | dev_dbg(&aic26->spi->dev, "aic26_hw_params(substream=%p, params=%p)\n", | |
136 | substream, params); | |
137 | dev_dbg(&aic26->spi->dev, "rate=%i format=%i\n", params_rate(params), | |
138 | params_format(params)); | |
139 | ||
140 | switch (params_rate(params)) { | |
141 | case 8000: fsref = 48000; divisor = AIC26_DIV_6; break; | |
142 | case 11025: fsref = 44100; divisor = AIC26_DIV_4; break; | |
143 | case 12000: fsref = 48000; divisor = AIC26_DIV_4; break; | |
144 | case 16000: fsref = 48000; divisor = AIC26_DIV_3; break; | |
145 | case 22050: fsref = 44100; divisor = AIC26_DIV_2; break; | |
146 | case 24000: fsref = 48000; divisor = AIC26_DIV_2; break; | |
147 | case 32000: fsref = 48000; divisor = AIC26_DIV_1_5; break; | |
148 | case 44100: fsref = 44100; divisor = AIC26_DIV_1; break; | |
149 | case 48000: fsref = 48000; divisor = AIC26_DIV_1; break; | |
150 | default: | |
151 | dev_dbg(&aic26->spi->dev, "bad rate\n"); return -EINVAL; | |
152 | } | |
153 | ||
154 | /* select data word length */ | |
155 | switch (params_format(params)) { | |
156 | case SNDRV_PCM_FORMAT_S8: wlen = AIC26_WLEN_16; break; | |
157 | case SNDRV_PCM_FORMAT_S16_BE: wlen = AIC26_WLEN_16; break; | |
158 | case SNDRV_PCM_FORMAT_S24_BE: wlen = AIC26_WLEN_24; break; | |
159 | case SNDRV_PCM_FORMAT_S32_BE: wlen = AIC26_WLEN_32; break; | |
160 | default: | |
161 | dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL; | |
162 | } | |
163 | ||
2aba76f0 MW |
164 | /** |
165 | * Configure PLL | |
166 | * fsref = (mclk * PLLM) / 2048 | |
167 | * where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal) | |
168 | */ | |
d8e3bb73 | 169 | pval = 1; |
2aba76f0 MW |
170 | /* compute J portion of multiplier */ |
171 | jval = fsref / (aic26->mclk / 2048); | |
172 | /* compute fractional DDDD component of multiplier */ | |
173 | dval = fsref - (jval * (aic26->mclk / 2048)); | |
174 | dval = (10000 * dval) / (aic26->mclk / 2048); | |
175 | dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval); | |
d8e3bb73 GL |
176 | qval = 0; |
177 | reg = 0x8000 | qval << 11 | pval << 8 | jval << 2; | |
178 | aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg); | |
179 | reg = dval << 2; | |
180 | aic26_reg_write(codec, AIC26_REG_PLL_PROG2, reg); | |
181 | ||
182 | /* Audio Control 3 (master mode, fsref rate) */ | |
183 | reg = aic26_reg_read_cache(codec, AIC26_REG_AUDIO_CTRL3); | |
184 | reg &= ~0xf800; | |
185 | if (aic26->master) | |
186 | reg |= 0x0800; | |
187 | if (fsref == 48000) | |
188 | reg |= 0x2000; | |
189 | aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg); | |
190 | ||
191 | /* Audio Control 1 (FSref divisor) */ | |
192 | reg = aic26_reg_read_cache(codec, AIC26_REG_AUDIO_CTRL1); | |
193 | reg &= ~0x0fff; | |
194 | reg |= wlen | aic26->datfm | (divisor << 3) | divisor; | |
195 | aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL1, reg); | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | /** | |
201 | * aic26_mute - Mute control to reduce noise when changing audio format | |
202 | */ | |
203 | static int aic26_mute(struct snd_soc_dai *dai, int mute) | |
204 | { | |
205 | struct snd_soc_codec *codec = dai->codec; | |
d4a8ca24 | 206 | struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec); |
d8e3bb73 GL |
207 | u16 reg = aic26_reg_read_cache(codec, AIC26_REG_DAC_GAIN); |
208 | ||
209 | dev_dbg(&aic26->spi->dev, "aic26_mute(dai=%p, mute=%i)\n", | |
210 | dai, mute); | |
211 | ||
212 | if (mute) | |
213 | reg |= 0x8080; | |
214 | else | |
215 | reg &= ~0x8080; | |
216 | aic26_reg_write(codec, AIC26_REG_DAC_GAIN, reg); | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | static int aic26_set_sysclk(struct snd_soc_dai *codec_dai, | |
222 | int clk_id, unsigned int freq, int dir) | |
223 | { | |
224 | struct snd_soc_codec *codec = codec_dai->codec; | |
d4a8ca24 | 225 | struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec); |
d8e3bb73 GL |
226 | |
227 | dev_dbg(&aic26->spi->dev, "aic26_set_sysclk(dai=%p, clk_id==%i," | |
228 | " freq=%i, dir=%i)\n", | |
229 | codec_dai, clk_id, freq, dir); | |
230 | ||
231 | /* MCLK needs to fall between 2MHz and 50 MHz */ | |
232 | if ((freq < 2000000) || (freq > 50000000)) | |
233 | return -EINVAL; | |
234 | ||
235 | aic26->mclk = freq; | |
236 | return 0; | |
237 | } | |
238 | ||
239 | static int aic26_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
240 | { | |
241 | struct snd_soc_codec *codec = codec_dai->codec; | |
d4a8ca24 | 242 | struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec); |
d8e3bb73 GL |
243 | |
244 | dev_dbg(&aic26->spi->dev, "aic26_set_fmt(dai=%p, fmt==%i)\n", | |
245 | codec_dai, fmt); | |
246 | ||
247 | /* set master/slave audio interface */ | |
248 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
249 | case SND_SOC_DAIFMT_CBM_CFM: aic26->master = 1; break; | |
250 | case SND_SOC_DAIFMT_CBS_CFS: aic26->master = 0; break; | |
251 | default: | |
252 | dev_dbg(&aic26->spi->dev, "bad master\n"); return -EINVAL; | |
253 | } | |
254 | ||
255 | /* interface format */ | |
256 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
257 | case SND_SOC_DAIFMT_I2S: aic26->datfm = AIC26_DATFM_I2S; break; | |
258 | case SND_SOC_DAIFMT_DSP_A: aic26->datfm = AIC26_DATFM_DSP; break; | |
259 | case SND_SOC_DAIFMT_RIGHT_J: aic26->datfm = AIC26_DATFM_RIGHTJ; break; | |
260 | case SND_SOC_DAIFMT_LEFT_J: aic26->datfm = AIC26_DATFM_LEFTJ; break; | |
261 | default: | |
262 | dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL; | |
263 | } | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
268 | /* --------------------------------------------------------------------- | |
269 | * Digital Audio Interface Definition | |
270 | */ | |
271 | #define AIC26_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ | |
272 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ | |
273 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ | |
274 | SNDRV_PCM_RATE_48000) | |
275 | #define AIC26_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |\ | |
276 | SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE) | |
277 | ||
85e7652d | 278 | static const struct snd_soc_dai_ops aic26_dai_ops = { |
6335d055 EM |
279 | .hw_params = aic26_hw_params, |
280 | .digital_mute = aic26_mute, | |
281 | .set_sysclk = aic26_set_sysclk, | |
282 | .set_fmt = aic26_set_fmt, | |
283 | }; | |
284 | ||
f0fba2ad LG |
285 | static struct snd_soc_dai_driver aic26_dai = { |
286 | .name = "tlv320aic26-hifi", | |
d8e3bb73 GL |
287 | .playback = { |
288 | .stream_name = "Playback", | |
289 | .channels_min = 2, | |
290 | .channels_max = 2, | |
291 | .rates = AIC26_RATES, | |
292 | .formats = AIC26_FORMATS, | |
293 | }, | |
294 | .capture = { | |
295 | .stream_name = "Capture", | |
296 | .channels_min = 2, | |
297 | .channels_max = 2, | |
298 | .rates = AIC26_RATES, | |
299 | .formats = AIC26_FORMATS, | |
300 | }, | |
6335d055 | 301 | .ops = &aic26_dai_ops, |
d8e3bb73 | 302 | }; |
d8e3bb73 GL |
303 | |
304 | /* --------------------------------------------------------------------- | |
305 | * ALSA controls | |
306 | */ | |
307 | static const char *aic26_capture_src_text[] = {"Mic", "Aux"}; | |
308 | static const struct soc_enum aic26_capture_src_enum = | |
309 | SOC_ENUM_SINGLE(AIC26_REG_AUDIO_CTRL1, 12, 2, aic26_capture_src_text); | |
310 | ||
311 | static const struct snd_kcontrol_new aic26_snd_controls[] = { | |
312 | /* Output */ | |
313 | SOC_DOUBLE("PCM Playback Volume", AIC26_REG_DAC_GAIN, 8, 0, 0x7f, 1), | |
314 | SOC_DOUBLE("PCM Playback Switch", AIC26_REG_DAC_GAIN, 15, 7, 1, 1), | |
315 | SOC_SINGLE("PCM Capture Volume", AIC26_REG_ADC_GAIN, 8, 0x7f, 0), | |
316 | SOC_SINGLE("PCM Capture Mute", AIC26_REG_ADC_GAIN, 15, 1, 1), | |
317 | SOC_SINGLE("Keyclick activate", AIC26_REG_AUDIO_CTRL2, 15, 0x1, 0), | |
318 | SOC_SINGLE("Keyclick amplitude", AIC26_REG_AUDIO_CTRL2, 12, 0x7, 0), | |
319 | SOC_SINGLE("Keyclick frequency", AIC26_REG_AUDIO_CTRL2, 8, 0x7, 0), | |
320 | SOC_SINGLE("Keyclick period", AIC26_REG_AUDIO_CTRL2, 4, 0xf, 0), | |
321 | SOC_ENUM("Capture Source", aic26_capture_src_enum), | |
322 | }; | |
323 | ||
d8e3bb73 GL |
324 | /* --------------------------------------------------------------------- |
325 | * SPI device portion of driver: sysfs files for debugging | |
326 | */ | |
327 | ||
328 | static ssize_t aic26_keyclick_show(struct device *dev, | |
329 | struct device_attribute *attr, char *buf) | |
330 | { | |
331 | struct aic26 *aic26 = dev_get_drvdata(dev); | |
332 | int val, amp, freq, len; | |
333 | ||
334 | val = aic26_reg_read_cache(&aic26->codec, AIC26_REG_AUDIO_CTRL2); | |
335 | amp = (val >> 12) & 0x7; | |
336 | freq = (125 << ((val >> 8) & 0x7)) >> 1; | |
337 | len = 2 * (1 + ((val >> 4) & 0xf)); | |
338 | ||
339 | return sprintf(buf, "amp=%x freq=%iHz len=%iclks\n", amp, freq, len); | |
340 | } | |
341 | ||
342 | /* Any write to the keyclick attribute will trigger the keyclick event */ | |
343 | static ssize_t aic26_keyclick_set(struct device *dev, | |
344 | struct device_attribute *attr, | |
345 | const char *buf, size_t count) | |
346 | { | |
347 | struct aic26 *aic26 = dev_get_drvdata(dev); | |
348 | int val; | |
349 | ||
350 | val = aic26_reg_read_cache(&aic26->codec, AIC26_REG_AUDIO_CTRL2); | |
351 | val |= 0x8000; | |
352 | aic26_reg_write(&aic26->codec, AIC26_REG_AUDIO_CTRL2, val); | |
353 | ||
354 | return count; | |
355 | } | |
356 | ||
9cce39a1 | 357 | static DEVICE_ATTR(keyclick, 0644, aic26_keyclick_show, aic26_keyclick_set); |
d8e3bb73 GL |
358 | |
359 | /* --------------------------------------------------------------------- | |
f0fba2ad | 360 | * SoC CODEC portion of driver: probe and release routines |
d8e3bb73 | 361 | */ |
f0fba2ad | 362 | static int aic26_probe(struct snd_soc_codec *codec) |
d8e3bb73 | 363 | { |
f0fba2ad | 364 | int ret, err, i, reg; |
d8e3bb73 | 365 | |
f0fba2ad | 366 | dev_info(codec->dev, "Probing AIC26 SoC CODEC driver\n"); |
64089b84 | 367 | |
d8e3bb73 | 368 | /* Reset the codec to power on defaults */ |
f0fba2ad | 369 | aic26_reg_write(codec, AIC26_REG_RESET, 0xBB00); |
d8e3bb73 GL |
370 | |
371 | /* Power up CODEC */ | |
f0fba2ad | 372 | aic26_reg_write(codec, AIC26_REG_POWER_CTRL, 0); |
d8e3bb73 GL |
373 | |
374 | /* Audio Control 3 (master mode, fsref rate) */ | |
f0fba2ad | 375 | reg = aic26_reg_read(codec, AIC26_REG_AUDIO_CTRL3); |
d8e3bb73 GL |
376 | reg &= ~0xf800; |
377 | reg |= 0x0800; /* set master mode */ | |
f0fba2ad | 378 | aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg); |
d8e3bb73 GL |
379 | |
380 | /* Fill register cache */ | |
839d271c | 381 | for (i = 0; i < codec->driver->reg_cache_size; i++) |
f0fba2ad | 382 | aic26_reg_read(codec, i); |
d8e3bb73 GL |
383 | |
384 | /* Register the sysfs files for debugging */ | |
385 | /* Create SysFS files */ | |
f0fba2ad | 386 | ret = device_create_file(codec->dev, &dev_attr_keyclick); |
64089b84 | 387 | if (ret) |
f0fba2ad | 388 | dev_info(codec->dev, "error creating sysfs files\n"); |
d8e3bb73 | 389 | |
f0fba2ad LG |
390 | /* register controls */ |
391 | dev_dbg(codec->dev, "Registering controls\n"); | |
392 | err = snd_soc_add_controls(codec, aic26_snd_controls, | |
393 | ARRAY_SIZE(aic26_snd_controls)); | |
394 | WARN_ON(err < 0); | |
d8e3bb73 | 395 | |
d8e3bb73 GL |
396 | return 0; |
397 | } | |
398 | ||
f0fba2ad LG |
399 | static struct snd_soc_codec_driver aic26_soc_codec_dev = { |
400 | .probe = aic26_probe, | |
401 | .read = aic26_reg_read, | |
402 | .write = aic26_reg_write, | |
403 | .reg_cache_size = AIC26_NUM_REGS, | |
404 | .reg_word_size = sizeof(u16), | |
405 | }; | |
406 | ||
407 | /* --------------------------------------------------------------------- | |
408 | * SPI device portion of driver: probe and release routines and SPI | |
409 | * driver registration. | |
410 | */ | |
411 | static int aic26_spi_probe(struct spi_device *spi) | |
d8e3bb73 | 412 | { |
f0fba2ad LG |
413 | struct aic26 *aic26; |
414 | int ret; | |
d8e3bb73 | 415 | |
f0fba2ad LG |
416 | dev_dbg(&spi->dev, "probing tlv320aic26 spi device\n"); |
417 | ||
418 | /* Allocate driver data */ | |
a8163023 | 419 | aic26 = devm_kzalloc(&spi->dev, sizeof *aic26, GFP_KERNEL); |
f0fba2ad LG |
420 | if (!aic26) |
421 | return -ENOMEM; | |
d8e3bb73 | 422 | |
f0fba2ad LG |
423 | /* Initialize the driver data */ |
424 | aic26->spi = spi; | |
425 | dev_set_drvdata(&spi->dev, aic26); | |
426 | aic26->master = 1; | |
427 | ||
428 | ret = snd_soc_register_codec(&spi->dev, | |
429 | &aic26_soc_codec_dev, &aic26_dai, 1); | |
f0fba2ad | 430 | return ret; |
f0fba2ad LG |
431 | } |
432 | ||
433 | static int aic26_spi_remove(struct spi_device *spi) | |
434 | { | |
435 | snd_soc_unregister_codec(&spi->dev); | |
d8e3bb73 GL |
436 | return 0; |
437 | } | |
438 | ||
439 | static struct spi_driver aic26_spi = { | |
440 | .driver = { | |
f0fba2ad | 441 | .name = "tlv320aic26-codec", |
d8e3bb73 GL |
442 | .owner = THIS_MODULE, |
443 | }, | |
444 | .probe = aic26_spi_probe, | |
445 | .remove = aic26_spi_remove, | |
446 | }; | |
447 | ||
448 | static int __init aic26_init(void) | |
449 | { | |
450 | return spi_register_driver(&aic26_spi); | |
451 | } | |
452 | module_init(aic26_init); | |
453 | ||
454 | static void __exit aic26_exit(void) | |
455 | { | |
456 | spi_unregister_driver(&aic26_spi); | |
457 | } | |
458 | module_exit(aic26_exit); |