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Linux 3.17-rc1
[deliverable/linux.git] / sound / soc / codecs / tlv320aic31xx.c
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e00447fa
JS		 1/*
2 * ALSA SoC TLV320AIC31XX codec driver
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc.
5 *
6 * Author: Jyri Sarha <jsarha@ti.com>
7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * THIS PACKAGE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 * The TLV320AIC31xx series of audio codec is a low-power, highly integrated
19 * high performance codec which provides a stereo DAC, a mono ADC,
20 * and mono/stereo Class-D speaker driver.
21 */
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/pm.h>
28#include <linux/i2c.h>
29#include <linux/gpio.h>
30#include <linux/regulator/consumer.h>
0faabc4f 31#include <linux/of.h>
e00447fa
JS		 32#include <linux/of_gpio.h>
33#include <linux/slab.h>
34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/initval.h>
39#include <sound/tlv.h>
40#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
41
42#include "tlv320aic31xx.h"
43
44static const struct reg_default aic31xx_reg_defaults[] = {
45 { AIC31XX_CLKMUX, 0x00 },
46 { AIC31XX_PLLPR, 0x11 },
47 { AIC31XX_PLLJ, 0x04 },
48 { AIC31XX_PLLDMSB, 0x00 },
49 { AIC31XX_PLLDLSB, 0x00 },
50 { AIC31XX_NDAC, 0x01 },
51 { AIC31XX_MDAC, 0x01 },
52 { AIC31XX_DOSRMSB, 0x00 },
53 { AIC31XX_DOSRLSB, 0x80 },
54 { AIC31XX_NADC, 0x01 },
55 { AIC31XX_MADC, 0x01 },
56 { AIC31XX_AOSR, 0x80 },
57 { AIC31XX_IFACE1, 0x00 },
58 { AIC31XX_DATA_OFFSET, 0x00 },
59 { AIC31XX_IFACE2, 0x00 },
60 { AIC31XX_BCLKN, 0x01 },
61 { AIC31XX_DACSETUP, 0x14 },
62 { AIC31XX_DACMUTE, 0x0c },
63 { AIC31XX_LDACVOL, 0x00 },
64 { AIC31XX_RDACVOL, 0x00 },
65 { AIC31XX_ADCSETUP, 0x00 },
66 { AIC31XX_ADCFGA, 0x80 },
67 { AIC31XX_ADCVOL, 0x00 },
68 { AIC31XX_HPDRIVER, 0x04 },
69 { AIC31XX_SPKAMP, 0x06 },
70 { AIC31XX_DACMIXERROUTE, 0x00 },
71 { AIC31XX_LANALOGHPL, 0x7f },
72 { AIC31XX_RANALOGHPR, 0x7f },
73 { AIC31XX_LANALOGSPL, 0x7f },
74 { AIC31XX_RANALOGSPR, 0x7f },
75 { AIC31XX_HPLGAIN, 0x02 },
76 { AIC31XX_HPRGAIN, 0x02 },
77 { AIC31XX_SPLGAIN, 0x00 },
78 { AIC31XX_SPRGAIN, 0x00 },
79 { AIC31XX_MICBIAS, 0x00 },
80 { AIC31XX_MICPGA, 0x80 },
81 { AIC31XX_MICPGAPI, 0x00 },
82 { AIC31XX_MICPGAMI, 0x00 },
83};
84
85static bool aic31xx_volatile(struct device *dev, unsigned int reg)
86{
87 switch (reg) {
88 case AIC31XX_PAGECTL: /* regmap implementation requires this */
89 case AIC31XX_RESET: /* always clears after write */
90 case AIC31XX_OT_FLAG:
91 case AIC31XX_ADCFLAG:
92 case AIC31XX_DACFLAG1:
93 case AIC31XX_DACFLAG2:
94 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
95 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
96 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
97 case AIC31XX_INTRDACFLAG2:
98 case AIC31XX_INTRADCFLAG2:
99 return true;
100 }
101 return false;
102}
103
104static bool aic31xx_writeable(struct device *dev, unsigned int reg)
105{
106 switch (reg) {
107 case AIC31XX_OT_FLAG:
108 case AIC31XX_ADCFLAG:
109 case AIC31XX_DACFLAG1:
110 case AIC31XX_DACFLAG2:
111 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
112 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
113 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
114 case AIC31XX_INTRDACFLAG2:
115 case AIC31XX_INTRADCFLAG2:
116 return false;
117 }
118 return true;
119}
120
121static const struct regmap_range_cfg aic31xx_ranges[] = {
122 {
123 .range_min = 0,
124 .range_max = 12 * 128,
125 .selector_reg = AIC31XX_PAGECTL,
126 .selector_mask = 0xff,
127 .selector_shift = 0,
128 .window_start = 0,
129 .window_len = 128,
130 },
131};
132
9296f4da 133static const struct regmap_config aic31xx_i2c_regmap = {
e00447fa
JS		 134 .reg_bits = 8,
135 .val_bits = 8,
136 .writeable_reg = aic31xx_writeable,
137 .volatile_reg = aic31xx_volatile,
138 .reg_defaults = aic31xx_reg_defaults,
139 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
140 .cache_type = REGCACHE_RBTREE,
141 .ranges = aic31xx_ranges,
142 .num_ranges = ARRAY_SIZE(aic31xx_ranges),
143 .max_register = 12 * 128,
144};
145
146#define AIC31XX_NUM_SUPPLIES 6
147static const char * const aic31xx_supply_names[AIC31XX_NUM_SUPPLIES] = {
148 "HPVDD",
149 "SPRVDD",
150 "SPLVDD",
151 "AVDD",
152 "IOVDD",
153 "DVDD",
154};
155
156struct aic31xx_disable_nb {
157 struct notifier_block nb;
158 struct aic31xx_priv *aic31xx;
159};
160
161struct aic31xx_priv {
162 struct snd_soc_codec *codec;
163 u8 i2c_regs_status;
164 struct device *dev;
165 struct regmap *regmap;
166 struct aic31xx_pdata pdata;
167 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
168 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
169 unsigned int sysclk;
170 int rate_div_line;
171};
172
173struct aic31xx_rate_divs {
174 u32 mclk;
175 u32 rate;
176 u8 p_val;
177 u8 pll_j;
178 u16 pll_d;
179 u16 dosr;
180 u8 ndac;
181 u8 mdac;
182 u8 aosr;
183 u8 nadc;
184 u8 madc;
185};
186
187/* ADC dividers can be disabled by cofiguring them to 0 */
188static const struct aic31xx_rate_divs aic31xx_divs[] = {
189 /* mclk rate pll: p j d dosr ndac mdac aors nadc madc */
190 /* 8k rate */
191 {12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
192 {24000000, 8000, 2, 8, 1920, 128, 48, 2, 128, 48, 2},
193 {25000000, 8000, 2, 7, 8643, 128, 48, 2, 128, 48, 2},
194 /* 11.025k rate */
195 {12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
196 {24000000, 11025, 2, 7, 5264, 128, 32, 2, 128, 32, 2},
197 {25000000, 11025, 2, 7, 2253, 128, 32, 2, 128, 32, 2},
198 /* 16k rate */
199 {12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
200 {24000000, 16000, 2, 8, 1920, 128, 24, 2, 128, 24, 2},
201 {25000000, 16000, 2, 7, 8643, 128, 24, 2, 128, 24, 2},
202 /* 22.05k rate */
203 {12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
204 {24000000, 22050, 2, 7, 5264, 128, 16, 2, 128, 16, 2},
205 {25000000, 22050, 2, 7, 2253, 128, 16, 2, 128, 16, 2},
206 /* 32k rate */
207 {12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
208 {24000000, 32000, 2, 8, 1920, 128, 12, 2, 128, 12, 2},
209 {25000000, 32000, 2, 7, 8643, 128, 12, 2, 128, 12, 2},
210 /* 44.1k rate */
211 {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
212 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 128, 8, 2},
213 {25000000, 44100, 2, 7, 2253, 128, 8, 2, 128, 8, 2},
214 /* 48k rate */
215 {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
216 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 128, 8, 2},
217 {25000000, 48000, 2, 7, 8643, 128, 8, 2, 128, 8, 2},
218 /* 88.2k rate */
219 {12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
220 {24000000, 88200, 2, 7, 5264, 64, 8, 2, 64, 8, 2},
221 {25000000, 88200, 2, 7, 2253, 64, 8, 2, 64, 8, 2},
222 /* 96k rate */
223 {12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
224 {24000000, 96000, 2, 8, 1920, 64, 8, 2, 64, 8, 2},
225 {25000000, 96000, 2, 7, 8643, 64, 8, 2, 64, 8, 2},
226 /* 176.4k rate */
227 {12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
228 {24000000, 176400, 2, 7, 5264, 32, 8, 2, 32, 8, 2},
229 {25000000, 176400, 2, 7, 2253, 32, 8, 2, 32, 8, 2},
230 /* 192k rate */
231 {12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
232 {24000000, 192000, 2, 8, 1920, 32, 8, 2, 32, 8, 2},
233 {25000000, 192000, 2, 7, 8643, 32, 8, 2, 32, 8, 2},
234};
235
236static const char * const ldac_in_text[] = {
237 "Off", "Left Data", "Right Data", "Mono"
238};
239
240static const char * const rdac_in_text[] = {
241 "Off", "Right Data", "Left Data", "Mono"
242};
243
244static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
245
246static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
247
248static const char * const mic_select_text[] = {
249 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
250};
251
914bc160
LPC		 252static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
253 mic_select_text);
254static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
255 mic_select_text);
256static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
257 mic_select_text);
e00447fa 258
914bc160
LPC		 259static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text);
260static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
261 mic_select_text);
e00447fa
JS		 262
263static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
264static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
265static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
266static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
267static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
268static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
269static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
270static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
271
272/*
273 * controls to be exported to the user space
274 */
275static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
276 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
277 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
278
279 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
280 adc_fgain_tlv),
281
282 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
283 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
284 0, -24, 40, 6, 0, adc_cgain_tlv),
285
286 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
287 119, 0, mic_pga_tlv),
288
289 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
290 AIC31XX_HPRGAIN, 2, 1, 0),
291 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
292 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
293
294 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
295 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
296};
297
298static const struct snd_kcontrol_new aic311x_snd_controls[] = {
299 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
300 AIC31XX_SPRGAIN, 2, 1, 0),
301 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
302 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
303
304 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
305 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
306};
307
308static const struct snd_kcontrol_new aic310x_snd_controls[] = {
309 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
310 2, 1, 0),
311 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
312 3, 3, 0, class_D_drv_tlv),
313
314 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
315 0, 0x7F, 1, sp_vol_tlv),
316};
317
318static const struct snd_kcontrol_new ldac_in_control =
319 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
320
321static const struct snd_kcontrol_new rdac_in_control =
322 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
323
9296f4da
MB		 324static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
325 unsigned int mask, unsigned int wbits, int sleep,
326 int count)
e00447fa
JS		 327{
328 unsigned int bits;
329 int counter = count;
330 int ret = regmap_read(aic31xx->regmap, reg, &bits);
423ca88e 331
e00447fa
JS		 332 while ((bits & mask) != wbits && counter && !ret) {
333 usleep_range(sleep, sleep * 2);
334 ret = regmap_read(aic31xx->regmap, reg, &bits);
335 counter--;
336 }
337 if ((bits & mask) != wbits) {
338 dev_err(aic31xx->dev,
339 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
340 __func__, reg, bits, wbits, ret, mask,
341 (count - counter) * sleep);
342 ret = -1;
343 }
344 return ret;
345}
346
347#define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
348
349static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
350 struct snd_kcontrol *kcontrol, int event)
351{
352 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(w->codec);
353 unsigned int reg = AIC31XX_DACFLAG1;
354 unsigned int mask;
355
356 switch (WIDGET_BIT(w->reg, w->shift)) {
357 case WIDGET_BIT(AIC31XX_DACSETUP, 7):
358 mask = AIC31XX_LDACPWRSTATUS_MASK;
359 break;
360 case WIDGET_BIT(AIC31XX_DACSETUP, 6):
361 mask = AIC31XX_RDACPWRSTATUS_MASK;
362 break;
363 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
364 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
365 break;
366 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
367 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
368 break;
369 case WIDGET_BIT(AIC31XX_SPKAMP, 7):
370 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
371 break;
372 case WIDGET_BIT(AIC31XX_SPKAMP, 6):
373 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
374 break;
375 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
376 mask = AIC31XX_ADCPWRSTATUS_MASK;
377 reg = AIC31XX_ADCFLAG;
378 break;
379 default:
2a1c23e3 380 dev_err(w->codec->dev, "Unknown widget '%s' calling %s\n",
e00447fa
JS		 381 w->name, __func__);
382 return -EINVAL;
383 }
384
385 switch (event) {
386 case SND_SOC_DAPM_POST_PMU:
387 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100);
388 case SND_SOC_DAPM_POST_PMD:
389 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100);
390 default:
391 dev_dbg(w->codec->dev,
392 "Unhandled dapm widget event %d from %s\n",
393 event, w->name);
394 }
395 return 0;
396}
397
398static const struct snd_kcontrol_new left_output_switches[] = {
399 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
400 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
401 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
402};
403
404static const struct snd_kcontrol_new right_output_switches[] = {
405 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
406 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
407};
408
409static const struct snd_kcontrol_new p_term_mic1lp =
410 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
411
412static const struct snd_kcontrol_new p_term_mic1rp =
413 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
414
415static const struct snd_kcontrol_new p_term_mic1lm =
416 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
417
418static const struct snd_kcontrol_new m_term_mic1lm =
419 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
420
421static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
422 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
423
424static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
425 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
426
427static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
428 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
429
430static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
431 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
432
433static int mic_bias_event(struct snd_soc_dapm_widget *w,
434 struct snd_kcontrol *kcontrol, int event)
435{
436 struct snd_soc_codec *codec = w->codec;
437 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
423ca88e 438
e00447fa
JS		 439 switch (event) {
440 case SND_SOC_DAPM_POST_PMU:
441 /* change mic bias voltage to user defined */
442 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
443 AIC31XX_MICBIAS_MASK,
444 aic31xx->pdata.micbias_vg <<
445 AIC31XX_MICBIAS_SHIFT);
446 dev_dbg(codec->dev, "%s: turned on\n", __func__);
447 break;
448 case SND_SOC_DAPM_PRE_PMD:
449 /* turn mic bias off */
450 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
451 AIC31XX_MICBIAS_MASK, 0);
452 dev_dbg(codec->dev, "%s: turned off\n", __func__);
453 break;
454 }
455 return 0;
456}
457
458static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
459 SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0),
460
461 SND_SOC_DAPM_MUX("DAC Left Input",
462 SND_SOC_NOPM, 0, 0, &ldac_in_control),
463 SND_SOC_DAPM_MUX("DAC Right Input",
464 SND_SOC_NOPM, 0, 0, &rdac_in_control),
465 /* DACs */
466 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
467 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
468 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
469
470 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
471 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
472 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
473
474 /* Output Mixers */
475 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
476 left_output_switches,
477 ARRAY_SIZE(left_output_switches)),
478 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
479 right_output_switches,
480 ARRAY_SIZE(right_output_switches)),
481
482 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
483 &aic31xx_dapm_hpl_switch),
484 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
485 &aic31xx_dapm_hpr_switch),
486
487 /* Output drivers */
488 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
489 NULL, 0, aic31xx_dapm_power_event,
490 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
491 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
492 NULL, 0, aic31xx_dapm_power_event,
493 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
494
495 /* ADC */
496 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
497 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
498 SND_SOC_DAPM_POST_PMD),
499
500 /* Input Selection to MIC_PGA */
501 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
502 &p_term_mic1lp),
503 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
504 &p_term_mic1rp),
505 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
506 &p_term_mic1lm),
507
508 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
509 &m_term_mic1lm),
510 /* Enabling & Disabling MIC Gain Ctl */
511 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
512 7, 1, NULL, 0),
513
514 /* Mic Bias */
515 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
516 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
517
518 /* Outputs */
519 SND_SOC_DAPM_OUTPUT("HPL"),
520 SND_SOC_DAPM_OUTPUT("HPR"),
521
522 /* Inputs */
523 SND_SOC_DAPM_INPUT("MIC1LP"),
524 SND_SOC_DAPM_INPUT("MIC1RP"),
525 SND_SOC_DAPM_INPUT("MIC1LM"),
526};
527
528static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
529 /* AIC3111 and AIC3110 have stereo class-D amplifier */
530 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
531 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
532 SND_SOC_DAPM_POST_PMD),
533 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
534 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
535 SND_SOC_DAPM_POST_PMD),
536 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
537 &aic31xx_dapm_spl_switch),
538 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
539 &aic31xx_dapm_spr_switch),
540 SND_SOC_DAPM_OUTPUT("SPL"),
541 SND_SOC_DAPM_OUTPUT("SPR"),
542};
543
544/* AIC3100 and AIC3120 have only mono class-D amplifier */
545static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
546 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
547 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
548 SND_SOC_DAPM_POST_PMD),
549 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
550 &aic31xx_dapm_spl_switch),
551 SND_SOC_DAPM_OUTPUT("SPK"),
552};
553
554static const struct snd_soc_dapm_route
555aic31xx_audio_map[] = {
556 /* DAC Input Routing */
557 {"DAC Left Input", "Left Data", "DAC IN"},
558 {"DAC Left Input", "Right Data", "DAC IN"},
559 {"DAC Left Input", "Mono", "DAC IN"},
560 {"DAC Right Input", "Left Data", "DAC IN"},
561 {"DAC Right Input", "Right Data", "DAC IN"},
562 {"DAC Right Input", "Mono", "DAC IN"},
563 {"DAC Left", NULL, "DAC Left Input"},
564 {"DAC Right", NULL, "DAC Right Input"},
565
566 /* Mic input */
567 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
568 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
569 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
570 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
571 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
572 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
573 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
574 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
575 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
576
577 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
578 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
579 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
580
581 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
582 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
583 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
584 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
585
586 {"ADC", NULL, "MIC_GAIN_CTL"},
587
588 /* Left Output */
589 {"Output Left", "From Left DAC", "DAC Left"},
590 {"Output Left", "From MIC1LP", "MIC1LP"},
591 {"Output Left", "From MIC1RP", "MIC1RP"},
592
593 /* Right Output */
594 {"Output Right", "From Right DAC", "DAC Right"},
595 {"Output Right", "From MIC1RP", "MIC1RP"},
596
597 /* HPL path */
598 {"HP Left", "Switch", "Output Left"},
599 {"HPL Driver", NULL, "HP Left"},
600 {"HPL", NULL, "HPL Driver"},
601
602 /* HPR path */
603 {"HP Right", "Switch", "Output Right"},
604 {"HPR Driver", NULL, "HP Right"},
605 {"HPR", NULL, "HPR Driver"},
606};
607
608static const struct snd_soc_dapm_route
609aic311x_audio_map[] = {
610 /* SP L path */
611 {"Speaker Left", "Switch", "Output Left"},
612 {"SPL ClassD", NULL, "Speaker Left"},
613 {"SPL", NULL, "SPL ClassD"},
614
615 /* SP R path */
616 {"Speaker Right", "Switch", "Output Right"},
617 {"SPR ClassD", NULL, "Speaker Right"},
618 {"SPR", NULL, "SPR ClassD"},
619};
620
621static const struct snd_soc_dapm_route
622aic310x_audio_map[] = {
623 /* SP L path */
624 {"Speaker", "Switch", "Output Left"},
625 {"SPK ClassD", NULL, "Speaker"},
626 {"SPK", NULL, "SPK ClassD"},
627};
628
629static int aic31xx_add_controls(struct snd_soc_codec *codec)
630{
631 int ret = 0;
632 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
633
634 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT)
635 ret = snd_soc_add_codec_controls(
636 codec, aic311x_snd_controls,
637 ARRAY_SIZE(aic311x_snd_controls));
638 else
639 ret = snd_soc_add_codec_controls(
640 codec, aic310x_snd_controls,
641 ARRAY_SIZE(aic310x_snd_controls));
642
643 return ret;
644}
645
646static int aic31xx_add_widgets(struct snd_soc_codec *codec)
647{
648 struct snd_soc_dapm_context *dapm = &codec->dapm;
649 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
650 int ret = 0;
651
652 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
653 ret = snd_soc_dapm_new_controls(
654 dapm, aic311x_dapm_widgets,
655 ARRAY_SIZE(aic311x_dapm_widgets));
656 if (ret)
657 return ret;
658
659 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
660 ARRAY_SIZE(aic311x_audio_map));
661 if (ret)
662 return ret;
663 } else {
664 ret = snd_soc_dapm_new_controls(
665 dapm, aic310x_dapm_widgets,
666 ARRAY_SIZE(aic310x_dapm_widgets));
667 if (ret)
668 return ret;
669
670 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
671 ARRAY_SIZE(aic310x_audio_map));
672 if (ret)
673 return ret;
674 }
675
676 return 0;
677}
678
679static int aic31xx_setup_pll(struct snd_soc_codec *codec,
680 struct snd_pcm_hw_params *params)
681{
682 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
683 int bclk_n = 0;
684 int i;
685
686 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
687 snd_soc_update_bits(codec, AIC31XX_CLKMUX,
688 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
689 snd_soc_update_bits(codec, AIC31XX_IFACE2,
690 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
691
692 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
693 if (aic31xx_divs[i].rate == params_rate(params) &&
694 aic31xx_divs[i].mclk == aic31xx->sysclk)
695 break;
696 }
697
698 if (i == ARRAY_SIZE(aic31xx_divs)) {
699 dev_err(codec->dev, "%s: Sampling rate %u not supported\n",
700 __func__, params_rate(params));
701 return -EINVAL;
702 }
703
704 /* PLL configuration */
705 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
706 (aic31xx_divs[i].p_val << 4) | 0x01);
707 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
708
709 snd_soc_write(codec, AIC31XX_PLLDMSB,
710 aic31xx_divs[i].pll_d >> 8);
711 snd_soc_write(codec, AIC31XX_PLLDLSB,
712 aic31xx_divs[i].pll_d & 0xff);
713
714 /* DAC dividers configuration */
715 snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK,
716 aic31xx_divs[i].ndac);
717 snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK,
718 aic31xx_divs[i].mdac);
719
720 snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
721 snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
722
723 /* ADC dividers configuration. Write reset value 1 if not used. */
724 snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK,
725 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
726 snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK,
727 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
728
729 snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr);
730
731 /* Bit clock divider configuration. */
732 bclk_n = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac)
733 / snd_soc_params_to_frame_size(params);
734 if (bclk_n == 0) {
735 dev_err(codec->dev, "%s: Not enough BLCK bandwidth\n",
736 __func__);
737 return -EINVAL;
738 }
739
740 snd_soc_update_bits(codec, AIC31XX_BCLKN,
741 AIC31XX_PLL_MASK, bclk_n);
742
743 aic31xx->rate_div_line = i;
744
745 dev_dbg(codec->dev,
746 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
747 aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d,
748 aic31xx_divs[i].p_val, aic31xx_divs[i].dosr,
749 aic31xx_divs[i].ndac, aic31xx_divs[i].mdac,
750 aic31xx_divs[i].aosr, aic31xx_divs[i].nadc,
751 aic31xx_divs[i].madc, bclk_n);
752
753 return 0;
754}
755
756static int aic31xx_hw_params(struct snd_pcm_substream *substream,
757 struct snd_pcm_hw_params *params,
ab64246c 758 struct snd_soc_dai *dai)
e00447fa 759{
ab64246c 760 struct snd_soc_codec *codec = dai->codec;
e00447fa
JS		 761 u8 data = 0;
762
88be681b
MB		 763 dev_dbg(codec->dev, "## %s: width %d rate %d\n",
764 __func__, params_width(params),
e00447fa
JS		 765 params_rate(params));
766
767 switch (params_width(params)) {
768 case 16:
769 break;
770 case 20:
771 data = (AIC31XX_WORD_LEN_20BITS <<
772 AIC31XX_IFACE1_DATALEN_SHIFT);
773 break;
774 case 24:
775 data = (AIC31XX_WORD_LEN_24BITS <<
776 AIC31XX_IFACE1_DATALEN_SHIFT);
777 break;
778 case 32:
779 data = (AIC31XX_WORD_LEN_32BITS <<
780 AIC31XX_IFACE1_DATALEN_SHIFT);
781 break;
782 default:
88be681b
MB		 783 dev_err(codec->dev, "%s: Unsupported width %d\n",
784 __func__, params_width(params));
e00447fa
JS		 785 return -EINVAL;
786 }
787
788 snd_soc_update_bits(codec, AIC31XX_IFACE1,
789 AIC31XX_IFACE1_DATALEN_MASK,
790 data);
791
792 return aic31xx_setup_pll(codec, params);
793}
794
795static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute)
796{
797 struct snd_soc_codec *codec = codec_dai->codec;
798
799 if (mute) {
800 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
801 AIC31XX_DACMUTE_MASK,
802 AIC31XX_DACMUTE_MASK);
803 } else {
804 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
805 AIC31XX_DACMUTE_MASK, 0x0);
806 }
807
808 return 0;
809}
810
811static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
812 unsigned int fmt)
813{
814 struct snd_soc_codec *codec = codec_dai->codec;
815 u8 iface_reg1 = 0;
816 u8 iface_reg3 = 0;
817 u8 dsp_a_val = 0;
818
819 dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
820
821 /* set master/slave audio interface */
822 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
823 case SND_SOC_DAIFMT_CBM_CFM:
824 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
825 break;
826 default:
827 dev_alert(codec->dev, "Invalid DAI master/slave interface\n");
828 return -EINVAL;
829 }
830
831 /* interface format */
832 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
833 case SND_SOC_DAIFMT_I2S:
834 break;
835 case SND_SOC_DAIFMT_DSP_A:
836 dsp_a_val = 0x1;
837 case SND_SOC_DAIFMT_DSP_B:
838 /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */
839 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
840 case SND_SOC_DAIFMT_NB_NF:
841 iface_reg3 |= AIC31XX_BCLKINV_MASK;
842 break;
843 case SND_SOC_DAIFMT_IB_NF:
844 break;
845 default:
846 return -EINVAL;
847 }
848 iface_reg1 |= (AIC31XX_DSP_MODE <<
849 AIC31XX_IFACE1_DATATYPE_SHIFT);
850 break;
851 case SND_SOC_DAIFMT_RIGHT_J:
852 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
853 AIC31XX_IFACE1_DATATYPE_SHIFT);
854 break;
855 case SND_SOC_DAIFMT_LEFT_J:
856 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
857 AIC31XX_IFACE1_DATATYPE_SHIFT);
858 break;
859 default:
860 dev_err(codec->dev, "Invalid DAI interface format\n");
861 return -EINVAL;
862 }
863
864 snd_soc_update_bits(codec, AIC31XX_IFACE1,
865 AIC31XX_IFACE1_DATATYPE_MASK |
866 AIC31XX_IFACE1_MASTER_MASK,
867 iface_reg1);
868 snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET,
869 AIC31XX_DATA_OFFSET_MASK,
870 dsp_a_val);
871 snd_soc_update_bits(codec, AIC31XX_IFACE2,
872 AIC31XX_BCLKINV_MASK,
873 iface_reg3);
874
875 return 0;
876}
877
878static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
879 int clk_id, unsigned int freq, int dir)
880{
881 struct snd_soc_codec *codec = codec_dai->codec;
882 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
883 int i;
884
885 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
886 __func__, clk_id, freq, dir);
887
888 for (i = 0; aic31xx_divs[i].mclk != freq; i++) {
889 if (i == ARRAY_SIZE(aic31xx_divs)) {
890 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
891 __func__, freq);
892 return -EINVAL;
893 }
894 }
895
896 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
897 snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
898 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
899
900 aic31xx->sysclk = freq;
901 return 0;
902}
903
904static int aic31xx_regulator_event(struct notifier_block *nb,
905 unsigned long event, void *data)
906{
907 struct aic31xx_disable_nb *disable_nb =
908 container_of(nb, struct aic31xx_disable_nb, nb);
909 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
910
911 if (event & REGULATOR_EVENT_DISABLE) {
912 /*
913 * Put codec to reset and as at least one of the
914 * supplies was disabled.
915 */
916 if (gpio_is_valid(aic31xx->pdata.gpio_reset))
917 gpio_set_value(aic31xx->pdata.gpio_reset, 0);
918
919 regcache_mark_dirty(aic31xx->regmap);
920 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
921 }
922
923 return 0;
924}
925
926static void aic31xx_clk_on(struct snd_soc_codec *codec)
927{
928 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
929 u8 mask = AIC31XX_PM_MASK;
930 u8 on = AIC31XX_PM_MASK;
931
932 dev_dbg(codec->dev, "codec clock -> on (rate %d)\n",
933 aic31xx_divs[aic31xx->rate_div_line].rate);
934 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on);
935 mdelay(10);
936 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on);
937 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on);
938 if (aic31xx_divs[aic31xx->rate_div_line].nadc)
939 snd_soc_update_bits(codec, AIC31XX_NADC, mask, on);
940 if (aic31xx_divs[aic31xx->rate_div_line].madc)
941 snd_soc_update_bits(codec, AIC31XX_MADC, mask, on);
942 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on);
943}
944
945static void aic31xx_clk_off(struct snd_soc_codec *codec)
946{
e00447fa
JS		 947 u8 mask = AIC31XX_PM_MASK;
948 u8 off = 0;
949
950 dev_dbg(codec->dev, "codec clock -> off\n");
951 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off);
952 snd_soc_update_bits(codec, AIC31XX_MADC, mask, off);
953 snd_soc_update_bits(codec, AIC31XX_NADC, mask, off);
954 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off);
955 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off);
956 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off);
957}
958
959static int aic31xx_power_on(struct snd_soc_codec *codec)
960{
961 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
962 int ret = 0;
963
964 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
965 aic31xx->supplies);
966 if (ret)
967 return ret;
968
969 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) {
970 gpio_set_value(aic31xx->pdata.gpio_reset, 1);
971 udelay(100);
972 }
973 regcache_cache_only(aic31xx->regmap, false);
974 ret = regcache_sync(aic31xx->regmap);
975 if (ret != 0) {
976 dev_err(codec->dev,
977 "Failed to restore cache: %d\n", ret);
978 regcache_cache_only(aic31xx->regmap, true);
979 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
980 aic31xx->supplies);
981 return ret;
982 }
983 return 0;
984}
985
986static int aic31xx_power_off(struct snd_soc_codec *codec)
987{
988 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
989 int ret = 0;
990
991 regcache_cache_only(aic31xx->regmap, true);
992 ret = regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
993 aic31xx->supplies);
994
995 return ret;
996}
997
998static int aic31xx_set_bias_level(struct snd_soc_codec *codec,
999 enum snd_soc_bias_level level)
1000{
1001 dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__,
1002 codec->dapm.bias_level, level);
1003
1004 switch (level) {
1005 case SND_SOC_BIAS_ON:
1006 break;
1007 case SND_SOC_BIAS_PREPARE:
1008 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
1009 aic31xx_clk_on(codec);
1010 break;
1011 case SND_SOC_BIAS_STANDBY:
1012 switch (codec->dapm.bias_level) {
1013 case SND_SOC_BIAS_OFF:
1014 aic31xx_power_on(codec);
1015 break;
1016 case SND_SOC_BIAS_PREPARE:
1017 aic31xx_clk_off(codec);
1018 break;
1019 default:
1020 BUG();
1021 }
1022 break;
1023 case SND_SOC_BIAS_OFF:
fd218aa3
JS		 1024 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
1025 aic31xx_power_off(codec);
e00447fa
JS		 1026 break;
1027 }
1028 codec->dapm.bias_level = level;
1029
1030 return 0;
1031}
1032
1033static int aic31xx_suspend(struct snd_soc_codec *codec)
1034{
1035 aic31xx_set_bias_level(codec, SND_SOC_BIAS_OFF);
1036 return 0;
1037}
1038
1039static int aic31xx_resume(struct snd_soc_codec *codec)
1040{
1041 aic31xx_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1042 return 0;
1043}
1044
1045static int aic31xx_codec_probe(struct snd_soc_codec *codec)
1046{
1047 int ret = 0;
1048 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1049 int i;
1050
1051 dev_dbg(aic31xx->dev, "## %s\n", __func__);
1052
1053 aic31xx = snd_soc_codec_get_drvdata(codec);
e00447fa
JS		 1054
1055 aic31xx->codec = codec;
1056
e00447fa
JS		 1057 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1058 aic31xx->disable_nb[i].nb.notifier_call =
1059 aic31xx_regulator_event;
1060 aic31xx->disable_nb[i].aic31xx = aic31xx;
1061 ret = regulator_register_notifier(aic31xx->supplies[i].consumer,
1062 &aic31xx->disable_nb[i].nb);
1063 if (ret) {
1064 dev_err(codec->dev,
1065 "Failed to request regulator notifier: %d\n",
1066 ret);
1067 return ret;
1068 }
1069 }
1070
1071 regcache_cache_only(aic31xx->regmap, true);
1072 regcache_mark_dirty(aic31xx->regmap);
1073
1074 ret = aic31xx_add_controls(codec);
1075 if (ret)
1076 return ret;
1077
1078 ret = aic31xx_add_widgets(codec);
1079
1080 return ret;
1081}
1082
1083static int aic31xx_codec_remove(struct snd_soc_codec *codec)
1084{
1085 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1086 int i;
1087 /* power down chip */
1088 aic31xx_set_bias_level(codec, SND_SOC_BIAS_OFF);
1089
1090 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1091 regulator_unregister_notifier(aic31xx->supplies[i].consumer,
1092 &aic31xx->disable_nb[i].nb);
1093
1094 return 0;
1095}
1096
1097static struct snd_soc_codec_driver soc_codec_driver_aic31xx = {
1098 .probe = aic31xx_codec_probe,
1099 .remove = aic31xx_codec_remove,
1100 .suspend = aic31xx_suspend,
1101 .resume = aic31xx_resume,
1102 .set_bias_level = aic31xx_set_bias_level,
1103 .controls = aic31xx_snd_controls,
1104 .num_controls = ARRAY_SIZE(aic31xx_snd_controls),
1105 .dapm_widgets = aic31xx_dapm_widgets,
1106 .num_dapm_widgets = ARRAY_SIZE(aic31xx_dapm_widgets),
1107 .dapm_routes = aic31xx_audio_map,
1108 .num_dapm_routes = ARRAY_SIZE(aic31xx_audio_map),
1109};
1110
1111static struct snd_soc_dai_ops aic31xx_dai_ops = {
1112 .hw_params = aic31xx_hw_params,
1113 .set_sysclk = aic31xx_set_dai_sysclk,
1114 .set_fmt = aic31xx_set_dai_fmt,
1115 .digital_mute = aic31xx_dac_mute,
1116};
1117
1118static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1119 {
1120 .name = "tlv320aic31xx-hifi",
1121 .playback = {
1122 .stream_name = "Playback",
1123 .channels_min = 1,
1124 .channels_max = 2,
1125 .rates = AIC31XX_RATES,
1126 .formats = AIC31XX_FORMATS,
1127 },
1128 .capture = {
1129 .stream_name = "Capture",
1130 .channels_min = 1,
1131 .channels_max = 2,
1132 .rates = AIC31XX_RATES,
1133 .formats = AIC31XX_FORMATS,
1134 },
1135 .ops = &aic31xx_dai_ops,
1136 .symmetric_rates = 1,
1137 }
1138};
1139
1140#if defined(CONFIG_OF)
1141static const struct of_device_id tlv320aic31xx_of_match[] = {
1142 { .compatible = "ti,tlv320aic310x" },
1143 { .compatible = "ti,tlv320aic311x" },
1144 { .compatible = "ti,tlv320aic3100" },
1145 { .compatible = "ti,tlv320aic3110" },
1146 { .compatible = "ti,tlv320aic3120" },
1147 { .compatible = "ti,tlv320aic3111" },
1148 {},
1149};
1150MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
1151
1152static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1153{
1154 struct device_node *np = aic31xx->dev->of_node;
1155 unsigned int value = MICBIAS_2_0V;
1156 int ret;
1157
1158 of_property_read_u32(np, "ai31xx-micbias-vg", &value);
1159 switch (value) {
1160 case MICBIAS_2_0V:
1161 case MICBIAS_2_5V:
1162 case MICBIAS_AVDDV:
1163 aic31xx->pdata.micbias_vg = value;
1164 break;
1165 default:
1166 dev_err(aic31xx->dev,
1167 "Bad ai31xx-micbias-vg value %d DT\n",
1168 value);
1169 aic31xx->pdata.micbias_vg = MICBIAS_2_0V;
1170 }
1171
1172 ret = of_get_named_gpio(np, "gpio-reset", 0);
1173 if (ret > 0)
1174 aic31xx->pdata.gpio_reset = ret;
1175}
1176#else /* CONFIG_OF */
1177static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1178{
1179}
1180#endif /* CONFIG_OF */
1181
a72d2abb 1182static int aic31xx_device_init(struct aic31xx_priv *aic31xx)
e00447fa
JS		 1183{
1184 int ret, i;
1185
1186 dev_set_drvdata(aic31xx->dev, aic31xx);
1187
1188 if (dev_get_platdata(aic31xx->dev))
1189 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev),
1190 sizeof(aic31xx->pdata));
1191 else if (aic31xx->dev->of_node)
1192 aic31xx_pdata_from_of(aic31xx);
1193
1194 if (aic31xx->pdata.gpio_reset) {
1195 ret = devm_gpio_request_one(aic31xx->dev,
1196 aic31xx->pdata.gpio_reset,
1197 GPIOF_OUT_INIT_HIGH,
1198 "aic31xx-reset-pin");
1199 if (ret < 0) {
1200 dev_err(aic31xx->dev, "not able to acquire gpio\n");
a72d2abb 1201 return ret;
e00447fa
JS		 1202 }
1203 }
1204
1205 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1206 aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1207
1208 ret = devm_regulator_bulk_get(aic31xx->dev,
1209 ARRAY_SIZE(aic31xx->supplies),
1210 aic31xx->supplies);
1211 if (ret != 0)
1212 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret);
1213
a72d2abb 1214 return ret;
e00447fa
JS		 1215}
1216
1217static int aic31xx_i2c_probe(struct i2c_client *i2c,
1218 const struct i2c_device_id *id)
1219{
1220 struct aic31xx_priv *aic31xx;
1221 int ret;
1222 const struct regmap_config *regmap_config;
1223
1224 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1225 id->name, (int) id->driver_data);
1226
1227 regmap_config = &aic31xx_i2c_regmap;
1228
1229 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
1230 if (aic31xx == NULL)
1231 return -ENOMEM;
1232
1233 aic31xx->regmap = devm_regmap_init_i2c(i2c, regmap_config);
e00447fa
JS		 1234 if (IS_ERR(aic31xx->regmap)) {
1235 ret = PTR_ERR(aic31xx->regmap);
1236 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1237 ret);
1238 return ret;
1239 }
1240 aic31xx->dev = &i2c->dev;
1241
1242 aic31xx->pdata.codec_type = id->driver_data;
1243
a72d2abb
PU		 1244 ret = aic31xx_device_init(aic31xx);
1245 if (ret)
1246 return ret;
e00447fa 1247
dac7e404 1248 return snd_soc_register_codec(&i2c->dev, &soc_codec_driver_aic31xx,
e00447fa
JS		 1249 aic31xx_dai_driver,
1250 ARRAY_SIZE(aic31xx_dai_driver));
e00447fa
JS		 1251}
1252
1253static int aic31xx_i2c_remove(struct i2c_client *i2c)
1254{
dac7e404 1255 snd_soc_unregister_codec(&i2c->dev);
e00447fa
JS		 1256 return 0;
1257}
1258
1259static const struct i2c_device_id aic31xx_i2c_id[] = {
1260 { "tlv320aic310x", AIC3100 },
1261 { "tlv320aic311x", AIC3110 },
1262 { "tlv320aic3100", AIC3100 },
1263 { "tlv320aic3110", AIC3110 },
1264 { "tlv320aic3120", AIC3120 },
1265 { "tlv320aic3111", AIC3111 },
1266 { }
1267};
1268MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1269
1270static struct i2c_driver aic31xx_i2c_driver = {
1271 .driver = {
1272 .name = "tlv320aic31xx-codec",
1273 .owner = THIS_MODULE,
1274 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
1275 },
1276 .probe = aic31xx_i2c_probe,
dac7e404 1277 .remove = aic31xx_i2c_remove,
e00447fa
JS		 1278 .id_table = aic31xx_i2c_id,
1279};
1280
1281module_i2c_driver(aic31xx_i2c_driver);
1282
1283MODULE_DESCRIPTION("ASoC TLV320AIC3111 codec driver");
1284MODULE_AUTHOR("Jyri Sarha");
1285MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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