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Merge branch 'fix/tlv320aic31xx' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / sound / soc / codecs / tlv320aic31xx.c
CommitLineData
e00447fa
JS		 1/*
2 * ALSA SoC TLV320AIC31XX codec driver
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc.
5 *
6 * Author: Jyri Sarha <jsarha@ti.com>
7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * THIS PACKAGE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 * The TLV320AIC31xx series of audio codec is a low-power, highly integrated
19 * high performance codec which provides a stereo DAC, a mono ADC,
20 * and mono/stereo Class-D speaker driver.
21 */
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/pm.h>
28#include <linux/i2c.h>
29#include <linux/gpio.h>
30#include <linux/regulator/consumer.h>
0faabc4f 31#include <linux/of.h>
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JS		 32#include <linux/of_gpio.h>
33#include <linux/slab.h>
34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/initval.h>
39#include <sound/tlv.h>
40#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
41
42#include "tlv320aic31xx.h"
43
44static const struct reg_default aic31xx_reg_defaults[] = {
45 { AIC31XX_CLKMUX, 0x00 },
46 { AIC31XX_PLLPR, 0x11 },
47 { AIC31XX_PLLJ, 0x04 },
48 { AIC31XX_PLLDMSB, 0x00 },
49 { AIC31XX_PLLDLSB, 0x00 },
50 { AIC31XX_NDAC, 0x01 },
51 { AIC31XX_MDAC, 0x01 },
52 { AIC31XX_DOSRMSB, 0x00 },
53 { AIC31XX_DOSRLSB, 0x80 },
54 { AIC31XX_NADC, 0x01 },
55 { AIC31XX_MADC, 0x01 },
56 { AIC31XX_AOSR, 0x80 },
57 { AIC31XX_IFACE1, 0x00 },
58 { AIC31XX_DATA_OFFSET, 0x00 },
59 { AIC31XX_IFACE2, 0x00 },
60 { AIC31XX_BCLKN, 0x01 },
61 { AIC31XX_DACSETUP, 0x14 },
62 { AIC31XX_DACMUTE, 0x0c },
63 { AIC31XX_LDACVOL, 0x00 },
64 { AIC31XX_RDACVOL, 0x00 },
65 { AIC31XX_ADCSETUP, 0x00 },
66 { AIC31XX_ADCFGA, 0x80 },
67 { AIC31XX_ADCVOL, 0x00 },
68 { AIC31XX_HPDRIVER, 0x04 },
69 { AIC31XX_SPKAMP, 0x06 },
70 { AIC31XX_DACMIXERROUTE, 0x00 },
71 { AIC31XX_LANALOGHPL, 0x7f },
72 { AIC31XX_RANALOGHPR, 0x7f },
73 { AIC31XX_LANALOGSPL, 0x7f },
74 { AIC31XX_RANALOGSPR, 0x7f },
75 { AIC31XX_HPLGAIN, 0x02 },
76 { AIC31XX_HPRGAIN, 0x02 },
77 { AIC31XX_SPLGAIN, 0x00 },
78 { AIC31XX_SPRGAIN, 0x00 },
79 { AIC31XX_MICBIAS, 0x00 },
80 { AIC31XX_MICPGA, 0x80 },
81 { AIC31XX_MICPGAPI, 0x00 },
82 { AIC31XX_MICPGAMI, 0x00 },
83};
84
85static bool aic31xx_volatile(struct device *dev, unsigned int reg)
86{
87 switch (reg) {
88 case AIC31XX_PAGECTL: /* regmap implementation requires this */
89 case AIC31XX_RESET: /* always clears after write */
90 case AIC31XX_OT_FLAG:
91 case AIC31XX_ADCFLAG:
92 case AIC31XX_DACFLAG1:
93 case AIC31XX_DACFLAG2:
94 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
95 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
96 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
97 case AIC31XX_INTRDACFLAG2:
98 case AIC31XX_INTRADCFLAG2:
99 return true;
100 }
101 return false;
102}
103
104static bool aic31xx_writeable(struct device *dev, unsigned int reg)
105{
106 switch (reg) {
107 case AIC31XX_OT_FLAG:
108 case AIC31XX_ADCFLAG:
109 case AIC31XX_DACFLAG1:
110 case AIC31XX_DACFLAG2:
111 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
112 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
113 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
114 case AIC31XX_INTRDACFLAG2:
115 case AIC31XX_INTRADCFLAG2:
116 return false;
117 }
118 return true;
119}
120
121static const struct regmap_range_cfg aic31xx_ranges[] = {
122 {
123 .range_min = 0,
124 .range_max = 12 * 128,
125 .selector_reg = AIC31XX_PAGECTL,
126 .selector_mask = 0xff,
127 .selector_shift = 0,
128 .window_start = 0,
129 .window_len = 128,
130 },
131};
132
9296f4da 133static const struct regmap_config aic31xx_i2c_regmap = {
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JS		 134 .reg_bits = 8,
135 .val_bits = 8,
136 .writeable_reg = aic31xx_writeable,
137 .volatile_reg = aic31xx_volatile,
138 .reg_defaults = aic31xx_reg_defaults,
139 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
140 .cache_type = REGCACHE_RBTREE,
141 .ranges = aic31xx_ranges,
142 .num_ranges = ARRAY_SIZE(aic31xx_ranges),
143 .max_register = 12 * 128,
144};
145
146#define AIC31XX_NUM_SUPPLIES 6
147static const char * const aic31xx_supply_names[AIC31XX_NUM_SUPPLIES] = {
148 "HPVDD",
149 "SPRVDD",
150 "SPLVDD",
151 "AVDD",
152 "IOVDD",
153 "DVDD",
154};
155
156struct aic31xx_disable_nb {
157 struct notifier_block nb;
158 struct aic31xx_priv *aic31xx;
159};
160
161struct aic31xx_priv {
162 struct snd_soc_codec *codec;
163 u8 i2c_regs_status;
164 struct device *dev;
165 struct regmap *regmap;
166 struct aic31xx_pdata pdata;
167 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
168 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
169 unsigned int sysclk;
170 int rate_div_line;
171};
172
173struct aic31xx_rate_divs {
174 u32 mclk;
175 u32 rate;
176 u8 p_val;
177 u8 pll_j;
178 u16 pll_d;
179 u16 dosr;
180 u8 ndac;
181 u8 mdac;
182 u8 aosr;
183 u8 nadc;
184 u8 madc;
185};
186
187/* ADC dividers can be disabled by cofiguring them to 0 */
188static const struct aic31xx_rate_divs aic31xx_divs[] = {
189 /* mclk rate pll: p j d dosr ndac mdac aors nadc madc */
190 /* 8k rate */
191 {12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
03be88ee 192 {12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3},
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JS		 193 {24000000, 8000, 2, 8, 1920, 128, 48, 2, 128, 48, 2},
194 {25000000, 8000, 2, 7, 8643, 128, 48, 2, 128, 48, 2},
195 /* 11.025k rate */
196 {12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
03be88ee 197 {12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3},
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JS		 198 {24000000, 11025, 2, 7, 5264, 128, 32, 2, 128, 32, 2},
199 {25000000, 11025, 2, 7, 2253, 128, 32, 2, 128, 32, 2},
200 /* 16k rate */
201 {12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
03be88ee 202 {12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3},
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JS		 203 {24000000, 16000, 2, 8, 1920, 128, 24, 2, 128, 24, 2},
204 {25000000, 16000, 2, 7, 8643, 128, 24, 2, 128, 24, 2},
205 /* 22.05k rate */
206 {12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
03be88ee 207 {12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3},
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JS		 208 {24000000, 22050, 2, 7, 5264, 128, 16, 2, 128, 16, 2},
209 {25000000, 22050, 2, 7, 2253, 128, 16, 2, 128, 16, 2},
210 /* 32k rate */
211 {12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
03be88ee 212 {12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3},
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JS		 213 {24000000, 32000, 2, 8, 1920, 128, 12, 2, 128, 12, 2},
214 {25000000, 32000, 2, 7, 8643, 128, 12, 2, 128, 12, 2},
215 /* 44.1k rate */
216 {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
03be88ee 217 {12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3},
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JS		 218 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 128, 8, 2},
219 {25000000, 44100, 2, 7, 2253, 128, 8, 2, 128, 8, 2},
220 /* 48k rate */
221 {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
03be88ee 222 {12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4},
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JS		 223 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 128, 8, 2},
224 {25000000, 48000, 2, 7, 8643, 128, 8, 2, 128, 8, 2},
225 /* 88.2k rate */
226 {12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
03be88ee 227 {12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3},
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JS		 228 {24000000, 88200, 2, 7, 5264, 64, 8, 2, 64, 8, 2},
229 {25000000, 88200, 2, 7, 2253, 64, 8, 2, 64, 8, 2},
230 /* 96k rate */
231 {12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
03be88ee 232 {12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4},
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JS		 233 {24000000, 96000, 2, 8, 1920, 64, 8, 2, 64, 8, 2},
234 {25000000, 96000, 2, 7, 8643, 64, 8, 2, 64, 8, 2},
235 /* 176.4k rate */
236 {12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
03be88ee 237 {12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3},
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JS		 238 {24000000, 176400, 2, 7, 5264, 32, 8, 2, 32, 8, 2},
239 {25000000, 176400, 2, 7, 2253, 32, 8, 2, 32, 8, 2},
240 /* 192k rate */
241 {12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
03be88ee 242 {12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4},
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JS		 243 {24000000, 192000, 2, 8, 1920, 32, 8, 2, 32, 8, 2},
244 {25000000, 192000, 2, 7, 8643, 32, 8, 2, 32, 8, 2},
245};
246
247static const char * const ldac_in_text[] = {
248 "Off", "Left Data", "Right Data", "Mono"
249};
250
251static const char * const rdac_in_text[] = {
252 "Off", "Right Data", "Left Data", "Mono"
253};
254
255static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
256
257static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
258
259static const char * const mic_select_text[] = {
260 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
261};
262
914bc160
LPC		 263static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
264 mic_select_text);
265static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
266 mic_select_text);
267static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
268 mic_select_text);
e00447fa 269
914bc160
LPC		 270static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text);
271static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
272 mic_select_text);
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JS		 273
274static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
275static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
276static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
277static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
278static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
279static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
280static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
281static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
282
283/*
284 * controls to be exported to the user space
285 */
286static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
287 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
288 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
289
290 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
291 adc_fgain_tlv),
292
293 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
294 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
295 0, -24, 40, 6, 0, adc_cgain_tlv),
296
297 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
298 119, 0, mic_pga_tlv),
299
300 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
301 AIC31XX_HPRGAIN, 2, 1, 0),
302 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
303 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
304
305 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
306 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
307};
308
309static const struct snd_kcontrol_new aic311x_snd_controls[] = {
310 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
311 AIC31XX_SPRGAIN, 2, 1, 0),
312 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
313 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
314
315 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
316 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
317};
318
319static const struct snd_kcontrol_new aic310x_snd_controls[] = {
320 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
321 2, 1, 0),
322 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
323 3, 3, 0, class_D_drv_tlv),
324
325 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
326 0, 0x7F, 1, sp_vol_tlv),
327};
328
329static const struct snd_kcontrol_new ldac_in_control =
330 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
331
332static const struct snd_kcontrol_new rdac_in_control =
333 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
334
9296f4da
MB		 335static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
336 unsigned int mask, unsigned int wbits, int sleep,
337 int count)
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JS		 338{
339 unsigned int bits;
340 int counter = count;
341 int ret = regmap_read(aic31xx->regmap, reg, &bits);
423ca88e 342
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JS		 343 while ((bits & mask) != wbits && counter && !ret) {
344 usleep_range(sleep, sleep * 2);
345 ret = regmap_read(aic31xx->regmap, reg, &bits);
346 counter--;
347 }
348 if ((bits & mask) != wbits) {
349 dev_err(aic31xx->dev,
350 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
351 __func__, reg, bits, wbits, ret, mask,
352 (count - counter) * sleep);
353 ret = -1;
354 }
355 return ret;
356}
357
358#define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
359
360static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
361 struct snd_kcontrol *kcontrol, int event)
362{
363 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(w->codec);
364 unsigned int reg = AIC31XX_DACFLAG1;
365 unsigned int mask;
366
367 switch (WIDGET_BIT(w->reg, w->shift)) {
368 case WIDGET_BIT(AIC31XX_DACSETUP, 7):
369 mask = AIC31XX_LDACPWRSTATUS_MASK;
370 break;
371 case WIDGET_BIT(AIC31XX_DACSETUP, 6):
372 mask = AIC31XX_RDACPWRSTATUS_MASK;
373 break;
374 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
375 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
376 break;
377 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
378 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
379 break;
380 case WIDGET_BIT(AIC31XX_SPKAMP, 7):
381 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
382 break;
383 case WIDGET_BIT(AIC31XX_SPKAMP, 6):
384 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
385 break;
386 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
387 mask = AIC31XX_ADCPWRSTATUS_MASK;
388 reg = AIC31XX_ADCFLAG;
389 break;
390 default:
2a1c23e3 391 dev_err(w->codec->dev, "Unknown widget '%s' calling %s\n",
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JS		 392 w->name, __func__);
393 return -EINVAL;
394 }
395
396 switch (event) {
397 case SND_SOC_DAPM_POST_PMU:
398 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100);
399 case SND_SOC_DAPM_POST_PMD:
400 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100);
401 default:
402 dev_dbg(w->codec->dev,
403 "Unhandled dapm widget event %d from %s\n",
404 event, w->name);
405 }
406 return 0;
407}
408
409static const struct snd_kcontrol_new left_output_switches[] = {
410 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
411 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
412 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
413};
414
415static const struct snd_kcontrol_new right_output_switches[] = {
416 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
417 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
418};
419
420static const struct snd_kcontrol_new p_term_mic1lp =
421 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
422
423static const struct snd_kcontrol_new p_term_mic1rp =
424 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
425
426static const struct snd_kcontrol_new p_term_mic1lm =
427 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
428
429static const struct snd_kcontrol_new m_term_mic1lm =
430 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
431
432static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
433 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
434
435static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
436 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
437
438static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
439 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
440
441static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
442 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
443
444static int mic_bias_event(struct snd_soc_dapm_widget *w,
445 struct snd_kcontrol *kcontrol, int event)
446{
447 struct snd_soc_codec *codec = w->codec;
448 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
423ca88e 449
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JS		 450 switch (event) {
451 case SND_SOC_DAPM_POST_PMU:
452 /* change mic bias voltage to user defined */
453 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
454 AIC31XX_MICBIAS_MASK,
455 aic31xx->pdata.micbias_vg <<
456 AIC31XX_MICBIAS_SHIFT);
457 dev_dbg(codec->dev, "%s: turned on\n", __func__);
458 break;
459 case SND_SOC_DAPM_PRE_PMD:
460 /* turn mic bias off */
461 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
462 AIC31XX_MICBIAS_MASK, 0);
463 dev_dbg(codec->dev, "%s: turned off\n", __func__);
464 break;
465 }
466 return 0;
467}
468
469static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
470 SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0),
471
472 SND_SOC_DAPM_MUX("DAC Left Input",
473 SND_SOC_NOPM, 0, 0, &ldac_in_control),
474 SND_SOC_DAPM_MUX("DAC Right Input",
475 SND_SOC_NOPM, 0, 0, &rdac_in_control),
476 /* DACs */
477 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
478 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
479 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
480
481 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
482 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
483 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
484
485 /* Output Mixers */
486 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
487 left_output_switches,
488 ARRAY_SIZE(left_output_switches)),
489 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
490 right_output_switches,
491 ARRAY_SIZE(right_output_switches)),
492
493 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
494 &aic31xx_dapm_hpl_switch),
495 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
496 &aic31xx_dapm_hpr_switch),
497
498 /* Output drivers */
499 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
500 NULL, 0, aic31xx_dapm_power_event,
501 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
502 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
503 NULL, 0, aic31xx_dapm_power_event,
504 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
505
506 /* ADC */
507 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
508 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
509 SND_SOC_DAPM_POST_PMD),
510
511 /* Input Selection to MIC_PGA */
512 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
513 &p_term_mic1lp),
514 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
515 &p_term_mic1rp),
516 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
517 &p_term_mic1lm),
518
519 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
520 &m_term_mic1lm),
521 /* Enabling & Disabling MIC Gain Ctl */
522 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
523 7, 1, NULL, 0),
524
525 /* Mic Bias */
526 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
527 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
528
529 /* Outputs */
530 SND_SOC_DAPM_OUTPUT("HPL"),
531 SND_SOC_DAPM_OUTPUT("HPR"),
532
533 /* Inputs */
534 SND_SOC_DAPM_INPUT("MIC1LP"),
535 SND_SOC_DAPM_INPUT("MIC1RP"),
536 SND_SOC_DAPM_INPUT("MIC1LM"),
537};
538
539static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
540 /* AIC3111 and AIC3110 have stereo class-D amplifier */
541 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
542 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
543 SND_SOC_DAPM_POST_PMD),
544 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
545 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
546 SND_SOC_DAPM_POST_PMD),
547 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
548 &aic31xx_dapm_spl_switch),
549 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
550 &aic31xx_dapm_spr_switch),
551 SND_SOC_DAPM_OUTPUT("SPL"),
552 SND_SOC_DAPM_OUTPUT("SPR"),
553};
554
555/* AIC3100 and AIC3120 have only mono class-D amplifier */
556static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
557 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
558 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
559 SND_SOC_DAPM_POST_PMD),
560 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
561 &aic31xx_dapm_spl_switch),
562 SND_SOC_DAPM_OUTPUT("SPK"),
563};
564
565static const struct snd_soc_dapm_route
566aic31xx_audio_map[] = {
567 /* DAC Input Routing */
568 {"DAC Left Input", "Left Data", "DAC IN"},
569 {"DAC Left Input", "Right Data", "DAC IN"},
570 {"DAC Left Input", "Mono", "DAC IN"},
571 {"DAC Right Input", "Left Data", "DAC IN"},
572 {"DAC Right Input", "Right Data", "DAC IN"},
573 {"DAC Right Input", "Mono", "DAC IN"},
574 {"DAC Left", NULL, "DAC Left Input"},
575 {"DAC Right", NULL, "DAC Right Input"},
576
577 /* Mic input */
578 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
579 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
580 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
581 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
582 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
583 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
584 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
585 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
586 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
587
588 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
589 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
590 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
591
592 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
593 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
594 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
595 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
596
597 {"ADC", NULL, "MIC_GAIN_CTL"},
598
599 /* Left Output */
600 {"Output Left", "From Left DAC", "DAC Left"},
601 {"Output Left", "From MIC1LP", "MIC1LP"},
602 {"Output Left", "From MIC1RP", "MIC1RP"},
603
604 /* Right Output */
605 {"Output Right", "From Right DAC", "DAC Right"},
606 {"Output Right", "From MIC1RP", "MIC1RP"},
607
608 /* HPL path */
609 {"HP Left", "Switch", "Output Left"},
610 {"HPL Driver", NULL, "HP Left"},
611 {"HPL", NULL, "HPL Driver"},
612
613 /* HPR path */
614 {"HP Right", "Switch", "Output Right"},
615 {"HPR Driver", NULL, "HP Right"},
616 {"HPR", NULL, "HPR Driver"},
617};
618
619static const struct snd_soc_dapm_route
620aic311x_audio_map[] = {
621 /* SP L path */
622 {"Speaker Left", "Switch", "Output Left"},
623 {"SPL ClassD", NULL, "Speaker Left"},
624 {"SPL", NULL, "SPL ClassD"},
625
626 /* SP R path */
627 {"Speaker Right", "Switch", "Output Right"},
628 {"SPR ClassD", NULL, "Speaker Right"},
629 {"SPR", NULL, "SPR ClassD"},
630};
631
632static const struct snd_soc_dapm_route
633aic310x_audio_map[] = {
634 /* SP L path */
635 {"Speaker", "Switch", "Output Left"},
636 {"SPK ClassD", NULL, "Speaker"},
637 {"SPK", NULL, "SPK ClassD"},
638};
639
640static int aic31xx_add_controls(struct snd_soc_codec *codec)
641{
642 int ret = 0;
643 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
644
645 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT)
646 ret = snd_soc_add_codec_controls(
647 codec, aic311x_snd_controls,
648 ARRAY_SIZE(aic311x_snd_controls));
649 else
650 ret = snd_soc_add_codec_controls(
651 codec, aic310x_snd_controls,
652 ARRAY_SIZE(aic310x_snd_controls));
653
654 return ret;
655}
656
657static int aic31xx_add_widgets(struct snd_soc_codec *codec)
658{
659 struct snd_soc_dapm_context *dapm = &codec->dapm;
660 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
661 int ret = 0;
662
663 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
664 ret = snd_soc_dapm_new_controls(
665 dapm, aic311x_dapm_widgets,
666 ARRAY_SIZE(aic311x_dapm_widgets));
667 if (ret)
668 return ret;
669
670 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
671 ARRAY_SIZE(aic311x_audio_map));
672 if (ret)
673 return ret;
674 } else {
675 ret = snd_soc_dapm_new_controls(
676 dapm, aic310x_dapm_widgets,
677 ARRAY_SIZE(aic310x_dapm_widgets));
678 if (ret)
679 return ret;
680
681 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
682 ARRAY_SIZE(aic310x_audio_map));
683 if (ret)
684 return ret;
685 }
686
687 return 0;
688}
689
690static int aic31xx_setup_pll(struct snd_soc_codec *codec,
691 struct snd_pcm_hw_params *params)
692{
693 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
03be88ee 694 int bclk_score = snd_soc_params_to_frame_size(params);
e00447fa 695 int bclk_n = 0;
03be88ee 696 int match = -1;
e00447fa
JS		 697 int i;
698
699 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
700 snd_soc_update_bits(codec, AIC31XX_CLKMUX,
701 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
702 snd_soc_update_bits(codec, AIC31XX_IFACE2,
703 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
704
705 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
706 if (aic31xx_divs[i].rate == params_rate(params) &&
03be88ee
JS		 707 aic31xx_divs[i].mclk == aic31xx->sysclk) {
708 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
709 snd_soc_params_to_frame_size(params);
710 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
711 snd_soc_params_to_frame_size(params);
712 if (s < bclk_score && bn > 0) {
713 match = i;
714 bclk_n = bn;
715 bclk_score = s;
716 }
717 }
e00447fa
JS		 718 }
719
03be88ee
JS		 720 if (match == -1) {
721 dev_err(codec->dev,
722 "%s: Sample rate (%u) and format not supported\n",
e00447fa 723 __func__, params_rate(params));
03be88ee 724 /* See bellow for details how fix this. */
e00447fa
JS		 725 return -EINVAL;
726 }
03be88ee
JS		 727 if (bclk_score != 0) {
728 dev_warn(codec->dev, "Can not produce exact bitclock");
729 /* This is fine if using dsp format, but if using i2s
730 there may be trouble. To fix the issue edit the
731 aic31xx_divs table for your mclk and sample
732 rate. Details can be found from:
733 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
734 Section: 5.6 CLOCK Generation and PLL
735 */
736 }
737 i = match;
e00447fa
JS		 738
739 /* PLL configuration */
740 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
741 (aic31xx_divs[i].p_val << 4) | 0x01);
742 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
743
744 snd_soc_write(codec, AIC31XX_PLLDMSB,
745 aic31xx_divs[i].pll_d >> 8);
746 snd_soc_write(codec, AIC31XX_PLLDLSB,
747 aic31xx_divs[i].pll_d & 0xff);
748
749 /* DAC dividers configuration */
750 snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK,
751 aic31xx_divs[i].ndac);
752 snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK,
753 aic31xx_divs[i].mdac);
754
755 snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
756 snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
757
758 /* ADC dividers configuration. Write reset value 1 if not used. */
759 snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK,
760 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
761 snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK,
762 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
763
764 snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr);
765
766 /* Bit clock divider configuration. */
e00447fa
JS		 767 snd_soc_update_bits(codec, AIC31XX_BCLKN,
768 AIC31XX_PLL_MASK, bclk_n);
769
770 aic31xx->rate_div_line = i;
771
772 dev_dbg(codec->dev,
773 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
774 aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d,
775 aic31xx_divs[i].p_val, aic31xx_divs[i].dosr,
776 aic31xx_divs[i].ndac, aic31xx_divs[i].mdac,
777 aic31xx_divs[i].aosr, aic31xx_divs[i].nadc,
778 aic31xx_divs[i].madc, bclk_n);
779
780 return 0;
781}
782
783static int aic31xx_hw_params(struct snd_pcm_substream *substream,
784 struct snd_pcm_hw_params *params,
ab64246c 785 struct snd_soc_dai *dai)
e00447fa 786{
ab64246c 787 struct snd_soc_codec *codec = dai->codec;
e00447fa
JS		 788 u8 data = 0;
789
88be681b
MB		 790 dev_dbg(codec->dev, "## %s: width %d rate %d\n",
791 __func__, params_width(params),
e00447fa
JS		 792 params_rate(params));
793
794 switch (params_width(params)) {
795 case 16:
796 break;
797 case 20:
798 data = (AIC31XX_WORD_LEN_20BITS <<
799 AIC31XX_IFACE1_DATALEN_SHIFT);
800 break;
801 case 24:
802 data = (AIC31XX_WORD_LEN_24BITS <<
803 AIC31XX_IFACE1_DATALEN_SHIFT);
804 break;
805 case 32:
806 data = (AIC31XX_WORD_LEN_32BITS <<
807 AIC31XX_IFACE1_DATALEN_SHIFT);
808 break;
809 default:
88be681b
MB		 810 dev_err(codec->dev, "%s: Unsupported width %d\n",
811 __func__, params_width(params));
e00447fa
JS		 812 return -EINVAL;
813 }
814
815 snd_soc_update_bits(codec, AIC31XX_IFACE1,
816 AIC31XX_IFACE1_DATALEN_MASK,
817 data);
818
819 return aic31xx_setup_pll(codec, params);
820}
821
822static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute)
823{
824 struct snd_soc_codec *codec = codec_dai->codec;
825
826 if (mute) {
827 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
828 AIC31XX_DACMUTE_MASK,
829 AIC31XX_DACMUTE_MASK);
830 } else {
831 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
832 AIC31XX_DACMUTE_MASK, 0x0);
833 }
834
835 return 0;
836}
837
838static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
839 unsigned int fmt)
840{
841 struct snd_soc_codec *codec = codec_dai->codec;
842 u8 iface_reg1 = 0;
085f3ec6 843 u8 iface_reg2 = 0;
e00447fa
JS		 844 u8 dsp_a_val = 0;
845
846 dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
847
848 /* set master/slave audio interface */
849 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
850 case SND_SOC_DAIFMT_CBM_CFM:
851 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
852 break;
853 default:
854 dev_alert(codec->dev, "Invalid DAI master/slave interface\n");
855 return -EINVAL;
856 }
857
858 /* interface format */
859 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
860 case SND_SOC_DAIFMT_I2S:
861 break;
862 case SND_SOC_DAIFMT_DSP_A:
863 dsp_a_val = 0x1;
864 case SND_SOC_DAIFMT_DSP_B:
865 /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */
866 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
867 case SND_SOC_DAIFMT_NB_NF:
085f3ec6 868 iface_reg2 |= AIC31XX_BCLKINV_MASK;
e00447fa
JS		 869 break;
870 case SND_SOC_DAIFMT_IB_NF:
871 break;
872 default:
873 return -EINVAL;
874 }
875 iface_reg1 |= (AIC31XX_DSP_MODE <<
876 AIC31XX_IFACE1_DATATYPE_SHIFT);
877 break;
878 case SND_SOC_DAIFMT_RIGHT_J:
879 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
880 AIC31XX_IFACE1_DATATYPE_SHIFT);
881 break;
882 case SND_SOC_DAIFMT_LEFT_J:
883 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
884 AIC31XX_IFACE1_DATATYPE_SHIFT);
885 break;
886 default:
887 dev_err(codec->dev, "Invalid DAI interface format\n");
888 return -EINVAL;
889 }
890
891 snd_soc_update_bits(codec, AIC31XX_IFACE1,
892 AIC31XX_IFACE1_DATATYPE_MASK |
893 AIC31XX_IFACE1_MASTER_MASK,
894 iface_reg1);
895 snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET,
896 AIC31XX_DATA_OFFSET_MASK,
897 dsp_a_val);
898 snd_soc_update_bits(codec, AIC31XX_IFACE2,
899 AIC31XX_BCLKINV_MASK,
085f3ec6 900 iface_reg2);
e00447fa
JS		 901
902 return 0;
903}
904
905static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
906 int clk_id, unsigned int freq, int dir)
907{
908 struct snd_soc_codec *codec = codec_dai->codec;
909 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
910 int i;
911
912 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
913 __func__, clk_id, freq, dir);
914
915 for (i = 0; aic31xx_divs[i].mclk != freq; i++) {
916 if (i == ARRAY_SIZE(aic31xx_divs)) {
917 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
918 __func__, freq);
919 return -EINVAL;
920 }
921 }
922
923 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
924 snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
925 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
926
927 aic31xx->sysclk = freq;
928 return 0;
929}
930
931static int aic31xx_regulator_event(struct notifier_block *nb,
932 unsigned long event, void *data)
933{
934 struct aic31xx_disable_nb *disable_nb =
935 container_of(nb, struct aic31xx_disable_nb, nb);
936 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
937
938 if (event & REGULATOR_EVENT_DISABLE) {
939 /*
940 * Put codec to reset and as at least one of the
941 * supplies was disabled.
942 */
943 if (gpio_is_valid(aic31xx->pdata.gpio_reset))
944 gpio_set_value(aic31xx->pdata.gpio_reset, 0);
945
946 regcache_mark_dirty(aic31xx->regmap);
947 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
948 }
949
950 return 0;
951}
952
953static void aic31xx_clk_on(struct snd_soc_codec *codec)
954{
955 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
956 u8 mask = AIC31XX_PM_MASK;
957 u8 on = AIC31XX_PM_MASK;
958
959 dev_dbg(codec->dev, "codec clock -> on (rate %d)\n",
960 aic31xx_divs[aic31xx->rate_div_line].rate);
961 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on);
962 mdelay(10);
963 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on);
964 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on);
965 if (aic31xx_divs[aic31xx->rate_div_line].nadc)
966 snd_soc_update_bits(codec, AIC31XX_NADC, mask, on);
967 if (aic31xx_divs[aic31xx->rate_div_line].madc)
968 snd_soc_update_bits(codec, AIC31XX_MADC, mask, on);
969 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on);
970}
971
972static void aic31xx_clk_off(struct snd_soc_codec *codec)
973{
e00447fa
JS		 974 u8 mask = AIC31XX_PM_MASK;
975 u8 off = 0;
976
977 dev_dbg(codec->dev, "codec clock -> off\n");
978 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off);
979 snd_soc_update_bits(codec, AIC31XX_MADC, mask, off);
980 snd_soc_update_bits(codec, AIC31XX_NADC, mask, off);
981 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off);
982 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off);
983 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off);
984}
985
986static int aic31xx_power_on(struct snd_soc_codec *codec)
987{
988 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
989 int ret = 0;
990
991 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
992 aic31xx->supplies);
993 if (ret)
994 return ret;
995
996 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) {
997 gpio_set_value(aic31xx->pdata.gpio_reset, 1);
998 udelay(100);
999 }
1000 regcache_cache_only(aic31xx->regmap, false);
1001 ret = regcache_sync(aic31xx->regmap);
1002 if (ret != 0) {
1003 dev_err(codec->dev,
1004 "Failed to restore cache: %d\n", ret);
1005 regcache_cache_only(aic31xx->regmap, true);
1006 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1007 aic31xx->supplies);
1008 return ret;
1009 }
1010 return 0;
1011}
1012
1013static int aic31xx_power_off(struct snd_soc_codec *codec)
1014{
1015 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1016 int ret = 0;
1017
1018 regcache_cache_only(aic31xx->regmap, true);
1019 ret = regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1020 aic31xx->supplies);
1021
1022 return ret;
1023}
1024
1025static int aic31xx_set_bias_level(struct snd_soc_codec *codec,
1026 enum snd_soc_bias_level level)
1027{
1028 dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__,
1029 codec->dapm.bias_level, level);
1030
1031 switch (level) {
1032 case SND_SOC_BIAS_ON:
1033 break;
1034 case SND_SOC_BIAS_PREPARE:
1035 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
1036 aic31xx_clk_on(codec);
1037 break;
1038 case SND_SOC_BIAS_STANDBY:
1039 switch (codec->dapm.bias_level) {
1040 case SND_SOC_BIAS_OFF:
1041 aic31xx_power_on(codec);
1042 break;
1043 case SND_SOC_BIAS_PREPARE:
1044 aic31xx_clk_off(codec);
1045 break;
1046 default:
1047 BUG();
1048 }
1049 break;
1050 case SND_SOC_BIAS_OFF:
fd218aa3
JS		 1051 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
1052 aic31xx_power_off(codec);
e00447fa
JS		 1053 break;
1054 }
1055 codec->dapm.bias_level = level;
1056
1057 return 0;
1058}
1059
1060static int aic31xx_suspend(struct snd_soc_codec *codec)
1061{
1062 aic31xx_set_bias_level(codec, SND_SOC_BIAS_OFF);
1063 return 0;
1064}
1065
1066static int aic31xx_resume(struct snd_soc_codec *codec)
1067{
1068 aic31xx_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1069 return 0;
1070}
1071
1072static int aic31xx_codec_probe(struct snd_soc_codec *codec)
1073{
1074 int ret = 0;
1075 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1076 int i;
1077
1078 dev_dbg(aic31xx->dev, "## %s\n", __func__);
1079
1080 aic31xx = snd_soc_codec_get_drvdata(codec);
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JS		 1081
1082 aic31xx->codec = codec;
1083
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JS		 1084 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1085 aic31xx->disable_nb[i].nb.notifier_call =
1086 aic31xx_regulator_event;
1087 aic31xx->disable_nb[i].aic31xx = aic31xx;
1088 ret = regulator_register_notifier(aic31xx->supplies[i].consumer,
1089 &aic31xx->disable_nb[i].nb);
1090 if (ret) {
1091 dev_err(codec->dev,
1092 "Failed to request regulator notifier: %d\n",
1093 ret);
1094 return ret;
1095 }
1096 }
1097
1098 regcache_cache_only(aic31xx->regmap, true);
1099 regcache_mark_dirty(aic31xx->regmap);
1100
1101 ret = aic31xx_add_controls(codec);
1102 if (ret)
1103 return ret;
1104
1105 ret = aic31xx_add_widgets(codec);
1106
1107 return ret;
1108}
1109
1110static int aic31xx_codec_remove(struct snd_soc_codec *codec)
1111{
1112 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1113 int i;
1114 /* power down chip */
1115 aic31xx_set_bias_level(codec, SND_SOC_BIAS_OFF);
1116
1117 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1118 regulator_unregister_notifier(aic31xx->supplies[i].consumer,
1119 &aic31xx->disable_nb[i].nb);
1120
1121 return 0;
1122}
1123
1124static struct snd_soc_codec_driver soc_codec_driver_aic31xx = {
1125 .probe = aic31xx_codec_probe,
1126 .remove = aic31xx_codec_remove,
1127 .suspend = aic31xx_suspend,
1128 .resume = aic31xx_resume,
1129 .set_bias_level = aic31xx_set_bias_level,
1130 .controls = aic31xx_snd_controls,
1131 .num_controls = ARRAY_SIZE(aic31xx_snd_controls),
1132 .dapm_widgets = aic31xx_dapm_widgets,
1133 .num_dapm_widgets = ARRAY_SIZE(aic31xx_dapm_widgets),
1134 .dapm_routes = aic31xx_audio_map,
1135 .num_dapm_routes = ARRAY_SIZE(aic31xx_audio_map),
1136};
1137
1138static struct snd_soc_dai_ops aic31xx_dai_ops = {
1139 .hw_params = aic31xx_hw_params,
1140 .set_sysclk = aic31xx_set_dai_sysclk,
1141 .set_fmt = aic31xx_set_dai_fmt,
1142 .digital_mute = aic31xx_dac_mute,
1143};
1144
1145static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1146 {
1147 .name = "tlv320aic31xx-hifi",
1148 .playback = {
1149 .stream_name = "Playback",
1150 .channels_min = 1,
1151 .channels_max = 2,
1152 .rates = AIC31XX_RATES,
1153 .formats = AIC31XX_FORMATS,
1154 },
1155 .capture = {
1156 .stream_name = "Capture",
1157 .channels_min = 1,
1158 .channels_max = 2,
1159 .rates = AIC31XX_RATES,
1160 .formats = AIC31XX_FORMATS,
1161 },
1162 .ops = &aic31xx_dai_ops,
1163 .symmetric_rates = 1,
1164 }
1165};
1166
1167#if defined(CONFIG_OF)
1168static const struct of_device_id tlv320aic31xx_of_match[] = {
1169 { .compatible = "ti,tlv320aic310x" },
1170 { .compatible = "ti,tlv320aic311x" },
1171 { .compatible = "ti,tlv320aic3100" },
1172 { .compatible = "ti,tlv320aic3110" },
1173 { .compatible = "ti,tlv320aic3120" },
1174 { .compatible = "ti,tlv320aic3111" },
1175 {},
1176};
1177MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
1178
1179static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1180{
1181 struct device_node *np = aic31xx->dev->of_node;
1182 unsigned int value = MICBIAS_2_0V;
1183 int ret;
1184
1185 of_property_read_u32(np, "ai31xx-micbias-vg", &value);
1186 switch (value) {
1187 case MICBIAS_2_0V:
1188 case MICBIAS_2_5V:
1189 case MICBIAS_AVDDV:
1190 aic31xx->pdata.micbias_vg = value;
1191 break;
1192 default:
1193 dev_err(aic31xx->dev,
1194 "Bad ai31xx-micbias-vg value %d DT\n",
1195 value);
1196 aic31xx->pdata.micbias_vg = MICBIAS_2_0V;
1197 }
1198
1199 ret = of_get_named_gpio(np, "gpio-reset", 0);
1200 if (ret > 0)
1201 aic31xx->pdata.gpio_reset = ret;
1202}
1203#else /* CONFIG_OF */
1204static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1205{
1206}
1207#endif /* CONFIG_OF */
1208
a72d2abb 1209static int aic31xx_device_init(struct aic31xx_priv *aic31xx)
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JS		 1210{
1211 int ret, i;
1212
1213 dev_set_drvdata(aic31xx->dev, aic31xx);
1214
1215 if (dev_get_platdata(aic31xx->dev))
1216 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev),
1217 sizeof(aic31xx->pdata));
1218 else if (aic31xx->dev->of_node)
1219 aic31xx_pdata_from_of(aic31xx);
1220
1221 if (aic31xx->pdata.gpio_reset) {
1222 ret = devm_gpio_request_one(aic31xx->dev,
1223 aic31xx->pdata.gpio_reset,
1224 GPIOF_OUT_INIT_HIGH,
1225 "aic31xx-reset-pin");
1226 if (ret < 0) {
1227 dev_err(aic31xx->dev, "not able to acquire gpio\n");
a72d2abb 1228 return ret;
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JS		 1229 }
1230 }
1231
1232 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1233 aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1234
1235 ret = devm_regulator_bulk_get(aic31xx->dev,
1236 ARRAY_SIZE(aic31xx->supplies),
1237 aic31xx->supplies);
1238 if (ret != 0)
1239 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret);
1240
a72d2abb 1241 return ret;
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JS		 1242}
1243
1244static int aic31xx_i2c_probe(struct i2c_client *i2c,
1245 const struct i2c_device_id *id)
1246{
1247 struct aic31xx_priv *aic31xx;
1248 int ret;
1249 const struct regmap_config *regmap_config;
1250
1251 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1252 id->name, (int) id->driver_data);
1253
1254 regmap_config = &aic31xx_i2c_regmap;
1255
1256 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
1257 if (aic31xx == NULL)
1258 return -ENOMEM;
1259
1260 aic31xx->regmap = devm_regmap_init_i2c(i2c, regmap_config);
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JS		 1261 if (IS_ERR(aic31xx->regmap)) {
1262 ret = PTR_ERR(aic31xx->regmap);
1263 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1264 ret);
1265 return ret;
1266 }
1267 aic31xx->dev = &i2c->dev;
1268
1269 aic31xx->pdata.codec_type = id->driver_data;
1270
a72d2abb
PU		 1271 ret = aic31xx_device_init(aic31xx);
1272 if (ret)
1273 return ret;
e00447fa 1274
dac7e404 1275 return snd_soc_register_codec(&i2c->dev, &soc_codec_driver_aic31xx,
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JS		 1276 aic31xx_dai_driver,
1277 ARRAY_SIZE(aic31xx_dai_driver));
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JS		 1278}
1279
1280static int aic31xx_i2c_remove(struct i2c_client *i2c)
1281{
dac7e404 1282 snd_soc_unregister_codec(&i2c->dev);
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JS		 1283 return 0;
1284}
1285
1286static const struct i2c_device_id aic31xx_i2c_id[] = {
1287 { "tlv320aic310x", AIC3100 },
1288 { "tlv320aic311x", AIC3110 },
1289 { "tlv320aic3100", AIC3100 },
1290 { "tlv320aic3110", AIC3110 },
1291 { "tlv320aic3120", AIC3120 },
1292 { "tlv320aic3111", AIC3111 },
1293 { }
1294};
1295MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1296
1297static struct i2c_driver aic31xx_i2c_driver = {
1298 .driver = {
1299 .name = "tlv320aic31xx-codec",
1300 .owner = THIS_MODULE,
1301 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
1302 },
1303 .probe = aic31xx_i2c_probe,
dac7e404 1304 .remove = aic31xx_i2c_remove,
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JS		 1305 .id_table = aic31xx_i2c_id,
1306};
1307
1308module_i2c_driver(aic31xx_i2c_driver);
1309
1310MODULE_DESCRIPTION("ASoC TLV320AIC3111 codec driver");
1311MODULE_AUTHOR("Jyri Sarha");
1312MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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