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Linux 4.6-rc1
[deliverable/linux.git] / sound / soc / codecs / tlv320aic31xx.c
CommitLineData
e00447fa
JS		 1/*
2 * ALSA SoC TLV320AIC31XX codec driver
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc.
5 *
6 * Author: Jyri Sarha <jsarha@ti.com>
7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * THIS PACKAGE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 *
18 * The TLV320AIC31xx series of audio codec is a low-power, highly integrated
19 * high performance codec which provides a stereo DAC, a mono ADC,
20 * and mono/stereo Class-D speaker driver.
21 */
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/pm.h>
28#include <linux/i2c.h>
29#include <linux/gpio.h>
30#include <linux/regulator/consumer.h>
0faabc4f 31#include <linux/of.h>
e00447fa
JS		 32#include <linux/of_gpio.h>
33#include <linux/slab.h>
34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/initval.h>
39#include <sound/tlv.h>
40#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
41
42#include "tlv320aic31xx.h"
43
44static const struct reg_default aic31xx_reg_defaults[] = {
45 { AIC31XX_CLKMUX, 0x00 },
46 { AIC31XX_PLLPR, 0x11 },
47 { AIC31XX_PLLJ, 0x04 },
48 { AIC31XX_PLLDMSB, 0x00 },
49 { AIC31XX_PLLDLSB, 0x00 },
50 { AIC31XX_NDAC, 0x01 },
51 { AIC31XX_MDAC, 0x01 },
52 { AIC31XX_DOSRMSB, 0x00 },
53 { AIC31XX_DOSRLSB, 0x80 },
54 { AIC31XX_NADC, 0x01 },
55 { AIC31XX_MADC, 0x01 },
56 { AIC31XX_AOSR, 0x80 },
57 { AIC31XX_IFACE1, 0x00 },
58 { AIC31XX_DATA_OFFSET, 0x00 },
59 { AIC31XX_IFACE2, 0x00 },
60 { AIC31XX_BCLKN, 0x01 },
61 { AIC31XX_DACSETUP, 0x14 },
62 { AIC31XX_DACMUTE, 0x0c },
63 { AIC31XX_LDACVOL, 0x00 },
64 { AIC31XX_RDACVOL, 0x00 },
65 { AIC31XX_ADCSETUP, 0x00 },
66 { AIC31XX_ADCFGA, 0x80 },
67 { AIC31XX_ADCVOL, 0x00 },
68 { AIC31XX_HPDRIVER, 0x04 },
69 { AIC31XX_SPKAMP, 0x06 },
70 { AIC31XX_DACMIXERROUTE, 0x00 },
71 { AIC31XX_LANALOGHPL, 0x7f },
72 { AIC31XX_RANALOGHPR, 0x7f },
73 { AIC31XX_LANALOGSPL, 0x7f },
74 { AIC31XX_RANALOGSPR, 0x7f },
75 { AIC31XX_HPLGAIN, 0x02 },
76 { AIC31XX_HPRGAIN, 0x02 },
77 { AIC31XX_SPLGAIN, 0x00 },
78 { AIC31XX_SPRGAIN, 0x00 },
79 { AIC31XX_MICBIAS, 0x00 },
80 { AIC31XX_MICPGA, 0x80 },
81 { AIC31XX_MICPGAPI, 0x00 },
82 { AIC31XX_MICPGAMI, 0x00 },
83};
84
85static bool aic31xx_volatile(struct device *dev, unsigned int reg)
86{
87 switch (reg) {
88 case AIC31XX_PAGECTL: /* regmap implementation requires this */
89 case AIC31XX_RESET: /* always clears after write */
90 case AIC31XX_OT_FLAG:
91 case AIC31XX_ADCFLAG:
92 case AIC31XX_DACFLAG1:
93 case AIC31XX_DACFLAG2:
94 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
95 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
96 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
97 case AIC31XX_INTRDACFLAG2:
98 case AIC31XX_INTRADCFLAG2:
99 return true;
100 }
101 return false;
102}
103
104static bool aic31xx_writeable(struct device *dev, unsigned int reg)
105{
106 switch (reg) {
107 case AIC31XX_OT_FLAG:
108 case AIC31XX_ADCFLAG:
109 case AIC31XX_DACFLAG1:
110 case AIC31XX_DACFLAG2:
111 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
112 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
113 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
114 case AIC31XX_INTRDACFLAG2:
115 case AIC31XX_INTRADCFLAG2:
116 return false;
117 }
118 return true;
119}
120
121static const struct regmap_range_cfg aic31xx_ranges[] = {
122 {
123 .range_min = 0,
124 .range_max = 12 * 128,
125 .selector_reg = AIC31XX_PAGECTL,
126 .selector_mask = 0xff,
127 .selector_shift = 0,
128 .window_start = 0,
129 .window_len = 128,
130 },
131};
132
9296f4da 133static const struct regmap_config aic31xx_i2c_regmap = {
e00447fa
JS		 134 .reg_bits = 8,
135 .val_bits = 8,
136 .writeable_reg = aic31xx_writeable,
137 .volatile_reg = aic31xx_volatile,
138 .reg_defaults = aic31xx_reg_defaults,
139 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
140 .cache_type = REGCACHE_RBTREE,
141 .ranges = aic31xx_ranges,
142 .num_ranges = ARRAY_SIZE(aic31xx_ranges),
143 .max_register = 12 * 128,
144};
145
146#define AIC31XX_NUM_SUPPLIES 6
147static const char * const aic31xx_supply_names[AIC31XX_NUM_SUPPLIES] = {
148 "HPVDD",
149 "SPRVDD",
150 "SPLVDD",
151 "AVDD",
152 "IOVDD",
153 "DVDD",
154};
155
156struct aic31xx_disable_nb {
157 struct notifier_block nb;
158 struct aic31xx_priv *aic31xx;
159};
160
161struct aic31xx_priv {
162 struct snd_soc_codec *codec;
163 u8 i2c_regs_status;
164 struct device *dev;
165 struct regmap *regmap;
166 struct aic31xx_pdata pdata;
167 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
168 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
169 unsigned int sysclk;
7ed36e96 170 u8 p_div;
e00447fa
JS		 171 int rate_div_line;
172};
173
174struct aic31xx_rate_divs {
7ed36e96 175 u32 mclk_p;
e00447fa 176 u32 rate;
e00447fa
JS		 177 u8 pll_j;
178 u16 pll_d;
179 u16 dosr;
180 u8 ndac;
181 u8 mdac;
182 u8 aosr;
183 u8 nadc;
184 u8 madc;
185};
186
187/* ADC dividers can be disabled by cofiguring them to 0 */
188static const struct aic31xx_rate_divs aic31xx_divs[] = {
7ed36e96 189 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
e00447fa 190 /* 8k rate */
7ed36e96
JS		 191 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
192 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
193 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
e00447fa 194 /* 11.025k rate */
7ed36e96
JS		 195 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
196 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
197 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
e00447fa 198 /* 16k rate */
7ed36e96
JS		 199 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
200 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
201 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
e00447fa 202 /* 22.05k rate */
7ed36e96
JS		 203 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
204 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
205 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
e00447fa 206 /* 32k rate */
7ed36e96
JS		 207 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
208 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
209 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
e00447fa 210 /* 44.1k rate */
7ed36e96
JS		 211 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
212 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
213 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
e00447fa 214 /* 48k rate */
7ed36e96
JS		 215 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
216 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
217 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
e00447fa 218 /* 88.2k rate */
7ed36e96
JS		 219 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
220 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
221 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
e00447fa 222 /* 96k rate */
7ed36e96
JS		 223 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
224 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
225 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
e00447fa 226 /* 176.4k rate */
7ed36e96
JS		 227 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
228 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
229 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
e00447fa 230 /* 192k rate */
7ed36e96
JS		 231 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
232 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
233 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
e00447fa
JS		 234};
235
236static const char * const ldac_in_text[] = {
237 "Off", "Left Data", "Right Data", "Mono"
238};
239
240static const char * const rdac_in_text[] = {
241 "Off", "Right Data", "Left Data", "Mono"
242};
243
244static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
245
246static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
247
248static const char * const mic_select_text[] = {
249 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
250};
251
914bc160
LPC		 252static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
253 mic_select_text);
254static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
255 mic_select_text);
256static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
257 mic_select_text);
e00447fa 258
914bc160
LPC		 259static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text);
260static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
261 mic_select_text);
e00447fa
JS		 262
263static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
264static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
265static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
266static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
267static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
268static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
269static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
270static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
271
272/*
273 * controls to be exported to the user space
274 */
275static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
276 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
277 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
278
279 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
280 adc_fgain_tlv),
281
282 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
283 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
284 0, -24, 40, 6, 0, adc_cgain_tlv),
285
286 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
287 119, 0, mic_pga_tlv),
288
289 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
290 AIC31XX_HPRGAIN, 2, 1, 0),
291 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
292 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
293
294 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
295 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
296};
297
298static const struct snd_kcontrol_new aic311x_snd_controls[] = {
299 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
300 AIC31XX_SPRGAIN, 2, 1, 0),
301 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
302 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
303
304 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
305 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
306};
307
308static const struct snd_kcontrol_new aic310x_snd_controls[] = {
309 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
310 2, 1, 0),
311 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
312 3, 3, 0, class_D_drv_tlv),
313
314 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
315 0, 0x7F, 1, sp_vol_tlv),
316};
317
318static const struct snd_kcontrol_new ldac_in_control =
319 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
320
321static const struct snd_kcontrol_new rdac_in_control =
322 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
323
9296f4da
MB		 324static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
325 unsigned int mask, unsigned int wbits, int sleep,
326 int count)
e00447fa
JS		 327{
328 unsigned int bits;
329 int counter = count;
330 int ret = regmap_read(aic31xx->regmap, reg, &bits);
423ca88e 331
e00447fa
JS		 332 while ((bits & mask) != wbits && counter && !ret) {
333 usleep_range(sleep, sleep * 2);
334 ret = regmap_read(aic31xx->regmap, reg, &bits);
335 counter--;
336 }
337 if ((bits & mask) != wbits) {
338 dev_err(aic31xx->dev,
339 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
340 __func__, reg, bits, wbits, ret, mask,
341 (count - counter) * sleep);
342 ret = -1;
343 }
344 return ret;
345}
346
347#define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
348
349static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
350 struct snd_kcontrol *kcontrol, int event)
351{
dd943d36
LPC		 352 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
353 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
e00447fa
JS		 354 unsigned int reg = AIC31XX_DACFLAG1;
355 unsigned int mask;
356
357 switch (WIDGET_BIT(w->reg, w->shift)) {
358 case WIDGET_BIT(AIC31XX_DACSETUP, 7):
359 mask = AIC31XX_LDACPWRSTATUS_MASK;
360 break;
361 case WIDGET_BIT(AIC31XX_DACSETUP, 6):
362 mask = AIC31XX_RDACPWRSTATUS_MASK;
363 break;
364 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
365 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
366 break;
367 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
368 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
369 break;
370 case WIDGET_BIT(AIC31XX_SPKAMP, 7):
371 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
372 break;
373 case WIDGET_BIT(AIC31XX_SPKAMP, 6):
374 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
375 break;
376 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
377 mask = AIC31XX_ADCPWRSTATUS_MASK;
378 reg = AIC31XX_ADCFLAG;
379 break;
380 default:
dd943d36 381 dev_err(codec->dev, "Unknown widget '%s' calling %s\n",
e00447fa
JS		 382 w->name, __func__);
383 return -EINVAL;
384 }
385
386 switch (event) {
387 case SND_SOC_DAPM_POST_PMU:
388 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100);
389 case SND_SOC_DAPM_POST_PMD:
390 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100);
391 default:
dd943d36 392 dev_dbg(codec->dev,
e00447fa
JS		 393 "Unhandled dapm widget event %d from %s\n",
394 event, w->name);
395 }
396 return 0;
397}
398
399static const struct snd_kcontrol_new left_output_switches[] = {
400 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
401 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
402 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
403};
404
405static const struct snd_kcontrol_new right_output_switches[] = {
406 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
407 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
408};
409
410static const struct snd_kcontrol_new p_term_mic1lp =
411 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
412
413static const struct snd_kcontrol_new p_term_mic1rp =
414 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
415
416static const struct snd_kcontrol_new p_term_mic1lm =
417 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
418
419static const struct snd_kcontrol_new m_term_mic1lm =
420 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
421
422static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
423 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
424
425static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
426 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
427
428static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
429 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
430
431static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
432 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
433
434static int mic_bias_event(struct snd_soc_dapm_widget *w,
435 struct snd_kcontrol *kcontrol, int event)
436{
dd943d36 437 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e00447fa 438 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
423ca88e 439
e00447fa
JS		 440 switch (event) {
441 case SND_SOC_DAPM_POST_PMU:
442 /* change mic bias voltage to user defined */
443 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
444 AIC31XX_MICBIAS_MASK,
445 aic31xx->pdata.micbias_vg <<
446 AIC31XX_MICBIAS_SHIFT);
447 dev_dbg(codec->dev, "%s: turned on\n", __func__);
448 break;
449 case SND_SOC_DAPM_PRE_PMD:
450 /* turn mic bias off */
451 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
452 AIC31XX_MICBIAS_MASK, 0);
453 dev_dbg(codec->dev, "%s: turned off\n", __func__);
454 break;
455 }
456 return 0;
457}
458
459static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
460 SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0),
461
462 SND_SOC_DAPM_MUX("DAC Left Input",
463 SND_SOC_NOPM, 0, 0, &ldac_in_control),
464 SND_SOC_DAPM_MUX("DAC Right Input",
465 SND_SOC_NOPM, 0, 0, &rdac_in_control),
466 /* DACs */
467 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
468 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
469 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
470
471 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
472 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
473 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
474
475 /* Output Mixers */
476 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
477 left_output_switches,
478 ARRAY_SIZE(left_output_switches)),
479 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
480 right_output_switches,
481 ARRAY_SIZE(right_output_switches)),
482
483 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
484 &aic31xx_dapm_hpl_switch),
485 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
486 &aic31xx_dapm_hpr_switch),
487
488 /* Output drivers */
489 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
490 NULL, 0, aic31xx_dapm_power_event,
491 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
492 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
493 NULL, 0, aic31xx_dapm_power_event,
494 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
495
496 /* ADC */
497 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
498 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
499 SND_SOC_DAPM_POST_PMD),
500
501 /* Input Selection to MIC_PGA */
502 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
503 &p_term_mic1lp),
504 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
505 &p_term_mic1rp),
506 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
507 &p_term_mic1lm),
508
509 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
510 &m_term_mic1lm),
511 /* Enabling & Disabling MIC Gain Ctl */
512 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
513 7, 1, NULL, 0),
514
515 /* Mic Bias */
516 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
517 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
518
519 /* Outputs */
520 SND_SOC_DAPM_OUTPUT("HPL"),
521 SND_SOC_DAPM_OUTPUT("HPR"),
522
523 /* Inputs */
524 SND_SOC_DAPM_INPUT("MIC1LP"),
525 SND_SOC_DAPM_INPUT("MIC1RP"),
526 SND_SOC_DAPM_INPUT("MIC1LM"),
527};
528
529static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
530 /* AIC3111 and AIC3110 have stereo class-D amplifier */
531 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
532 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
533 SND_SOC_DAPM_POST_PMD),
534 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
535 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
536 SND_SOC_DAPM_POST_PMD),
537 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
538 &aic31xx_dapm_spl_switch),
539 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
540 &aic31xx_dapm_spr_switch),
541 SND_SOC_DAPM_OUTPUT("SPL"),
542 SND_SOC_DAPM_OUTPUT("SPR"),
543};
544
545/* AIC3100 and AIC3120 have only mono class-D amplifier */
546static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
547 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
548 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
549 SND_SOC_DAPM_POST_PMD),
550 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
551 &aic31xx_dapm_spl_switch),
552 SND_SOC_DAPM_OUTPUT("SPK"),
553};
554
555static const struct snd_soc_dapm_route
556aic31xx_audio_map[] = {
557 /* DAC Input Routing */
558 {"DAC Left Input", "Left Data", "DAC IN"},
559 {"DAC Left Input", "Right Data", "DAC IN"},
560 {"DAC Left Input", "Mono", "DAC IN"},
561 {"DAC Right Input", "Left Data", "DAC IN"},
562 {"DAC Right Input", "Right Data", "DAC IN"},
563 {"DAC Right Input", "Mono", "DAC IN"},
564 {"DAC Left", NULL, "DAC Left Input"},
565 {"DAC Right", NULL, "DAC Right Input"},
566
567 /* Mic input */
568 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
569 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
570 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
571 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
572 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
573 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
574 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
575 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
576 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
577
578 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
579 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
580 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
581
582 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
583 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
584 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
585 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
586
587 {"ADC", NULL, "MIC_GAIN_CTL"},
588
589 /* Left Output */
590 {"Output Left", "From Left DAC", "DAC Left"},
591 {"Output Left", "From MIC1LP", "MIC1LP"},
592 {"Output Left", "From MIC1RP", "MIC1RP"},
593
594 /* Right Output */
595 {"Output Right", "From Right DAC", "DAC Right"},
596 {"Output Right", "From MIC1RP", "MIC1RP"},
597
598 /* HPL path */
599 {"HP Left", "Switch", "Output Left"},
600 {"HPL Driver", NULL, "HP Left"},
601 {"HPL", NULL, "HPL Driver"},
602
603 /* HPR path */
604 {"HP Right", "Switch", "Output Right"},
605 {"HPR Driver", NULL, "HP Right"},
606 {"HPR", NULL, "HPR Driver"},
607};
608
609static const struct snd_soc_dapm_route
610aic311x_audio_map[] = {
611 /* SP L path */
612 {"Speaker Left", "Switch", "Output Left"},
613 {"SPL ClassD", NULL, "Speaker Left"},
614 {"SPL", NULL, "SPL ClassD"},
615
616 /* SP R path */
617 {"Speaker Right", "Switch", "Output Right"},
618 {"SPR ClassD", NULL, "Speaker Right"},
619 {"SPR", NULL, "SPR ClassD"},
620};
621
622static const struct snd_soc_dapm_route
623aic310x_audio_map[] = {
624 /* SP L path */
625 {"Speaker", "Switch", "Output Left"},
626 {"SPK ClassD", NULL, "Speaker"},
627 {"SPK", NULL, "SPK ClassD"},
628};
629
630static int aic31xx_add_controls(struct snd_soc_codec *codec)
631{
632 int ret = 0;
633 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
634
635 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT)
636 ret = snd_soc_add_codec_controls(
637 codec, aic311x_snd_controls,
638 ARRAY_SIZE(aic311x_snd_controls));
639 else
640 ret = snd_soc_add_codec_controls(
641 codec, aic310x_snd_controls,
642 ARRAY_SIZE(aic310x_snd_controls));
643
644 return ret;
645}
646
647static int aic31xx_add_widgets(struct snd_soc_codec *codec)
648{
378d1e43 649 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
e00447fa
JS		 650 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
651 int ret = 0;
652
653 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
654 ret = snd_soc_dapm_new_controls(
655 dapm, aic311x_dapm_widgets,
656 ARRAY_SIZE(aic311x_dapm_widgets));
657 if (ret)
658 return ret;
659
660 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
661 ARRAY_SIZE(aic311x_audio_map));
662 if (ret)
663 return ret;
664 } else {
665 ret = snd_soc_dapm_new_controls(
666 dapm, aic310x_dapm_widgets,
667 ARRAY_SIZE(aic310x_dapm_widgets));
668 if (ret)
669 return ret;
670
671 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
672 ARRAY_SIZE(aic310x_audio_map));
673 if (ret)
674 return ret;
675 }
676
677 return 0;
678}
679
680static int aic31xx_setup_pll(struct snd_soc_codec *codec,
681 struct snd_pcm_hw_params *params)
682{
683 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
03be88ee 684 int bclk_score = snd_soc_params_to_frame_size(params);
7ed36e96 685 int mclk_p = aic31xx->sysclk / aic31xx->p_div;
e00447fa 686 int bclk_n = 0;
03be88ee 687 int match = -1;
e00447fa
JS		 688 int i;
689
690 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
691 snd_soc_update_bits(codec, AIC31XX_CLKMUX,
692 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
693 snd_soc_update_bits(codec, AIC31XX_IFACE2,
694 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
695
696 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
697 if (aic31xx_divs[i].rate == params_rate(params) &&
7ed36e96 698 aic31xx_divs[i].mclk_p == mclk_p) {
03be88ee
JS		 699 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
700 snd_soc_params_to_frame_size(params);
701 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
702 snd_soc_params_to_frame_size(params);
703 if (s < bclk_score && bn > 0) {
704 match = i;
705 bclk_n = bn;
706 bclk_score = s;
707 }
708 }
e00447fa
JS		 709 }
710
03be88ee
JS		 711 if (match == -1) {
712 dev_err(codec->dev,
713 "%s: Sample rate (%u) and format not supported\n",
e00447fa 714 __func__, params_rate(params));
03be88ee 715 /* See bellow for details how fix this. */
e00447fa
JS		 716 return -EINVAL;
717 }
03be88ee
JS		 718 if (bclk_score != 0) {
719 dev_warn(codec->dev, "Can not produce exact bitclock");
720 /* This is fine if using dsp format, but if using i2s
721 there may be trouble. To fix the issue edit the
722 aic31xx_divs table for your mclk and sample
723 rate. Details can be found from:
724 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
725 Section: 5.6 CLOCK Generation and PLL
726 */
727 }
728 i = match;
e00447fa
JS		 729
730 /* PLL configuration */
731 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
7ed36e96 732 (aic31xx->p_div << 4) | 0x01);
e00447fa
JS		 733 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
734
735 snd_soc_write(codec, AIC31XX_PLLDMSB,
736 aic31xx_divs[i].pll_d >> 8);
737 snd_soc_write(codec, AIC31XX_PLLDLSB,
738 aic31xx_divs[i].pll_d & 0xff);
739
740 /* DAC dividers configuration */
741 snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK,
742 aic31xx_divs[i].ndac);
743 snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK,
744 aic31xx_divs[i].mdac);
745
746 snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
747 snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
748
749 /* ADC dividers configuration. Write reset value 1 if not used. */
750 snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK,
751 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
752 snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK,
753 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
754
755 snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr);
756
757 /* Bit clock divider configuration. */
e00447fa
JS		 758 snd_soc_update_bits(codec, AIC31XX_BCLKN,
759 AIC31XX_PLL_MASK, bclk_n);
760
761 aic31xx->rate_div_line = i;
762
763 dev_dbg(codec->dev,
764 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
765 aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d,
7ed36e96 766 aic31xx->p_div, aic31xx_divs[i].dosr,
e00447fa
JS		 767 aic31xx_divs[i].ndac, aic31xx_divs[i].mdac,
768 aic31xx_divs[i].aosr, aic31xx_divs[i].nadc,
769 aic31xx_divs[i].madc, bclk_n);
770
771 return 0;
772}
773
774static int aic31xx_hw_params(struct snd_pcm_substream *substream,
775 struct snd_pcm_hw_params *params,
ab64246c 776 struct snd_soc_dai *dai)
e00447fa 777{
ab64246c 778 struct snd_soc_codec *codec = dai->codec;
e00447fa
JS		 779 u8 data = 0;
780
88be681b
MB		 781 dev_dbg(codec->dev, "## %s: width %d rate %d\n",
782 __func__, params_width(params),
e00447fa
JS		 783 params_rate(params));
784
785 switch (params_width(params)) {
786 case 16:
787 break;
788 case 20:
789 data = (AIC31XX_WORD_LEN_20BITS <<
790 AIC31XX_IFACE1_DATALEN_SHIFT);
791 break;
792 case 24:
793 data = (AIC31XX_WORD_LEN_24BITS <<
794 AIC31XX_IFACE1_DATALEN_SHIFT);
795 break;
796 case 32:
797 data = (AIC31XX_WORD_LEN_32BITS <<
798 AIC31XX_IFACE1_DATALEN_SHIFT);
799 break;
800 default:
88be681b
MB		 801 dev_err(codec->dev, "%s: Unsupported width %d\n",
802 __func__, params_width(params));
e00447fa
JS		 803 return -EINVAL;
804 }
805
806 snd_soc_update_bits(codec, AIC31XX_IFACE1,
807 AIC31XX_IFACE1_DATALEN_MASK,
808 data);
809
810 return aic31xx_setup_pll(codec, params);
811}
812
813static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute)
814{
815 struct snd_soc_codec *codec = codec_dai->codec;
816
817 if (mute) {
818 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
819 AIC31XX_DACMUTE_MASK,
820 AIC31XX_DACMUTE_MASK);
821 } else {
822 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
823 AIC31XX_DACMUTE_MASK, 0x0);
824 }
825
826 return 0;
827}
828
829static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
830 unsigned int fmt)
831{
832 struct snd_soc_codec *codec = codec_dai->codec;
833 u8 iface_reg1 = 0;
085f3ec6 834 u8 iface_reg2 = 0;
e00447fa
JS		 835 u8 dsp_a_val = 0;
836
837 dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
838
839 /* set master/slave audio interface */
840 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
841 case SND_SOC_DAIFMT_CBM_CFM:
842 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
843 break;
844 default:
845 dev_alert(codec->dev, "Invalid DAI master/slave interface\n");
846 return -EINVAL;
847 }
848
849 /* interface format */
850 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
851 case SND_SOC_DAIFMT_I2S:
852 break;
853 case SND_SOC_DAIFMT_DSP_A:
854 dsp_a_val = 0x1;
855 case SND_SOC_DAIFMT_DSP_B:
856 /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */
857 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
858 case SND_SOC_DAIFMT_NB_NF:
085f3ec6 859 iface_reg2 |= AIC31XX_BCLKINV_MASK;
e00447fa
JS		 860 break;
861 case SND_SOC_DAIFMT_IB_NF:
862 break;
863 default:
864 return -EINVAL;
865 }
866 iface_reg1 |= (AIC31XX_DSP_MODE <<
867 AIC31XX_IFACE1_DATATYPE_SHIFT);
868 break;
869 case SND_SOC_DAIFMT_RIGHT_J:
870 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
871 AIC31XX_IFACE1_DATATYPE_SHIFT);
872 break;
873 case SND_SOC_DAIFMT_LEFT_J:
874 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
875 AIC31XX_IFACE1_DATATYPE_SHIFT);
876 break;
877 default:
878 dev_err(codec->dev, "Invalid DAI interface format\n");
879 return -EINVAL;
880 }
881
882 snd_soc_update_bits(codec, AIC31XX_IFACE1,
883 AIC31XX_IFACE1_DATATYPE_MASK |
884 AIC31XX_IFACE1_MASTER_MASK,
885 iface_reg1);
886 snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET,
887 AIC31XX_DATA_OFFSET_MASK,
888 dsp_a_val);
889 snd_soc_update_bits(codec, AIC31XX_IFACE2,
890 AIC31XX_BCLKINV_MASK,
085f3ec6 891 iface_reg2);
e00447fa
JS		 892
893 return 0;
894}
895
896static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
897 int clk_id, unsigned int freq, int dir)
898{
899 struct snd_soc_codec *codec = codec_dai->codec;
900 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
901 int i;
902
903 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
904 __func__, clk_id, freq, dir);
905
7ed36e96
JS		 906 for (i = 1; freq/i > 20000000 && i < 8; i++)
907 ;
908 if (freq/i > 20000000) {
909 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
910 __func__, freq);
911 return -EINVAL;
912 }
913 aic31xx->p_div = i;
914
bbc686b3
JS		 915 for (i = 0; i < ARRAY_SIZE(aic31xx_divs) &&
916 aic31xx_divs[i].mclk_p != freq/aic31xx->p_div; i++)
917 ;
918 if (i == ARRAY_SIZE(aic31xx_divs)) {
919 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
920 __func__, freq);
921 return -EINVAL;
e00447fa
JS		 922 }
923
924 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
925 snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
926 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
927
928 aic31xx->sysclk = freq;
929 return 0;
930}
931
932static int aic31xx_regulator_event(struct notifier_block *nb,
933 unsigned long event, void *data)
934{
935 struct aic31xx_disable_nb *disable_nb =
936 container_of(nb, struct aic31xx_disable_nb, nb);
937 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
938
939 if (event & REGULATOR_EVENT_DISABLE) {
940 /*
941 * Put codec to reset and as at least one of the
942 * supplies was disabled.
943 */
944 if (gpio_is_valid(aic31xx->pdata.gpio_reset))
945 gpio_set_value(aic31xx->pdata.gpio_reset, 0);
946
947 regcache_mark_dirty(aic31xx->regmap);
948 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
949 }
950
951 return 0;
952}
953
954static void aic31xx_clk_on(struct snd_soc_codec *codec)
955{
956 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
957 u8 mask = AIC31XX_PM_MASK;
958 u8 on = AIC31XX_PM_MASK;
959
960 dev_dbg(codec->dev, "codec clock -> on (rate %d)\n",
961 aic31xx_divs[aic31xx->rate_div_line].rate);
962 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on);
963 mdelay(10);
964 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on);
965 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on);
966 if (aic31xx_divs[aic31xx->rate_div_line].nadc)
967 snd_soc_update_bits(codec, AIC31XX_NADC, mask, on);
968 if (aic31xx_divs[aic31xx->rate_div_line].madc)
969 snd_soc_update_bits(codec, AIC31XX_MADC, mask, on);
970 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on);
971}
972
973static void aic31xx_clk_off(struct snd_soc_codec *codec)
974{
e00447fa
JS		 975 u8 mask = AIC31XX_PM_MASK;
976 u8 off = 0;
977
978 dev_dbg(codec->dev, "codec clock -> off\n");
979 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off);
980 snd_soc_update_bits(codec, AIC31XX_MADC, mask, off);
981 snd_soc_update_bits(codec, AIC31XX_NADC, mask, off);
982 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off);
983 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off);
984 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off);
985}
986
987static int aic31xx_power_on(struct snd_soc_codec *codec)
988{
989 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
990 int ret = 0;
991
992 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
993 aic31xx->supplies);
994 if (ret)
995 return ret;
996
997 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) {
998 gpio_set_value(aic31xx->pdata.gpio_reset, 1);
999 udelay(100);
1000 }
1001 regcache_cache_only(aic31xx->regmap, false);
1002 ret = regcache_sync(aic31xx->regmap);
1003 if (ret != 0) {
1004 dev_err(codec->dev,
1005 "Failed to restore cache: %d\n", ret);
1006 regcache_cache_only(aic31xx->regmap, true);
1007 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1008 aic31xx->supplies);
1009 return ret;
1010 }
1011 return 0;
1012}
1013
1014static int aic31xx_power_off(struct snd_soc_codec *codec)
1015{
1016 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1017 int ret = 0;
1018
1019 regcache_cache_only(aic31xx->regmap, true);
1020 ret = regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1021 aic31xx->supplies);
1022
1023 return ret;
1024}
1025
1026static int aic31xx_set_bias_level(struct snd_soc_codec *codec,
1027 enum snd_soc_bias_level level)
1028{
1029 dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__,
378d1e43 1030 snd_soc_codec_get_bias_level(codec), level);
e00447fa
JS		 1031
1032 switch (level) {
1033 case SND_SOC_BIAS_ON:
1034 break;
1035 case SND_SOC_BIAS_PREPARE:
378d1e43 1036 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
e00447fa
JS		 1037 aic31xx_clk_on(codec);
1038 break;
1039 case SND_SOC_BIAS_STANDBY:
378d1e43 1040 switch (snd_soc_codec_get_bias_level(codec)) {
e00447fa
JS		 1041 case SND_SOC_BIAS_OFF:
1042 aic31xx_power_on(codec);
1043 break;
1044 case SND_SOC_BIAS_PREPARE:
1045 aic31xx_clk_off(codec);
1046 break;
1047 default:
1048 BUG();
1049 }
1050 break;
1051 case SND_SOC_BIAS_OFF:
378d1e43 1052 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
fd218aa3 1053 aic31xx_power_off(codec);
e00447fa
JS		 1054 break;
1055 }
e00447fa
JS		 1056
1057 return 0;
1058}
1059
e00447fa
JS		 1060static int aic31xx_codec_probe(struct snd_soc_codec *codec)
1061{
1062 int ret = 0;
1063 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1064 int i;
1065
1066 dev_dbg(aic31xx->dev, "## %s\n", __func__);
1067
1068 aic31xx = snd_soc_codec_get_drvdata(codec);
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JS		 1069
1070 aic31xx->codec = codec;
1071
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JS		 1072 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1073 aic31xx->disable_nb[i].nb.notifier_call =
1074 aic31xx_regulator_event;
1075 aic31xx->disable_nb[i].aic31xx = aic31xx;
1076 ret = regulator_register_notifier(aic31xx->supplies[i].consumer,
1077 &aic31xx->disable_nb[i].nb);
1078 if (ret) {
1079 dev_err(codec->dev,
1080 "Failed to request regulator notifier: %d\n",
1081 ret);
1082 return ret;
1083 }
1084 }
1085
1086 regcache_cache_only(aic31xx->regmap, true);
1087 regcache_mark_dirty(aic31xx->regmap);
1088
1089 ret = aic31xx_add_controls(codec);
1090 if (ret)
1091 return ret;
1092
1093 ret = aic31xx_add_widgets(codec);
1094
1095 return ret;
1096}
1097
1098static int aic31xx_codec_remove(struct snd_soc_codec *codec)
1099{
1100 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1101 int i;
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JS		 1102
1103 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1104 regulator_unregister_notifier(aic31xx->supplies[i].consumer,
1105 &aic31xx->disable_nb[i].nb);
1106
1107 return 0;
1108}
1109
1110static struct snd_soc_codec_driver soc_codec_driver_aic31xx = {
1111 .probe = aic31xx_codec_probe,
1112 .remove = aic31xx_codec_remove,
e00447fa 1113 .set_bias_level = aic31xx_set_bias_level,
a43a2629
LPC		 1114 .suspend_bias_off = true,
1115
e00447fa
JS		 1116 .controls = aic31xx_snd_controls,
1117 .num_controls = ARRAY_SIZE(aic31xx_snd_controls),
1118 .dapm_widgets = aic31xx_dapm_widgets,
1119 .num_dapm_widgets = ARRAY_SIZE(aic31xx_dapm_widgets),
1120 .dapm_routes = aic31xx_audio_map,
1121 .num_dapm_routes = ARRAY_SIZE(aic31xx_audio_map),
1122};
1123
64793047 1124static const struct snd_soc_dai_ops aic31xx_dai_ops = {
e00447fa
JS		 1125 .hw_params = aic31xx_hw_params,
1126 .set_sysclk = aic31xx_set_dai_sysclk,
1127 .set_fmt = aic31xx_set_dai_fmt,
1128 .digital_mute = aic31xx_dac_mute,
1129};
1130
1131static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1132 {
1133 .name = "tlv320aic31xx-hifi",
1134 .playback = {
1135 .stream_name = "Playback",
1136 .channels_min = 1,
1137 .channels_max = 2,
1138 .rates = AIC31XX_RATES,
1139 .formats = AIC31XX_FORMATS,
1140 },
1141 .capture = {
1142 .stream_name = "Capture",
1143 .channels_min = 1,
1144 .channels_max = 2,
1145 .rates = AIC31XX_RATES,
1146 .formats = AIC31XX_FORMATS,
1147 },
1148 .ops = &aic31xx_dai_ops,
1149 .symmetric_rates = 1,
1150 }
1151};
1152
1153#if defined(CONFIG_OF)
1154static const struct of_device_id tlv320aic31xx_of_match[] = {
1155 { .compatible = "ti,tlv320aic310x" },
1156 { .compatible = "ti,tlv320aic311x" },
1157 { .compatible = "ti,tlv320aic3100" },
1158 { .compatible = "ti,tlv320aic3110" },
1159 { .compatible = "ti,tlv320aic3120" },
1160 { .compatible = "ti,tlv320aic3111" },
1161 {},
1162};
1163MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
1164
1165static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1166{
1167 struct device_node *np = aic31xx->dev->of_node;
1168 unsigned int value = MICBIAS_2_0V;
1169 int ret;
1170
1171 of_property_read_u32(np, "ai31xx-micbias-vg", &value);
1172 switch (value) {
1173 case MICBIAS_2_0V:
1174 case MICBIAS_2_5V:
1175 case MICBIAS_AVDDV:
1176 aic31xx->pdata.micbias_vg = value;
1177 break;
1178 default:
1179 dev_err(aic31xx->dev,
1180 "Bad ai31xx-micbias-vg value %d DT\n",
1181 value);
1182 aic31xx->pdata.micbias_vg = MICBIAS_2_0V;
1183 }
1184
1185 ret = of_get_named_gpio(np, "gpio-reset", 0);
1186 if (ret > 0)
1187 aic31xx->pdata.gpio_reset = ret;
1188}
1189#else /* CONFIG_OF */
1190static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1191{
1192}
1193#endif /* CONFIG_OF */
1194
a72d2abb 1195static int aic31xx_device_init(struct aic31xx_priv *aic31xx)
e00447fa
JS		 1196{
1197 int ret, i;
1198
1199 dev_set_drvdata(aic31xx->dev, aic31xx);
1200
1201 if (dev_get_platdata(aic31xx->dev))
1202 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev),
1203 sizeof(aic31xx->pdata));
1204 else if (aic31xx->dev->of_node)
1205 aic31xx_pdata_from_of(aic31xx);
1206
1207 if (aic31xx->pdata.gpio_reset) {
1208 ret = devm_gpio_request_one(aic31xx->dev,
1209 aic31xx->pdata.gpio_reset,
1210 GPIOF_OUT_INIT_HIGH,
1211 "aic31xx-reset-pin");
1212 if (ret < 0) {
1213 dev_err(aic31xx->dev, "not able to acquire gpio\n");
a72d2abb 1214 return ret;
e00447fa
JS		 1215 }
1216 }
1217
1218 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1219 aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1220
1221 ret = devm_regulator_bulk_get(aic31xx->dev,
1222 ARRAY_SIZE(aic31xx->supplies),
1223 aic31xx->supplies);
1224 if (ret != 0)
1225 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret);
1226
a72d2abb 1227 return ret;
e00447fa
JS		 1228}
1229
1230static int aic31xx_i2c_probe(struct i2c_client *i2c,
1231 const struct i2c_device_id *id)
1232{
1233 struct aic31xx_priv *aic31xx;
1234 int ret;
1235 const struct regmap_config *regmap_config;
1236
1237 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1238 id->name, (int) id->driver_data);
1239
1240 regmap_config = &aic31xx_i2c_regmap;
1241
1242 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
1243 if (aic31xx == NULL)
1244 return -ENOMEM;
1245
1246 aic31xx->regmap = devm_regmap_init_i2c(i2c, regmap_config);
e00447fa
JS		 1247 if (IS_ERR(aic31xx->regmap)) {
1248 ret = PTR_ERR(aic31xx->regmap);
1249 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1250 ret);
1251 return ret;
1252 }
1253 aic31xx->dev = &i2c->dev;
1254
1255 aic31xx->pdata.codec_type = id->driver_data;
1256
a72d2abb
PU		 1257 ret = aic31xx_device_init(aic31xx);
1258 if (ret)
1259 return ret;
e00447fa 1260
dac7e404 1261 return snd_soc_register_codec(&i2c->dev, &soc_codec_driver_aic31xx,
e00447fa
JS		 1262 aic31xx_dai_driver,
1263 ARRAY_SIZE(aic31xx_dai_driver));
e00447fa
JS		 1264}
1265
1266static int aic31xx_i2c_remove(struct i2c_client *i2c)
1267{
dac7e404 1268 snd_soc_unregister_codec(&i2c->dev);
e00447fa
JS		 1269 return 0;
1270}
1271
1272static const struct i2c_device_id aic31xx_i2c_id[] = {
1273 { "tlv320aic310x", AIC3100 },
1274 { "tlv320aic311x", AIC3110 },
1275 { "tlv320aic3100", AIC3100 },
1276 { "tlv320aic3110", AIC3110 },
1277 { "tlv320aic3120", AIC3120 },
1278 { "tlv320aic3111", AIC3111 },
1279 { }
1280};
1281MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1282
1283static struct i2c_driver aic31xx_i2c_driver = {
1284 .driver = {
1285 .name = "tlv320aic31xx-codec",
e00447fa
JS		 1286 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
1287 },
1288 .probe = aic31xx_i2c_probe,
dac7e404 1289 .remove = aic31xx_i2c_remove,
e00447fa
JS		 1290 .id_table = aic31xx_i2c_id,
1291};
1292
1293module_i2c_driver(aic31xx_i2c_driver);
1294
1295MODULE_DESCRIPTION("ASoC TLV320AIC3111 codec driver");
1296MODULE_AUTHOR("Jyri Sarha");
1297MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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