[deliverable/linux.git] / sound / soc / codecs / tlv320aic31xx.h

/*
 * ALSA SoC TLV320AIC31XX codec driver
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * This package is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 *
 */
#ifndef _TLV320AIC31XX_H
#define _TLV320AIC31XX_H

#define AIC31XX_RATES	SNDRV_PCM_RATE_8000_192000

#define AIC31XX_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
			 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)


#define AIC31XX_STEREO_CLASS_D_BIT	0x1
#define AIC31XX_MINIDSP_BIT		0x2

enum aic31xx_type {
	AIC3100	= 0,
	AIC3110 = AIC31XX_STEREO_CLASS_D_BIT,
	AIC3120 = AIC31XX_MINIDSP_BIT,
	AIC3111 = (AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT),
};

struct aic31xx_pdata {
	enum aic31xx_type codec_type;
	unsigned int gpio_reset;
	int micbias_vg;
};

/* Page Control Register */
#define AIC31XX_PAGECTL				0x00

/* Page 0 Registers */
/* Software reset register */
#define AIC31XX_RESET				0x01
/* OT FLAG register */
#define AIC31XX_OT_FLAG				0x03
/* Clock clock Gen muxing, Multiplexers*/
#define AIC31XX_CLKMUX				0x04
/* PLL P and R-VAL register */
#define AIC31XX_PLLPR				0x05
/* PLL J-VAL register */
#define AIC31XX_PLLJ				0x06
/* PLL D-VAL MSB register */
#define AIC31XX_PLLDMSB				0x07
/* PLL D-VAL LSB register */
#define AIC31XX_PLLDLSB				0x08
/* DAC NDAC_VAL register*/
#define AIC31XX_NDAC				0x0B
/* DAC MDAC_VAL register */
#define AIC31XX_MDAC				0x0C
/* DAC OSR setting register 1, MSB value */
#define AIC31XX_DOSRMSB				0x0D
/* DAC OSR setting register 2, LSB value */
#define AIC31XX_DOSRLSB				0x0E
#define AIC31XX_MINI_DSP_INPOL			0x10
/* Clock setting register 8, PLL */
#define AIC31XX_NADC				0x12
/* Clock setting register 9, PLL */
#define AIC31XX_MADC				0x13
/* ADC Oversampling (AOSR) Register */
#define AIC31XX_AOSR				0x14
/* Clock setting register 9, Multiplexers */
#define AIC31XX_CLKOUTMUX			0x19
/* Clock setting register 10, CLOCKOUT M divider value */
#define AIC31XX_CLKOUTMVAL			0x1A
/* Audio Interface Setting Register 1 */
#define AIC31XX_IFACE1				0x1B
/* Audio Data Slot Offset Programming */
#define AIC31XX_DATA_OFFSET			0x1C
/* Audio Interface Setting Register 2 */
#define AIC31XX_IFACE2				0x1D
/* Clock setting register 11, BCLK N Divider */
#define AIC31XX_BCLKN				0x1E
/* Audio Interface Setting Register 3, Secondary Audio Interface */
#define AIC31XX_IFACESEC1			0x1F
/* Audio Interface Setting Register 4 */
#define AIC31XX_IFACESEC2			0x20
/* Audio Interface Setting Register 5 */
#define AIC31XX_IFACESEC3			0x21
/* I2C Bus Condition */
#define AIC31XX_I2C				0x22
/* ADC FLAG */
#define AIC31XX_ADCFLAG				0x24
/* DAC Flag Registers */
#define AIC31XX_DACFLAG1			0x25
#define AIC31XX_DACFLAG2			0x26
/* Sticky Interrupt flag (overflow) */
#define AIC31XX_OFFLAG				0x27
/* Sticy DAC Interrupt flags */
#define AIC31XX_INTRDACFLAG			0x2C
/* Sticy ADC Interrupt flags */
#define AIC31XX_INTRADCFLAG			0x2D
/* DAC Interrupt flags 2 */
#define AIC31XX_INTRDACFLAG2			0x2E
/* ADC Interrupt flags 2 */
#define AIC31XX_INTRADCFLAG2			0x2F
/* INT1 interrupt control */
#define AIC31XX_INT1CTRL			0x30
/* INT2 interrupt control */
#define AIC31XX_INT2CTRL			0x31
/* GPIO1 control */
#define AIC31XX_GPIO1				0x33

#define AIC31XX_DACPRB				0x3C
/* ADC Instruction Set Register */
#define AIC31XX_ADCPRB				0x3D
/* DAC channel setup register */
#define AIC31XX_DACSETUP			0x3F
/* DAC Mute and volume control register */
#define AIC31XX_DACMUTE				0x40
/* Left DAC channel digital volume control */
#define AIC31XX_LDACVOL				0x41
/* Right DAC channel digital volume control */
#define AIC31XX_RDACVOL				0x42
/* Headset detection */
#define AIC31XX_HSDETECT			0x43
/* ADC Digital Mic */
#define AIC31XX_ADCSETUP			0x51
/* ADC Digital Volume Control Fine Adjust */
#define AIC31XX_ADCFGA				0x52
/* ADC Digital Volume Control Coarse Adjust */
#define AIC31XX_ADCVOL				0x53


/* Page 1 Registers */
/* Headphone drivers */
#define AIC31XX_HPDRIVER			0x9F
/* Class-D Speakear Amplifier */
#define AIC31XX_SPKAMP				0xA0
/* HP Output Drivers POP Removal Settings */
#define AIC31XX_HPPOP				0xA1
/* Output Driver PGA Ramp-Down Period Control */
#define AIC31XX_SPPGARAMP			0xA2
/* DAC_L and DAC_R Output Mixer Routing */
#define AIC31XX_DACMIXERROUTE			0xA3
/* Left Analog Vol to HPL */
#define AIC31XX_LANALOGHPL			0xA4
/* Right Analog Vol to HPR */
#define AIC31XX_RANALOGHPR			0xA5
/* Left Analog Vol to SPL */
#define AIC31XX_LANALOGSPL			0xA6
/* Right Analog Vol to SPR */
#define AIC31XX_RANALOGSPR			0xA7
/* HPL Driver */
#define AIC31XX_HPLGAIN				0xA8
/* HPR Driver */
#define AIC31XX_HPRGAIN				0xA9
/* SPL Driver */
#define AIC31XX_SPLGAIN				0xAA
/* SPR Driver */
#define AIC31XX_SPRGAIN				0xAB
/* HP Driver Control */
#define AIC31XX_HPCONTROL			0xAC
/* MIC Bias Control */
#define AIC31XX_MICBIAS				0xAE
/* MIC PGA*/
#define AIC31XX_MICPGA				0xAF
/* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */
#define AIC31XX_MICPGAPI			0xB0
/* ADC Input Selection for M-Terminal */
#define AIC31XX_MICPGAMI			0xB1
/* Input CM Settings */
#define AIC31XX_MICPGACM			0xB2

/* Bits, masks and shifts */

/* AIC31XX_CLKMUX */
#define AIC31XX_PLL_CLKIN_MASK			0x0c
#define AIC31XX_PLL_CLKIN_SHIFT			2
#define AIC31XX_PLL_CLKIN_MCLK			0
#define AIC31XX_CODEC_CLKIN_MASK		0x03
#define AIC31XX_CODEC_CLKIN_SHIFT		0
#define AIC31XX_CODEC_CLKIN_PLL			3
#define AIC31XX_CODEC_CLKIN_BCLK		1

/* AIC31XX_PLLPR, AIC31XX_NDAC, AIC31XX_MDAC, AIC31XX_NADC, AIC31XX_MADC,
   AIC31XX_BCLKN */
#define AIC31XX_PLL_MASK		0x7f
#define AIC31XX_PM_MASK			0x80

/* AIC31XX_IFACE1 */
#define AIC31XX_WORD_LEN_16BITS		0x00
#define AIC31XX_WORD_LEN_20BITS		0x01
#define AIC31XX_WORD_LEN_24BITS		0x02
#define AIC31XX_WORD_LEN_32BITS		0x03
#define AIC31XX_IFACE1_DATALEN_MASK	0x30
#define AIC31XX_IFACE1_DATALEN_SHIFT	(4)
#define AIC31XX_IFACE1_DATATYPE_MASK	0xC0
#define AIC31XX_IFACE1_DATATYPE_SHIFT	(6)
#define AIC31XX_I2S_MODE		0x00
#define AIC31XX_DSP_MODE		0x01
#define AIC31XX_RIGHT_JUSTIFIED_MODE	0x02
#define AIC31XX_LEFT_JUSTIFIED_MODE	0x03
#define AIC31XX_IFACE1_MASTER_MASK	0x0C
#define AIC31XX_BCLK_MASTER		0x08
#define AIC31XX_WCLK_MASTER		0x04

/* AIC31XX_DATA_OFFSET */
#define AIC31XX_DATA_OFFSET_MASK	0xFF

/* AIC31XX_IFACE2 */
#define AIC31XX_BCLKINV_MASK		0x08
#define AIC31XX_BDIVCLK_MASK		0x03
#define AIC31XX_DAC2BCLK		0x00
#define AIC31XX_DACMOD2BCLK		0x01
#define AIC31XX_ADC2BCLK		0x02
#define AIC31XX_ADCMOD2BCLK		0x03

/* AIC31XX_ADCFLAG */
#define AIC31XX_ADCPWRSTATUS_MASK		0x40

/* AIC31XX_DACFLAG1 */
#define AIC31XX_LDACPWRSTATUS_MASK		0x80
#define AIC31XX_RDACPWRSTATUS_MASK		0x08
#define AIC31XX_HPLDRVPWRSTATUS_MASK		0x20
#define AIC31XX_HPRDRVPWRSTATUS_MASK		0x02
#define AIC31XX_SPLDRVPWRSTATUS_MASK		0x10
#define AIC31XX_SPRDRVPWRSTATUS_MASK		0x01

/* AIC31XX_INTRDACFLAG */
#define AIC31XX_HPSCDETECT_MASK			0x80
#define AIC31XX_BUTTONPRESS_MASK		0x20
#define AIC31XX_HSPLUG_MASK			0x10
#define AIC31XX_LDRCTHRES_MASK			0x08
#define AIC31XX_RDRCTHRES_MASK			0x04
#define AIC31XX_DACSINT_MASK			0x02
#define AIC31XX_DACAINT_MASK			0x01

/* AIC31XX_INT1CTRL */
#define AIC31XX_HSPLUGDET_MASK			0x80
#define AIC31XX_BUTTONPRESSDET_MASK		0x40
#define AIC31XX_DRCTHRES_MASK			0x20
#define AIC31XX_AGCNOISE_MASK			0x10
#define AIC31XX_OC_MASK				0x08
#define AIC31XX_ENGINE_MASK			0x04

/* AIC31XX_DACSETUP */
#define AIC31XX_SOFTSTEP_MASK			0x03

/* AIC31XX_DACMUTE */
#define AIC31XX_DACMUTE_MASK			0x0C

/* AIC31XX_MICBIAS */
#define AIC31XX_MICBIAS_MASK			0x03
#define AIC31XX_MICBIAS_SHIFT			0

#endif	/* _TLV320AIC31XX_H */
Commit	Line	Data
e00447fa JS	1	/*
	2	* ALSA SoC TLV320AIC31XX codec driver
	3	*
	4	* Copyright (C) 2013 Texas Instruments, Inc.
	5	*
	6	* This package is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
	11	* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
	12	* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
	13	*
	14	*/
	15	#ifndef _TLV320AIC31XX_H
	16	#define _TLV320AIC31XX_H
	17
	18	#define AIC31XX_RATES SNDRV_PCM_RATE_8000_192000
	19
	20	#define AIC31XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S20_3LE \
	21	\| SNDRV_PCM_FMTBIT_S24_3LE \| SNDRV_PCM_FMTBIT_S32_LE)
	22
	23
	24	#define AIC31XX_STEREO_CLASS_D_BIT 0x1
	25	#define AIC31XX_MINIDSP_BIT 0x2
	26
	27	enum aic31xx_type {
	28	AIC3100 = 0,
	29	AIC3110 = AIC31XX_STEREO_CLASS_D_BIT,
	30	AIC3120 = AIC31XX_MINIDSP_BIT,
	31	AIC3111 = (AIC31XX_STEREO_CLASS_D_BIT \| AIC31XX_MINIDSP_BIT),
	32	};
	33
	34	struct aic31xx_pdata {
	35	enum aic31xx_type codec_type;
	36	unsigned int gpio_reset;
	37	int micbias_vg;
	38	};
	39
	40	/* Page Control Register */
	41	#define AIC31XX_PAGECTL 0x00
	42
	43	/* Page 0 Registers */
	44	/* Software reset register */
	45	#define AIC31XX_RESET 0x01
	46	/* OT FLAG register */
	47	#define AIC31XX_OT_FLAG 0x03
	48	/* Clock clock Gen muxing, Multiplexers*/
	49	#define AIC31XX_CLKMUX 0x04
	50	/* PLL P and R-VAL register */
	51	#define AIC31XX_PLLPR 0x05
	52	/* PLL J-VAL register */
	53	#define AIC31XX_PLLJ 0x06
	54	/* PLL D-VAL MSB register */
	55	#define AIC31XX_PLLDMSB 0x07
	56	/* PLL D-VAL LSB register */
	57	#define AIC31XX_PLLDLSB 0x08
	58	/* DAC NDAC_VAL register*/
	59	#define AIC31XX_NDAC 0x0B
	60	/* DAC MDAC_VAL register */
	61	#define AIC31XX_MDAC 0x0C
	62	/* DAC OSR setting register 1, MSB value */
	63	#define AIC31XX_DOSRMSB 0x0D
	64	/* DAC OSR setting register 2, LSB value */
65	#define AIC31XX_DOSRLSB 0x0E
66	#define AIC31XX_MINI_DSP_INPOL 0x10
67	/* Clock setting register 8, PLL */
68	#define AIC31XX_NADC 0x12
69	/* Clock setting register 9, PLL */
70	#define AIC31XX_MADC 0x13
71	/* ADC Oversampling (AOSR) Register */
72	#define AIC31XX_AOSR 0x14
73	/* Clock setting register 9, Multiplexers */
74	#define AIC31XX_CLKOUTMUX 0x19
75	/* Clock setting register 10, CLOCKOUT M divider value */
76	#define AIC31XX_CLKOUTMVAL 0x1A
77	/* Audio Interface Setting Register 1 */
78	#define AIC31XX_IFACE1 0x1B
79	/* Audio Data Slot Offset Programming */
80	#define AIC31XX_DATA_OFFSET 0x1C
81	/* Audio Interface Setting Register 2 */
82	#define AIC31XX_IFACE2 0x1D
83	/* Clock setting register 11, BCLK N Divider */
84	#define AIC31XX_BCLKN 0x1E
85	/* Audio Interface Setting Register 3, Secondary Audio Interface */
86	#define AIC31XX_IFACESEC1 0x1F
87	/* Audio Interface Setting Register 4 */
88	#define AIC31XX_IFACESEC2 0x20
89	/* Audio Interface Setting Register 5 */
90	#define AIC31XX_IFACESEC3 0x21
91	/* I2C Bus Condition */
92	#define AIC31XX_I2C 0x22
93	/* ADC FLAG */
94	#define AIC31XX_ADCFLAG 0x24
95	/* DAC Flag Registers */
96	#define AIC31XX_DACFLAG1 0x25
97	#define AIC31XX_DACFLAG2 0x26
98	/* Sticky Interrupt flag (overflow) */
99	#define AIC31XX_OFFLAG 0x27
100	/* Sticy DAC Interrupt flags */
101	#define AIC31XX_INTRDACFLAG 0x2C
102	/* Sticy ADC Interrupt flags */
103	#define AIC31XX_INTRADCFLAG 0x2D
104	/* DAC Interrupt flags 2 */
105	#define AIC31XX_INTRDACFLAG2 0x2E
106	/* ADC Interrupt flags 2 */
107	#define AIC31XX_INTRADCFLAG2 0x2F
108	/* INT1 interrupt control */
109	#define AIC31XX_INT1CTRL 0x30
110	/* INT2 interrupt control */
111	#define AIC31XX_INT2CTRL 0x31
112	/* GPIO1 control */
113	#define AIC31XX_GPIO1 0x33
114
115	#define AIC31XX_DACPRB 0x3C
116	/* ADC Instruction Set Register */
117	#define AIC31XX_ADCPRB 0x3D
118	/* DAC channel setup register */
119	#define AIC31XX_DACSETUP 0x3F
120	/* DAC Mute and volume control register */
121	#define AIC31XX_DACMUTE 0x40
122	/* Left DAC channel digital volume control */
123	#define AIC31XX_LDACVOL 0x41
124	/* Right DAC channel digital volume control */
125	#define AIC31XX_RDACVOL 0x42
126	/* Headset detection */
127	#define AIC31XX_HSDETECT 0x43
128	/* ADC Digital Mic */
129	#define AIC31XX_ADCSETUP 0x51
130	/* ADC Digital Volume Control Fine Adjust */
131	#define AIC31XX_ADCFGA 0x52
132	/* ADC Digital Volume Control Coarse Adjust */
133	#define AIC31XX_ADCVOL 0x53
134
135
136	/* Page 1 Registers */
137	/* Headphone drivers */
138	#define AIC31XX_HPDRIVER 0x9F
139	/* Class-D Speakear Amplifier */
140	#define AIC31XX_SPKAMP 0xA0
141	/* HP Output Drivers POP Removal Settings */
142	#define AIC31XX_HPPOP 0xA1
143	/* Output Driver PGA Ramp-Down Period Control */
144	#define AIC31XX_SPPGARAMP 0xA2
145	/* DAC_L and DAC_R Output Mixer Routing */
146	#define AIC31XX_DACMIXERROUTE 0xA3
147	/* Left Analog Vol to HPL */
148	#define AIC31XX_LANALOGHPL 0xA4
149	/* Right Analog Vol to HPR */
150	#define AIC31XX_RANALOGHPR 0xA5
151	/* Left Analog Vol to SPL */
152	#define AIC31XX_LANALOGSPL 0xA6
153	/* Right Analog Vol to SPR */
154	#define AIC31XX_RANALOGSPR 0xA7
155	/* HPL Driver */
156	#define AIC31XX_HPLGAIN 0xA8
157	/* HPR Driver */
158	#define AIC31XX_HPRGAIN 0xA9
159	/* SPL Driver */
160	#define AIC31XX_SPLGAIN 0xAA
161	/* SPR Driver */
162	#define AIC31XX_SPRGAIN 0xAB
163	/* HP Driver Control */
164	#define AIC31XX_HPCONTROL 0xAC
165	/* MIC Bias Control */
166	#define AIC31XX_MICBIAS 0xAE
167	/* MIC PGA*/
168	#define AIC31XX_MICPGA 0xAF
169	/* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */
170	#define AIC31XX_MICPGAPI 0xB0
171	/* ADC Input Selection for M-Terminal */
172	#define AIC31XX_MICPGAMI 0xB1
173	/* Input CM Settings */
174	#define AIC31XX_MICPGACM 0xB2
175
176	/* Bits, masks and shifts */
177
178	/* AIC31XX_CLKMUX */
179	#define AIC31XX_PLL_CLKIN_MASK 0x0c
180	#define AIC31XX_PLL_CLKIN_SHIFT 2
181	#define AIC31XX_PLL_CLKIN_MCLK 0
182	#define AIC31XX_CODEC_CLKIN_MASK 0x03
183	#define AIC31XX_CODEC_CLKIN_SHIFT 0
184	#define AIC31XX_CODEC_CLKIN_PLL 3
185	#define AIC31XX_CODEC_CLKIN_BCLK 1
186
187	/* AIC31XX_PLLPR, AIC31XX_NDAC, AIC31XX_MDAC, AIC31XX_NADC, AIC31XX_MADC,
188	AIC31XX_BCLKN */
189	#define AIC31XX_PLL_MASK 0x7f
190	#define AIC31XX_PM_MASK 0x80
191
192	/* AIC31XX_IFACE1 */
193	#define AIC31XX_WORD_LEN_16BITS 0x00
194	#define AIC31XX_WORD_LEN_20BITS 0x01
195	#define AIC31XX_WORD_LEN_24BITS 0x02
196	#define AIC31XX_WORD_LEN_32BITS 0x03
197	#define AIC31XX_IFACE1_DATALEN_MASK 0x30
198	#define AIC31XX_IFACE1_DATALEN_SHIFT (4)
199	#define AIC31XX_IFACE1_DATATYPE_MASK 0xC0
200	#define AIC31XX_IFACE1_DATATYPE_SHIFT (6)
201	#define AIC31XX_I2S_MODE 0x00
202	#define AIC31XX_DSP_MODE 0x01
203	#define AIC31XX_RIGHT_JUSTIFIED_MODE 0x02
204	#define AIC31XX_LEFT_JUSTIFIED_MODE 0x03
205	#define AIC31XX_IFACE1_MASTER_MASK 0x0C
206	#define AIC31XX_BCLK_MASTER 0x08
207	#define AIC31XX_WCLK_MASTER 0x04
208
209	/* AIC31XX_DATA_OFFSET */
210	#define AIC31XX_DATA_OFFSET_MASK 0xFF
211
212	/* AIC31XX_IFACE2 */
213	#define AIC31XX_BCLKINV_MASK 0x08
214	#define AIC31XX_BDIVCLK_MASK 0x03
215	#define AIC31XX_DAC2BCLK 0x00
216	#define AIC31XX_DACMOD2BCLK 0x01
217	#define AIC31XX_ADC2BCLK 0x02
218	#define AIC31XX_ADCMOD2BCLK 0x03
219
220	/* AIC31XX_ADCFLAG */
221	#define AIC31XX_ADCPWRSTATUS_MASK 0x40
222
223	/* AIC31XX_DACFLAG1 */
224	#define AIC31XX_LDACPWRSTATUS_MASK 0x80
225	#define AIC31XX_RDACPWRSTATUS_MASK 0x08
226	#define AIC31XX_HPLDRVPWRSTATUS_MASK 0x20
227	#define AIC31XX_HPRDRVPWRSTATUS_MASK 0x02
228	#define AIC31XX_SPLDRVPWRSTATUS_MASK 0x10
229	#define AIC31XX_SPRDRVPWRSTATUS_MASK 0x01
230
231	/* AIC31XX_INTRDACFLAG */
232	#define AIC31XX_HPSCDETECT_MASK 0x80
233	#define AIC31XX_BUTTONPRESS_MASK 0x20
234	#define AIC31XX_HSPLUG_MASK 0x10
235	#define AIC31XX_LDRCTHRES_MASK 0x08
236	#define AIC31XX_RDRCTHRES_MASK 0x04
237	#define AIC31XX_DACSINT_MASK 0x02
238	#define AIC31XX_DACAINT_MASK 0x01
239
240	/* AIC31XX_INT1CTRL */
241	#define AIC31XX_HSPLUGDET_MASK 0x80
242	#define AIC31XX_BUTTONPRESSDET_MASK 0x40
243	#define AIC31XX_DRCTHRES_MASK 0x20
244	#define AIC31XX_AGCNOISE_MASK 0x10
245	#define AIC31XX_OC_MASK 0x08
246	#define AIC31XX_ENGINE_MASK 0x04
247
248	/* AIC31XX_DACSETUP */
249	#define AIC31XX_SOFTSTEP_MASK 0x03
250
251	/* AIC31XX_DACMUTE */
252	#define AIC31XX_DACMUTE_MASK 0x0C
253
254	/* AIC31XX_MICBIAS */
255	#define AIC31XX_MICBIAS_MASK 0x03
256	#define AIC31XX_MICBIAS_SHIFT 0
257
258	#endif /* _TLV320AIC31XX_H */