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ASoC: tlv320aic32x4: Implement resistors on input pins
[deliverable/linux.git] / sound / soc / codecs / tlv320aic32x4.c
CommitLineData
1d471cd1
JM		 1/*
2 * linux/sound/soc/codecs/tlv320aic32x4.c
3 *
4 * Copyright 2011 Vista Silicon S.L.
5 *
6 * Author: Javier Martin <javier.martin@vista-silicon.com>
7 *
8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 * MA 02110-1301, USA.
24 */
25
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
1858fe97 31#include <linux/gpio.h>
4d16700d 32#include <linux/of_gpio.h>
1d471cd1
JM		 33#include <linux/cdev.h>
34#include <linux/slab.h>
98b664e2 35#include <linux/clk.h>
239b669b 36#include <linux/regulator/consumer.h>
1d471cd1
JM		 37
38#include <sound/tlv320aic32x4.h>
39#include <sound/core.h>
40#include <sound/pcm.h>
41#include <sound/pcm_params.h>
42#include <sound/soc.h>
43#include <sound/soc-dapm.h>
44#include <sound/initval.h>
45#include <sound/tlv.h>
46
47#include "tlv320aic32x4.h"
48
49struct aic32x4_rate_divs {
50 u32 mclk;
51 u32 rate;
52 u8 p_val;
53 u8 pll_j;
54 u16 pll_d;
55 u16 dosr;
56 u8 ndac;
57 u8 mdac;
58 u8 aosr;
59 u8 nadc;
60 u8 madc;
61 u8 blck_N;
62};
63
64struct aic32x4_priv {
4d208ca4 65 struct regmap *regmap;
1d471cd1 66 u32 sysclk;
1d471cd1
JM		 67 u32 power_cfg;
68 u32 micpga_routing;
69 bool swapdacs;
1858fe97 70 int rstn_gpio;
98b664e2 71 struct clk *mclk;
239b669b
MP		 72
73 struct regulator *supply_ldo;
74 struct regulator *supply_iov;
75 struct regulator *supply_dv;
76 struct regulator *supply_av;
1d471cd1
JM		 77};
78
1d471cd1
JM		 79/* 0dB min, 0.5dB steps */
80static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
c671e79d
MP		 81/* -63.5dB min, 0.5dB steps */
82static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
83/* -6dB min, 1dB steps */
84static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
85/* -12dB min, 0.5dB steps */
86static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
1d471cd1
JM		 87
88static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
c671e79d
MP		 89 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
90 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
91 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
92 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
93 tlv_driver_gain),
94 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
95 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
96 tlv_driver_gain),
1d471cd1
JM		 97 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
98 AIC32X4_HPRGAIN, 6, 0x01, 1),
99 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
100 AIC32X4_LORGAIN, 6, 0x01, 1),
101 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
102 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
103
104 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
105 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
106
c671e79d
MP		 107 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
108 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
1d471cd1
JM		 109 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
110 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
111
112 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
113
114 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
115 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
116 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
117 4, 0x07, 0),
118 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
119 0, 0x03, 0),
120 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
121 6, 0x03, 0),
122 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
123 1, 0x1F, 0),
124 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
125 0, 0x7F, 0),
126 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
127 3, 0x1F, 0),
128 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
129 3, 0x1F, 0),
130 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
131 0, 0x1F, 0),
132 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
133 0, 0x0F, 0),
134};
135
136static const struct aic32x4_rate_divs aic32x4_divs[] = {
137 /* 8k rate */
138 {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
139 {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
140 {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
141 /* 11.025k rate */
142 {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
143 {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
144 /* 16k rate */
145 {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
146 {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
147 {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
148 /* 22.05k rate */
149 {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
150 {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
151 {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
152 /* 32k rate */
153 {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
154 {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
155 /* 44.1k rate */
156 {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
157 {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
158 {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
159 /* 48k rate */
160 {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
161 {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
041f9d33
JM		 162 {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4},
163
164 /* 96k rate */
165 {AIC32X4_FREQ_25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1},
1d471cd1
JM		 166};
167
168static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
169 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
170 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
171};
172
173static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
174 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
175 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
176};
177
178static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
179 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
180};
181
182static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
183 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
184};
185
20d2cecb
JM		 186static const char * const resistor_text[] = {
187 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
188};
189
190static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6,
191 resistor_text);
192static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4,
193 resistor_text);
194static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2,
195 resistor_text);
196
1d471cd1 197static const struct snd_kcontrol_new left_input_mixer_controls[] = {
20d2cecb
JM		 198 SOC_DAPM_ENUM("IN1_L P Switch", in1l_lpga_p_enum),
199 SOC_DAPM_ENUM("IN2_L P Switch", in2l_lpga_p_enum),
200 SOC_DAPM_ENUM("IN3_L P Switch", in3l_lpga_p_enum),
1d471cd1
JM		 201};
202
20d2cecb
JM		 203static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6,
204 resistor_text);
205static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4,
206 resistor_text);
207static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2,
208 resistor_text);
209
1d471cd1 210static const struct snd_kcontrol_new right_input_mixer_controls[] = {
20d2cecb
JM		 211 SOC_DAPM_ENUM("IN1_R P Switch", in1r_rpga_p_enum),
212 SOC_DAPM_ENUM("IN2_R P Switch", in2r_rpga_p_enum),
213 SOC_DAPM_ENUM("IN3_R P Switch", in3r_rpga_p_enum),
1d471cd1
JM		 214};
215
216static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
217 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
218 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
219 &hpl_output_mixer_controls[0],
220 ARRAY_SIZE(hpl_output_mixer_controls)),
221 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
222
223 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
224 &lol_output_mixer_controls[0],
225 ARRAY_SIZE(lol_output_mixer_controls)),
226 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
227
228 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
229 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
230 &hpr_output_mixer_controls[0],
231 ARRAY_SIZE(hpr_output_mixer_controls)),
232 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
233 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
234 &lor_output_mixer_controls[0],
235 ARRAY_SIZE(lor_output_mixer_controls)),
236 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
237 SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
238 &left_input_mixer_controls[0],
239 ARRAY_SIZE(left_input_mixer_controls)),
240 SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
241 &right_input_mixer_controls[0],
242 ARRAY_SIZE(right_input_mixer_controls)),
243 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
244 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
245 SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
246
247 SND_SOC_DAPM_OUTPUT("HPL"),
248 SND_SOC_DAPM_OUTPUT("HPR"),
249 SND_SOC_DAPM_OUTPUT("LOL"),
250 SND_SOC_DAPM_OUTPUT("LOR"),
251 SND_SOC_DAPM_INPUT("IN1_L"),
252 SND_SOC_DAPM_INPUT("IN1_R"),
253 SND_SOC_DAPM_INPUT("IN2_L"),
254 SND_SOC_DAPM_INPUT("IN2_R"),
255 SND_SOC_DAPM_INPUT("IN3_L"),
256 SND_SOC_DAPM_INPUT("IN3_R"),
257};
258
259static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
260 /* Left Output */
261 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
262 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
263
264 {"HPL Power", NULL, "HPL Output Mixer"},
265 {"HPL", NULL, "HPL Power"},
266
267 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
268
269 {"LOL Power", NULL, "LOL Output Mixer"},
270 {"LOL", NULL, "LOL Power"},
271
272 /* Right Output */
273 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
274 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
275
276 {"HPR Power", NULL, "HPR Output Mixer"},
277 {"HPR", NULL, "HPR Power"},
278
279 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
280
281 {"LOR Power", NULL, "LOR Output Mixer"},
282 {"LOR", NULL, "LOR Power"},
283
284 /* Left input */
285 {"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
286 {"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
287 {"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
288
289 {"Left ADC", NULL, "Left Input Mixer"},
290
291 /* Right Input */
292 {"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
293 {"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
294 {"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
295
296 {"Right ADC", NULL, "Right Input Mixer"},
297};
298
4d208ca4
MB		 299static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
300 {
301 .selector_reg = 0,
302 .selector_mask = 0xff,
303 .window_start = 0,
304 .window_len = 128,
e8e08c52 305 .range_min = 0,
6d0d5103 306 .range_max = AIC32X4_RMICPGAVOL,
4d208ca4
MB		 307 },
308};
1d471cd1 309
3bcfd222 310const struct regmap_config aic32x4_regmap_config = {
4d208ca4
MB		 311 .max_register = AIC32X4_RMICPGAVOL,
312 .ranges = aic32x4_regmap_pages,
313 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
314};
3bcfd222 315EXPORT_SYMBOL(aic32x4_regmap_config);
1d471cd1
JM		 316
317static inline int aic32x4_get_divs(int mclk, int rate)
318{
319 int i;
320
321 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
322 if ((aic32x4_divs[i].rate == rate)
323 && (aic32x4_divs[i].mclk == mclk)) {
324 return i;
325 }
326 }
327 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
328 return -EINVAL;
329}
330
1d471cd1
JM		 331static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
332 int clk_id, unsigned int freq, int dir)
333{
334 struct snd_soc_codec *codec = codec_dai->codec;
335 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
336
337 switch (freq) {
338 case AIC32X4_FREQ_12000000:
339 case AIC32X4_FREQ_24000000:
340 case AIC32X4_FREQ_25000000:
341 aic32x4->sysclk = freq;
342 return 0;
343 }
344 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
345 return -EINVAL;
346}
347
348static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
349{
350 struct snd_soc_codec *codec = codec_dai->codec;
1d471cd1
JM		 351 u8 iface_reg_1;
352 u8 iface_reg_2;
353 u8 iface_reg_3;
354
355 iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
356 iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
357 iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
358 iface_reg_2 = 0;
359 iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
360 iface_reg_3 = iface_reg_3 & ~(1 << 3);
361
362 /* set master/slave audio interface */
363 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
364 case SND_SOC_DAIFMT_CBM_CFM:
1d471cd1
JM		 365 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
366 break;
367 case SND_SOC_DAIFMT_CBS_CFS:
1d471cd1
JM		 368 break;
369 default:
370 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
371 return -EINVAL;
372 }
373
374 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
375 case SND_SOC_DAIFMT_I2S:
376 break;
377 case SND_SOC_DAIFMT_DSP_A:
378 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
379 iface_reg_3 |= (1 << 3); /* invert bit clock */
380 iface_reg_2 = 0x01; /* add offset 1 */
381 break;
382 case SND_SOC_DAIFMT_DSP_B:
383 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
384 iface_reg_3 |= (1 << 3); /* invert bit clock */
385 break;
386 case SND_SOC_DAIFMT_RIGHT_J:
387 iface_reg_1 |=
388 (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
389 break;
390 case SND_SOC_DAIFMT_LEFT_J:
391 iface_reg_1 |=
392 (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
393 break;
394 default:
395 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
396 return -EINVAL;
397 }
398
399 snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
400 snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
401 snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
402 return 0;
403}
404
405static int aic32x4_hw_params(struct snd_pcm_substream *substream,
406 struct snd_pcm_hw_params *params,
407 struct snd_soc_dai *dai)
408{
409 struct snd_soc_codec *codec = dai->codec;
410 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
411 u8 data;
412 int i;
413
414 i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
415 if (i < 0) {
416 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
417 return i;
418 }
419
420 /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
421 snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
422 snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
423
424 /* We will fix R value to 1 and will make P & J=K.D as varialble */
425 data = snd_soc_read(codec, AIC32X4_PLLPR);
426 data &= ~(7 << 4);
427 snd_soc_write(codec, AIC32X4_PLLPR,
428 (data | (aic32x4_divs[i].p_val << 4) | 0x01));
429
430 snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
431
432 snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
433 snd_soc_write(codec, AIC32X4_PLLDLSB,
434 (aic32x4_divs[i].pll_d & 0xff));
435
436 /* NDAC divider value */
437 data = snd_soc_read(codec, AIC32X4_NDAC);
438 data &= ~(0x7f);
439 snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
440
441 /* MDAC divider value */
442 data = snd_soc_read(codec, AIC32X4_MDAC);
443 data &= ~(0x7f);
444 snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
445
446 /* DOSR MSB & LSB values */
447 snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
448 snd_soc_write(codec, AIC32X4_DOSRLSB,
449 (aic32x4_divs[i].dosr & 0xff));
450
451 /* NADC divider value */
452 data = snd_soc_read(codec, AIC32X4_NADC);
453 data &= ~(0x7f);
454 snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
455
456 /* MADC divider value */
457 data = snd_soc_read(codec, AIC32X4_MADC);
458 data &= ~(0x7f);
459 snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
460
461 /* AOSR value */
462 snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
463
464 /* BCLK N divider */
465 data = snd_soc_read(codec, AIC32X4_BCLKN);
466 data &= ~(0x7f);
467 snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
468
469 data = snd_soc_read(codec, AIC32X4_IFACE1);
470 data = data & ~(3 << 4);
bd8a5711
MB		 471 switch (params_width(params)) {
472 case 16:
1d471cd1 473 break;
bd8a5711 474 case 20:
1d471cd1
JM		 475 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
476 break;
bd8a5711 477 case 24:
1d471cd1
JM		 478 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
479 break;
bd8a5711 480 case 32:
1d471cd1
JM		 481 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
482 break;
483 }
484 snd_soc_write(codec, AIC32X4_IFACE1, data);
485
b44aa40f
MP		 486 if (params_channels(params) == 1) {
487 data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
488 } else {
489 if (aic32x4->swapdacs)
490 data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
491 else
492 data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
493 }
494 snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK,
495 data);
496
1d471cd1
JM		 497 return 0;
498}
499
500static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
501{
502 struct snd_soc_codec *codec = dai->codec;
503 u8 dac_reg;
504
505 dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
506 if (mute)
507 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
508 else
509 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
510 return 0;
511}
512
513static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
514 enum snd_soc_bias_level level)
515{
98b664e2
MP		 516 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
517 int ret;
518
1d471cd1
JM		 519 switch (level) {
520 case SND_SOC_BIAS_ON:
98b664e2
MP		 521 /* Switch on master clock */
522 ret = clk_prepare_enable(aic32x4->mclk);
523 if (ret) {
524 dev_err(codec->dev, "Failed to enable master clock\n");
525 return ret;
526 }
527
01b37e94
WS		 528 /* Switch on PLL */
529 snd_soc_update_bits(codec, AIC32X4_PLLPR,
530 AIC32X4_PLLEN, AIC32X4_PLLEN);
531
532 /* Switch on NDAC Divider */
533 snd_soc_update_bits(codec, AIC32X4_NDAC,
534 AIC32X4_NDACEN, AIC32X4_NDACEN);
535
536 /* Switch on MDAC Divider */
537 snd_soc_update_bits(codec, AIC32X4_MDAC,
538 AIC32X4_MDACEN, AIC32X4_MDACEN);
539
540 /* Switch on NADC Divider */
541 snd_soc_update_bits(codec, AIC32X4_NADC,
542 AIC32X4_NADCEN, AIC32X4_NADCEN);
543
544 /* Switch on MADC Divider */
545 snd_soc_update_bits(codec, AIC32X4_MADC,
546 AIC32X4_MADCEN, AIC32X4_MADCEN);
547
548 /* Switch on BCLK_N Divider */
549 snd_soc_update_bits(codec, AIC32X4_BCLKN,
550 AIC32X4_BCLKEN, AIC32X4_BCLKEN);
1d471cd1
JM		 551 break;
552 case SND_SOC_BIAS_PREPARE:
553 break;
554 case SND_SOC_BIAS_STANDBY:
3154cc74
MP		 555 /* Switch off BCLK_N Divider */
556 snd_soc_update_bits(codec, AIC32X4_BCLKN,
557 AIC32X4_BCLKEN, 0);
01b37e94 558
3154cc74
MP		 559 /* Switch off MADC Divider */
560 snd_soc_update_bits(codec, AIC32X4_MADC,
561 AIC32X4_MADCEN, 0);
01b37e94
WS		 562
563 /* Switch off NADC Divider */
564 snd_soc_update_bits(codec, AIC32X4_NADC,
565 AIC32X4_NADCEN, 0);
566
3154cc74
MP		 567 /* Switch off MDAC Divider */
568 snd_soc_update_bits(codec, AIC32X4_MDAC,
569 AIC32X4_MDACEN, 0);
01b37e94 570
3154cc74
MP		 571 /* Switch off NDAC Divider */
572 snd_soc_update_bits(codec, AIC32X4_NDAC,
573 AIC32X4_NDACEN, 0);
574
575 /* Switch off PLL */
576 snd_soc_update_bits(codec, AIC32X4_PLLPR,
577 AIC32X4_PLLEN, 0);
98b664e2
MP		 578
579 /* Switch off master clock */
580 clk_disable_unprepare(aic32x4->mclk);
1d471cd1
JM		 581 break;
582 case SND_SOC_BIAS_OFF:
583 break;
584 }
1d471cd1
JM		 585 return 0;
586}
587
041f9d33 588#define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000
1d471cd1
JM		 589#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
590 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
591
85e7652d 592static const struct snd_soc_dai_ops aic32x4_ops = {
1d471cd1
JM		 593 .hw_params = aic32x4_hw_params,
594 .digital_mute = aic32x4_mute,
595 .set_fmt = aic32x4_set_dai_fmt,
596 .set_sysclk = aic32x4_set_dai_sysclk,
597};
598
599static struct snd_soc_dai_driver aic32x4_dai = {
600 .name = "tlv320aic32x4-hifi",
601 .playback = {
602 .stream_name = "Playback",
603 .channels_min = 1,
604 .channels_max = 2,
605 .rates = AIC32X4_RATES,
606 .formats = AIC32X4_FORMATS,},
607 .capture = {
608 .stream_name = "Capture",
609 .channels_min = 1,
610 .channels_max = 2,
611 .rates = AIC32X4_RATES,
612 .formats = AIC32X4_FORMATS,},
613 .ops = &aic32x4_ops,
614 .symmetric_rates = 1,
615};
616
ec513886 617static int aic32x4_codec_probe(struct snd_soc_codec *codec)
1d471cd1
JM		 618{
619 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
620 u32 tmp_reg;
621
a74ab512 622 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1858fe97
JM		 623 ndelay(10);
624 gpio_set_value(aic32x4->rstn_gpio, 1);
625 }
626
1d471cd1
JM		 627 snd_soc_write(codec, AIC32X4_RESET, 0x01);
628
629 /* Power platform configuration */
630 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
631 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
632 AIC32X4_MICBIAS_2075V);
633 }
eb72cbdf 634 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1d471cd1 635 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
0c93a167
WS		 636
637 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
638 AIC32X4_LDOCTLEN : 0;
639 snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
640
1d471cd1 641 tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
eb72cbdf 642 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1d471cd1 643 tmp_reg |= AIC32X4_LDOIN_18_36;
eb72cbdf 644 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1d471cd1 645 tmp_reg |= AIC32X4_LDOIN2HP;
1d471cd1
JM		 646 snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
647
1d471cd1 648 /* Mic PGA routing */
609e6025 649 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
43bf38ba
SS		 650 snd_soc_write(codec, AIC32X4_LMICPGANIN,
651 AIC32X4_LMICPGANIN_IN2R_10K);
609e6025 652 else
43bf38ba
SS		 653 snd_soc_write(codec, AIC32X4_LMICPGANIN,
654 AIC32X4_LMICPGANIN_CM1L_10K);
609e6025 655 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
43bf38ba
SS		 656 snd_soc_write(codec, AIC32X4_RMICPGANIN,
657 AIC32X4_RMICPGANIN_IN1L_10K);
609e6025 658 else
43bf38ba
SS		 659 snd_soc_write(codec, AIC32X4_RMICPGANIN,
660 AIC32X4_RMICPGANIN_CM1R_10K);
1d471cd1 661
a405387c
JM		 662 /*
663 * Workaround: for an unknown reason, the ADC needs to be powered up
664 * and down for the first capture to work properly. It seems related to
665 * a HW BUG or some kind of behavior not documented in the datasheet.
666 */
667 tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
668 snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
669 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
670 snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
671
1d471cd1
JM		 672 return 0;
673}
674
1d471cd1 675static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
ec513886 676 .probe = aic32x4_codec_probe,
1d471cd1 677 .set_bias_level = aic32x4_set_bias_level,
f10c0a71 678 .suspend_bias_off = true,
aac97b5f
LPC		 679
680 .controls = aic32x4_snd_controls,
681 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
682 .dapm_widgets = aic32x4_dapm_widgets,
683 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
684 .dapm_routes = aic32x4_dapm_routes,
685 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1d471cd1
JM		 686};
687
4d16700d
MP		 688static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
689 struct device_node *np)
690{
691 aic32x4->swapdacs = false;
692 aic32x4->micpga_routing = 0;
693 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
694
695 return 0;
696}
697
239b669b
MP		 698static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
699{
700 regulator_disable(aic32x4->supply_iov);
701
702 if (!IS_ERR(aic32x4->supply_ldo))
703 regulator_disable(aic32x4->supply_ldo);
704
705 if (!IS_ERR(aic32x4->supply_dv))
706 regulator_disable(aic32x4->supply_dv);
707
708 if (!IS_ERR(aic32x4->supply_av))
709 regulator_disable(aic32x4->supply_av);
710}
711
712static int aic32x4_setup_regulators(struct device *dev,
713 struct aic32x4_priv *aic32x4)
714{
715 int ret = 0;
716
717 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
718 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
719 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
720 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
721
722 /* Check if the regulator requirements are fulfilled */
723
724 if (IS_ERR(aic32x4->supply_iov)) {
725 dev_err(dev, "Missing supply 'iov'\n");
726 return PTR_ERR(aic32x4->supply_iov);
727 }
728
729 if (IS_ERR(aic32x4->supply_ldo)) {
730 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
731 return -EPROBE_DEFER;
732
733 if (IS_ERR(aic32x4->supply_dv)) {
734 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
735 return PTR_ERR(aic32x4->supply_dv);
736 }
737 if (IS_ERR(aic32x4->supply_av)) {
738 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
739 return PTR_ERR(aic32x4->supply_av);
740 }
741 } else {
742 if (IS_ERR(aic32x4->supply_dv) &&
743 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
744 return -EPROBE_DEFER;
745 if (IS_ERR(aic32x4->supply_av) &&
746 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
747 return -EPROBE_DEFER;
748 }
749
750 ret = regulator_enable(aic32x4->supply_iov);
751 if (ret) {
752 dev_err(dev, "Failed to enable regulator iov\n");
753 return ret;
754 }
755
756 if (!IS_ERR(aic32x4->supply_ldo)) {
757 ret = regulator_enable(aic32x4->supply_ldo);
758 if (ret) {
759 dev_err(dev, "Failed to enable regulator ldo\n");
760 goto error_ldo;
761 }
762 }
763
764 if (!IS_ERR(aic32x4->supply_dv)) {
765 ret = regulator_enable(aic32x4->supply_dv);
766 if (ret) {
767 dev_err(dev, "Failed to enable regulator dv\n");
768 goto error_dv;
769 }
770 }
771
772 if (!IS_ERR(aic32x4->supply_av)) {
773 ret = regulator_enable(aic32x4->supply_av);
774 if (ret) {
775 dev_err(dev, "Failed to enable regulator av\n");
776 goto error_av;
777 }
778 }
779
780 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
781 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
782
783 return 0;
784
785error_av:
786 if (!IS_ERR(aic32x4->supply_dv))
787 regulator_disable(aic32x4->supply_dv);
788
789error_dv:
790 if (!IS_ERR(aic32x4->supply_ldo))
791 regulator_disable(aic32x4->supply_ldo);
792
793error_ldo:
794 regulator_disable(aic32x4->supply_iov);
795 return ret;
796}
797
3bcfd222 798int aic32x4_probe(struct device *dev, struct regmap *regmap)
1d471cd1 799{
1d471cd1 800 struct aic32x4_priv *aic32x4;
3bcfd222
JM		 801 struct aic32x4_pdata *pdata = dev->platform_data;
802 struct device_node *np = dev->of_node;
1d471cd1
JM		 803 int ret;
804
3bcfd222
JM		 805 if (IS_ERR(regmap))
806 return PTR_ERR(regmap);
807
808 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
658ecf77 809 GFP_KERNEL);
1d471cd1
JM		 810 if (aic32x4 == NULL)
811 return -ENOMEM;
812
3bcfd222 813 dev_set_drvdata(dev, aic32x4);
1d471cd1
JM		 814
815 if (pdata) {
816 aic32x4->power_cfg = pdata->power_cfg;
817 aic32x4->swapdacs = pdata->swapdacs;
818 aic32x4->micpga_routing = pdata->micpga_routing;
1858fe97 819 aic32x4->rstn_gpio = pdata->rstn_gpio;
4d16700d
MP		 820 } else if (np) {
821 ret = aic32x4_parse_dt(aic32x4, np);
822 if (ret) {
3bcfd222 823 dev_err(dev, "Failed to parse DT node\n");
4d16700d
MP		 824 return ret;
825 }
1d471cd1
JM		 826 } else {
827 aic32x4->power_cfg = 0;
828 aic32x4->swapdacs = false;
829 aic32x4->micpga_routing = 0;
1858fe97 830 aic32x4->rstn_gpio = -1;
1d471cd1
JM		 831 }
832
3bcfd222 833 aic32x4->mclk = devm_clk_get(dev, "mclk");
98b664e2 834 if (IS_ERR(aic32x4->mclk)) {
3bcfd222 835 dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
98b664e2
MP		 836 return PTR_ERR(aic32x4->mclk);
837 }
838
a74ab512 839 if (gpio_is_valid(aic32x4->rstn_gpio)) {
3bcfd222 840 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
752b7764
MB		 841 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
842 if (ret != 0)
843 return ret;
844 }
845
3bcfd222 846 ret = aic32x4_setup_regulators(dev, aic32x4);
239b669b 847 if (ret) {
3bcfd222 848 dev_err(dev, "Failed to setup regulators\n");
239b669b
MP		 849 return ret;
850 }
851
3bcfd222 852 ret = snd_soc_register_codec(dev,
1d471cd1 853 &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
239b669b 854 if (ret) {
3bcfd222 855 dev_err(dev, "Failed to register codec\n");
239b669b
MP		 856 aic32x4_disable_regulators(aic32x4);
857 return ret;
858 }
859
239b669b 860 return 0;
1d471cd1 861}
3bcfd222 862EXPORT_SYMBOL(aic32x4_probe);
1d471cd1 863
3bcfd222 864int aic32x4_remove(struct device *dev)
1d471cd1 865{
3bcfd222 866 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
239b669b
MP		 867
868 aic32x4_disable_regulators(aic32x4);
869
3bcfd222
JM		 870 snd_soc_unregister_codec(dev);
871
1d471cd1
JM		 872 return 0;
873}
3bcfd222 874EXPORT_SYMBOL(aic32x4_remove);
1d471cd1
JM		 875
876MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
877MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
878MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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