Commit | Line | Data |
---|---|---|
1d471cd1 JM |
1 | /* |
2 | * tlv320aic32x4.h | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | ||
10 | #ifndef _TLV320AIC32X4_H | |
11 | #define _TLV320AIC32X4_H | |
12 | ||
13 | /* tlv320aic32x4 register space (in decimal to match datasheet) */ | |
14 | ||
15 | #define AIC32X4_PAGE1 128 | |
16 | ||
17 | #define AIC32X4_PSEL 0 | |
18 | #define AIC32X4_RESET 1 | |
19 | #define AIC32X4_CLKMUX 4 | |
20 | #define AIC32X4_PLLPR 5 | |
21 | #define AIC32X4_PLLJ 6 | |
22 | #define AIC32X4_PLLDMSB 7 | |
23 | #define AIC32X4_PLLDLSB 8 | |
24 | #define AIC32X4_NDAC 11 | |
25 | #define AIC32X4_MDAC 12 | |
26 | #define AIC32X4_DOSRMSB 13 | |
27 | #define AIC32X4_DOSRLSB 14 | |
28 | #define AIC32X4_NADC 18 | |
29 | #define AIC32X4_MADC 19 | |
30 | #define AIC32X4_AOSR 20 | |
31 | #define AIC32X4_CLKMUX2 25 | |
32 | #define AIC32X4_CLKOUTM 26 | |
33 | #define AIC32X4_IFACE1 27 | |
34 | #define AIC32X4_IFACE2 28 | |
35 | #define AIC32X4_IFACE3 29 | |
36 | #define AIC32X4_BCLKN 30 | |
37 | #define AIC32X4_IFACE4 31 | |
38 | #define AIC32X4_IFACE5 32 | |
39 | #define AIC32X4_IFACE6 33 | |
40 | #define AIC32X4_DOUTCTL 53 | |
41 | #define AIC32X4_DINCTL 54 | |
42 | #define AIC32X4_DACSPB 60 | |
43 | #define AIC32X4_ADCSPB 61 | |
44 | #define AIC32X4_DACSETUP 63 | |
45 | #define AIC32X4_DACMUTE 64 | |
46 | #define AIC32X4_LDACVOL 65 | |
47 | #define AIC32X4_RDACVOL 66 | |
48 | #define AIC32X4_ADCSETUP 81 | |
49 | #define AIC32X4_ADCFGA 82 | |
50 | #define AIC32X4_LADCVOL 83 | |
51 | #define AIC32X4_RADCVOL 84 | |
52 | #define AIC32X4_LAGC1 86 | |
53 | #define AIC32X4_LAGC2 87 | |
54 | #define AIC32X4_LAGC3 88 | |
55 | #define AIC32X4_LAGC4 89 | |
56 | #define AIC32X4_LAGC5 90 | |
57 | #define AIC32X4_LAGC6 91 | |
58 | #define AIC32X4_LAGC7 92 | |
59 | #define AIC32X4_RAGC1 94 | |
60 | #define AIC32X4_RAGC2 95 | |
61 | #define AIC32X4_RAGC3 96 | |
62 | #define AIC32X4_RAGC4 97 | |
63 | #define AIC32X4_RAGC5 98 | |
64 | #define AIC32X4_RAGC6 99 | |
65 | #define AIC32X4_RAGC7 100 | |
66 | #define AIC32X4_PWRCFG (AIC32X4_PAGE1 + 1) | |
67 | #define AIC32X4_LDOCTL (AIC32X4_PAGE1 + 2) | |
68 | #define AIC32X4_OUTPWRCTL (AIC32X4_PAGE1 + 9) | |
69 | #define AIC32X4_CMMODE (AIC32X4_PAGE1 + 10) | |
70 | #define AIC32X4_HPLROUTE (AIC32X4_PAGE1 + 12) | |
71 | #define AIC32X4_HPRROUTE (AIC32X4_PAGE1 + 13) | |
72 | #define AIC32X4_LOLROUTE (AIC32X4_PAGE1 + 14) | |
73 | #define AIC32X4_LORROUTE (AIC32X4_PAGE1 + 15) | |
74 | #define AIC32X4_HPLGAIN (AIC32X4_PAGE1 + 16) | |
75 | #define AIC32X4_HPRGAIN (AIC32X4_PAGE1 + 17) | |
76 | #define AIC32X4_LOLGAIN (AIC32X4_PAGE1 + 18) | |
77 | #define AIC32X4_LORGAIN (AIC32X4_PAGE1 + 19) | |
78 | #define AIC32X4_HEADSTART (AIC32X4_PAGE1 + 20) | |
79 | #define AIC32X4_MICBIAS (AIC32X4_PAGE1 + 51) | |
80 | #define AIC32X4_LMICPGAPIN (AIC32X4_PAGE1 + 52) | |
81 | #define AIC32X4_LMICPGANIN (AIC32X4_PAGE1 + 54) | |
82 | #define AIC32X4_RMICPGAPIN (AIC32X4_PAGE1 + 55) | |
83 | #define AIC32X4_RMICPGANIN (AIC32X4_PAGE1 + 57) | |
84 | #define AIC32X4_FLOATINGINPUT (AIC32X4_PAGE1 + 58) | |
85 | #define AIC32X4_LMICPGAVOL (AIC32X4_PAGE1 + 59) | |
86 | #define AIC32X4_RMICPGAVOL (AIC32X4_PAGE1 + 60) | |
87 | ||
88 | #define AIC32X4_FREQ_12000000 12000000 | |
89 | #define AIC32X4_FREQ_24000000 24000000 | |
90 | #define AIC32X4_FREQ_25000000 25000000 | |
91 | ||
92 | #define AIC32X4_WORD_LEN_16BITS 0x00 | |
93 | #define AIC32X4_WORD_LEN_20BITS 0x01 | |
94 | #define AIC32X4_WORD_LEN_24BITS 0x02 | |
95 | #define AIC32X4_WORD_LEN_32BITS 0x03 | |
96 | ||
a405387c JM |
97 | #define AIC32X4_LADC_EN (1 << 7) |
98 | #define AIC32X4_RADC_EN (1 << 6) | |
99 | ||
1d471cd1 JM |
100 | #define AIC32X4_I2S_MODE 0x00 |
101 | #define AIC32X4_DSP_MODE 0x01 | |
102 | #define AIC32X4_RIGHT_JUSTIFIED_MODE 0x02 | |
103 | #define AIC32X4_LEFT_JUSTIFIED_MODE 0x03 | |
104 | ||
105 | #define AIC32X4_AVDDWEAKDISABLE 0x08 | |
106 | #define AIC32X4_LDOCTLEN 0x01 | |
107 | ||
108 | #define AIC32X4_LDOIN_18_36 0x01 | |
109 | #define AIC32X4_LDOIN2HP 0x02 | |
110 | ||
111 | #define AIC32X4_DACSPBLOCK_MASK 0x1f | |
112 | #define AIC32X4_ADCSPBLOCK_MASK 0x1f | |
113 | ||
114 | #define AIC32X4_PLLJ_SHIFT 6 | |
115 | #define AIC32X4_DOSRMSB_SHIFT 4 | |
116 | ||
117 | #define AIC32X4_PLLCLKIN 0x03 | |
118 | ||
119 | #define AIC32X4_MICBIAS_LDOIN 0x08 | |
120 | #define AIC32X4_MICBIAS_2075V 0x60 | |
121 | ||
122 | #define AIC32X4_LMICPGANIN_IN2R_10K 0x10 | |
609e6025 | 123 | #define AIC32X4_LMICPGANIN_CM1L_10K 0x40 |
1d471cd1 | 124 | #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 |
609e6025 | 125 | #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 |
1d471cd1 JM |
126 | |
127 | #define AIC32X4_LMICPGAVOL_NOGAIN 0x80 | |
128 | #define AIC32X4_RMICPGAVOL_NOGAIN 0x80 | |
129 | ||
130 | #define AIC32X4_BCLKMASTER 0x08 | |
131 | #define AIC32X4_WCLKMASTER 0x04 | |
132 | #define AIC32X4_PLLEN (0x01 << 7) | |
133 | #define AIC32X4_NDACEN (0x01 << 7) | |
134 | #define AIC32X4_MDACEN (0x01 << 7) | |
135 | #define AIC32X4_NADCEN (0x01 << 7) | |
136 | #define AIC32X4_MADCEN (0x01 << 7) | |
137 | #define AIC32X4_BCLKEN (0x01 << 7) | |
138 | #define AIC32X4_DACEN (0x03 << 6) | |
139 | #define AIC32X4_RDAC2LCHN (0x02 << 2) | |
140 | #define AIC32X4_LDAC2RCHN (0x02 << 4) | |
141 | #define AIC32X4_LDAC2LCHN (0x01 << 4) | |
142 | #define AIC32X4_RDAC2RCHN (0x01 << 2) | |
b44aa40f | 143 | #define AIC32X4_DAC_CHAN_MASK 0x3c |
1d471cd1 JM |
144 | |
145 | #define AIC32X4_SSTEP2WCLK 0x01 | |
146 | #define AIC32X4_MUTEON 0x0C | |
147 | #define AIC32X4_DACMOD2BCLK 0x01 | |
148 | ||
149 | #endif /* _TLV320AIC32X4_H */ |