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Merge commit 'v3.1-rc2' into HEAD
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
44d0a879 43#include <linux/platform_device.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
44d0a879 49#include <sound/initval.h>
7565fc38 50#include <sound/tlv.h>
5193d62f 51#include <sound/tlv320aic3x.h>
44d0a879
VB		 52
53#include "tlv320aic3x.h"
54
07779fdd
JN		 55#define AIC3X_NUM_SUPPLIES 4
56static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD", /* I/O Voltage */
58 "DVDD", /* Digital Core Voltage */
59 "AVDD", /* Analog DAC Voltage */
60 "DRVDD", /* ADC Analog and Output Driver Voltage */
61};
44d0a879 62
414c73ab
JN		 63static LIST_HEAD(reset_list);
64
5a895f8a
JN		 65struct aic3x_priv;
66
67struct aic3x_disable_nb {
68 struct notifier_block nb;
69 struct aic3x_priv *aic3x;
70};
71
44d0a879
VB		 72/* codec private data */
73struct aic3x_priv {
5a895f8a 74 struct snd_soc_codec *codec;
07779fdd 75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 77 enum snd_soc_control_type control_type;
78 struct aic3x_setup_data *setup;
79 void *control_data;
44d0a879 80 unsigned int sysclk;
414c73ab 81 struct list_head list;
44d0a879 82 int master;
5193d62f 83 int gpio_reset;
6c1a7d40 84 int power;
6184f105
RC		 85#define AIC3X_MODEL_3X 0
86#define AIC3X_MODEL_33 1
87#define AIC3X_MODEL_3007 2
88 u16 model;
44d0a879
VB		 89};
90
91/*
92 * AIC3X register cache
93 * We can't read the AIC3X register space when we are
94 * using 2 wire for device control, so we cache them instead.
95 * There is no point in caching the reset register
96 */
97static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
98 0x00, 0x00, 0x00, 0x10, /* 0 */
99 0x04, 0x00, 0x00, 0x00, /* 4 */
100 0x00, 0x00, 0x00, 0x01, /* 8 */
101 0x00, 0x00, 0x00, 0x80, /* 12 */
102 0x80, 0xff, 0xff, 0x78, /* 16 */
103 0x78, 0x78, 0x78, 0x78, /* 20 */
104 0x78, 0x00, 0x00, 0xfe, /* 24 */
105 0x00, 0x00, 0xfe, 0x00, /* 28 */
106 0x18, 0x18, 0x00, 0x00, /* 32 */
107 0x00, 0x00, 0x00, 0x00, /* 36 */
108 0x00, 0x00, 0x00, 0x80, /* 40 */
109 0x80, 0x00, 0x00, 0x00, /* 44 */
110 0x00, 0x00, 0x00, 0x04, /* 48 */
111 0x00, 0x00, 0x00, 0x00, /* 52 */
112 0x00, 0x00, 0x04, 0x00, /* 56 */
113 0x00, 0x00, 0x00, 0x00, /* 60 */
114 0x00, 0x04, 0x00, 0x00, /* 64 */
115 0x00, 0x00, 0x00, 0x00, /* 68 */
116 0x04, 0x00, 0x00, 0x00, /* 72 */
117 0x00, 0x00, 0x00, 0x00, /* 76 */
118 0x00, 0x00, 0x00, 0x00, /* 80 */
119 0x00, 0x00, 0x00, 0x00, /* 84 */
120 0x00, 0x00, 0x00, 0x00, /* 88 */
121 0x00, 0x00, 0x00, 0x00, /* 92 */
122 0x00, 0x00, 0x00, 0x00, /* 96 */
123 0x00, 0x00, 0x02, /* 100 */
124};
125
126/*
9900daa8
JN		 127 * read from the aic3x register space. Only use for this function is if
128 * wanting to read volatile bits from those registers that has both read-only
129 * and read/write bits. All other cases should use snd_soc_read.
44d0a879 130 */
54e7e616
DM		 131static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
132 u8 *value)
44d0a879
VB		 133{
134 u8 *cache = codec->reg_cache;
44d0a879 135
5a895f8a
JN		 136 if (codec->cache_only)
137 return -EINVAL;
44d0a879 138 if (reg >= AIC3X_CACHEREGNUM)
9900daa8 139 return -1;
5f345346 140
9900daa8
JN		 141 *value = codec->hw_read(codec, reg);
142 cache[reg] = *value;
54e7e616 143
54e7e616
DM		 144 return 0;
145}
146
44d0a879
VB		 147#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
148{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
149 .info = snd_soc_info_volsw, \
150 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
151 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
152
153/*
154 * All input lines are connected when !0xf and disconnected with 0xf bit field,
155 * so we have to use specific dapm_put call for input mixer
156 */
157static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
158 struct snd_ctl_elem_value *ucontrol)
159{
9d03545d
JN		 160 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
161 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
4453dba5
EN		 162 struct soc_mixer_control *mc =
163 (struct soc_mixer_control *)kcontrol->private_value;
164 unsigned int reg = mc->reg;
165 unsigned int shift = mc->shift;
166 int max = mc->max;
167 unsigned int mask = (1 << fls(max)) - 1;
168 unsigned int invert = mc->invert;
44d0a879
VB		 169 unsigned short val, val_mask;
170 int ret;
171 struct snd_soc_dapm_path *path;
172 int found = 0;
173
174 val = (ucontrol->value.integer.value[0] & mask);
175
176 mask = 0xf;
177 if (val)
178 val = mask;
179
180 if (invert)
181 val = mask - val;
182 val_mask = mask << shift;
183 val = val << shift;
184
185 mutex_lock(&widget->codec->mutex);
186
187 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
188 /* find dapm widget path assoc with kcontrol */
8ddab3f5 189 list_for_each_entry(path, &widget->dapm->card->paths, list) {
44d0a879
VB		 190 if (path->kcontrol != kcontrol)
191 continue;
192
193 /* found, now check type */
194 found = 1;
195 if (val)
196 /* new connection */
197 path->connect = invert ? 0 : 1;
198 else
199 /* old connection must be powered down */
200 path->connect = invert ? 1 : 0;
201 break;
202 }
203
204 if (found)
ce6120cc 205 snd_soc_dapm_sync(widget->dapm);
44d0a879
VB		 206 }
207
208 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
209
210 mutex_unlock(&widget->codec->mutex);
211 return ret;
212}
213
214static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
215static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
216static const char *aic3x_left_hpcom_mux[] =
217 { "differential of HPLOUT", "constant VCM", "single-ended" };
218static const char *aic3x_right_hpcom_mux[] =
219 { "differential of HPROUT", "constant VCM", "single-ended",
220 "differential of HPLCOM", "external feedback" };
221static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 222static const char *aic3x_adc_hpf[] =
223 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 224
225#define LDAC_ENUM 0
226#define RDAC_ENUM 1
227#define LHPCOM_ENUM 2
228#define RHPCOM_ENUM 3
404b5665
JN		 229#define LINE1L_2_L_ENUM 4
230#define LINE1L_2_R_ENUM 5
231#define LINE1R_2_L_ENUM 6
232#define LINE1R_2_R_ENUM 7
233#define LINE2L_ENUM 8
234#define LINE2R_ENUM 9
235#define ADC_HPF_ENUM 10
44d0a879
VB		 236
237static const struct soc_enum aic3x_enum[] = {
238 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
239 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
240 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
241 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
242 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
404b5665
JN		 243 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
244 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
44d0a879
VB		 245 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
246 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
247 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 248 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 249};
250
7565fc38
JN		 251/*
252 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
253 */
254static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
255/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
256static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
257/*
258 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
259 * Step size is approximately 0.5 dB over most of the scale but increasing
260 * near the very low levels.
261 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
262 * but having increasing dB difference below that (and where it doesn't count
263 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
264 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
265 */
266static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
267
44d0a879
VB		 268static const struct snd_kcontrol_new aic3x_snd_controls[] = {
269 /* Output */
7565fc38
JN		 270 SOC_DOUBLE_R_TLV("PCM Playback Volume",
271 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 272
098b1718
JN		 273 /*
274 * Output controls that map to output mixer switches. Note these are
275 * only for swapped L-to-R and R-to-L routes. See below stereo controls
276 * for direct L-to-L and R-to-R routes.
277 */
278 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
279 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
280 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
281 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
282 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
283 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
284
285 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
286 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
287 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
288 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
289 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
290 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
291
292 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
293 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
294 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
295 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
296 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
297 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
298
299 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
300 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
301 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
302 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
303 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
304 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
305
306 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
307 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
308 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
309 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
310 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
311 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
312
313 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
314 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
315 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
316 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
317 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
318 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
319
320 /* Stereo output controls for direct L-to-L and R-to-R routes */
321 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
322 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
323 0, 118, 1, output_stage_tlv),
324 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
325 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
326 0, 118, 1, output_stage_tlv),
7565fc38
JN		 327 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
328 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
329 0, 118, 1, output_stage_tlv),
098b1718
JN		 330
331 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
332 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 333 0, 118, 1, output_stage_tlv),
098b1718
JN		 334 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
335 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 336 0, 118, 1, output_stage_tlv),
7565fc38
JN		 337 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
338 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
339 0, 118, 1, output_stage_tlv),
098b1718
JN		 340
341 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
342 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 343 0, 118, 1, output_stage_tlv),
098b1718
JN		 344 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
345 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 346 0, 118, 1, output_stage_tlv),
7565fc38
JN		 347 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
348 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
349 0, 118, 1, output_stage_tlv),
098b1718
JN		 350
351 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
352 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 353 0, 118, 1, output_stage_tlv),
098b1718
JN		 354 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
355 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 356 0, 118, 1, output_stage_tlv),
7565fc38
JN		 357 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
358 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
359 0, 118, 1, output_stage_tlv),
098b1718
JN		 360
361 /* Output pin mute controls */
362 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
363 0x01, 0),
364 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
365 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
366 0x01, 0),
f9bc0297 367 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 368 0x01, 0),
44d0a879
VB		 369
370 /*
371 * Note: enable Automatic input Gain Controller with care. It can
372 * adjust PGA to max value when ADC is on and will never go back.
373 */
374 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
375
376 /* Input */
7565fc38
JN		 377 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
378 0, 119, 0, adc_tlv),
44d0a879 379 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 380
381 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 382};
383
6184f105
RC		 384/*
385 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
386 */
387static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
388
389static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
390 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
391
44d0a879
VB		 392/* Left DAC Mux */
393static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
394SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
395
396/* Right DAC Mux */
397static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
398SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
399
400/* Left HPCOM Mux */
401static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
402SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
403
404/* Right HPCOM Mux */
405static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
406SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
407
c3b79e05
JN		 408/* Left Line Mixer */
409static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
410 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
411 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
412 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
413 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
414 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 416};
417
c3b79e05
JN		 418/* Right Line Mixer */
419static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
420 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
421 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
422 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
423 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
426};
427
428/* Mono Mixer */
429static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
430 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
431 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
432 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
436};
437
438/* Left HP Mixer */
439static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
440 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
441 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
442 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
446};
447
448/* Right HP Mixer */
449static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
450 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
452 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
456};
457
458/* Left HPCOM Mixer */
459static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
460 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
462 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
463 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
464 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
466};
467
468/* Right HPCOM Mixer */
469static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
470 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
472 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
473 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
474 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
475 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 476};
477
478/* Left PGA Mixer */
479static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
480 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 481 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 482 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
483 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 484 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 485};
486
487/* Right PGA Mixer */
488static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
489 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 490 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 491 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 492 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 493 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
494};
495
496/* Left Line1 Mux */
404b5665
JN		 497static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
498SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
499static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
500SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
44d0a879
VB		 501
502/* Right Line1 Mux */
404b5665
JN		 503static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
504SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
505static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
506SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
44d0a879
VB		 507
508/* Left Line2 Mux */
509static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
510SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
511
512/* Right Line2 Mux */
513static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
514SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
515
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VB		 516static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
517 /* Left DAC to Left Outputs */
518 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
519 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
520 &aic3x_left_dac_mux_controls),
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VB		 521 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
522 &aic3x_left_hpcom_mux_controls),
523 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
524 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
525 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
526
527 /* Right DAC to Right Outputs */
528 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
529 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
530 &aic3x_right_dac_mux_controls),
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VB		 531 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
532 &aic3x_right_hpcom_mux_controls),
533 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
534 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
535 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
536
537 /* Mono Output */
538 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
539
54f01916 540 /* Inputs to Left ADC */
44d0a879
VB		 541 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
542 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
543 &aic3x_left_pga_mixer_controls[0],
544 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
545 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 546 &aic3x_left_line1l_mux_controls),
54f01916 547 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 548 &aic3x_left_line1r_mux_controls),
44d0a879
VB		 549 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
550 &aic3x_left_line2_mux_controls),
551
54f01916 552 /* Inputs to Right ADC */
44d0a879
VB		 553 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
554 LINE1R_2_RADC_CTRL, 2, 0),
555 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
556 &aic3x_right_pga_mixer_controls[0],
557 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916 558 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 559 &aic3x_right_line1l_mux_controls),
44d0a879 560 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 561 &aic3x_right_line1r_mux_controls),
44d0a879
VB		 562 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
563 &aic3x_right_line2_mux_controls),
564
ee15ffdb
JN		 565 /*
566 * Not a real mic bias widget but similar function. This is for dynamic
567 * control of GPIO1 digital mic modulator clock output function when
568 * using digital mic.
569 */
570 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
571 AIC3X_GPIO1_REG, 4, 0xf,
572 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
573 AIC3X_GPIO1_FUNC_DISABLED),
574
575 /*
576 * Also similar function like mic bias. Selects digital mic with
577 * configurable oversampling rate instead of ADC converter.
578 */
579 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
580 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
581 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
582 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
583 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
584 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
585
44d0a879 586 /* Mic Bias */
0bd72a3d
JN		 587 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
588 MICBIAS_CTRL, 6, 3, 1, 0),
589 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
590 MICBIAS_CTRL, 6, 3, 2, 0),
591 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
592 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 593
c3b79e05
JN		 594 /* Output mixers */
595 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
596 &aic3x_left_line_mixer_controls[0],
597 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
598 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
599 &aic3x_right_line_mixer_controls[0],
600 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
601 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
602 &aic3x_mono_mixer_controls[0],
603 ARRAY_SIZE(aic3x_mono_mixer_controls)),
604 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
605 &aic3x_left_hp_mixer_controls[0],
606 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
607 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
608 &aic3x_right_hp_mixer_controls[0],
609 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
610 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
611 &aic3x_left_hpcom_mixer_controls[0],
612 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
613 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
614 &aic3x_right_hpcom_mixer_controls[0],
615 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 616
617 SND_SOC_DAPM_OUTPUT("LLOUT"),
618 SND_SOC_DAPM_OUTPUT("RLOUT"),
619 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
620 SND_SOC_DAPM_OUTPUT("HPLOUT"),
621 SND_SOC_DAPM_OUTPUT("HPROUT"),
622 SND_SOC_DAPM_OUTPUT("HPLCOM"),
623 SND_SOC_DAPM_OUTPUT("HPRCOM"),
624
625 SND_SOC_DAPM_INPUT("MIC3L"),
626 SND_SOC_DAPM_INPUT("MIC3R"),
627 SND_SOC_DAPM_INPUT("LINE1L"),
628 SND_SOC_DAPM_INPUT("LINE1R"),
629 SND_SOC_DAPM_INPUT("LINE2L"),
630 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 631
632 /*
633 * Virtual output pin to detection block inside codec. This can be
634 * used to keep codec bias on if gpio or detection features are needed.
635 * Force pin on or construct a path with an input jack and mic bias
636 * widgets.
637 */
638 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 639};
640
6184f105
RC		 641static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
642 /* Class-D outputs */
643 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
644 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
645
646 SND_SOC_DAPM_OUTPUT("SPOP"),
647 SND_SOC_DAPM_OUTPUT("SPOM"),
648};
649
d0cc0d3a 650static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 651 /* Left Input */
652 {"Left Line1L Mux", "single-ended", "LINE1L"},
653 {"Left Line1L Mux", "differential", "LINE1L"},
654
655 {"Left Line2L Mux", "single-ended", "LINE2L"},
656 {"Left Line2L Mux", "differential", "LINE2L"},
657
658 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 659 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 660 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
661 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 662 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 663
664 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 665 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 666
667 /* Right Input */
668 {"Right Line1R Mux", "single-ended", "LINE1R"},
669 {"Right Line1R Mux", "differential", "LINE1R"},
670
671 {"Right Line2R Mux", "single-ended", "LINE2R"},
672 {"Right Line2R Mux", "differential", "LINE2R"},
673
54f01916 674 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 675 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
676 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 677 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 678 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
679
680 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 681 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 682
ee15ffdb
JN		 683 /*
684 * Logical path between digital mic enable and GPIO1 modulator clock
685 * output function
686 */
687 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
688 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
689 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 690
691 /* Left DAC Output */
692 {"Left DAC Mux", "DAC_L1", "Left DAC"},
693 {"Left DAC Mux", "DAC_L2", "Left DAC"},
694 {"Left DAC Mux", "DAC_L3", "Left DAC"},
695
696 /* Right DAC Output */
697 {"Right DAC Mux", "DAC_R1", "Right DAC"},
698 {"Right DAC Mux", "DAC_R2", "Right DAC"},
699 {"Right DAC Mux", "DAC_R3", "Right DAC"},
700
701 /* Left Line Output */
702 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
703 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
704 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
705 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
706 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
707 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
708
709 {"Left Line Out", NULL, "Left Line Mixer"},
710 {"Left Line Out", NULL, "Left DAC Mux"},
711 {"LLOUT", NULL, "Left Line Out"},
712
713 /* Right Line Output */
714 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
715 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
716 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
717 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
718 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
719 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
720
721 {"Right Line Out", NULL, "Right Line Mixer"},
722 {"Right Line Out", NULL, "Right DAC Mux"},
723 {"RLOUT", NULL, "Right Line Out"},
724
725 /* Mono Output */
726 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
727 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
728 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
729 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
730 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
731 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
732
733 {"Mono Out", NULL, "Mono Mixer"},
734 {"MONO_LOUT", NULL, "Mono Out"},
735
736 /* Left HP Output */
737 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
738 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
739 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
740 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
741 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
742 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
743
744 {"Left HP Out", NULL, "Left HP Mixer"},
745 {"Left HP Out", NULL, "Left DAC Mux"},
746 {"HPLOUT", NULL, "Left HP Out"},
747
748 /* Right HP Output */
749 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
750 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
751 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
752 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
753 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
754 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
755
756 {"Right HP Out", NULL, "Right HP Mixer"},
757 {"Right HP Out", NULL, "Right DAC Mux"},
758 {"HPROUT", NULL, "Right HP Out"},
759
760 /* Left HPCOM Output */
761 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
762 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
763 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
764 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
765 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
766 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
767
768 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
769 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
770 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
771 {"Left HP Com", NULL, "Left HPCOM Mux"},
772 {"HPLCOM", NULL, "Left HP Com"},
773
774 /* Right HPCOM Output */
775 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
776 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
777 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
778 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
779 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
780 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
781
782 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
783 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
784 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
785 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
786 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
787 {"Right HP Com", NULL, "Right HPCOM Mux"},
788 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 789};
790
6184f105
RC		 791static const struct snd_soc_dapm_route intercon_3007[] = {
792 /* Class-D outputs */
793 {"Left Class-D Out", NULL, "Left Line Out"},
794 {"Right Class-D Out", NULL, "Left Line Out"},
795 {"SPOP", NULL, "Left Class-D Out"},
796 {"SPOM", NULL, "Right Class-D Out"},
797};
798
44d0a879
VB		 799static int aic3x_add_widgets(struct snd_soc_codec *codec)
800{
6184f105 801 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 802 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 803
ce6120cc 804 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
d0cc0d3a 805 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 806
807 /* set up audio path interconnects */
ce6120cc 808 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
44d0a879 809
6184f105 810 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 811 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 812 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 813 snd_soc_dapm_add_routes(dapm, intercon_3007,
814 ARRAY_SIZE(intercon_3007));
6184f105
RC		 815 }
816
44d0a879
VB		 817 return 0;
818}
819
44d0a879 820static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 821 struct snd_pcm_hw_params *params,
822 struct snd_soc_dai *dai)
44d0a879
VB		 823{
824 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 825 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 826 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 827 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 828 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
829 u16 d, pll_d = 1;
06c71282 830 u8 reg;
255173b4 831 int clk;
44d0a879 832
4f9c16cc 833 /* select data word length */
e18eca43 834 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 835 switch (params_format(params)) {
836 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 837 break;
4f9c16cc
DM		 838 case SNDRV_PCM_FORMAT_S20_3LE:
839 data |= (0x01 << 4);
44d0a879 840 break;
4f9c16cc
DM		 841 case SNDRV_PCM_FORMAT_S24_LE:
842 data |= (0x02 << 4);
44d0a879 843 break;
4f9c16cc
DM		 844 case SNDRV_PCM_FORMAT_S32_LE:
845 data |= (0x03 << 4);
44d0a879
VB		 846 break;
847 }
e18eca43 848 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 849
850 /* Fsref can be 44100 or 48000 */
851 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
852
853 /* Try to find a value for Q which allows us to bypass the PLL and
854 * generate CODEC_CLK directly. */
855 for (pll_q = 2; pll_q < 18; pll_q++)
856 if (aic3x->sysclk / (128 * pll_q) == fsref) {
857 bypass_pll = 1;
858 break;
859 }
860
861 if (bypass_pll) {
862 pll_q &= 0xf;
e18eca43
JN		 863 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
864 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 865 /* disable PLL if it is bypassed */
e18eca43
JN		 866 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
867 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
06c71282
C		 868
869 } else {
e18eca43 870 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 871 /* enable PLL when it is used */
e18eca43
JN		 872 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
873 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
06c71282 874 }
4f9c16cc
DM		 875
876 /* Route Left DAC to left channel input and
877 * right DAC to right channel input */
878 data = (LDAC2LCH | RDAC2RCH);
879 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
880 if (params_rate(params) >= 64000)
881 data |= DUAL_RATE_MODE;
e18eca43 882 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 883
884 /* codec sample rate select */
4f9c16cc
DM		 885 data = (fsref * 20) / params_rate(params);
886 if (params_rate(params) < 64000)
887 data /= 2;
888 data /= 5;
889 data -= 2;
44d0a879 890 data |= (data << 4);
e18eca43 891 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 892
4f9c16cc
DM		 893 if (bypass_pll)
894 return 0;
895
25985edc 896 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 897 * one wins the game. Try with d==0 first, next with d!=0.
898 * Constraints for j are according to the datasheet.
4f9c16cc 899 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 900 */
255173b4 901
4f9c16cc
DM		 902 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
903
904 for (r = 1; r <= 16; r++)
905 for (p = 1; p <= 8; p++) {
255173b4
PM		 906 for (j = 4; j <= 55; j++) {
907 /* This is actually 1000*((j+(d/10000))*r)/p
908 * The term had to be converted to get
909 * rid of the division by 10000; d = 0 here
910 */
5baf8315 911 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 912
913 /* Check whether this values get closer than
914 * the best ones we had before
915 */
5baf8315 916 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 917 abs(codec_clk - last_clk)) {
918 pll_j = j; pll_d = 0;
919 pll_r = r; pll_p = p;
5baf8315 920 last_clk = tmp_clk;
255173b4
PM		 921 }
922
923 /* Early exit for exact matches */
5baf8315 924 if (tmp_clk == codec_clk)
255173b4
PM		 925 goto found;
926 }
927 }
4f9c16cc 928
255173b4
PM		 929 /* try with d != 0 */
930 for (p = 1; p <= 8; p++) {
931 j = codec_clk * p / 1000;
4f9c16cc 932
255173b4
PM		 933 if (j < 4 || j > 11)
934 continue;
4f9c16cc 935
255173b4
PM		 936 /* do not use codec_clk here since we'd loose precision */
937 d = ((2048 * p * fsref) - j * aic3x->sysclk)
938 * 100 / (aic3x->sysclk/100);
4f9c16cc 939
255173b4 940 clk = (10000 * j + d) / (10 * p);
4f9c16cc 941
255173b4
PM		 942 /* check whether this values get closer than the best
943 * ones we had before */
944 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
945 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
946 last_clk = clk;
4f9c16cc
DM		 947 }
948
255173b4
PM		 949 /* Early exit for exact matches */
950 if (clk == codec_clk)
951 goto found;
952 }
953
4f9c16cc
DM		 954 if (last_clk == 0) {
955 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
956 return -EINVAL;
957 }
44d0a879 958
255173b4 959found:
e18eca43
JN		 960 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
961 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
962 data | (pll_p << PLLP_SHIFT));
963 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
964 pll_r << PLLR_SHIFT);
965 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
966 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
967 (pll_d >> 6) << PLLD_MSB_SHIFT);
968 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
969 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 970
44d0a879
VB		 971 return 0;
972}
973
e550e17f 974static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 975{
976 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 977 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
978 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 979
980 if (mute) {
e18eca43
JN		 981 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
982 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 983 } else {
e18eca43
JN		 984 snd_soc_write(codec, LDAC_VOL, ldac_reg);
985 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 986 }
987
988 return 0;
989}
990
e550e17f 991static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 992 int clk_id, unsigned int freq, int dir)
993{
994 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 995 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 996
4f9c16cc
DM		 997 aic3x->sysclk = freq;
998 return 0;
44d0a879
VB		 999}
1000
e550e17f 1001static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1002 unsigned int fmt)
1003{
1004 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1005 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 1006 u8 iface_areg, iface_breg;
a24f4f68 1007 int delay = 0;
81971a14 1008
e18eca43
JN		 1009 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1010 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1011
1012 /* set master/slave audio interface */
1013 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1014 case SND_SOC_DAIFMT_CBM_CFM:
1015 aic3x->master = 1;
1016 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1017 break;
1018 case SND_SOC_DAIFMT_CBS_CFS:
1019 aic3x->master = 0;
1020 break;
1021 default:
1022 return -EINVAL;
1023 }
1024
4b7d2831
JN		 1025 /*
1026 * match both interface format and signal polarities since they
1027 * are fixed
1028 */
1029 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1030 SND_SOC_DAIFMT_INV_MASK)) {
1031 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1032 break;
a24f4f68
TK		 1033 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1034 delay = 1;
4b7d2831 1035 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1036 iface_breg |= (0x01 << 6);
1037 break;
4b7d2831 1038 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1039 iface_breg |= (0x02 << 6);
1040 break;
4b7d2831 1041 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1042 iface_breg |= (0x03 << 6);
1043 break;
1044 default:
1045 return -EINVAL;
1046 }
1047
1048 /* set iface */
e18eca43
JN		 1049 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1050 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1051 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1052
1053 return 0;
1054}
1055
6c1a7d40
JN		 1056static int aic3x_init_3007(struct snd_soc_codec *codec)
1057{
1058 u8 tmp1, tmp2, *cache = codec->reg_cache;
1059
1060 /*
1061 * There is no need to cache writes to undocumented page 0xD but
1062 * respective page 0 register cache entries must be preserved
1063 */
1064 tmp1 = cache[0xD];
1065 tmp2 = cache[0x8];
1066 /* Class-D speaker driver init; datasheet p. 46 */
1067 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1068 snd_soc_write(codec, 0xD, 0x0D);
1069 snd_soc_write(codec, 0x8, 0x5C);
1070 snd_soc_write(codec, 0x8, 0x5D);
1071 snd_soc_write(codec, 0x8, 0x5C);
1072 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1073 cache[0xD] = tmp1;
1074 cache[0x8] = tmp2;
1075
1076 return 0;
1077}
1078
5a895f8a
JN		 1079static int aic3x_regulator_event(struct notifier_block *nb,
1080 unsigned long event, void *data)
1081{
1082 struct aic3x_disable_nb *disable_nb =
1083 container_of(nb, struct aic3x_disable_nb, nb);
1084 struct aic3x_priv *aic3x = disable_nb->aic3x;
1085
1086 if (event & REGULATOR_EVENT_DISABLE) {
1087 /*
1088 * Put codec to reset and require cache sync as at least one
1089 * of the supplies was disabled
1090 */
79ee820d 1091 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a
JN		 1092 gpio_set_value(aic3x->gpio_reset, 0);
1093 aic3x->codec->cache_sync = 1;
1094 }
1095
1096 return 0;
1097}
1098
6c1a7d40
JN		 1099static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1100{
1101 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1102 int i, ret;
1103 u8 *cache = codec->reg_cache;
1104
1105 if (power) {
1106 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1107 aic3x->supplies);
1108 if (ret)
1109 goto out;
1110 aic3x->power = 1;
5a895f8a
JN		 1111 /*
1112 * Reset release and cache sync is necessary only if some
1113 * supply was off or if there were cached writes
1114 */
1115 if (!codec->cache_sync)
1116 goto out;
1117
79ee820d 1118 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1119 udelay(1);
1120 gpio_set_value(aic3x->gpio_reset, 1);
1121 }
1122
1123 /* Sync reg_cache with the hardware */
1124 codec->cache_only = 0;
508b7686 1125 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
6c1a7d40
JN		 1126 snd_soc_write(codec, i, cache[i]);
1127 if (aic3x->model == AIC3X_MODEL_3007)
1128 aic3x_init_3007(codec);
1129 codec->cache_sync = 0;
1130 } else {
9fb352b1
JN		 1131 /*
1132 * Do soft reset to this codec instance in order to clear
1133 * possible VDD leakage currents in case the supply regulators
1134 * remain on
1135 */
1136 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1137 codec->cache_sync = 1;
6c1a7d40 1138 aic3x->power = 0;
5a895f8a
JN		 1139 /* HW writes are needless when bias is off */
1140 codec->cache_only = 1;
6c1a7d40
JN		 1141 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1142 aic3x->supplies);
1143 }
1144out:
1145 return ret;
1146}
1147
0be9898a
MB		 1148static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1149 enum snd_soc_bias_level level)
44d0a879 1150{
b2c812e2 1151 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 1152 u8 reg;
1153
0be9898a
MB		 1154 switch (level) {
1155 case SND_SOC_BIAS_ON:
db13802e
JN		 1156 break;
1157 case SND_SOC_BIAS_PREPARE:
ce6120cc 1158 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1159 aic3x->master) {
44d0a879 1160 /* enable pll */
e18eca43
JN		 1161 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1162 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1163 reg | PLL_ENABLE);
44d0a879
VB		 1164 }
1165 break;
0be9898a 1166 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1167 if (!aic3x->power)
1168 aic3x_set_power(codec, 1);
ce6120cc 1169 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1170 aic3x->master) {
44d0a879 1171 /* disable pll */
e18eca43
JN		 1172 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1173 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1174 reg & ~PLL_ENABLE);
44d0a879
VB		 1175 }
1176 break;
c23fd751 1177 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1178 if (aic3x->power)
1179 aic3x_set_power(codec, 0);
c23fd751 1180 break;
44d0a879 1181 }
ce6120cc 1182 codec->dapm.bias_level = level;
44d0a879
VB		 1183
1184 return 0;
1185}
1186
54e7e616
DM		 1187void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1188{
1189 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1190 u8 bit = gpio ? 3: 0;
e18eca43
JN		 1191 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1192 snd_soc_write(codec, reg, val | (!!state << bit));
54e7e616
DM		 1193}
1194EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1195
1196int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1197{
1198 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
fe99b559 1199 u8 val = 0, bit = gpio ? 2 : 1;
54e7e616
DM		 1200
1201 aic3x_read(codec, reg, &val);
1202 return (val >> bit) & 1;
1203}
1204EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1205
6f2a974b
DM		 1206void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1207 int headset_debounce, int button_debounce)
1208{
1209 u8 val;
1210
1211 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1212 << AIC3X_HEADSET_DETECT_SHIFT) |
1213 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1214 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1215 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1216 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1217
1218 if (detect & AIC3X_HEADSET_DETECT_MASK)
1219 val |= AIC3X_HEADSET_DETECT_ENABLED;
1220
e18eca43 1221 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
6f2a974b
DM		 1222}
1223EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1224
54e7e616
DM		 1225int aic3x_headset_detected(struct snd_soc_codec *codec)
1226{
fe99b559 1227 u8 val = 0;
6f2a974b
DM		 1228 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1229 return (val >> 4) & 1;
54e7e616
DM		 1230}
1231EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1232
6f2a974b
DM		 1233int aic3x_button_pressed(struct snd_soc_codec *codec)
1234{
fe99b559 1235 u8 val = 0;
6f2a974b
DM		 1236 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1237 return (val >> 5) & 1;
1238}
1239EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1240
44d0a879
VB		 1241#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1242#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1243 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1244
6335d055
EM		 1245static struct snd_soc_dai_ops aic3x_dai_ops = {
1246 .hw_params = aic3x_hw_params,
1247 .digital_mute = aic3x_mute,
1248 .set_sysclk = aic3x_set_dai_sysclk,
1249 .set_fmt = aic3x_set_dai_fmt,
1250};
1251
f0fba2ad
LG		 1252static struct snd_soc_dai_driver aic3x_dai = {
1253 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1254 .playback = {
1255 .stream_name = "Playback",
1256 .channels_min = 1,
1257 .channels_max = 2,
1258 .rates = AIC3X_RATES,
1259 .formats = AIC3X_FORMATS,},
1260 .capture = {
1261 .stream_name = "Capture",
1262 .channels_min = 1,
1263 .channels_max = 2,
1264 .rates = AIC3X_RATES,
1265 .formats = AIC3X_FORMATS,},
6335d055 1266 .ops = &aic3x_dai_ops,
14017615 1267 .symmetric_rates = 1,
44d0a879 1268};
44d0a879 1269
f0fba2ad 1270static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
44d0a879 1271{
0be9898a 1272 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1273
1274 return 0;
1275}
1276
f0fba2ad 1277static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1278{
29e189c2 1279 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1280
1281 return 0;
1282}
1283
1284/*
1285 * initialise the AIC3X driver
1286 * register the mixer and dsp interfaces with the kernel
1287 */
cb3826f5 1288static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1289{
6184f105 1290 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5
BD		 1291 int reg;
1292
e18eca43
JN		 1293 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1294 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1295
44d0a879 1296 /* DAC default volume and mute */
e18eca43
JN		 1297 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1298 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1299
1300 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1301 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1302 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1303 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1304 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1305 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1306 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1307 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1308 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1309 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1310 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1311
1312 /* unmute all outputs */
e18eca43
JN		 1313 reg = snd_soc_read(codec, LLOPM_CTRL);
1314 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
1315 reg = snd_soc_read(codec, RLOPM_CTRL);
1316 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
1317 reg = snd_soc_read(codec, MONOLOPM_CTRL);
1318 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1319 reg = snd_soc_read(codec, HPLOUT_CTRL);
1320 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1321 reg = snd_soc_read(codec, HPROUT_CTRL);
1322 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
1323 reg = snd_soc_read(codec, HPLCOM_CTRL);
1324 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1325 reg = snd_soc_read(codec, HPRCOM_CTRL);
1326 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
44d0a879
VB		 1327
1328 /* ADC default volume and unmute */
e18eca43
JN		 1329 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1330 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1331 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1332 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1333 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1334
1335 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1336 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1337 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1338 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1339 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1340 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1341 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1342 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1343 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1344 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1345 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1346
1347 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1348 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1349 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1350 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1351 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1352 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1353 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1354 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1355 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1356 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1357 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1358
6184f105 1359 if (aic3x->model == AIC3X_MODEL_3007) {
6c1a7d40 1360 aic3x_init_3007(codec);
e18eca43 1361 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1362 }
1363
cb3826f5
BD		 1364 return 0;
1365}
54e7e616 1366
414c73ab
JN		 1367static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1368{
1369 struct aic3x_priv *a;
1370
1371 list_for_each_entry(a, &reset_list, list) {
1372 if (gpio_is_valid(aic3x->gpio_reset) &&
1373 aic3x->gpio_reset == a->gpio_reset)
1374 return true;
1375 }
1376
1377 return false;
1378}
1379
f0fba2ad 1380static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1381{
f0fba2ad 1382 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1383 int ret, i;
f0fba2ad 1384
414c73ab 1385 INIT_LIST_HEAD(&aic3x->list);
f0fba2ad 1386 codec->control_data = aic3x->control_data;
5a895f8a 1387 aic3x->codec = codec;
ce6120cc 1388 codec->dapm.idle_bias_off = 1;
cb3826f5 1389
a84a441b
JN		 1390 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1391 if (ret != 0) {
1392 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1393 return ret;
1394 }
1395
414c73ab
JN		 1396 if (gpio_is_valid(aic3x->gpio_reset) &&
1397 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1398 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1399 if (ret != 0)
1400 goto err_gpio;
1401 gpio_direction_output(aic3x->gpio_reset, 0);
1402 }
1403
1404 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1405 aic3x->supplies[i].supply = aic3x_supply_names[i];
1406
1407 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1408 aic3x->supplies);
1409 if (ret != 0) {
1410 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1411 goto err_get;
1412 }
5a895f8a
JN		 1413 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1414 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1415 aic3x->disable_nb[i].aic3x = aic3x;
1416 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1417 &aic3x->disable_nb[i].nb);
1418 if (ret) {
1419 dev_err(codec->dev,
1420 "Failed to request regulator notifier: %d\n",
1421 ret);
1422 goto err_notif;
1423 }
1424 }
2f24111a 1425
7d1be0a6 1426 codec->cache_only = 1;
37b47656
JN		 1427 aic3x_init(codec);
1428
f0fba2ad
LG		 1429 if (aic3x->setup) {
1430 /* setup GPIO functions */
e18eca43
JN		 1431 snd_soc_write(codec, AIC3X_GPIO1_REG,
1432 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1433 snd_soc_write(codec, AIC3X_GPIO2_REG,
1434 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1435 }
1436
f0fba2ad
LG		 1437 snd_soc_add_controls(codec, aic3x_snd_controls,
1438 ARRAY_SIZE(aic3x_snd_controls));
6184f105
RC		 1439 if (aic3x->model == AIC3X_MODEL_3007)
1440 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1441
f0fba2ad 1442 aic3x_add_widgets(codec);
414c73ab 1443 list_add(&aic3x->list, &reset_list);
cb3826f5
BD		 1444
1445 return 0;
2f24111a 1446
5a895f8a
JN		 1447err_notif:
1448 while (i--)
1449 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1450 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1451 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1452err_get:
414c73ab
JN		 1453 if (gpio_is_valid(aic3x->gpio_reset) &&
1454 !aic3x_is_shared_reset(aic3x))
2f24111a
JN		 1455 gpio_free(aic3x->gpio_reset);
1456err_gpio:
2f24111a 1457 return ret;
44d0a879
VB		 1458}
1459
f0fba2ad 1460static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1461{
2f24111a 1462 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1463 int i;
2f24111a 1464
f0fba2ad 1465 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
414c73ab
JN		 1466 list_del(&aic3x->list);
1467 if (gpio_is_valid(aic3x->gpio_reset) &&
1468 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1469 gpio_set_value(aic3x->gpio_reset, 0);
1470 gpio_free(aic3x->gpio_reset);
1471 }
5a895f8a
JN		 1472 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1473 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1474 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1475 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1476
cb3826f5
BD		 1477 return 0;
1478}
44d0a879 1479
f0fba2ad 1480static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad
LG		 1481 .set_bias_level = aic3x_set_bias_level,
1482 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1483 .reg_word_size = sizeof(u8),
1484 .reg_cache_default = aic3x_reg,
1485 .probe = aic3x_probe,
1486 .remove = aic3x_remove,
1487 .suspend = aic3x_suspend,
1488 .resume = aic3x_resume,
1489};
1490
44d0a879
VB		 1491#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1492/*
1493 * AIC3X 2 wire address can be up to 4 devices with device addresses
1494 * 0x18, 0x19, 0x1A, 0x1B
1495 */
44d0a879 1496
6184f105
RC		 1497static const struct i2c_device_id aic3x_i2c_id[] = {
1498 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1499 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1500 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1501 { }
1502};
1503MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1504
44d0a879
VB		 1505/*
1506 * If the i2c layer weren't so broken, we could pass this kind of data
1507 * around
1508 */
ba8ed121
JD		 1509static int aic3x_i2c_probe(struct i2c_client *i2c,
1510 const struct i2c_device_id *id)
44d0a879 1511{
5193d62f 1512 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1513 struct aic3x_priv *aic3x;
2f24111a 1514 int ret;
6184f105 1515 const struct i2c_device_id *tbl;
44d0a879 1516
cb3826f5
BD		 1517 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1518 if (aic3x == NULL) {
1519 dev_err(&i2c->dev, "failed to create private data\n");
1520 return -ENOMEM;
1521 }
1522
f0fba2ad 1523 aic3x->control_data = i2c;
a84a441b
JN		 1524 aic3x->control_type = SND_SOC_I2C;
1525
cb3826f5 1526 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1527 if (pdata) {
1528 aic3x->gpio_reset = pdata->gpio_reset;
1529 aic3x->setup = pdata->setup;
1530 } else {
1531 aic3x->gpio_reset = -1;
1532 }
cb3826f5 1533
6184f105
RC		 1534 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1535 if (!strcmp(tbl->name, id->name))
1536 break;
1537 }
1538 aic3x->model = tbl - aic3x_i2c_id;
1539
f0fba2ad
LG		 1540 ret = snd_soc_register_codec(&i2c->dev,
1541 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1542 if (ret < 0)
2f24111a 1543 kfree(aic3x);
07779fdd 1544 return ret;
44d0a879
VB		 1545}
1546
ba8ed121 1547static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1548{
f0fba2ad
LG		 1549 snd_soc_unregister_codec(&client->dev);
1550 kfree(i2c_get_clientdata(client));
1551 return 0;
44d0a879
VB		 1552}
1553
44d0a879
VB		 1554/* machine i2c codec control layer */
1555static struct i2c_driver aic3x_i2c_driver = {
1556 .driver = {
f0fba2ad 1557 .name = "tlv320aic3x-codec",
44d0a879
VB		 1558 .owner = THIS_MODULE,
1559 },
cb3826f5 1560 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1561 .remove = aic3x_i2c_remove,
1562 .id_table = aic3x_i2c_id,
44d0a879
VB		 1563};
1564#endif
1565
f0fba2ad 1566static int __init aic3x_modinit(void)
44d0a879 1567{
44d0a879 1568 int ret = 0;
f0fba2ad
LG		 1569#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1570 ret = i2c_add_driver(&aic3x_i2c_driver);
1571 if (ret != 0) {
1572 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1573 ret);
44d0a879 1574 }
f0fba2ad 1575#endif
44d0a879
VB		 1576 return ret;
1577}
64089b84
MB		 1578module_init(aic3x_modinit);
1579
1580static void __exit aic3x_exit(void)
1581{
f0fba2ad
LG		 1582#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1583 i2c_del_driver(&aic3x_i2c_driver);
1584#endif
64089b84
MB		 1585}
1586module_exit(aic3x_exit);
1587
44d0a879
VB		 1588MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1589MODULE_AUTHOR("Vladimir Barinov");
1590MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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