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44d0a879 VB |
1 | /* |
2 | * ALSA SoC TLV320AIC3X codec driver | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
44d0a879 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * Based on sound/soc/codecs/wm8753.c by Liam Girdwood | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * Notes: | |
14 | * The AIC3X is a driver for a low power stereo audio | |
15 | * codecs aic31, aic32, aic33. | |
16 | * | |
17 | * It supports full aic33 codec functionality. | |
18 | * The compatibility with aic32, aic31 is as follows: | |
19 | * aic32 | aic31 | |
20 | * --------------------------------------- | |
21 | * MONO_LOUT -> N/A | MONO_LOUT -> N/A | |
22 | * | IN1L -> LINE1L | |
23 | * | IN1R -> LINE1R | |
24 | * | IN2L -> LINE2L | |
25 | * | IN2R -> LINE2R | |
26 | * | MIC3L/R -> N/A | |
27 | * truncated internal functionality in | |
28 | * accordance with documentation | |
29 | * --------------------------------------- | |
30 | * | |
31 | * Hence the machine layer should disable unsupported inputs/outputs by | |
a5302181 | 32 | * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. |
44d0a879 VB |
33 | */ |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/pm.h> | |
40 | #include <linux/i2c.h> | |
41 | #include <linux/platform_device.h> | |
44d0a879 VB |
42 | #include <sound/core.h> |
43 | #include <sound/pcm.h> | |
44 | #include <sound/pcm_params.h> | |
45 | #include <sound/soc.h> | |
46 | #include <sound/soc-dapm.h> | |
47 | #include <sound/initval.h> | |
7565fc38 | 48 | #include <sound/tlv.h> |
44d0a879 VB |
49 | |
50 | #include "tlv320aic3x.h" | |
51 | ||
4f9c16cc | 52 | #define AIC3X_VERSION "0.2" |
44d0a879 VB |
53 | |
54 | /* codec private data */ | |
55 | struct aic3x_priv { | |
cb3826f5 | 56 | struct snd_soc_codec codec; |
44d0a879 VB |
57 | unsigned int sysclk; |
58 | int master; | |
59 | }; | |
60 | ||
61 | /* | |
62 | * AIC3X register cache | |
63 | * We can't read the AIC3X register space when we are | |
64 | * using 2 wire for device control, so we cache them instead. | |
65 | * There is no point in caching the reset register | |
66 | */ | |
67 | static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { | |
68 | 0x00, 0x00, 0x00, 0x10, /* 0 */ | |
69 | 0x04, 0x00, 0x00, 0x00, /* 4 */ | |
70 | 0x00, 0x00, 0x00, 0x01, /* 8 */ | |
71 | 0x00, 0x00, 0x00, 0x80, /* 12 */ | |
72 | 0x80, 0xff, 0xff, 0x78, /* 16 */ | |
73 | 0x78, 0x78, 0x78, 0x78, /* 20 */ | |
74 | 0x78, 0x00, 0x00, 0xfe, /* 24 */ | |
75 | 0x00, 0x00, 0xfe, 0x00, /* 28 */ | |
76 | 0x18, 0x18, 0x00, 0x00, /* 32 */ | |
77 | 0x00, 0x00, 0x00, 0x00, /* 36 */ | |
78 | 0x00, 0x00, 0x00, 0x80, /* 40 */ | |
79 | 0x80, 0x00, 0x00, 0x00, /* 44 */ | |
80 | 0x00, 0x00, 0x00, 0x04, /* 48 */ | |
81 | 0x00, 0x00, 0x00, 0x00, /* 52 */ | |
82 | 0x00, 0x00, 0x04, 0x00, /* 56 */ | |
83 | 0x00, 0x00, 0x00, 0x00, /* 60 */ | |
84 | 0x00, 0x04, 0x00, 0x00, /* 64 */ | |
85 | 0x00, 0x00, 0x00, 0x00, /* 68 */ | |
86 | 0x04, 0x00, 0x00, 0x00, /* 72 */ | |
87 | 0x00, 0x00, 0x00, 0x00, /* 76 */ | |
88 | 0x00, 0x00, 0x00, 0x00, /* 80 */ | |
89 | 0x00, 0x00, 0x00, 0x00, /* 84 */ | |
90 | 0x00, 0x00, 0x00, 0x00, /* 88 */ | |
91 | 0x00, 0x00, 0x00, 0x00, /* 92 */ | |
92 | 0x00, 0x00, 0x00, 0x00, /* 96 */ | |
93 | 0x00, 0x00, 0x02, /* 100 */ | |
94 | }; | |
95 | ||
96 | /* | |
97 | * read aic3x register cache | |
98 | */ | |
99 | static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec, | |
100 | unsigned int reg) | |
101 | { | |
102 | u8 *cache = codec->reg_cache; | |
103 | if (reg >= AIC3X_CACHEREGNUM) | |
104 | return -1; | |
105 | return cache[reg]; | |
106 | } | |
107 | ||
108 | /* | |
109 | * write aic3x register cache | |
110 | */ | |
111 | static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec, | |
112 | u8 reg, u8 value) | |
113 | { | |
114 | u8 *cache = codec->reg_cache; | |
115 | if (reg >= AIC3X_CACHEREGNUM) | |
116 | return; | |
117 | cache[reg] = value; | |
118 | } | |
119 | ||
120 | /* | |
121 | * write to the aic3x register space | |
122 | */ | |
123 | static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg, | |
124 | unsigned int value) | |
125 | { | |
126 | u8 data[2]; | |
127 | ||
128 | /* data is | |
129 | * D15..D8 aic3x register offset | |
130 | * D7...D0 register data | |
131 | */ | |
132 | data[0] = reg & 0xff; | |
133 | data[1] = value & 0xff; | |
134 | ||
135 | aic3x_write_reg_cache(codec, data[0], data[1]); | |
136 | if (codec->hw_write(codec->control_data, data, 2) == 2) | |
137 | return 0; | |
138 | else | |
139 | return -EIO; | |
140 | } | |
141 | ||
54e7e616 DM |
142 | /* |
143 | * read from the aic3x register space | |
144 | */ | |
145 | static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg, | |
146 | u8 *value) | |
147 | { | |
148 | *value = reg & 0xff; | |
5f345346 MB |
149 | |
150 | value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]); | |
54e7e616 DM |
151 | |
152 | aic3x_write_reg_cache(codec, reg, *value); | |
153 | return 0; | |
154 | } | |
155 | ||
44d0a879 VB |
156 | #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ |
157 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
158 | .info = snd_soc_info_volsw, \ | |
159 | .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ | |
160 | .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } | |
161 | ||
162 | /* | |
163 | * All input lines are connected when !0xf and disconnected with 0xf bit field, | |
164 | * so we have to use specific dapm_put call for input mixer | |
165 | */ | |
166 | static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, | |
167 | struct snd_ctl_elem_value *ucontrol) | |
168 | { | |
169 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); | |
4453dba5 EN |
170 | struct soc_mixer_control *mc = |
171 | (struct soc_mixer_control *)kcontrol->private_value; | |
172 | unsigned int reg = mc->reg; | |
173 | unsigned int shift = mc->shift; | |
174 | int max = mc->max; | |
175 | unsigned int mask = (1 << fls(max)) - 1; | |
176 | unsigned int invert = mc->invert; | |
44d0a879 VB |
177 | unsigned short val, val_mask; |
178 | int ret; | |
179 | struct snd_soc_dapm_path *path; | |
180 | int found = 0; | |
181 | ||
182 | val = (ucontrol->value.integer.value[0] & mask); | |
183 | ||
184 | mask = 0xf; | |
185 | if (val) | |
186 | val = mask; | |
187 | ||
188 | if (invert) | |
189 | val = mask - val; | |
190 | val_mask = mask << shift; | |
191 | val = val << shift; | |
192 | ||
193 | mutex_lock(&widget->codec->mutex); | |
194 | ||
195 | if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { | |
196 | /* find dapm widget path assoc with kcontrol */ | |
197 | list_for_each_entry(path, &widget->codec->dapm_paths, list) { | |
198 | if (path->kcontrol != kcontrol) | |
199 | continue; | |
200 | ||
201 | /* found, now check type */ | |
202 | found = 1; | |
203 | if (val) | |
204 | /* new connection */ | |
205 | path->connect = invert ? 0 : 1; | |
206 | else | |
207 | /* old connection must be powered down */ | |
208 | path->connect = invert ? 1 : 0; | |
209 | break; | |
210 | } | |
211 | ||
212 | if (found) | |
a5302181 | 213 | snd_soc_dapm_sync(widget->codec); |
44d0a879 VB |
214 | } |
215 | ||
216 | ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); | |
217 | ||
218 | mutex_unlock(&widget->codec->mutex); | |
219 | return ret; | |
220 | } | |
221 | ||
222 | static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; | |
223 | static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; | |
224 | static const char *aic3x_left_hpcom_mux[] = | |
225 | { "differential of HPLOUT", "constant VCM", "single-ended" }; | |
226 | static const char *aic3x_right_hpcom_mux[] = | |
227 | { "differential of HPROUT", "constant VCM", "single-ended", | |
228 | "differential of HPLCOM", "external feedback" }; | |
229 | static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; | |
4d20f70a JN |
230 | static const char *aic3x_adc_hpf[] = |
231 | { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; | |
44d0a879 VB |
232 | |
233 | #define LDAC_ENUM 0 | |
234 | #define RDAC_ENUM 1 | |
235 | #define LHPCOM_ENUM 2 | |
236 | #define RHPCOM_ENUM 3 | |
237 | #define LINE1L_ENUM 4 | |
238 | #define LINE1R_ENUM 5 | |
239 | #define LINE2L_ENUM 6 | |
240 | #define LINE2R_ENUM 7 | |
4d20f70a | 241 | #define ADC_HPF_ENUM 8 |
44d0a879 VB |
242 | |
243 | static const struct soc_enum aic3x_enum[] = { | |
244 | SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), | |
245 | SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), | |
246 | SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), | |
247 | SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), | |
248 | SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
249 | SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
250 | SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
251 | SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
4d20f70a | 252 | SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), |
44d0a879 VB |
253 | }; |
254 | ||
7565fc38 JN |
255 | /* |
256 | * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps | |
257 | */ | |
258 | static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); | |
259 | /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ | |
260 | static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); | |
261 | /* | |
262 | * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. | |
263 | * Step size is approximately 0.5 dB over most of the scale but increasing | |
264 | * near the very low levels. | |
265 | * Define dB scale so that it is mostly correct for range about -55 to 0 dB | |
266 | * but having increasing dB difference below that (and where it doesn't count | |
267 | * so much). This setting shows -50 dB (actual is -50.3 dB) for register | |
268 | * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. | |
269 | */ | |
270 | static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); | |
271 | ||
44d0a879 VB |
272 | static const struct snd_kcontrol_new aic3x_snd_controls[] = { |
273 | /* Output */ | |
7565fc38 JN |
274 | SOC_DOUBLE_R_TLV("PCM Playback Volume", |
275 | LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), | |
44d0a879 | 276 | |
7565fc38 JN |
277 | SOC_DOUBLE_R_TLV("Line DAC Playback Volume", |
278 | DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, | |
279 | 0, 118, 1, output_stage_tlv), | |
28a1d869 DM |
280 | SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0), |
281 | SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0), | |
7565fc38 JN |
282 | SOC_DOUBLE_R_TLV("LineL DAC Playback Volume", |
283 | DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL, | |
284 | 0, 118, 1, output_stage_tlv), | |
285 | SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume", | |
286 | PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
287 | SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume", | |
288 | PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
289 | SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume", | |
290 | LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL, | |
291 | 0, 118, 1, output_stage_tlv), | |
292 | SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume", | |
293 | LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL, | |
294 | 0, 118, 1, output_stage_tlv), | |
295 | ||
296 | SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", | |
297 | DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, | |
298 | 0, 118, 1, output_stage_tlv), | |
44d0a879 | 299 | SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), |
7565fc38 JN |
300 | SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume", |
301 | PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, | |
302 | 0, 118, 1, output_stage_tlv), | |
303 | SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume", | |
304 | LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, | |
305 | 0, 118, 1, output_stage_tlv), | |
306 | ||
307 | SOC_DOUBLE_R_TLV("HP DAC Playback Volume", | |
308 | DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, | |
309 | 0, 118, 1, output_stage_tlv), | |
44d0a879 VB |
310 | SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, |
311 | 0x01, 0), | |
7565fc38 JN |
312 | SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume", |
313 | PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, | |
314 | 0, 118, 1, output_stage_tlv), | |
315 | SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume", | |
316 | PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), | |
317 | SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume", | |
318 | PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), | |
319 | SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume", | |
320 | LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, | |
321 | 0, 118, 1, output_stage_tlv), | |
322 | ||
323 | SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", | |
324 | DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, | |
325 | 0, 118, 1, output_stage_tlv), | |
44d0a879 VB |
326 | SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, |
327 | 0x01, 0), | |
7565fc38 JN |
328 | SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume", |
329 | PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), | |
330 | SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume", | |
331 | PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), | |
332 | SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume", | |
333 | LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, | |
334 | 0, 118, 1, output_stage_tlv), | |
44d0a879 VB |
335 | |
336 | /* | |
337 | * Note: enable Automatic input Gain Controller with care. It can | |
338 | * adjust PGA to max value when ADC is on and will never go back. | |
339 | */ | |
340 | SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), | |
341 | ||
342 | /* Input */ | |
7565fc38 JN |
343 | SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, |
344 | 0, 119, 0, adc_tlv), | |
44d0a879 | 345 | SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), |
4d20f70a JN |
346 | |
347 | SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), | |
44d0a879 VB |
348 | }; |
349 | ||
44d0a879 VB |
350 | /* Left DAC Mux */ |
351 | static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = | |
352 | SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); | |
353 | ||
354 | /* Right DAC Mux */ | |
355 | static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = | |
356 | SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); | |
357 | ||
358 | /* Left HPCOM Mux */ | |
359 | static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = | |
360 | SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); | |
361 | ||
362 | /* Right HPCOM Mux */ | |
363 | static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = | |
364 | SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); | |
365 | ||
366 | /* Left DAC_L1 Mixer */ | |
367 | static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = { | |
54f01916 DM |
368 | SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), |
369 | SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 VB |
370 | SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), |
371 | SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), | |
372 | SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), | |
373 | }; | |
374 | ||
375 | /* Right DAC_R1 Mixer */ | |
376 | static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = { | |
54f01916 DM |
377 | SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), |
378 | SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 VB |
379 | SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), |
380 | SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), | |
381 | SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), | |
382 | }; | |
383 | ||
384 | /* Left PGA Mixer */ | |
385 | static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { | |
386 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), | |
54f01916 | 387 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), |
44d0a879 VB |
388 | SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), |
389 | SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), | |
54f01916 | 390 | SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), |
44d0a879 VB |
391 | }; |
392 | ||
393 | /* Right PGA Mixer */ | |
394 | static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { | |
395 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), | |
54f01916 | 396 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), |
44d0a879 | 397 | SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), |
54f01916 | 398 | SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), |
44d0a879 VB |
399 | SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), |
400 | }; | |
401 | ||
402 | /* Left Line1 Mux */ | |
403 | static const struct snd_kcontrol_new aic3x_left_line1_mux_controls = | |
404 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]); | |
405 | ||
406 | /* Right Line1 Mux */ | |
407 | static const struct snd_kcontrol_new aic3x_right_line1_mux_controls = | |
408 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]); | |
409 | ||
410 | /* Left Line2 Mux */ | |
411 | static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = | |
412 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); | |
413 | ||
414 | /* Right Line2 Mux */ | |
415 | static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = | |
416 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); | |
417 | ||
418 | /* Left PGA Bypass Mixer */ | |
419 | static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = { | |
54f01916 DM |
420 | SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), |
421 | SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 | 422 | SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), |
54f01916 DM |
423 | SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), |
424 | SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), | |
425 | SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), | |
426 | SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), | |
44d0a879 VB |
427 | }; |
428 | ||
429 | /* Right PGA Bypass Mixer */ | |
430 | static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = { | |
54f01916 DM |
431 | SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), |
432 | SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 | 433 | SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), |
54f01916 DM |
434 | SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), |
435 | SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), | |
436 | SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), | |
437 | SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), | |
44d0a879 VB |
438 | }; |
439 | ||
440 | /* Left Line2 Bypass Mixer */ | |
441 | static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = { | |
54f01916 DM |
442 | SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), |
443 | SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 VB |
444 | SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), |
445 | SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), | |
54f01916 | 446 | SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), |
44d0a879 VB |
447 | }; |
448 | ||
449 | /* Right Line2 Bypass Mixer */ | |
450 | static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = { | |
54f01916 DM |
451 | SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), |
452 | SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 VB |
453 | SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), |
454 | SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), | |
54f01916 | 455 | SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), |
44d0a879 VB |
456 | }; |
457 | ||
458 | static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { | |
459 | /* Left DAC to Left Outputs */ | |
460 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), | |
461 | SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, | |
462 | &aic3x_left_dac_mux_controls), | |
463 | SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0, | |
464 | &aic3x_left_dac_mixer_controls[0], | |
465 | ARRAY_SIZE(aic3x_left_dac_mixer_controls)), | |
466 | SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, | |
467 | &aic3x_left_hpcom_mux_controls), | |
468 | SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), | |
469 | SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), | |
470 | SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), | |
471 | ||
472 | /* Right DAC to Right Outputs */ | |
473 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), | |
474 | SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, | |
475 | &aic3x_right_dac_mux_controls), | |
476 | SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0, | |
477 | &aic3x_right_dac_mixer_controls[0], | |
478 | ARRAY_SIZE(aic3x_right_dac_mixer_controls)), | |
479 | SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, | |
480 | &aic3x_right_hpcom_mux_controls), | |
481 | SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), | |
482 | SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), | |
483 | SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), | |
484 | ||
485 | /* Mono Output */ | |
486 | SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), | |
487 | ||
54f01916 | 488 | /* Inputs to Left ADC */ |
44d0a879 VB |
489 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), |
490 | SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, | |
491 | &aic3x_left_pga_mixer_controls[0], | |
492 | ARRAY_SIZE(aic3x_left_pga_mixer_controls)), | |
493 | SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, | |
494 | &aic3x_left_line1_mux_controls), | |
54f01916 DM |
495 | SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, |
496 | &aic3x_left_line1_mux_controls), | |
44d0a879 VB |
497 | SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, |
498 | &aic3x_left_line2_mux_controls), | |
499 | ||
54f01916 | 500 | /* Inputs to Right ADC */ |
44d0a879 VB |
501 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", |
502 | LINE1R_2_RADC_CTRL, 2, 0), | |
503 | SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, | |
504 | &aic3x_right_pga_mixer_controls[0], | |
505 | ARRAY_SIZE(aic3x_right_pga_mixer_controls)), | |
54f01916 DM |
506 | SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, |
507 | &aic3x_right_line1_mux_controls), | |
44d0a879 VB |
508 | SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, |
509 | &aic3x_right_line1_mux_controls), | |
510 | SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, | |
511 | &aic3x_right_line2_mux_controls), | |
512 | ||
ee15ffdb JN |
513 | /* |
514 | * Not a real mic bias widget but similar function. This is for dynamic | |
515 | * control of GPIO1 digital mic modulator clock output function when | |
516 | * using digital mic. | |
517 | */ | |
518 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", | |
519 | AIC3X_GPIO1_REG, 4, 0xf, | |
520 | AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, | |
521 | AIC3X_GPIO1_FUNC_DISABLED), | |
522 | ||
523 | /* | |
524 | * Also similar function like mic bias. Selects digital mic with | |
525 | * configurable oversampling rate instead of ADC converter. | |
526 | */ | |
527 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", | |
528 | AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), | |
529 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", | |
530 | AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), | |
531 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", | |
532 | AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), | |
533 | ||
44d0a879 | 534 | /* Mic Bias */ |
0bd72a3d JN |
535 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", |
536 | MICBIAS_CTRL, 6, 3, 1, 0), | |
537 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", | |
538 | MICBIAS_CTRL, 6, 3, 2, 0), | |
539 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", | |
540 | MICBIAS_CTRL, 6, 3, 3, 0), | |
44d0a879 VB |
541 | |
542 | /* Left PGA to Left Output bypass */ | |
543 | SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
544 | &aic3x_left_pga_bp_mixer_controls[0], | |
545 | ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)), | |
546 | ||
547 | /* Right PGA to Right Output bypass */ | |
548 | SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
549 | &aic3x_right_pga_bp_mixer_controls[0], | |
550 | ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)), | |
551 | ||
552 | /* Left Line2 to Left Output bypass */ | |
553 | SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
554 | &aic3x_left_line2_bp_mixer_controls[0], | |
555 | ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)), | |
556 | ||
557 | /* Right Line2 to Right Output bypass */ | |
558 | SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
559 | &aic3x_right_line2_bp_mixer_controls[0], | |
560 | ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)), | |
561 | ||
562 | SND_SOC_DAPM_OUTPUT("LLOUT"), | |
563 | SND_SOC_DAPM_OUTPUT("RLOUT"), | |
564 | SND_SOC_DAPM_OUTPUT("MONO_LOUT"), | |
565 | SND_SOC_DAPM_OUTPUT("HPLOUT"), | |
566 | SND_SOC_DAPM_OUTPUT("HPROUT"), | |
567 | SND_SOC_DAPM_OUTPUT("HPLCOM"), | |
568 | SND_SOC_DAPM_OUTPUT("HPRCOM"), | |
569 | ||
570 | SND_SOC_DAPM_INPUT("MIC3L"), | |
571 | SND_SOC_DAPM_INPUT("MIC3R"), | |
572 | SND_SOC_DAPM_INPUT("LINE1L"), | |
573 | SND_SOC_DAPM_INPUT("LINE1R"), | |
574 | SND_SOC_DAPM_INPUT("LINE2L"), | |
575 | SND_SOC_DAPM_INPUT("LINE2R"), | |
576 | }; | |
577 | ||
d0cc0d3a | 578 | static const struct snd_soc_dapm_route intercon[] = { |
44d0a879 VB |
579 | /* Left Output */ |
580 | {"Left DAC Mux", "DAC_L1", "Left DAC"}, | |
581 | {"Left DAC Mux", "DAC_L2", "Left DAC"}, | |
582 | {"Left DAC Mux", "DAC_L3", "Left DAC"}, | |
583 | ||
54f01916 DM |
584 | {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"}, |
585 | {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"}, | |
44d0a879 VB |
586 | {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"}, |
587 | {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"}, | |
588 | {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"}, | |
589 | {"Left Line Out", NULL, "Left DAC Mux"}, | |
590 | {"Left HP Out", NULL, "Left DAC Mux"}, | |
591 | ||
592 | {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"}, | |
593 | {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"}, | |
594 | {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"}, | |
595 | ||
596 | {"Left Line Out", NULL, "Left DAC_L1 Mixer"}, | |
597 | {"Mono Out", NULL, "Left DAC_L1 Mixer"}, | |
598 | {"Left HP Out", NULL, "Left DAC_L1 Mixer"}, | |
599 | {"Left HP Com", NULL, "Left HPCOM Mux"}, | |
600 | ||
601 | {"LLOUT", NULL, "Left Line Out"}, | |
602 | {"LLOUT", NULL, "Left Line Out"}, | |
603 | {"HPLOUT", NULL, "Left HP Out"}, | |
604 | {"HPLCOM", NULL, "Left HP Com"}, | |
605 | ||
606 | /* Right Output */ | |
607 | {"Right DAC Mux", "DAC_R1", "Right DAC"}, | |
608 | {"Right DAC Mux", "DAC_R2", "Right DAC"}, | |
609 | {"Right DAC Mux", "DAC_R3", "Right DAC"}, | |
610 | ||
54f01916 DM |
611 | {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"}, |
612 | {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"}, | |
44d0a879 VB |
613 | {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"}, |
614 | {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"}, | |
615 | {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"}, | |
616 | {"Right Line Out", NULL, "Right DAC Mux"}, | |
617 | {"Right HP Out", NULL, "Right DAC Mux"}, | |
618 | ||
619 | {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"}, | |
620 | {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"}, | |
621 | {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"}, | |
622 | {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"}, | |
623 | {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"}, | |
624 | ||
625 | {"Right Line Out", NULL, "Right DAC_R1 Mixer"}, | |
626 | {"Mono Out", NULL, "Right DAC_R1 Mixer"}, | |
627 | {"Right HP Out", NULL, "Right DAC_R1 Mixer"}, | |
628 | {"Right HP Com", NULL, "Right HPCOM Mux"}, | |
629 | ||
630 | {"RLOUT", NULL, "Right Line Out"}, | |
631 | {"RLOUT", NULL, "Right Line Out"}, | |
632 | {"HPROUT", NULL, "Right HP Out"}, | |
633 | {"HPRCOM", NULL, "Right HP Com"}, | |
634 | ||
635 | /* Mono Output */ | |
5b006137 JN |
636 | {"MONO_LOUT", NULL, "Mono Out"}, |
637 | {"MONO_LOUT", NULL, "Mono Out"}, | |
44d0a879 VB |
638 | |
639 | /* Left Input */ | |
640 | {"Left Line1L Mux", "single-ended", "LINE1L"}, | |
641 | {"Left Line1L Mux", "differential", "LINE1L"}, | |
642 | ||
643 | {"Left Line2L Mux", "single-ended", "LINE2L"}, | |
644 | {"Left Line2L Mux", "differential", "LINE2L"}, | |
645 | ||
646 | {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, | |
54f01916 | 647 | {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, |
44d0a879 VB |
648 | {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, |
649 | {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, | |
54f01916 | 650 | {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, |
44d0a879 VB |
651 | |
652 | {"Left ADC", NULL, "Left PGA Mixer"}, | |
ee15ffdb | 653 | {"Left ADC", NULL, "GPIO1 dmic modclk"}, |
44d0a879 VB |
654 | |
655 | /* Right Input */ | |
656 | {"Right Line1R Mux", "single-ended", "LINE1R"}, | |
657 | {"Right Line1R Mux", "differential", "LINE1R"}, | |
658 | ||
659 | {"Right Line2R Mux", "single-ended", "LINE2R"}, | |
660 | {"Right Line2R Mux", "differential", "LINE2R"}, | |
661 | ||
54f01916 | 662 | {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, |
44d0a879 VB |
663 | {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, |
664 | {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, | |
54f01916 | 665 | {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, |
44d0a879 VB |
666 | {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, |
667 | ||
668 | {"Right ADC", NULL, "Right PGA Mixer"}, | |
ee15ffdb | 669 | {"Right ADC", NULL, "GPIO1 dmic modclk"}, |
44d0a879 VB |
670 | |
671 | /* Left PGA Bypass */ | |
54f01916 DM |
672 | {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"}, |
673 | {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"}, | |
44d0a879 | 674 | {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"}, |
54f01916 DM |
675 | {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"}, |
676 | {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"}, | |
677 | {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"}, | |
678 | {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"}, | |
44d0a879 VB |
679 | |
680 | {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"}, | |
681 | {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"}, | |
682 | {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"}, | |
683 | ||
684 | {"Left Line Out", NULL, "Left PGA Bypass Mixer"}, | |
685 | {"Mono Out", NULL, "Left PGA Bypass Mixer"}, | |
686 | {"Left HP Out", NULL, "Left PGA Bypass Mixer"}, | |
687 | ||
688 | /* Right PGA Bypass */ | |
54f01916 DM |
689 | {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"}, |
690 | {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"}, | |
44d0a879 | 691 | {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"}, |
54f01916 DM |
692 | {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"}, |
693 | {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"}, | |
694 | {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"}, | |
695 | {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"}, | |
44d0a879 VB |
696 | |
697 | {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"}, | |
698 | {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"}, | |
699 | {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"}, | |
700 | {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"}, | |
701 | {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"}, | |
702 | ||
703 | {"Right Line Out", NULL, "Right PGA Bypass Mixer"}, | |
704 | {"Mono Out", NULL, "Right PGA Bypass Mixer"}, | |
705 | {"Right HP Out", NULL, "Right PGA Bypass Mixer"}, | |
706 | ||
707 | /* Left Line2 Bypass */ | |
54f01916 DM |
708 | {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"}, |
709 | {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"}, | |
44d0a879 VB |
710 | {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"}, |
711 | {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"}, | |
54f01916 | 712 | {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"}, |
44d0a879 VB |
713 | |
714 | {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"}, | |
715 | {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"}, | |
716 | {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"}, | |
717 | ||
718 | {"Left Line Out", NULL, "Left Line2 Bypass Mixer"}, | |
719 | {"Mono Out", NULL, "Left Line2 Bypass Mixer"}, | |
720 | {"Left HP Out", NULL, "Left Line2 Bypass Mixer"}, | |
721 | ||
722 | /* Right Line2 Bypass */ | |
54f01916 DM |
723 | {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"}, |
724 | {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"}, | |
44d0a879 VB |
725 | {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"}, |
726 | {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"}, | |
54f01916 | 727 | {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"}, |
44d0a879 VB |
728 | |
729 | {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"}, | |
730 | {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"}, | |
731 | {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"}, | |
732 | {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"}, | |
733 | {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"}, | |
734 | ||
735 | {"Right Line Out", NULL, "Right Line2 Bypass Mixer"}, | |
736 | {"Mono Out", NULL, "Right Line2 Bypass Mixer"}, | |
737 | {"Right HP Out", NULL, "Right Line2 Bypass Mixer"}, | |
ee15ffdb JN |
738 | |
739 | /* | |
740 | * Logical path between digital mic enable and GPIO1 modulator clock | |
741 | * output function | |
742 | */ | |
743 | {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, | |
744 | {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, | |
745 | {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, | |
44d0a879 VB |
746 | }; |
747 | ||
748 | static int aic3x_add_widgets(struct snd_soc_codec *codec) | |
749 | { | |
d0cc0d3a MB |
750 | snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets, |
751 | ARRAY_SIZE(aic3x_dapm_widgets)); | |
44d0a879 VB |
752 | |
753 | /* set up audio path interconnects */ | |
d0cc0d3a | 754 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); |
44d0a879 | 755 | |
44d0a879 VB |
756 | return 0; |
757 | } | |
758 | ||
44d0a879 | 759 | static int aic3x_hw_params(struct snd_pcm_substream *substream, |
dee89c4d MB |
760 | struct snd_pcm_hw_params *params, |
761 | struct snd_soc_dai *dai) | |
44d0a879 VB |
762 | { |
763 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
764 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 765 | struct snd_soc_codec *codec = socdev->card->codec; |
44d0a879 | 766 | struct aic3x_priv *aic3x = codec->private_data; |
4f9c16cc DM |
767 | int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; |
768 | u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; | |
769 | u16 pll_d = 1; | |
06c71282 | 770 | u8 reg; |
44d0a879 | 771 | |
4f9c16cc DM |
772 | /* select data word length */ |
773 | data = | |
774 | aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); | |
775 | switch (params_format(params)) { | |
776 | case SNDRV_PCM_FORMAT_S16_LE: | |
44d0a879 | 777 | break; |
4f9c16cc DM |
778 | case SNDRV_PCM_FORMAT_S20_3LE: |
779 | data |= (0x01 << 4); | |
44d0a879 | 780 | break; |
4f9c16cc DM |
781 | case SNDRV_PCM_FORMAT_S24_LE: |
782 | data |= (0x02 << 4); | |
44d0a879 | 783 | break; |
4f9c16cc DM |
784 | case SNDRV_PCM_FORMAT_S32_LE: |
785 | data |= (0x03 << 4); | |
44d0a879 VB |
786 | break; |
787 | } | |
4f9c16cc DM |
788 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data); |
789 | ||
790 | /* Fsref can be 44100 or 48000 */ | |
791 | fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; | |
792 | ||
793 | /* Try to find a value for Q which allows us to bypass the PLL and | |
794 | * generate CODEC_CLK directly. */ | |
795 | for (pll_q = 2; pll_q < 18; pll_q++) | |
796 | if (aic3x->sysclk / (128 * pll_q) == fsref) { | |
797 | bypass_pll = 1; | |
798 | break; | |
799 | } | |
800 | ||
801 | if (bypass_pll) { | |
802 | pll_q &= 0xf; | |
803 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); | |
804 | aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); | |
06c71282 C |
805 | /* disable PLL if it is bypassed */ |
806 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
807 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE); | |
808 | ||
809 | } else { | |
4f9c16cc | 810 | aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); |
06c71282 C |
811 | /* enable PLL when it is used */ |
812 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
813 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE); | |
814 | } | |
4f9c16cc DM |
815 | |
816 | /* Route Left DAC to left channel input and | |
817 | * right DAC to right channel input */ | |
818 | data = (LDAC2LCH | RDAC2RCH); | |
819 | data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; | |
820 | if (params_rate(params) >= 64000) | |
821 | data |= DUAL_RATE_MODE; | |
44d0a879 VB |
822 | aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data); |
823 | ||
824 | /* codec sample rate select */ | |
4f9c16cc DM |
825 | data = (fsref * 20) / params_rate(params); |
826 | if (params_rate(params) < 64000) | |
827 | data /= 2; | |
828 | data /= 5; | |
829 | data -= 2; | |
44d0a879 VB |
830 | data |= (data << 4); |
831 | aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); | |
832 | ||
4f9c16cc DM |
833 | if (bypass_pll) |
834 | return 0; | |
835 | ||
836 | /* Use PLL | |
837 | * find an apropriate setup for j, d, r and p by iterating over | |
838 | * p and r - j and d are calculated for each fraction. | |
839 | * Up to 128 values are probed, the closest one wins the game. | |
840 | * The sysclk is divided by 1000 to prevent integer overflows. | |
44d0a879 | 841 | */ |
4f9c16cc DM |
842 | codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); |
843 | ||
844 | for (r = 1; r <= 16; r++) | |
845 | for (p = 1; p <= 8; p++) { | |
846 | int clk, tmp = (codec_clk * pll_r * 10) / pll_p; | |
847 | u8 j = tmp / 10000; | |
848 | u16 d = tmp % 10000; | |
849 | ||
850 | if (j > 63) | |
851 | continue; | |
852 | ||
853 | if (d != 0 && aic3x->sysclk < 10000000) | |
854 | continue; | |
855 | ||
856 | /* This is actually 1000 * ((j + (d/10000)) * r) / p | |
857 | * The term had to be converted to get rid of the | |
858 | * division by 10000 */ | |
859 | clk = ((10000 * j * r) + (d * r)) / (10 * p); | |
860 | ||
861 | /* check whether this values get closer than the best | |
862 | * ones we had before */ | |
863 | if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { | |
864 | pll_j = j; pll_d = d; pll_r = r; pll_p = p; | |
865 | last_clk = clk; | |
866 | } | |
867 | ||
868 | /* Early exit for exact matches */ | |
869 | if (clk == codec_clk) | |
870 | break; | |
871 | } | |
872 | ||
873 | if (last_clk == 0) { | |
874 | printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); | |
875 | return -EINVAL; | |
876 | } | |
44d0a879 VB |
877 | |
878 | data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
879 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT)); | |
880 | aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT); | |
881 | aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); | |
882 | aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT); | |
883 | aic3x_write(codec, AIC3X_PLL_PROGD_REG, | |
884 | (pll_d & 0x3F) << PLLD_LSB_SHIFT); | |
885 | ||
44d0a879 VB |
886 | return 0; |
887 | } | |
888 | ||
e550e17f | 889 | static int aic3x_mute(struct snd_soc_dai *dai, int mute) |
44d0a879 VB |
890 | { |
891 | struct snd_soc_codec *codec = dai->codec; | |
892 | u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON; | |
893 | u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON; | |
894 | ||
895 | if (mute) { | |
896 | aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); | |
897 | aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); | |
898 | } else { | |
899 | aic3x_write(codec, LDAC_VOL, ldac_reg); | |
900 | aic3x_write(codec, RDAC_VOL, rdac_reg); | |
901 | } | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
e550e17f | 906 | static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
44d0a879 VB |
907 | int clk_id, unsigned int freq, int dir) |
908 | { | |
909 | struct snd_soc_codec *codec = codec_dai->codec; | |
910 | struct aic3x_priv *aic3x = codec->private_data; | |
911 | ||
4f9c16cc DM |
912 | aic3x->sysclk = freq; |
913 | return 0; | |
44d0a879 VB |
914 | } |
915 | ||
e550e17f | 916 | static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, |
44d0a879 VB |
917 | unsigned int fmt) |
918 | { | |
919 | struct snd_soc_codec *codec = codec_dai->codec; | |
920 | struct aic3x_priv *aic3x = codec->private_data; | |
81971a14 | 921 | u8 iface_areg, iface_breg; |
a24f4f68 | 922 | int delay = 0; |
81971a14 JN |
923 | |
924 | iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; | |
925 | iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; | |
44d0a879 VB |
926 | |
927 | /* set master/slave audio interface */ | |
928 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
929 | case SND_SOC_DAIFMT_CBM_CFM: | |
930 | aic3x->master = 1; | |
931 | iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; | |
932 | break; | |
933 | case SND_SOC_DAIFMT_CBS_CFS: | |
934 | aic3x->master = 0; | |
935 | break; | |
936 | default: | |
937 | return -EINVAL; | |
938 | } | |
939 | ||
4b7d2831 JN |
940 | /* |
941 | * match both interface format and signal polarities since they | |
942 | * are fixed | |
943 | */ | |
944 | switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | | |
945 | SND_SOC_DAIFMT_INV_MASK)) { | |
946 | case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): | |
44d0a879 | 947 | break; |
a24f4f68 TK |
948 | case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): |
949 | delay = 1; | |
4b7d2831 | 950 | case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): |
44d0a879 VB |
951 | iface_breg |= (0x01 << 6); |
952 | break; | |
4b7d2831 | 953 | case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): |
44d0a879 VB |
954 | iface_breg |= (0x02 << 6); |
955 | break; | |
4b7d2831 | 956 | case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): |
44d0a879 VB |
957 | iface_breg |= (0x03 << 6); |
958 | break; | |
959 | default: | |
960 | return -EINVAL; | |
961 | } | |
962 | ||
963 | /* set iface */ | |
964 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); | |
965 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); | |
a24f4f68 | 966 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay); |
44d0a879 VB |
967 | |
968 | return 0; | |
969 | } | |
970 | ||
0be9898a MB |
971 | static int aic3x_set_bias_level(struct snd_soc_codec *codec, |
972 | enum snd_soc_bias_level level) | |
44d0a879 VB |
973 | { |
974 | struct aic3x_priv *aic3x = codec->private_data; | |
975 | u8 reg; | |
976 | ||
0be9898a MB |
977 | switch (level) { |
978 | case SND_SOC_BIAS_ON: | |
44d0a879 VB |
979 | /* all power is driven by DAPM system */ |
980 | if (aic3x->master) { | |
981 | /* enable pll */ | |
982 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
983 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | |
984 | reg | PLL_ENABLE); | |
985 | } | |
986 | break; | |
0be9898a | 987 | case SND_SOC_BIAS_PREPARE: |
44d0a879 | 988 | break; |
0be9898a | 989 | case SND_SOC_BIAS_STANDBY: |
44d0a879 VB |
990 | /* |
991 | * all power is driven by DAPM system, | |
992 | * so output power is safe if bypass was set | |
993 | */ | |
994 | if (aic3x->master) { | |
995 | /* disable pll */ | |
996 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
997 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | |
998 | reg & ~PLL_ENABLE); | |
999 | } | |
1000 | break; | |
0be9898a | 1001 | case SND_SOC_BIAS_OFF: |
44d0a879 VB |
1002 | /* force all power off */ |
1003 | reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL); | |
1004 | aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON); | |
1005 | reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL); | |
1006 | aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON); | |
1007 | ||
1008 | reg = aic3x_read_reg_cache(codec, DAC_PWR); | |
1009 | aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON)); | |
1010 | ||
1011 | reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); | |
1012 | aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON); | |
1013 | reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); | |
1014 | aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON); | |
1015 | ||
1016 | reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); | |
1017 | aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON); | |
1018 | reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); | |
1019 | aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON); | |
1020 | ||
1021 | reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); | |
1022 | aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON); | |
1023 | ||
1024 | reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); | |
1025 | aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON); | |
1026 | reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); | |
1027 | aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON); | |
1028 | ||
1029 | if (aic3x->master) { | |
1030 | /* disable pll */ | |
1031 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
1032 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | |
1033 | reg & ~PLL_ENABLE); | |
1034 | } | |
1035 | break; | |
1036 | } | |
0be9898a | 1037 | codec->bias_level = level; |
44d0a879 VB |
1038 | |
1039 | return 0; | |
1040 | } | |
1041 | ||
54e7e616 DM |
1042 | void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state) |
1043 | { | |
1044 | u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; | |
1045 | u8 bit = gpio ? 3: 0; | |
1046 | u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit); | |
1047 | aic3x_write(codec, reg, val | (!!state << bit)); | |
1048 | } | |
1049 | EXPORT_SYMBOL_GPL(aic3x_set_gpio); | |
1050 | ||
1051 | int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio) | |
1052 | { | |
1053 | u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; | |
1054 | u8 val, bit = gpio ? 2: 1; | |
1055 | ||
1056 | aic3x_read(codec, reg, &val); | |
1057 | return (val >> bit) & 1; | |
1058 | } | |
1059 | EXPORT_SYMBOL_GPL(aic3x_get_gpio); | |
1060 | ||
6f2a974b DM |
1061 | void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect, |
1062 | int headset_debounce, int button_debounce) | |
1063 | { | |
1064 | u8 val; | |
1065 | ||
1066 | val = ((detect & AIC3X_HEADSET_DETECT_MASK) | |
1067 | << AIC3X_HEADSET_DETECT_SHIFT) | | |
1068 | ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK) | |
1069 | << AIC3X_HEADSET_DEBOUNCE_SHIFT) | | |
1070 | ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK) | |
1071 | << AIC3X_BUTTON_DEBOUNCE_SHIFT); | |
1072 | ||
1073 | if (detect & AIC3X_HEADSET_DETECT_MASK) | |
1074 | val |= AIC3X_HEADSET_DETECT_ENABLED; | |
1075 | ||
1076 | aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val); | |
1077 | } | |
1078 | EXPORT_SYMBOL_GPL(aic3x_set_headset_detection); | |
1079 | ||
54e7e616 DM |
1080 | int aic3x_headset_detected(struct snd_soc_codec *codec) |
1081 | { | |
1082 | u8 val; | |
6f2a974b DM |
1083 | aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); |
1084 | return (val >> 4) & 1; | |
54e7e616 DM |
1085 | } |
1086 | EXPORT_SYMBOL_GPL(aic3x_headset_detected); | |
1087 | ||
6f2a974b DM |
1088 | int aic3x_button_pressed(struct snd_soc_codec *codec) |
1089 | { | |
1090 | u8 val; | |
1091 | aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); | |
1092 | return (val >> 5) & 1; | |
1093 | } | |
1094 | EXPORT_SYMBOL_GPL(aic3x_button_pressed); | |
1095 | ||
44d0a879 VB |
1096 | #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 |
1097 | #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
1098 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1099 | ||
6335d055 EM |
1100 | static struct snd_soc_dai_ops aic3x_dai_ops = { |
1101 | .hw_params = aic3x_hw_params, | |
1102 | .digital_mute = aic3x_mute, | |
1103 | .set_sysclk = aic3x_set_dai_sysclk, | |
1104 | .set_fmt = aic3x_set_dai_fmt, | |
1105 | }; | |
1106 | ||
e550e17f | 1107 | struct snd_soc_dai aic3x_dai = { |
e78cc18d | 1108 | .name = "tlv320aic3x", |
44d0a879 VB |
1109 | .playback = { |
1110 | .stream_name = "Playback", | |
1111 | .channels_min = 1, | |
1112 | .channels_max = 2, | |
1113 | .rates = AIC3X_RATES, | |
1114 | .formats = AIC3X_FORMATS,}, | |
1115 | .capture = { | |
1116 | .stream_name = "Capture", | |
1117 | .channels_min = 1, | |
1118 | .channels_max = 2, | |
1119 | .rates = AIC3X_RATES, | |
1120 | .formats = AIC3X_FORMATS,}, | |
6335d055 | 1121 | .ops = &aic3x_dai_ops, |
44d0a879 VB |
1122 | }; |
1123 | EXPORT_SYMBOL_GPL(aic3x_dai); | |
1124 | ||
1125 | static int aic3x_suspend(struct platform_device *pdev, pm_message_t state) | |
1126 | { | |
1127 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1128 | struct snd_soc_codec *codec = socdev->card->codec; |
44d0a879 | 1129 | |
0be9898a | 1130 | aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); |
44d0a879 VB |
1131 | |
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | static int aic3x_resume(struct platform_device *pdev) | |
1136 | { | |
1137 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1138 | struct snd_soc_codec *codec = socdev->card->codec; |
44d0a879 VB |
1139 | int i; |
1140 | u8 data[2]; | |
1141 | u8 *cache = codec->reg_cache; | |
1142 | ||
1143 | /* Sync reg_cache with the hardware */ | |
1144 | for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) { | |
1145 | data[0] = i; | |
1146 | data[1] = cache[i]; | |
1147 | codec->hw_write(codec->control_data, data, 2); | |
1148 | } | |
1149 | ||
0be9898a | 1150 | aic3x_set_bias_level(codec, codec->suspend_bias_level); |
44d0a879 VB |
1151 | |
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | /* | |
1156 | * initialise the AIC3X driver | |
1157 | * register the mixer and dsp interfaces with the kernel | |
1158 | */ | |
cb3826f5 | 1159 | static int aic3x_init(struct snd_soc_codec *codec) |
44d0a879 | 1160 | { |
cb3826f5 BD |
1161 | int reg; |
1162 | ||
1163 | mutex_init(&codec->mutex); | |
1164 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
1165 | INIT_LIST_HEAD(&codec->dapm_paths); | |
44d0a879 | 1166 | |
e78cc18d | 1167 | codec->name = "tlv320aic3x"; |
44d0a879 VB |
1168 | codec->owner = THIS_MODULE; |
1169 | codec->read = aic3x_read_reg_cache; | |
1170 | codec->write = aic3x_write; | |
0be9898a | 1171 | codec->set_bias_level = aic3x_set_bias_level; |
44d0a879 VB |
1172 | codec->dai = &aic3x_dai; |
1173 | codec->num_dai = 1; | |
ae2ff191 | 1174 | codec->reg_cache_size = ARRAY_SIZE(aic3x_reg); |
44d0a879 VB |
1175 | codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL); |
1176 | if (codec->reg_cache == NULL) | |
1177 | return -ENOMEM; | |
1178 | ||
1179 | aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); | |
1180 | aic3x_write(codec, AIC3X_RESET, SOFT_RESET); | |
1181 | ||
44d0a879 VB |
1182 | /* DAC default volume and mute */ |
1183 | aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); | |
1184 | aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); | |
1185 | ||
1186 | /* DAC to HP default volume and route to Output mixer */ | |
1187 | aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); | |
1188 | aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); | |
1189 | aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1190 | aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1191 | /* DAC to Line Out default volume and route to Output mixer */ | |
1192 | aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1193 | aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1194 | /* DAC to Mono Line Out default volume and route to Output mixer */ | |
1195 | aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1196 | aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1197 | ||
1198 | /* unmute all outputs */ | |
1199 | reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); | |
1200 | aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE); | |
1201 | reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); | |
1202 | aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE); | |
1203 | reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); | |
1204 | aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE); | |
1205 | reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); | |
1206 | aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE); | |
1207 | reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); | |
1208 | aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE); | |
1209 | reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); | |
1210 | aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE); | |
1211 | reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); | |
1212 | aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE); | |
1213 | ||
1214 | /* ADC default volume and unmute */ | |
1215 | aic3x_write(codec, LADC_VOL, DEFAULT_GAIN); | |
1216 | aic3x_write(codec, RADC_VOL, DEFAULT_GAIN); | |
1217 | /* By default route Line1 to ADC PGA mixer */ | |
1218 | aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0); | |
1219 | aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0); | |
1220 | ||
1221 | /* PGA to HP Bypass default volume, disconnect from Output Mixer */ | |
1222 | aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); | |
1223 | aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); | |
1224 | aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); | |
1225 | aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); | |
1226 | /* PGA to Line Out default volume, disconnect from Output Mixer */ | |
1227 | aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); | |
1228 | aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); | |
1229 | /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ | |
1230 | aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1231 | aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1232 | ||
1233 | /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ | |
1234 | aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); | |
1235 | aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); | |
1236 | aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); | |
1237 | aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); | |
1238 | /* Line2 Line Out default volume, disconnect from Output Mixer */ | |
1239 | aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); | |
1240 | aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); | |
1241 | /* Line2 to Mono Out default volume, disconnect from Output Mixer */ | |
1242 | aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1243 | aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1244 | ||
1245 | /* off, with power on */ | |
0be9898a | 1246 | aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
44d0a879 | 1247 | |
cb3826f5 BD |
1248 | return 0; |
1249 | } | |
54e7e616 | 1250 | |
cb3826f5 BD |
1251 | static struct snd_soc_codec *aic3x_codec; |
1252 | ||
1253 | static int aic3x_register(struct snd_soc_codec *codec) | |
1254 | { | |
1255 | int ret; | |
1256 | ||
1257 | ret = aic3x_init(codec); | |
44d0a879 | 1258 | if (ret < 0) { |
cb3826f5 BD |
1259 | dev_err(codec->dev, "Failed to initialise device\n"); |
1260 | return ret; | |
44d0a879 VB |
1261 | } |
1262 | ||
cb3826f5 | 1263 | aic3x_codec = codec; |
44d0a879 | 1264 | |
cb3826f5 BD |
1265 | ret = snd_soc_register_codec(codec); |
1266 | if (ret) { | |
1267 | dev_err(codec->dev, "Failed to register codec\n"); | |
1268 | return ret; | |
1269 | } | |
1270 | ||
1271 | ret = snd_soc_register_dai(&aic3x_dai); | |
1272 | if (ret) { | |
1273 | dev_err(codec->dev, "Failed to register dai\n"); | |
1274 | snd_soc_unregister_codec(codec); | |
1275 | return ret; | |
1276 | } | |
1277 | ||
1278 | return 0; | |
44d0a879 VB |
1279 | } |
1280 | ||
cb3826f5 BD |
1281 | static int aic3x_unregister(struct aic3x_priv *aic3x) |
1282 | { | |
1283 | aic3x_set_bias_level(&aic3x->codec, SND_SOC_BIAS_OFF); | |
1284 | ||
1285 | snd_soc_unregister_dai(&aic3x_dai); | |
1286 | snd_soc_unregister_codec(&aic3x->codec); | |
1287 | ||
1288 | kfree(aic3x); | |
1289 | aic3x_codec = NULL; | |
1290 | ||
1291 | return 0; | |
1292 | } | |
44d0a879 VB |
1293 | |
1294 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1295 | /* | |
1296 | * AIC3X 2 wire address can be up to 4 devices with device addresses | |
1297 | * 0x18, 0x19, 0x1A, 0x1B | |
1298 | */ | |
44d0a879 VB |
1299 | |
1300 | /* | |
1301 | * If the i2c layer weren't so broken, we could pass this kind of data | |
1302 | * around | |
1303 | */ | |
ba8ed121 JD |
1304 | static int aic3x_i2c_probe(struct i2c_client *i2c, |
1305 | const struct i2c_device_id *id) | |
44d0a879 | 1306 | { |
cb3826f5 BD |
1307 | struct snd_soc_codec *codec; |
1308 | struct aic3x_priv *aic3x; | |
44d0a879 | 1309 | |
cb3826f5 BD |
1310 | aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL); |
1311 | if (aic3x == NULL) { | |
1312 | dev_err(&i2c->dev, "failed to create private data\n"); | |
1313 | return -ENOMEM; | |
1314 | } | |
1315 | ||
1316 | codec = &aic3x->codec; | |
1317 | codec->dev = &i2c->dev; | |
1318 | codec->private_data = aic3x; | |
44d0a879 | 1319 | codec->control_data = i2c; |
cb3826f5 | 1320 | codec->hw_write = (hw_write_t) i2c_master_send; |
44d0a879 | 1321 | |
cb3826f5 BD |
1322 | i2c_set_clientdata(i2c, aic3x); |
1323 | ||
1324 | return aic3x_register(codec); | |
44d0a879 VB |
1325 | } |
1326 | ||
ba8ed121 | 1327 | static int aic3x_i2c_remove(struct i2c_client *client) |
44d0a879 | 1328 | { |
cb3826f5 BD |
1329 | struct aic3x_priv *aic3x = i2c_get_clientdata(client); |
1330 | ||
1331 | return aic3x_unregister(aic3x); | |
44d0a879 VB |
1332 | } |
1333 | ||
ba8ed121 JD |
1334 | static const struct i2c_device_id aic3x_i2c_id[] = { |
1335 | { "tlv320aic3x", 0 }, | |
cb3826f5 | 1336 | { "tlv320aic33", 0 }, |
ba8ed121 JD |
1337 | { } |
1338 | }; | |
1339 | MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); | |
44d0a879 VB |
1340 | |
1341 | /* machine i2c codec control layer */ | |
1342 | static struct i2c_driver aic3x_i2c_driver = { | |
1343 | .driver = { | |
1344 | .name = "aic3x I2C Codec", | |
1345 | .owner = THIS_MODULE, | |
1346 | }, | |
cb3826f5 | 1347 | .probe = aic3x_i2c_probe, |
ba8ed121 JD |
1348 | .remove = aic3x_i2c_remove, |
1349 | .id_table = aic3x_i2c_id, | |
44d0a879 | 1350 | }; |
54e7e616 | 1351 | |
cb3826f5 | 1352 | static inline void aic3x_i2c_init(void) |
ba8ed121 | 1353 | { |
ba8ed121 JD |
1354 | int ret; |
1355 | ||
1356 | ret = i2c_add_driver(&aic3x_i2c_driver); | |
cb3826f5 BD |
1357 | if (ret) |
1358 | printk(KERN_ERR "%s: error regsitering i2c driver, %d\n", | |
1359 | __func__, ret); | |
1360 | } | |
ba8ed121 | 1361 | |
cb3826f5 BD |
1362 | static inline void aic3x_i2c_exit(void) |
1363 | { | |
ba8ed121 | 1364 | i2c_del_driver(&aic3x_i2c_driver); |
ba8ed121 | 1365 | } |
cb3826f5 BD |
1366 | #else |
1367 | static inline void aic3x_i2c_init(void) { } | |
1368 | static inline void aic3x_i2c_exit(void) { } | |
44d0a879 VB |
1369 | #endif |
1370 | ||
1371 | static int aic3x_probe(struct platform_device *pdev) | |
1372 | { | |
1373 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1374 | struct aic3x_setup_data *setup; | |
1375 | struct snd_soc_codec *codec; | |
44d0a879 VB |
1376 | int ret = 0; |
1377 | ||
cb3826f5 BD |
1378 | codec = aic3x_codec; |
1379 | if (!codec) { | |
1380 | dev_err(&pdev->dev, "Codec not registered\n"); | |
1381 | return -ENODEV; | |
1382 | } | |
44d0a879 | 1383 | |
cb3826f5 | 1384 | socdev->card->codec = codec; |
44d0a879 | 1385 | setup = socdev->codec_data; |
44d0a879 | 1386 | |
977d49e0 MB |
1387 | if (setup) { |
1388 | /* setup GPIO functions */ | |
1389 | aic3x_write(codec, AIC3X_GPIO1_REG, | |
1390 | (setup->gpio_func[0] & 0xf) << 4); | |
1391 | aic3x_write(codec, AIC3X_GPIO2_REG, | |
1392 | (setup->gpio_func[1] & 0xf) << 4); | |
44d0a879 VB |
1393 | } |
1394 | ||
cb3826f5 BD |
1395 | /* register pcms */ |
1396 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
1397 | if (ret < 0) { | |
1398 | printk(KERN_ERR "aic3x: failed to create pcms\n"); | |
1399 | goto pcm_err; | |
44d0a879 | 1400 | } |
3051e41a | 1401 | |
cb3826f5 BD |
1402 | snd_soc_add_controls(codec, aic3x_snd_controls, |
1403 | ARRAY_SIZE(aic3x_snd_controls)); | |
1404 | ||
1405 | aic3x_add_widgets(codec); | |
1406 | ||
cb3826f5 BD |
1407 | return ret; |
1408 | ||
cb3826f5 BD |
1409 | pcm_err: |
1410 | kfree(codec->reg_cache); | |
44d0a879 VB |
1411 | return ret; |
1412 | } | |
1413 | ||
1414 | static int aic3x_remove(struct platform_device *pdev) | |
1415 | { | |
1416 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1417 | struct snd_soc_codec *codec = socdev->card->codec; |
44d0a879 VB |
1418 | |
1419 | /* power down chip */ | |
1420 | if (codec->control_data) | |
0be9898a | 1421 | aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); |
44d0a879 VB |
1422 | |
1423 | snd_soc_free_pcms(socdev); | |
1424 | snd_soc_dapm_free(socdev); | |
cb3826f5 BD |
1425 | |
1426 | kfree(codec->reg_cache); | |
44d0a879 VB |
1427 | |
1428 | return 0; | |
1429 | } | |
1430 | ||
1431 | struct snd_soc_codec_device soc_codec_dev_aic3x = { | |
1432 | .probe = aic3x_probe, | |
1433 | .remove = aic3x_remove, | |
1434 | .suspend = aic3x_suspend, | |
1435 | .resume = aic3x_resume, | |
1436 | }; | |
1437 | EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x); | |
1438 | ||
c9b3a40f | 1439 | static int __init aic3x_modinit(void) |
64089b84 | 1440 | { |
cb3826f5 BD |
1441 | aic3x_i2c_init(); |
1442 | ||
1443 | return 0; | |
64089b84 MB |
1444 | } |
1445 | module_init(aic3x_modinit); | |
1446 | ||
1447 | static void __exit aic3x_exit(void) | |
1448 | { | |
cb3826f5 | 1449 | aic3x_i2c_exit(); |
64089b84 MB |
1450 | } |
1451 | module_exit(aic3x_exit); | |
1452 | ||
44d0a879 VB |
1453 | MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); |
1454 | MODULE_AUTHOR("Vladimir Barinov"); | |
1455 | MODULE_LICENSE("GPL"); |