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ASoC: Samsung: Rename from s3c24xx to samsung
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
44d0a879 43#include <linux/platform_device.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
44d0a879 49#include <sound/initval.h>
7565fc38 50#include <sound/tlv.h>
5193d62f 51#include <sound/tlv320aic3x.h>
44d0a879
VB		 52
53#include "tlv320aic3x.h"
54
07779fdd
JN		 55#define AIC3X_NUM_SUPPLIES 4
56static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD", /* I/O Voltage */
58 "DVDD", /* Digital Core Voltage */
59 "AVDD", /* Analog DAC Voltage */
60 "DRVDD", /* ADC Analog and Output Driver Voltage */
61};
44d0a879 62
5a895f8a
JN		 63struct aic3x_priv;
64
65struct aic3x_disable_nb {
66 struct notifier_block nb;
67 struct aic3x_priv *aic3x;
68};
69
44d0a879
VB		 70/* codec private data */
71struct aic3x_priv {
5a895f8a 72 struct snd_soc_codec *codec;
07779fdd 73 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 74 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 75 enum snd_soc_control_type control_type;
76 struct aic3x_setup_data *setup;
77 void *control_data;
44d0a879
VB		 78 unsigned int sysclk;
79 int master;
5193d62f 80 int gpio_reset;
6c1a7d40 81 int power;
6184f105
RC		 82#define AIC3X_MODEL_3X 0
83#define AIC3X_MODEL_33 1
84#define AIC3X_MODEL_3007 2
85 u16 model;
44d0a879
VB		 86};
87
88/*
89 * AIC3X register cache
90 * We can't read the AIC3X register space when we are
91 * using 2 wire for device control, so we cache them instead.
92 * There is no point in caching the reset register
93 */
94static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
95 0x00, 0x00, 0x00, 0x10, /* 0 */
96 0x04, 0x00, 0x00, 0x00, /* 4 */
97 0x00, 0x00, 0x00, 0x01, /* 8 */
98 0x00, 0x00, 0x00, 0x80, /* 12 */
99 0x80, 0xff, 0xff, 0x78, /* 16 */
100 0x78, 0x78, 0x78, 0x78, /* 20 */
101 0x78, 0x00, 0x00, 0xfe, /* 24 */
102 0x00, 0x00, 0xfe, 0x00, /* 28 */
103 0x18, 0x18, 0x00, 0x00, /* 32 */
104 0x00, 0x00, 0x00, 0x00, /* 36 */
105 0x00, 0x00, 0x00, 0x80, /* 40 */
106 0x80, 0x00, 0x00, 0x00, /* 44 */
107 0x00, 0x00, 0x00, 0x04, /* 48 */
108 0x00, 0x00, 0x00, 0x00, /* 52 */
109 0x00, 0x00, 0x04, 0x00, /* 56 */
110 0x00, 0x00, 0x00, 0x00, /* 60 */
111 0x00, 0x04, 0x00, 0x00, /* 64 */
112 0x00, 0x00, 0x00, 0x00, /* 68 */
113 0x04, 0x00, 0x00, 0x00, /* 72 */
114 0x00, 0x00, 0x00, 0x00, /* 76 */
115 0x00, 0x00, 0x00, 0x00, /* 80 */
116 0x00, 0x00, 0x00, 0x00, /* 84 */
117 0x00, 0x00, 0x00, 0x00, /* 88 */
118 0x00, 0x00, 0x00, 0x00, /* 92 */
119 0x00, 0x00, 0x00, 0x00, /* 96 */
120 0x00, 0x00, 0x02, /* 100 */
121};
122
123/*
9900daa8
JN		 124 * read from the aic3x register space. Only use for this function is if
125 * wanting to read volatile bits from those registers that has both read-only
126 * and read/write bits. All other cases should use snd_soc_read.
44d0a879 127 */
54e7e616
DM		 128static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
129 u8 *value)
44d0a879
VB		 130{
131 u8 *cache = codec->reg_cache;
44d0a879 132
5a895f8a
JN		 133 if (codec->cache_only)
134 return -EINVAL;
44d0a879 135 if (reg >= AIC3X_CACHEREGNUM)
9900daa8 136 return -1;
5f345346 137
9900daa8
JN		 138 *value = codec->hw_read(codec, reg);
139 cache[reg] = *value;
54e7e616 140
54e7e616
DM		 141 return 0;
142}
143
44d0a879
VB		 144#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
145{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
146 .info = snd_soc_info_volsw, \
147 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
148 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
149
150/*
151 * All input lines are connected when !0xf and disconnected with 0xf bit field,
152 * so we have to use specific dapm_put call for input mixer
153 */
154static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
155 struct snd_ctl_elem_value *ucontrol)
156{
157 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
4453dba5
EN		 158 struct soc_mixer_control *mc =
159 (struct soc_mixer_control *)kcontrol->private_value;
160 unsigned int reg = mc->reg;
161 unsigned int shift = mc->shift;
162 int max = mc->max;
163 unsigned int mask = (1 << fls(max)) - 1;
164 unsigned int invert = mc->invert;
44d0a879
VB		 165 unsigned short val, val_mask;
166 int ret;
167 struct snd_soc_dapm_path *path;
168 int found = 0;
169
170 val = (ucontrol->value.integer.value[0] & mask);
171
172 mask = 0xf;
173 if (val)
174 val = mask;
175
176 if (invert)
177 val = mask - val;
178 val_mask = mask << shift;
179 val = val << shift;
180
181 mutex_lock(&widget->codec->mutex);
182
183 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
184 /* find dapm widget path assoc with kcontrol */
ce6120cc 185 list_for_each_entry(path, &widget->dapm->paths, list) {
44d0a879
VB		 186 if (path->kcontrol != kcontrol)
187 continue;
188
189 /* found, now check type */
190 found = 1;
191 if (val)
192 /* new connection */
193 path->connect = invert ? 0 : 1;
194 else
195 /* old connection must be powered down */
196 path->connect = invert ? 1 : 0;
197 break;
198 }
199
200 if (found)
ce6120cc 201 snd_soc_dapm_sync(widget->dapm);
44d0a879
VB		 202 }
203
204 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
205
206 mutex_unlock(&widget->codec->mutex);
207 return ret;
208}
209
210static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
211static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
212static const char *aic3x_left_hpcom_mux[] =
213 { "differential of HPLOUT", "constant VCM", "single-ended" };
214static const char *aic3x_right_hpcom_mux[] =
215 { "differential of HPROUT", "constant VCM", "single-ended",
216 "differential of HPLCOM", "external feedback" };
217static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 218static const char *aic3x_adc_hpf[] =
219 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 220
221#define LDAC_ENUM 0
222#define RDAC_ENUM 1
223#define LHPCOM_ENUM 2
224#define RHPCOM_ENUM 3
225#define LINE1L_ENUM 4
226#define LINE1R_ENUM 5
227#define LINE2L_ENUM 6
228#define LINE2R_ENUM 7
4d20f70a 229#define ADC_HPF_ENUM 8
44d0a879
VB		 230
231static const struct soc_enum aic3x_enum[] = {
232 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
233 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
234 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
235 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
236 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
237 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
238 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
239 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 240 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 241};
242
7565fc38
JN		 243/*
244 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
245 */
246static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
247/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
248static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
249/*
250 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
251 * Step size is approximately 0.5 dB over most of the scale but increasing
252 * near the very low levels.
253 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
254 * but having increasing dB difference below that (and where it doesn't count
255 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
256 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
257 */
258static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
259
44d0a879
VB		 260static const struct snd_kcontrol_new aic3x_snd_controls[] = {
261 /* Output */
7565fc38
JN		 262 SOC_DOUBLE_R_TLV("PCM Playback Volume",
263 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 264
098b1718
JN		 265 /*
266 * Output controls that map to output mixer switches. Note these are
267 * only for swapped L-to-R and R-to-L routes. See below stereo controls
268 * for direct L-to-L and R-to-R routes.
269 */
270 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
271 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
272 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
273 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
274 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
275 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
276
277 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
278 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
279 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
280 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
281 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
282 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
283
284 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
285 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
286 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
287 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
288 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
289 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
290
291 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
292 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
293 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
294 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
295 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
296 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
297
298 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
299 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
300 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
301 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
302 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
303 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
304
305 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
306 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
307 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
308 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
309 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
310 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
311
312 /* Stereo output controls for direct L-to-L and R-to-R routes */
313 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
314 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
315 0, 118, 1, output_stage_tlv),
316 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
317 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
318 0, 118, 1, output_stage_tlv),
7565fc38
JN		 319 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
320 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
321 0, 118, 1, output_stage_tlv),
098b1718
JN		 322
323 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
324 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 325 0, 118, 1, output_stage_tlv),
098b1718
JN		 326 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
327 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 328 0, 118, 1, output_stage_tlv),
7565fc38
JN		 329 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
330 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
331 0, 118, 1, output_stage_tlv),
098b1718
JN		 332
333 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
334 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 335 0, 118, 1, output_stage_tlv),
098b1718
JN		 336 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
337 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 338 0, 118, 1, output_stage_tlv),
7565fc38
JN		 339 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
340 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
341 0, 118, 1, output_stage_tlv),
098b1718
JN		 342
343 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
344 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 345 0, 118, 1, output_stage_tlv),
098b1718
JN		 346 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
347 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 348 0, 118, 1, output_stage_tlv),
7565fc38
JN		 349 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
350 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
351 0, 118, 1, output_stage_tlv),
098b1718
JN		 352
353 /* Output pin mute controls */
354 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
355 0x01, 0),
356 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
357 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
358 0x01, 0),
f9bc0297 359 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 360 0x01, 0),
44d0a879
VB		 361
362 /*
363 * Note: enable Automatic input Gain Controller with care. It can
364 * adjust PGA to max value when ADC is on and will never go back.
365 */
366 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
367
368 /* Input */
7565fc38
JN		 369 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
370 0, 119, 0, adc_tlv),
44d0a879 371 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 372
373 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 374};
375
6184f105
RC		 376/*
377 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
378 */
379static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
380
381static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
382 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
383
44d0a879
VB		 384/* Left DAC Mux */
385static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
386SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
387
388/* Right DAC Mux */
389static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
390SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
391
392/* Left HPCOM Mux */
393static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
394SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
395
396/* Right HPCOM Mux */
397static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
398SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
399
c3b79e05
JN		 400/* Left Line Mixer */
401static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
402 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
403 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 408};
409
c3b79e05
JN		 410/* Right Line Mixer */
411static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
412 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
413 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
414 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
418};
419
420/* Mono Mixer */
421static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
422 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
423 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
428};
429
430/* Left HP Mixer */
431static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
432 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
438};
439
440/* Right HP Mixer */
441static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
442 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
448};
449
450/* Left HPCOM Mixer */
451static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
452 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
458};
459
460/* Right HPCOM Mixer */
461static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
462 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
463 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
464 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 468};
469
470/* Left PGA Mixer */
471static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
472 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 473 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 474 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
475 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 476 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 477};
478
479/* Right PGA Mixer */
480static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
481 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 482 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 483 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 484 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 485 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
486};
487
488/* Left Line1 Mux */
489static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
490SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
491
492/* Right Line1 Mux */
493static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
494SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
495
496/* Left Line2 Mux */
497static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
498SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
499
500/* Right Line2 Mux */
501static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
502SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
503
44d0a879
VB		 504static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
505 /* Left DAC to Left Outputs */
506 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
507 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
508 &aic3x_left_dac_mux_controls),
44d0a879
VB		 509 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
510 &aic3x_left_hpcom_mux_controls),
511 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
512 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
513 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
514
515 /* Right DAC to Right Outputs */
516 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
517 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
518 &aic3x_right_dac_mux_controls),
44d0a879
VB		 519 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
520 &aic3x_right_hpcom_mux_controls),
521 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
522 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
523 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
524
525 /* Mono Output */
526 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
527
54f01916 528 /* Inputs to Left ADC */
44d0a879
VB		 529 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
530 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
531 &aic3x_left_pga_mixer_controls[0],
532 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
533 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
534 &aic3x_left_line1_mux_controls),
54f01916
DM		 535 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
536 &aic3x_left_line1_mux_controls),
44d0a879
VB		 537 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
538 &aic3x_left_line2_mux_controls),
539
54f01916 540 /* Inputs to Right ADC */
44d0a879
VB		 541 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
542 LINE1R_2_RADC_CTRL, 2, 0),
543 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
544 &aic3x_right_pga_mixer_controls[0],
545 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 546 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
547 &aic3x_right_line1_mux_controls),
44d0a879
VB		 548 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
549 &aic3x_right_line1_mux_controls),
550 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
551 &aic3x_right_line2_mux_controls),
552
ee15ffdb
JN		 553 /*
554 * Not a real mic bias widget but similar function. This is for dynamic
555 * control of GPIO1 digital mic modulator clock output function when
556 * using digital mic.
557 */
558 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
559 AIC3X_GPIO1_REG, 4, 0xf,
560 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
561 AIC3X_GPIO1_FUNC_DISABLED),
562
563 /*
564 * Also similar function like mic bias. Selects digital mic with
565 * configurable oversampling rate instead of ADC converter.
566 */
567 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
568 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
569 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
570 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
571 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
572 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
573
44d0a879 574 /* Mic Bias */
0bd72a3d
JN		 575 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
576 MICBIAS_CTRL, 6, 3, 1, 0),
577 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
578 MICBIAS_CTRL, 6, 3, 2, 0),
579 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
580 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 581
c3b79e05
JN		 582 /* Output mixers */
583 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
584 &aic3x_left_line_mixer_controls[0],
585 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
586 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
587 &aic3x_right_line_mixer_controls[0],
588 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
589 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
590 &aic3x_mono_mixer_controls[0],
591 ARRAY_SIZE(aic3x_mono_mixer_controls)),
592 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
593 &aic3x_left_hp_mixer_controls[0],
594 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
595 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
596 &aic3x_right_hp_mixer_controls[0],
597 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
598 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
599 &aic3x_left_hpcom_mixer_controls[0],
600 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
601 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
602 &aic3x_right_hpcom_mixer_controls[0],
603 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 604
605 SND_SOC_DAPM_OUTPUT("LLOUT"),
606 SND_SOC_DAPM_OUTPUT("RLOUT"),
607 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
608 SND_SOC_DAPM_OUTPUT("HPLOUT"),
609 SND_SOC_DAPM_OUTPUT("HPROUT"),
610 SND_SOC_DAPM_OUTPUT("HPLCOM"),
611 SND_SOC_DAPM_OUTPUT("HPRCOM"),
612
613 SND_SOC_DAPM_INPUT("MIC3L"),
614 SND_SOC_DAPM_INPUT("MIC3R"),
615 SND_SOC_DAPM_INPUT("LINE1L"),
616 SND_SOC_DAPM_INPUT("LINE1R"),
617 SND_SOC_DAPM_INPUT("LINE2L"),
618 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 619
620 /*
621 * Virtual output pin to detection block inside codec. This can be
622 * used to keep codec bias on if gpio or detection features are needed.
623 * Force pin on or construct a path with an input jack and mic bias
624 * widgets.
625 */
626 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 627};
628
6184f105
RC		 629static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
630 /* Class-D outputs */
631 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
632 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
633
634 SND_SOC_DAPM_OUTPUT("SPOP"),
635 SND_SOC_DAPM_OUTPUT("SPOM"),
636};
637
d0cc0d3a 638static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 639 /* Left Input */
640 {"Left Line1L Mux", "single-ended", "LINE1L"},
641 {"Left Line1L Mux", "differential", "LINE1L"},
642
643 {"Left Line2L Mux", "single-ended", "LINE2L"},
644 {"Left Line2L Mux", "differential", "LINE2L"},
645
646 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 647 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 648 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
649 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 650 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 651
652 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 653 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 654
655 /* Right Input */
656 {"Right Line1R Mux", "single-ended", "LINE1R"},
657 {"Right Line1R Mux", "differential", "LINE1R"},
658
659 {"Right Line2R Mux", "single-ended", "LINE2R"},
660 {"Right Line2R Mux", "differential", "LINE2R"},
661
54f01916 662 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 663 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
664 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 665 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 666 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
667
668 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 669 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 670
ee15ffdb
JN		 671 /*
672 * Logical path between digital mic enable and GPIO1 modulator clock
673 * output function
674 */
675 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
676 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
677 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 678
679 /* Left DAC Output */
680 {"Left DAC Mux", "DAC_L1", "Left DAC"},
681 {"Left DAC Mux", "DAC_L2", "Left DAC"},
682 {"Left DAC Mux", "DAC_L3", "Left DAC"},
683
684 /* Right DAC Output */
685 {"Right DAC Mux", "DAC_R1", "Right DAC"},
686 {"Right DAC Mux", "DAC_R2", "Right DAC"},
687 {"Right DAC Mux", "DAC_R3", "Right DAC"},
688
689 /* Left Line Output */
690 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
691 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
692 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
693 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
694 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
695 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
696
697 {"Left Line Out", NULL, "Left Line Mixer"},
698 {"Left Line Out", NULL, "Left DAC Mux"},
699 {"LLOUT", NULL, "Left Line Out"},
700
701 /* Right Line Output */
702 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
703 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
704 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
705 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
706 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
707 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
708
709 {"Right Line Out", NULL, "Right Line Mixer"},
710 {"Right Line Out", NULL, "Right DAC Mux"},
711 {"RLOUT", NULL, "Right Line Out"},
712
713 /* Mono Output */
714 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
715 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
716 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
717 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
718 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
719 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
720
721 {"Mono Out", NULL, "Mono Mixer"},
722 {"MONO_LOUT", NULL, "Mono Out"},
723
724 /* Left HP Output */
725 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
726 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
727 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
728 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
729 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
730 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
731
732 {"Left HP Out", NULL, "Left HP Mixer"},
733 {"Left HP Out", NULL, "Left DAC Mux"},
734 {"HPLOUT", NULL, "Left HP Out"},
735
736 /* Right HP Output */
737 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
738 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
739 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
740 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
741 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
742 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
743
744 {"Right HP Out", NULL, "Right HP Mixer"},
745 {"Right HP Out", NULL, "Right DAC Mux"},
746 {"HPROUT", NULL, "Right HP Out"},
747
748 /* Left HPCOM Output */
749 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
750 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
751 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
752 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
753 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
754 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
755
756 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
757 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
758 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
759 {"Left HP Com", NULL, "Left HPCOM Mux"},
760 {"HPLCOM", NULL, "Left HP Com"},
761
762 /* Right HPCOM Output */
763 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
764 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
765 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
766 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
767 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
768 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
769
770 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
771 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
772 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
773 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
774 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
775 {"Right HP Com", NULL, "Right HPCOM Mux"},
776 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 777};
778
6184f105
RC		 779static const struct snd_soc_dapm_route intercon_3007[] = {
780 /* Class-D outputs */
781 {"Left Class-D Out", NULL, "Left Line Out"},
782 {"Right Class-D Out", NULL, "Left Line Out"},
783 {"SPOP", NULL, "Left Class-D Out"},
784 {"SPOM", NULL, "Right Class-D Out"},
785};
786
44d0a879
VB		 787static int aic3x_add_widgets(struct snd_soc_codec *codec)
788{
6184f105 789 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 790 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 791
ce6120cc 792 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
d0cc0d3a 793 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 794
795 /* set up audio path interconnects */
ce6120cc 796 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
44d0a879 797
6184f105 798 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 799 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 800 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 801 snd_soc_dapm_add_routes(dapm, intercon_3007,
802 ARRAY_SIZE(intercon_3007));
6184f105
RC		 803 }
804
44d0a879
VB		 805 return 0;
806}
807
44d0a879 808static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 809 struct snd_pcm_hw_params *params,
810 struct snd_soc_dai *dai)
44d0a879
VB		 811{
812 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 813 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 814 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 815 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 816 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
817 u16 d, pll_d = 1;
06c71282 818 u8 reg;
255173b4 819 int clk;
44d0a879 820
4f9c16cc 821 /* select data word length */
e18eca43 822 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 823 switch (params_format(params)) {
824 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 825 break;
4f9c16cc
DM		 826 case SNDRV_PCM_FORMAT_S20_3LE:
827 data |= (0x01 << 4);
44d0a879 828 break;
4f9c16cc
DM		 829 case SNDRV_PCM_FORMAT_S24_LE:
830 data |= (0x02 << 4);
44d0a879 831 break;
4f9c16cc
DM		 832 case SNDRV_PCM_FORMAT_S32_LE:
833 data |= (0x03 << 4);
44d0a879
VB		 834 break;
835 }
e18eca43 836 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 837
838 /* Fsref can be 44100 or 48000 */
839 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
840
841 /* Try to find a value for Q which allows us to bypass the PLL and
842 * generate CODEC_CLK directly. */
843 for (pll_q = 2; pll_q < 18; pll_q++)
844 if (aic3x->sysclk / (128 * pll_q) == fsref) {
845 bypass_pll = 1;
846 break;
847 }
848
849 if (bypass_pll) {
850 pll_q &= 0xf;
e18eca43
JN		 851 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
852 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 853 /* disable PLL if it is bypassed */
e18eca43
JN		 854 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
855 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
06c71282
C		 856
857 } else {
e18eca43 858 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 859 /* enable PLL when it is used */
e18eca43
JN		 860 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
861 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
06c71282 862 }
4f9c16cc
DM		 863
864 /* Route Left DAC to left channel input and
865 * right DAC to right channel input */
866 data = (LDAC2LCH | RDAC2RCH);
867 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
868 if (params_rate(params) >= 64000)
869 data |= DUAL_RATE_MODE;
e18eca43 870 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 871
872 /* codec sample rate select */
4f9c16cc
DM		 873 data = (fsref * 20) / params_rate(params);
874 if (params_rate(params) < 64000)
875 data /= 2;
876 data /= 5;
877 data -= 2;
44d0a879 878 data |= (data << 4);
e18eca43 879 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 880
4f9c16cc
DM		 881 if (bypass_pll)
882 return 0;
883
255173b4
PM		 884 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
885 * one wins the game. Try with d==0 first, next with d!=0.
886 * Constraints for j are according to the datasheet.
4f9c16cc 887 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 888 */
255173b4 889
4f9c16cc
DM		 890 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
891
892 for (r = 1; r <= 16; r++)
893 for (p = 1; p <= 8; p++) {
255173b4
PM		 894 for (j = 4; j <= 55; j++) {
895 /* This is actually 1000*((j+(d/10000))*r)/p
896 * The term had to be converted to get
897 * rid of the division by 10000; d = 0 here
898 */
5baf8315 899 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 900
901 /* Check whether this values get closer than
902 * the best ones we had before
903 */
5baf8315 904 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 905 abs(codec_clk - last_clk)) {
906 pll_j = j; pll_d = 0;
907 pll_r = r; pll_p = p;
5baf8315 908 last_clk = tmp_clk;
255173b4
PM		 909 }
910
911 /* Early exit for exact matches */
5baf8315 912 if (tmp_clk == codec_clk)
255173b4
PM		 913 goto found;
914 }
915 }
4f9c16cc 916
255173b4
PM		 917 /* try with d != 0 */
918 for (p = 1; p <= 8; p++) {
919 j = codec_clk * p / 1000;
4f9c16cc 920
255173b4
PM		 921 if (j < 4 || j > 11)
922 continue;
4f9c16cc 923
255173b4
PM		 924 /* do not use codec_clk here since we'd loose precision */
925 d = ((2048 * p * fsref) - j * aic3x->sysclk)
926 * 100 / (aic3x->sysclk/100);
4f9c16cc 927
255173b4 928 clk = (10000 * j + d) / (10 * p);
4f9c16cc 929
255173b4
PM		 930 /* check whether this values get closer than the best
931 * ones we had before */
932 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
933 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
934 last_clk = clk;
4f9c16cc
DM		 935 }
936
255173b4
PM		 937 /* Early exit for exact matches */
938 if (clk == codec_clk)
939 goto found;
940 }
941
4f9c16cc
DM		 942 if (last_clk == 0) {
943 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
944 return -EINVAL;
945 }
44d0a879 946
255173b4 947found:
e18eca43
JN		 948 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
949 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
950 data | (pll_p << PLLP_SHIFT));
951 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
952 pll_r << PLLR_SHIFT);
953 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
954 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
955 (pll_d >> 6) << PLLD_MSB_SHIFT);
956 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
957 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 958
44d0a879
VB		 959 return 0;
960}
961
e550e17f 962static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 963{
964 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 965 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
966 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 967
968 if (mute) {
e18eca43
JN		 969 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
970 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 971 } else {
e18eca43
JN		 972 snd_soc_write(codec, LDAC_VOL, ldac_reg);
973 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 974 }
975
976 return 0;
977}
978
e550e17f 979static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 980 int clk_id, unsigned int freq, int dir)
981{
982 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 983 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 984
4f9c16cc
DM		 985 aic3x->sysclk = freq;
986 return 0;
44d0a879
VB		 987}
988
e550e17f 989static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 990 unsigned int fmt)
991{
992 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 993 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 994 u8 iface_areg, iface_breg;
a24f4f68 995 int delay = 0;
81971a14 996
e18eca43
JN		 997 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
998 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 999
1000 /* set master/slave audio interface */
1001 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1002 case SND_SOC_DAIFMT_CBM_CFM:
1003 aic3x->master = 1;
1004 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1005 break;
1006 case SND_SOC_DAIFMT_CBS_CFS:
1007 aic3x->master = 0;
1008 break;
1009 default:
1010 return -EINVAL;
1011 }
1012
4b7d2831
JN		 1013 /*
1014 * match both interface format and signal polarities since they
1015 * are fixed
1016 */
1017 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1018 SND_SOC_DAIFMT_INV_MASK)) {
1019 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1020 break;
a24f4f68
TK		 1021 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1022 delay = 1;
4b7d2831 1023 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1024 iface_breg |= (0x01 << 6);
1025 break;
4b7d2831 1026 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1027 iface_breg |= (0x02 << 6);
1028 break;
4b7d2831 1029 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1030 iface_breg |= (0x03 << 6);
1031 break;
1032 default:
1033 return -EINVAL;
1034 }
1035
1036 /* set iface */
e18eca43
JN		 1037 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1038 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1039 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1040
1041 return 0;
1042}
1043
6c1a7d40
JN		 1044static int aic3x_init_3007(struct snd_soc_codec *codec)
1045{
1046 u8 tmp1, tmp2, *cache = codec->reg_cache;
1047
1048 /*
1049 * There is no need to cache writes to undocumented page 0xD but
1050 * respective page 0 register cache entries must be preserved
1051 */
1052 tmp1 = cache[0xD];
1053 tmp2 = cache[0x8];
1054 /* Class-D speaker driver init; datasheet p. 46 */
1055 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1056 snd_soc_write(codec, 0xD, 0x0D);
1057 snd_soc_write(codec, 0x8, 0x5C);
1058 snd_soc_write(codec, 0x8, 0x5D);
1059 snd_soc_write(codec, 0x8, 0x5C);
1060 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1061 cache[0xD] = tmp1;
1062 cache[0x8] = tmp2;
1063
1064 return 0;
1065}
1066
5a895f8a
JN		 1067static int aic3x_regulator_event(struct notifier_block *nb,
1068 unsigned long event, void *data)
1069{
1070 struct aic3x_disable_nb *disable_nb =
1071 container_of(nb, struct aic3x_disable_nb, nb);
1072 struct aic3x_priv *aic3x = disable_nb->aic3x;
1073
1074 if (event & REGULATOR_EVENT_DISABLE) {
1075 /*
1076 * Put codec to reset and require cache sync as at least one
1077 * of the supplies was disabled
1078 */
1079 if (aic3x->gpio_reset >= 0)
1080 gpio_set_value(aic3x->gpio_reset, 0);
1081 aic3x->codec->cache_sync = 1;
1082 }
1083
1084 return 0;
1085}
1086
6c1a7d40
JN		 1087static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1088{
1089 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1090 int i, ret;
1091 u8 *cache = codec->reg_cache;
1092
1093 if (power) {
1094 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1095 aic3x->supplies);
1096 if (ret)
1097 goto out;
1098 aic3x->power = 1;
5a895f8a
JN		 1099 /*
1100 * Reset release and cache sync is necessary only if some
1101 * supply was off or if there were cached writes
1102 */
1103 if (!codec->cache_sync)
1104 goto out;
1105
6c1a7d40
JN		 1106 if (aic3x->gpio_reset >= 0) {
1107 udelay(1);
1108 gpio_set_value(aic3x->gpio_reset, 1);
1109 }
1110
1111 /* Sync reg_cache with the hardware */
1112 codec->cache_only = 0;
1113 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++)
1114 snd_soc_write(codec, i, cache[i]);
1115 if (aic3x->model == AIC3X_MODEL_3007)
1116 aic3x_init_3007(codec);
1117 codec->cache_sync = 0;
1118 } else {
1119 aic3x->power = 0;
5a895f8a
JN		 1120 /* HW writes are needless when bias is off */
1121 codec->cache_only = 1;
6c1a7d40
JN		 1122 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1123 aic3x->supplies);
1124 }
1125out:
1126 return ret;
1127}
1128
0be9898a
MB		 1129static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1130 enum snd_soc_bias_level level)
44d0a879 1131{
b2c812e2 1132 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 1133 u8 reg;
1134
0be9898a
MB		 1135 switch (level) {
1136 case SND_SOC_BIAS_ON:
db13802e
JN		 1137 break;
1138 case SND_SOC_BIAS_PREPARE:
ce6120cc 1139 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1140 aic3x->master) {
44d0a879 1141 /* enable pll */
e18eca43
JN		 1142 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1143 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1144 reg | PLL_ENABLE);
44d0a879
VB		 1145 }
1146 break;
0be9898a 1147 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1148 if (!aic3x->power)
1149 aic3x_set_power(codec, 1);
ce6120cc 1150 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1151 aic3x->master) {
44d0a879 1152 /* disable pll */
e18eca43
JN		 1153 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1154 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1155 reg & ~PLL_ENABLE);
44d0a879
VB		 1156 }
1157 break;
c23fd751 1158 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1159 if (aic3x->power)
1160 aic3x_set_power(codec, 0);
c23fd751 1161 break;
44d0a879 1162 }
ce6120cc 1163 codec->dapm.bias_level = level;
44d0a879
VB		 1164
1165 return 0;
1166}
1167
54e7e616
DM		 1168void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1169{
1170 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1171 u8 bit = gpio ? 3: 0;
e18eca43
JN		 1172 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1173 snd_soc_write(codec, reg, val | (!!state << bit));
54e7e616
DM		 1174}
1175EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1176
1177int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1178{
1179 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1180 u8 val, bit = gpio ? 2: 1;
1181
1182 aic3x_read(codec, reg, &val);
1183 return (val >> bit) & 1;
1184}
1185EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1186
6f2a974b
DM		 1187void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1188 int headset_debounce, int button_debounce)
1189{
1190 u8 val;
1191
1192 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1193 << AIC3X_HEADSET_DETECT_SHIFT) |
1194 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1195 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1196 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1197 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1198
1199 if (detect & AIC3X_HEADSET_DETECT_MASK)
1200 val |= AIC3X_HEADSET_DETECT_ENABLED;
1201
e18eca43 1202 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
6f2a974b
DM		 1203}
1204EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1205
54e7e616
DM		 1206int aic3x_headset_detected(struct snd_soc_codec *codec)
1207{
1208 u8 val;
6f2a974b
DM		 1209 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1210 return (val >> 4) & 1;
54e7e616
DM		 1211}
1212EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1213
6f2a974b
DM		 1214int aic3x_button_pressed(struct snd_soc_codec *codec)
1215{
1216 u8 val;
1217 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1218 return (val >> 5) & 1;
1219}
1220EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1221
44d0a879
VB		 1222#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1223#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1224 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1225
6335d055
EM		 1226static struct snd_soc_dai_ops aic3x_dai_ops = {
1227 .hw_params = aic3x_hw_params,
1228 .digital_mute = aic3x_mute,
1229 .set_sysclk = aic3x_set_dai_sysclk,
1230 .set_fmt = aic3x_set_dai_fmt,
1231};
1232
f0fba2ad
LG		 1233static struct snd_soc_dai_driver aic3x_dai = {
1234 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1235 .playback = {
1236 .stream_name = "Playback",
1237 .channels_min = 1,
1238 .channels_max = 2,
1239 .rates = AIC3X_RATES,
1240 .formats = AIC3X_FORMATS,},
1241 .capture = {
1242 .stream_name = "Capture",
1243 .channels_min = 1,
1244 .channels_max = 2,
1245 .rates = AIC3X_RATES,
1246 .formats = AIC3X_FORMATS,},
6335d055 1247 .ops = &aic3x_dai_ops,
14017615 1248 .symmetric_rates = 1,
44d0a879 1249};
44d0a879 1250
f0fba2ad 1251static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
44d0a879 1252{
0be9898a 1253 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1254
1255 return 0;
1256}
1257
f0fba2ad 1258static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1259{
29e189c2 1260 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1261
1262 return 0;
1263}
1264
1265/*
1266 * initialise the AIC3X driver
1267 * register the mixer and dsp interfaces with the kernel
1268 */
cb3826f5 1269static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1270{
6184f105 1271 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5
BD		 1272 int reg;
1273
e18eca43
JN		 1274 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1275 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1276
44d0a879 1277 /* DAC default volume and mute */
e18eca43
JN		 1278 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1279 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1280
1281 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1282 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1283 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1284 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1285 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1286 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1287 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1288 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1289 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1290 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1291 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1292
1293 /* unmute all outputs */
e18eca43
JN		 1294 reg = snd_soc_read(codec, LLOPM_CTRL);
1295 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
1296 reg = snd_soc_read(codec, RLOPM_CTRL);
1297 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
1298 reg = snd_soc_read(codec, MONOLOPM_CTRL);
1299 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1300 reg = snd_soc_read(codec, HPLOUT_CTRL);
1301 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1302 reg = snd_soc_read(codec, HPROUT_CTRL);
1303 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
1304 reg = snd_soc_read(codec, HPLCOM_CTRL);
1305 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1306 reg = snd_soc_read(codec, HPRCOM_CTRL);
1307 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
44d0a879
VB		 1308
1309 /* ADC default volume and unmute */
e18eca43
JN		 1310 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1311 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1312 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1313 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1314 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1315
1316 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1317 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1318 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1319 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1320 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1321 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1322 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1323 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1324 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1325 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1326 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1327
1328 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1329 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1330 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1331 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1332 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1333 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1334 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1335 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1336 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1337 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1338 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1339
6184f105 1340 if (aic3x->model == AIC3X_MODEL_3007) {
6c1a7d40 1341 aic3x_init_3007(codec);
e18eca43 1342 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1343 }
1344
cb3826f5
BD		 1345 return 0;
1346}
54e7e616 1347
f0fba2ad 1348static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1349{
f0fba2ad 1350 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1351 int ret, i;
f0fba2ad 1352
f0fba2ad 1353 codec->control_data = aic3x->control_data;
5a895f8a 1354 aic3x->codec = codec;
ce6120cc 1355 codec->dapm.idle_bias_off = 1;
cb3826f5 1356
a84a441b
JN		 1357 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1358 if (ret != 0) {
1359 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1360 return ret;
1361 }
1362
2f24111a
JN		 1363 if (aic3x->gpio_reset >= 0) {
1364 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1365 if (ret != 0)
1366 goto err_gpio;
1367 gpio_direction_output(aic3x->gpio_reset, 0);
1368 }
1369
1370 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1371 aic3x->supplies[i].supply = aic3x_supply_names[i];
1372
1373 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1374 aic3x->supplies);
1375 if (ret != 0) {
1376 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1377 goto err_get;
1378 }
5a895f8a
JN		 1379 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1380 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1381 aic3x->disable_nb[i].aic3x = aic3x;
1382 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1383 &aic3x->disable_nb[i].nb);
1384 if (ret) {
1385 dev_err(codec->dev,
1386 "Failed to request regulator notifier: %d\n",
1387 ret);
1388 goto err_notif;
1389 }
1390 }
2f24111a 1391
7d1be0a6 1392 codec->cache_only = 1;
37b47656
JN		 1393 aic3x_init(codec);
1394
f0fba2ad
LG		 1395 if (aic3x->setup) {
1396 /* setup GPIO functions */
e18eca43
JN		 1397 snd_soc_write(codec, AIC3X_GPIO1_REG,
1398 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1399 snd_soc_write(codec, AIC3X_GPIO2_REG,
1400 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1401 }
1402
f0fba2ad
LG		 1403 snd_soc_add_controls(codec, aic3x_snd_controls,
1404 ARRAY_SIZE(aic3x_snd_controls));
6184f105
RC		 1405 if (aic3x->model == AIC3X_MODEL_3007)
1406 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1407
f0fba2ad 1408 aic3x_add_widgets(codec);
cb3826f5
BD		 1409
1410 return 0;
2f24111a 1411
5a895f8a
JN		 1412err_notif:
1413 while (i--)
1414 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1415 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1416 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1417err_get:
1418 if (aic3x->gpio_reset >= 0)
1419 gpio_free(aic3x->gpio_reset);
1420err_gpio:
2f24111a 1421 return ret;
44d0a879
VB		 1422}
1423
f0fba2ad 1424static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1425{
2f24111a 1426 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1427 int i;
2f24111a 1428
f0fba2ad 1429 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
2f24111a
JN		 1430 if (aic3x->gpio_reset >= 0) {
1431 gpio_set_value(aic3x->gpio_reset, 0);
1432 gpio_free(aic3x->gpio_reset);
1433 }
5a895f8a
JN		 1434 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1435 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1436 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1437 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1438
cb3826f5
BD		 1439 return 0;
1440}
44d0a879 1441
f0fba2ad 1442static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad
LG		 1443 .set_bias_level = aic3x_set_bias_level,
1444 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1445 .reg_word_size = sizeof(u8),
1446 .reg_cache_default = aic3x_reg,
1447 .probe = aic3x_probe,
1448 .remove = aic3x_remove,
1449 .suspend = aic3x_suspend,
1450 .resume = aic3x_resume,
1451};
1452
44d0a879
VB		 1453#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1454/*
1455 * AIC3X 2 wire address can be up to 4 devices with device addresses
1456 * 0x18, 0x19, 0x1A, 0x1B
1457 */
44d0a879 1458
6184f105
RC		 1459static const struct i2c_device_id aic3x_i2c_id[] = {
1460 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1461 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1462 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1463 { }
1464};
1465MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1466
44d0a879
VB		 1467/*
1468 * If the i2c layer weren't so broken, we could pass this kind of data
1469 * around
1470 */
ba8ed121
JD		 1471static int aic3x_i2c_probe(struct i2c_client *i2c,
1472 const struct i2c_device_id *id)
44d0a879 1473{
5193d62f 1474 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1475 struct aic3x_priv *aic3x;
2f24111a 1476 int ret;
6184f105 1477 const struct i2c_device_id *tbl;
44d0a879 1478
cb3826f5
BD		 1479 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1480 if (aic3x == NULL) {
1481 dev_err(&i2c->dev, "failed to create private data\n");
1482 return -ENOMEM;
1483 }
1484
f0fba2ad 1485 aic3x->control_data = i2c;
a84a441b
JN		 1486 aic3x->control_type = SND_SOC_I2C;
1487
cb3826f5 1488 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1489 if (pdata) {
1490 aic3x->gpio_reset = pdata->gpio_reset;
1491 aic3x->setup = pdata->setup;
1492 } else {
1493 aic3x->gpio_reset = -1;
1494 }
cb3826f5 1495
6184f105
RC		 1496 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1497 if (!strcmp(tbl->name, id->name))
1498 break;
1499 }
1500 aic3x->model = tbl - aic3x_i2c_id;
1501
f0fba2ad
LG		 1502 ret = snd_soc_register_codec(&i2c->dev,
1503 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1504 if (ret < 0)
2f24111a 1505 kfree(aic3x);
07779fdd 1506 return ret;
44d0a879
VB		 1507}
1508
ba8ed121 1509static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1510{
f0fba2ad
LG		 1511 snd_soc_unregister_codec(&client->dev);
1512 kfree(i2c_get_clientdata(client));
1513 return 0;
44d0a879
VB		 1514}
1515
44d0a879
VB		 1516/* machine i2c codec control layer */
1517static struct i2c_driver aic3x_i2c_driver = {
1518 .driver = {
f0fba2ad 1519 .name = "tlv320aic3x-codec",
44d0a879
VB		 1520 .owner = THIS_MODULE,
1521 },
cb3826f5 1522 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1523 .remove = aic3x_i2c_remove,
1524 .id_table = aic3x_i2c_id,
44d0a879 1525};
54e7e616 1526
cb3826f5 1527static inline void aic3x_i2c_init(void)
ba8ed121 1528{
ba8ed121
JD		 1529 int ret;
1530
1531 ret = i2c_add_driver(&aic3x_i2c_driver);
cb3826f5
BD		 1532 if (ret)
1533 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1534 __func__, ret);
1535}
ba8ed121 1536
cb3826f5
BD		 1537static inline void aic3x_i2c_exit(void)
1538{
ba8ed121 1539 i2c_del_driver(&aic3x_i2c_driver);
ba8ed121 1540}
44d0a879
VB		 1541#endif
1542
f0fba2ad 1543static int __init aic3x_modinit(void)
44d0a879 1544{
44d0a879 1545 int ret = 0;
f0fba2ad
LG		 1546#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1547 ret = i2c_add_driver(&aic3x_i2c_driver);
1548 if (ret != 0) {
1549 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1550 ret);
44d0a879 1551 }
f0fba2ad 1552#endif
44d0a879
VB		 1553 return ret;
1554}
64089b84
MB		 1555module_init(aic3x_modinit);
1556
1557static void __exit aic3x_exit(void)
1558{
f0fba2ad
LG		 1559#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1560 i2c_del_driver(&aic3x_i2c_driver);
1561#endif
64089b84
MB		 1562}
1563module_exit(aic3x_exit);
1564
44d0a879
VB		 1565MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1566MODULE_AUTHOR("Vladimir Barinov");
1567MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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