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Merge branch 'upstream' of git://git.infradead.org/users/pcmoore/audit
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
b3b70786 43#include <linux/of.h>
c24fdc88 44#include <linux/of_gpio.h>
5a0e3ad6 45#include <linux/slab.h>
44d0a879
VB		 46#include <sound/core.h>
47#include <sound/pcm.h>
48#include <sound/pcm_params.h>
49#include <sound/soc.h>
44d0a879 50#include <sound/initval.h>
7565fc38 51#include <sound/tlv.h>
5193d62f 52#include <sound/tlv320aic3x.h>
44d0a879
VB		 53
54#include "tlv320aic3x.h"
55
07779fdd
JN		 56#define AIC3X_NUM_SUPPLIES 4
57static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62};
44d0a879 63
414c73ab
JN		 64static LIST_HEAD(reset_list);
65
5a895f8a
JN		 66struct aic3x_priv;
67
68struct aic3x_disable_nb {
69 struct notifier_block nb;
70 struct aic3x_priv *aic3x;
71};
72
44d0a879
VB		 73/* codec private data */
74struct aic3x_priv {
5a895f8a 75 struct snd_soc_codec *codec;
2a6fedec 76 struct regmap *regmap;
07779fdd 77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad 79 struct aic3x_setup_data *setup;
44d0a879 80 unsigned int sysclk;
36849409
PU		 81 unsigned int dai_fmt;
82 unsigned int tdm_delay;
414c73ab 83 struct list_head list;
44d0a879 84 int master;
5193d62f 85 int gpio_reset;
6c1a7d40 86 int power;
6184f105
RC		 87#define AIC3X_MODEL_3X 0
88#define AIC3X_MODEL_33 1
89#define AIC3X_MODEL_3007 2
90 u16 model;
e2e8bfdf
HG		 91
92 /* Selects the micbias voltage */
93 enum aic3x_micbias_voltage micbias_vg;
44d0a879
VB		 94};
95
2a6fedec
MB		 96static const struct reg_default aic3x_reg[] = {
97 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
98 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
99 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
100 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
101 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
102 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
103 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
104 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
105 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
106 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
107 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
108 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
109 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
110 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
111 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
112 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
113 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
114 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
115 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
116 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
117 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
118 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
119 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
120 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
121 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
122 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
123 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
124 { 108, 0x00 }, { 109, 0x00 },
125};
126
127static const struct regmap_config aic3x_regmap = {
128 .reg_bits = 8,
129 .val_bits = 8,
130
131 .max_register = DAC_ICC_ADJ,
132 .reg_defaults = aic3x_reg,
133 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
134 .cache_type = REGCACHE_RBTREE,
44d0a879
VB		 135};
136
44d0a879 137#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
1476f66f
LPC		 138 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
139 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
44d0a879
VB		 140
141/*
142 * All input lines are connected when !0xf and disconnected with 0xf bit field,
143 * so we have to use specific dapm_put call for input mixer
144 */
145static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
146 struct snd_ctl_elem_value *ucontrol)
147{
eee5d7f9 148 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
4453dba5
EN		 149 struct soc_mixer_control *mc =
150 (struct soc_mixer_control *)kcontrol->private_value;
151 unsigned int reg = mc->reg;
152 unsigned int shift = mc->shift;
153 int max = mc->max;
154 unsigned int mask = (1 << fls(max)) - 1;
155 unsigned int invert = mc->invert;
5d99d778
LPC		 156 unsigned short val;
157 struct snd_soc_dapm_update update;
158 int connect, change;
44d0a879
VB		 159
160 val = (ucontrol->value.integer.value[0] & mask);
161
162 mask = 0xf;
163 if (val)
164 val = mask;
165
5d99d778
LPC		 166 connect = !!val;
167
44d0a879
VB		 168 if (invert)
169 val = mask - val;
44d0a879 170
5d99d778
LPC		 171 mask <<= shift;
172 val <<= shift;
2894770e 173
e6c111fa 174 change = snd_soc_test_bits(codec, reg, mask, val);
5d99d778
LPC		 175 if (change) {
176 update.kcontrol = kcontrol;
177 update.reg = reg;
178 update.mask = mask;
179 update.val = val;
180
eee5d7f9 181 snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect,
5d99d778
LPC		 182 &update);
183 }
2894770e 184
5d99d778 185 return change;
44d0a879
VB		 186}
187
e2e8bfdf
HG		 188/*
189 * mic bias power on/off share the same register bits with
190 * output voltage of mic bias. when power on mic bias, we
191 * need reclaim it to voltage value.
192 * 0x0 = Powered off
193 * 0x1 = MICBIAS output is powered to 2.0V,
194 * 0x2 = MICBIAS output is powered to 2.5V
195 * 0x3 = MICBIAS output is connected to AVDD
196 */
197static int mic_bias_event(struct snd_soc_dapm_widget *w,
198 struct snd_kcontrol *kcontrol, int event)
199{
200 struct snd_soc_codec *codec = w->codec;
201 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
202
203 switch (event) {
204 case SND_SOC_DAPM_POST_PMU:
205 /* change mic bias voltage to user defined */
206 snd_soc_update_bits(codec, MICBIAS_CTRL,
207 MICBIAS_LEVEL_MASK,
208 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
209 break;
210
211 case SND_SOC_DAPM_PRE_PMD:
212 snd_soc_update_bits(codec, MICBIAS_CTRL,
213 MICBIAS_LEVEL_MASK, 0);
214 break;
215 }
216 return 0;
217}
218
a60e654b
PU		 219static const char * const aic3x_left_dac_mux[] = {
220 "DAC_L1", "DAC_L3", "DAC_L2" };
221static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
222 aic3x_left_dac_mux);
223
224static const char * const aic3x_right_dac_mux[] = {
225 "DAC_R1", "DAC_R3", "DAC_R2" };
226static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
227 aic3x_right_dac_mux);
228
229static const char * const aic3x_left_hpcom_mux[] = {
230 "differential of HPLOUT", "constant VCM", "single-ended" };
231static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
232 aic3x_left_hpcom_mux);
233
234static const char * const aic3x_right_hpcom_mux[] = {
235 "differential of HPROUT", "constant VCM", "single-ended",
236 "differential of HPLCOM", "external feedback" };
237static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
238 aic3x_right_hpcom_mux);
239
240static const char * const aic3x_linein_mode_mux[] = {
241 "single-ended", "differential" };
242static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
243 aic3x_linein_mode_mux);
244static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
245 aic3x_linein_mode_mux);
246static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
247 aic3x_linein_mode_mux);
248static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
249 aic3x_linein_mode_mux);
250static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
251 aic3x_linein_mode_mux);
252static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
253 aic3x_linein_mode_mux);
254
255static const char * const aic3x_adc_hpf[] = {
256 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
257static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
258 aic3x_adc_hpf);
259
260static const char * const aic3x_agc_level[] = {
261 "-5.5dB", "-8dB", "-10dB", "-12dB",
262 "-14dB", "-17dB", "-20dB", "-24dB" };
263static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
264 aic3x_agc_level);
265static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
266 aic3x_agc_level);
267
268static const char * const aic3x_agc_attack[] = {
269 "8ms", "11ms", "16ms", "20ms" };
270static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
271 aic3x_agc_attack);
272static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
273 aic3x_agc_attack);
274
275static const char * const aic3x_agc_decay[] = {
276 "100ms", "200ms", "400ms", "500ms" };
277static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
278 aic3x_agc_decay);
279static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
280 aic3x_agc_decay);
bb1daa80 281
68d66269
MLC		 282static const char * const aic3x_poweron_time[] = {
283 "0us", "10us", "100us", "1ms", "10ms", "50ms",
284 "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
285static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
286 aic3x_poweron_time);
287
288static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
289static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2,
290 aic3x_rampup_step);
291
7565fc38
JN		 292/*
293 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
294 */
295static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
296/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
297static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
298/*
299 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
300 * Step size is approximately 0.5 dB over most of the scale but increasing
301 * near the very low levels.
302 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
303 * but having increasing dB difference below that (and where it doesn't count
304 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
305 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
306 */
307static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
308
44d0a879
VB		 309static const struct snd_kcontrol_new aic3x_snd_controls[] = {
310 /* Output */
7565fc38
JN		 311 SOC_DOUBLE_R_TLV("PCM Playback Volume",
312 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 313
098b1718
JN		 314 /*
315 * Output controls that map to output mixer switches. Note these are
316 * only for swapped L-to-R and R-to-L routes. See below stereo controls
317 * for direct L-to-L and R-to-R routes.
318 */
319 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
320 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
321 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
322 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
323 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
324 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
325
326 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
327 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
328 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
329 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
330 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
331 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
332
333 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
334 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
335 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
336 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
337 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
338 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
339
340 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
341 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
342 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
343 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
344 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
345 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
346
347 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
348 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
349 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
350 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
351 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
352 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
353
354 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
355 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
356 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
357 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
358 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
359 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
360
361 /* Stereo output controls for direct L-to-L and R-to-R routes */
362 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
363 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
364 0, 118, 1, output_stage_tlv),
365 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
366 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
367 0, 118, 1, output_stage_tlv),
7565fc38
JN		 368 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
369 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
370 0, 118, 1, output_stage_tlv),
098b1718 371
098b1718
JN		 372 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
373 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 374 0, 118, 1, output_stage_tlv),
098b1718
JN		 375 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
376 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 377 0, 118, 1, output_stage_tlv),
7565fc38
JN		 378 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
379 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
380 0, 118, 1, output_stage_tlv),
098b1718
JN		 381
382 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
383 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 384 0, 118, 1, output_stage_tlv),
098b1718
JN		 385 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
386 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 387 0, 118, 1, output_stage_tlv),
7565fc38
JN		 388 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
389 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
390 0, 118, 1, output_stage_tlv),
098b1718
JN		 391
392 /* Output pin mute controls */
393 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
394 0x01, 0),
098b1718
JN		 395 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
396 0x01, 0),
f9bc0297 397 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 398 0x01, 0),
44d0a879
VB		 399
400 /*
401 * Note: enable Automatic input Gain Controller with care. It can
402 * adjust PGA to max value when ADC is on and will never go back.
403 */
404 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
a60e654b
PU		 405 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
406 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
407 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
408 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
409 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
410 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
44d0a879 411
77444191
JP		 412 /* De-emphasis */
413 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
44d0a879
VB		 414
415 /* Input */
7565fc38
JN		 416 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
417 0, 119, 0, adc_tlv),
44d0a879 418 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a 419
a60e654b 420 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
68d66269
MLC		 421
422 /* Pop reduction */
423 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
424 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
44d0a879
VB		 425};
426
58381da6
JW		 427static const struct snd_kcontrol_new aic3x_mono_controls[] = {
428 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
429 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
430 0, 118, 1, output_stage_tlv),
431 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
432 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
433 0, 118, 1, output_stage_tlv),
434 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
435 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
436 0, 118, 1, output_stage_tlv),
437
438 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
439};
440
6184f105
RC		 441/*
442 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
443 */
444static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
445
446static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
14a95fe8 447 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
6184f105 448
44d0a879
VB		 449/* Left DAC Mux */
450static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
a60e654b 451SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
44d0a879
VB		 452
453/* Right DAC Mux */
454static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
a60e654b 455SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
44d0a879
VB		 456
457/* Left HPCOM Mux */
458static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
a60e654b 459SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
44d0a879
VB		 460
461/* Right HPCOM Mux */
462static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
a60e654b 463SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
44d0a879 464
c3b79e05
JN		 465/* Left Line Mixer */
466static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
467 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
472 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 473};
474
c3b79e05
JN		 475/* Right Line Mixer */
476static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
477 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
480 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
481 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
482 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
483};
484
485/* Mono Mixer */
486static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
487 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
488 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
489 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
490 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
491 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
492 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
493};
494
495/* Left HP Mixer */
496static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
497 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
498 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
499 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
500 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
501 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
502 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
503};
504
505/* Right HP Mixer */
506static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
507 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
508 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
509 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
510 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
511 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
512 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
513};
514
515/* Left HPCOM Mixer */
516static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
517 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
518 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
519 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
520 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
521 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
522 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
523};
524
525/* Right HPCOM Mixer */
526static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
527 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
528 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
529 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
530 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
531 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
532 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 533};
534
535/* Left PGA Mixer */
536static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
537 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 538 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 539 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
540 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 541 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 542};
543
544/* Right PGA Mixer */
545static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
546 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 547 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 548 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 549 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 550 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
551};
552
553/* Left Line1 Mux */
404b5665 554static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
a60e654b 555SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
404b5665 556static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
a60e654b 557SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
44d0a879
VB		 558
559/* Right Line1 Mux */
404b5665 560static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
a60e654b 561SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
404b5665 562static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
a60e654b 563SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
44d0a879
VB		 564
565/* Left Line2 Mux */
566static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
a60e654b 567SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
44d0a879
VB		 568
569/* Right Line2 Mux */
570static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
a60e654b 571SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
44d0a879 572
44d0a879
VB		 573static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
574 /* Left DAC to Left Outputs */
575 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
576 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
577 &aic3x_left_dac_mux_controls),
44d0a879
VB		 578 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
579 &aic3x_left_hpcom_mux_controls),
580 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
581 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
582 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
583
584 /* Right DAC to Right Outputs */
585 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
586 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
587 &aic3x_right_dac_mux_controls),
44d0a879
VB		 588 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
589 &aic3x_right_hpcom_mux_controls),
590 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
591 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
592 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
593
54f01916 594 /* Inputs to Left ADC */
44d0a879
VB		 595 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
596 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
597 &aic3x_left_pga_mixer_controls[0],
598 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
599 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 600 &aic3x_left_line1l_mux_controls),
54f01916 601 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 602 &aic3x_left_line1r_mux_controls),
44d0a879
VB		 603 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
604 &aic3x_left_line2_mux_controls),
605
54f01916 606 /* Inputs to Right ADC */
44d0a879
VB		 607 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
608 LINE1R_2_RADC_CTRL, 2, 0),
609 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
610 &aic3x_right_pga_mixer_controls[0],
611 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916 612 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 613 &aic3x_right_line1l_mux_controls),
44d0a879 614 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 615 &aic3x_right_line1r_mux_controls),
44d0a879
VB		 616 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
617 &aic3x_right_line2_mux_controls),
618
ee15ffdb
JN		 619 /*
620 * Not a real mic bias widget but similar function. This is for dynamic
621 * control of GPIO1 digital mic modulator clock output function when
622 * using digital mic.
623 */
624 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
625 AIC3X_GPIO1_REG, 4, 0xf,
626 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
627 AIC3X_GPIO1_FUNC_DISABLED),
628
629 /*
630 * Also similar function like mic bias. Selects digital mic with
631 * configurable oversampling rate instead of ADC converter.
632 */
633 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
634 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
635 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
636 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
637 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
638 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
639
44d0a879 640 /* Mic Bias */
e2e8bfdf
HG		 641 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
642 mic_bias_event,
643 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
44d0a879 644
c3b79e05
JN		 645 /* Output mixers */
646 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
647 &aic3x_left_line_mixer_controls[0],
648 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
649 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
650 &aic3x_right_line_mixer_controls[0],
651 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
c3b79e05
JN		 652 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
653 &aic3x_left_hp_mixer_controls[0],
654 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
655 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
656 &aic3x_right_hp_mixer_controls[0],
657 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
658 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
659 &aic3x_left_hpcom_mixer_controls[0],
660 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
661 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
662 &aic3x_right_hpcom_mixer_controls[0],
663 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 664
665 SND_SOC_DAPM_OUTPUT("LLOUT"),
666 SND_SOC_DAPM_OUTPUT("RLOUT"),
44d0a879
VB		 667 SND_SOC_DAPM_OUTPUT("HPLOUT"),
668 SND_SOC_DAPM_OUTPUT("HPROUT"),
669 SND_SOC_DAPM_OUTPUT("HPLCOM"),
670 SND_SOC_DAPM_OUTPUT("HPRCOM"),
671
672 SND_SOC_DAPM_INPUT("MIC3L"),
673 SND_SOC_DAPM_INPUT("MIC3R"),
674 SND_SOC_DAPM_INPUT("LINE1L"),
675 SND_SOC_DAPM_INPUT("LINE1R"),
676 SND_SOC_DAPM_INPUT("LINE2L"),
677 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 678
679 /*
680 * Virtual output pin to detection block inside codec. This can be
681 * used to keep codec bias on if gpio or detection features are needed.
682 * Force pin on or construct a path with an input jack and mic bias
683 * widgets.
684 */
685 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 686};
687
58381da6
JW		 688static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
689 /* Mono Output */
690 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
691
692 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
693 &aic3x_mono_mixer_controls[0],
694 ARRAY_SIZE(aic3x_mono_mixer_controls)),
695
696 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
697};
698
6184f105
RC		 699static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
700 /* Class-D outputs */
701 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
702 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
703
704 SND_SOC_DAPM_OUTPUT("SPOP"),
705 SND_SOC_DAPM_OUTPUT("SPOM"),
706};
707
d0cc0d3a 708static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 709 /* Left Input */
710 {"Left Line1L Mux", "single-ended", "LINE1L"},
711 {"Left Line1L Mux", "differential", "LINE1L"},
6b2afee1
PU		 712 {"Left Line1R Mux", "single-ended", "LINE1R"},
713 {"Left Line1R Mux", "differential", "LINE1R"},
44d0a879
VB		 714
715 {"Left Line2L Mux", "single-ended", "LINE2L"},
716 {"Left Line2L Mux", "differential", "LINE2L"},
717
718 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 719 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 720 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
721 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 722 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 723
724 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 725 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 726
727 /* Right Input */
728 {"Right Line1R Mux", "single-ended", "LINE1R"},
729 {"Right Line1R Mux", "differential", "LINE1R"},
6b2afee1
PU		 730 {"Right Line1L Mux", "single-ended", "LINE1L"},
731 {"Right Line1L Mux", "differential", "LINE1L"},
44d0a879
VB		 732
733 {"Right Line2R Mux", "single-ended", "LINE2R"},
734 {"Right Line2R Mux", "differential", "LINE2R"},
735
54f01916 736 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 737 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
738 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 739 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 740 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
741
742 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 743 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 744
ee15ffdb
JN		 745 /*
746 * Logical path between digital mic enable and GPIO1 modulator clock
747 * output function
748 */
749 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
750 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
751 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 752
753 /* Left DAC Output */
754 {"Left DAC Mux", "DAC_L1", "Left DAC"},
755 {"Left DAC Mux", "DAC_L2", "Left DAC"},
756 {"Left DAC Mux", "DAC_L3", "Left DAC"},
757
758 /* Right DAC Output */
759 {"Right DAC Mux", "DAC_R1", "Right DAC"},
760 {"Right DAC Mux", "DAC_R2", "Right DAC"},
761 {"Right DAC Mux", "DAC_R3", "Right DAC"},
762
763 /* Left Line Output */
764 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
765 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
766 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
767 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
768 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
769 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
770
771 {"Left Line Out", NULL, "Left Line Mixer"},
772 {"Left Line Out", NULL, "Left DAC Mux"},
773 {"LLOUT", NULL, "Left Line Out"},
774
775 /* Right Line Output */
776 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
777 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
778 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
779 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
780 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
781 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
782
783 {"Right Line Out", NULL, "Right Line Mixer"},
784 {"Right Line Out", NULL, "Right DAC Mux"},
785 {"RLOUT", NULL, "Right Line Out"},
786
c3b79e05
JN		 787 /* Left HP Output */
788 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
789 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
790 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
791 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
792 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
793 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
794
795 {"Left HP Out", NULL, "Left HP Mixer"},
796 {"Left HP Out", NULL, "Left DAC Mux"},
797 {"HPLOUT", NULL, "Left HP Out"},
798
799 /* Right HP Output */
800 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
801 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
802 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
803 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
804 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
805 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
806
807 {"Right HP Out", NULL, "Right HP Mixer"},
808 {"Right HP Out", NULL, "Right DAC Mux"},
809 {"HPROUT", NULL, "Right HP Out"},
810
811 /* Left HPCOM Output */
812 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
813 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
814 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
815 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
816 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
817 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
818
819 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
820 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
821 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
822 {"Left HP Com", NULL, "Left HPCOM Mux"},
823 {"HPLCOM", NULL, "Left HP Com"},
824
825 /* Right HPCOM Output */
826 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
827 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
828 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
829 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
830 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
831 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
832
833 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
834 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
835 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
836 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
837 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
838 {"Right HP Com", NULL, "Right HPCOM Mux"},
839 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 840};
841
58381da6
JW		 842static const struct snd_soc_dapm_route intercon_mono[] = {
843 /* Mono Output */
844 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
845 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
846 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
847 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
848 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
849 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
850 {"Mono Out", NULL, "Mono Mixer"},
851 {"MONO_LOUT", NULL, "Mono Out"},
852};
853
6184f105
RC		 854static const struct snd_soc_dapm_route intercon_3007[] = {
855 /* Class-D outputs */
856 {"Left Class-D Out", NULL, "Left Line Out"},
857 {"Right Class-D Out", NULL, "Left Line Out"},
858 {"SPOP", NULL, "Left Class-D Out"},
859 {"SPOM", NULL, "Right Class-D Out"},
860};
861
44d0a879
VB		 862static int aic3x_add_widgets(struct snd_soc_codec *codec)
863{
6184f105 864 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 865 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 866
58381da6
JW		 867 switch (aic3x->model) {
868 case AIC3X_MODEL_3X:
869 case AIC3X_MODEL_33:
870 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
871 ARRAY_SIZE(aic3x_dapm_mono_widgets));
872 snd_soc_dapm_add_routes(dapm, intercon_mono,
873 ARRAY_SIZE(intercon_mono));
874 break;
875 case AIC3X_MODEL_3007:
ce6120cc 876 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 877 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 878 snd_soc_dapm_add_routes(dapm, intercon_3007,
879 ARRAY_SIZE(intercon_3007));
58381da6 880 break;
6184f105
RC		 881 }
882
44d0a879
VB		 883 return 0;
884}
885
44d0a879 886static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 887 struct snd_pcm_hw_params *params,
888 struct snd_soc_dai *dai)
44d0a879 889{
e6968a17 890 struct snd_soc_codec *codec = dai->codec;
b2c812e2 891 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 892 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 893 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
894 u16 d, pll_d = 1;
255173b4 895 int clk;
44d0a879 896
4f9c16cc 897 /* select data word length */
e18eca43 898 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
3e3e2922
MB		 899 switch (params_width(params)) {
900 case 16:
44d0a879 901 break;
3e3e2922 902 case 20:
4f9c16cc 903 data |= (0x01 << 4);
44d0a879 904 break;
3e3e2922 905 case 24:
4f9c16cc 906 data |= (0x02 << 4);
44d0a879 907 break;
3e3e2922 908 case 32:
4f9c16cc 909 data |= (0x03 << 4);
44d0a879
VB		 910 break;
911 }
e18eca43 912 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 913
914 /* Fsref can be 44100 or 48000 */
915 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
916
917 /* Try to find a value for Q which allows us to bypass the PLL and
918 * generate CODEC_CLK directly. */
919 for (pll_q = 2; pll_q < 18; pll_q++)
920 if (aic3x->sysclk / (128 * pll_q) == fsref) {
921 bypass_pll = 1;
922 break;
923 }
924
925 if (bypass_pll) {
926 pll_q &= 0xf;
e18eca43
JN		 927 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
928 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 929 /* disable PLL if it is bypassed */
9c173d15 930 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
06c71282
C		 931
932 } else {
e18eca43 933 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 934 /* enable PLL when it is used */
9c173d15
AL		 935 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
936 PLL_ENABLE, PLL_ENABLE);
06c71282 937 }
4f9c16cc
DM		 938
939 /* Route Left DAC to left channel input and
940 * right DAC to right channel input */
941 data = (LDAC2LCH | RDAC2RCH);
942 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
943 if (params_rate(params) >= 64000)
944 data |= DUAL_RATE_MODE;
e18eca43 945 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 946
947 /* codec sample rate select */
4f9c16cc
DM		 948 data = (fsref * 20) / params_rate(params);
949 if (params_rate(params) < 64000)
950 data /= 2;
951 data /= 5;
952 data -= 2;
44d0a879 953 data |= (data << 4);
e18eca43 954 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 955
4f9c16cc
DM		 956 if (bypass_pll)
957 return 0;
958
25985edc 959 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 960 * one wins the game. Try with d==0 first, next with d!=0.
961 * Constraints for j are according to the datasheet.
4f9c16cc 962 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 963 */
255173b4 964
4f9c16cc
DM		 965 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
966
967 for (r = 1; r <= 16; r++)
968 for (p = 1; p <= 8; p++) {
255173b4
PM		 969 for (j = 4; j <= 55; j++) {
970 /* This is actually 1000*((j+(d/10000))*r)/p
971 * The term had to be converted to get
972 * rid of the division by 10000; d = 0 here
973 */
5baf8315 974 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 975
976 /* Check whether this values get closer than
977 * the best ones we had before
978 */
5baf8315 979 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 980 abs(codec_clk - last_clk)) {
981 pll_j = j; pll_d = 0;
982 pll_r = r; pll_p = p;
5baf8315 983 last_clk = tmp_clk;
255173b4
PM		 984 }
985
986 /* Early exit for exact matches */
5baf8315 987 if (tmp_clk == codec_clk)
255173b4
PM		 988 goto found;
989 }
990 }
4f9c16cc 991
255173b4
PM		 992 /* try with d != 0 */
993 for (p = 1; p <= 8; p++) {
994 j = codec_clk * p / 1000;
4f9c16cc 995
255173b4
PM		 996 if (j < 4 || j > 11)
997 continue;
4f9c16cc 998
255173b4
PM		 999 /* do not use codec_clk here since we'd loose precision */
1000 d = ((2048 * p * fsref) - j * aic3x->sysclk)
1001 * 100 / (aic3x->sysclk/100);
4f9c16cc 1002
255173b4 1003 clk = (10000 * j + d) / (10 * p);
4f9c16cc 1004
255173b4
PM		 1005 /* check whether this values get closer than the best
1006 * ones we had before */
1007 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1008 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
1009 last_clk = clk;
4f9c16cc
DM		 1010 }
1011
255173b4
PM		 1012 /* Early exit for exact matches */
1013 if (clk == codec_clk)
1014 goto found;
1015 }
1016
4f9c16cc
DM		 1017 if (last_clk == 0) {
1018 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1019 return -EINVAL;
1020 }
44d0a879 1021
255173b4 1022found:
c9fe573a 1023 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
e18eca43
JN		 1024 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1025 pll_r << PLLR_SHIFT);
1026 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1027 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
1028 (pll_d >> 6) << PLLD_MSB_SHIFT);
1029 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
1030 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 1031
44d0a879
VB		 1032 return 0;
1033}
1034
36849409
PU		 1035static int aic3x_prepare(struct snd_pcm_substream *substream,
1036 struct snd_soc_dai *dai)
1037{
1038 struct snd_soc_codec *codec = dai->codec;
1039 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1040 int delay = 0;
1041
1042 /* TDM slot selection only valid in DSP_A/_B mode */
1043 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
1044 delay += (aic3x->tdm_delay + 1);
1045 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
1046 delay += aic3x->tdm_delay;
1047
1048 /* Configure data delay */
1049 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, aic3x->tdm_delay);
1050
1051 return 0;
1052}
1053
e550e17f 1054static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 1055{
1056 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 1057 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
1058 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 1059
1060 if (mute) {
e18eca43
JN		 1061 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1062 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 1063 } else {
e18eca43
JN		 1064 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1065 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 1066 }
1067
1068 return 0;
1069}
1070
e550e17f 1071static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1072 int clk_id, unsigned int freq, int dir)
1073{
1074 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1075 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1076
a1f34af0
JP		 1077 /* set clock on MCLK or GPIO2 or BCLK */
1078 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1079 clk_id << PLLCLK_IN_SHIFT);
1080 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1081 clk_id << CLKDIV_IN_SHIFT);
1082
4f9c16cc
DM		 1083 aic3x->sysclk = freq;
1084 return 0;
44d0a879
VB		 1085}
1086
e550e17f 1087static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1088 unsigned int fmt)
1089{
1090 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1091 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14
JN		 1092 u8 iface_areg, iface_breg;
1093
e18eca43
JN		 1094 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1095 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1096
1097 /* set master/slave audio interface */
1098 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1099 case SND_SOC_DAIFMT_CBM_CFM:
1100 aic3x->master = 1;
1101 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1102 break;
1103 case SND_SOC_DAIFMT_CBS_CFS:
1104 aic3x->master = 0;
68e47981 1105 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
44d0a879
VB		 1106 break;
1107 default:
1108 return -EINVAL;
1109 }
1110
4b7d2831
JN		 1111 /*
1112 * match both interface format and signal polarities since they
1113 * are fixed
1114 */
1115 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1116 SND_SOC_DAIFMT_INV_MASK)) {
1117 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1118 break;
a24f4f68 1119 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
4b7d2831 1120 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1121 iface_breg |= (0x01 << 6);
1122 break;
4b7d2831 1123 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1124 iface_breg |= (0x02 << 6);
1125 break;
4b7d2831 1126 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1127 iface_breg |= (0x03 << 6);
1128 break;
1129 default:
1130 return -EINVAL;
1131 }
1132
36849409
PU		 1133 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1134
44d0a879 1135 /* set iface */
e18eca43
JN		 1136 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1137 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
36849409
PU		 1138
1139 return 0;
1140}
1141
1142static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
1143 unsigned int tx_mask, unsigned int rx_mask,
1144 int slots, int slot_width)
1145{
1146 struct snd_soc_codec *codec = codec_dai->codec;
1147 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1148 unsigned int lsb;
1149
1150 if (tx_mask != rx_mask) {
1151 dev_err(codec->dev, "tx and rx masks must be symmetric\n");
1152 return -EINVAL;
1153 }
1154
1155 if (unlikely(!tx_mask)) {
1156 dev_err(codec->dev, "tx and rx masks need to be non 0\n");
1157 return -EINVAL;
1158 }
1159
1160 /* TDM based on DSP mode requires slots to be adjacent */
1161 lsb = __ffs(tx_mask);
1162 if ((lsb + 1) != __fls(tx_mask)) {
1163 dev_err(codec->dev, "Invalid mask, slots must be adjacent\n");
1164 return -EINVAL;
1165 }
1166
1167 aic3x->tdm_delay = lsb * slot_width;
1168
1169 /* DOUT in high-impedance on inactive bit clocks */
1170 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA,
1171 DOUT_TRISTATE, DOUT_TRISTATE);
44d0a879
VB		 1172
1173 return 0;
1174}
1175
5a895f8a
JN		 1176static int aic3x_regulator_event(struct notifier_block *nb,
1177 unsigned long event, void *data)
1178{
1179 struct aic3x_disable_nb *disable_nb =
1180 container_of(nb, struct aic3x_disable_nb, nb);
1181 struct aic3x_priv *aic3x = disable_nb->aic3x;
1182
1183 if (event & REGULATOR_EVENT_DISABLE) {
1184 /*
1185 * Put codec to reset and require cache sync as at least one
1186 * of the supplies was disabled
1187 */
79ee820d 1188 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a 1189 gpio_set_value(aic3x->gpio_reset, 0);
2a6fedec 1190 regcache_mark_dirty(aic3x->regmap);
5a895f8a
JN		 1191 }
1192
1193 return 0;
1194}
1195
6c1a7d40
JN		 1196static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1197{
1198 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
31d9f8fa 1199 unsigned int pll_c, pll_d;
2a6fedec 1200 int ret;
6c1a7d40
JN		 1201
1202 if (power) {
1203 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1204 aic3x->supplies);
1205 if (ret)
1206 goto out;
1207 aic3x->power = 1;
5a895f8a 1208
79ee820d 1209 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1210 udelay(1);
1211 gpio_set_value(aic3x->gpio_reset, 1);
1212 }
1213
1214 /* Sync reg_cache with the hardware */
2a6fedec
MB		 1215 regcache_cache_only(aic3x->regmap, false);
1216 regcache_sync(aic3x->regmap);
31d9f8fa
DL		 1217
1218 /* Rewrite paired PLL D registers in case cached sync skipped
1219 * writing one of them and thus caused other one also not
1220 * being written
1221 */
1222 pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG);
1223 pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG);
1224 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1225 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1226 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c);
1227 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d);
1228 }
6c1a7d40 1229 } else {
9fb352b1
JN		 1230 /*
1231 * Do soft reset to this codec instance in order to clear
1232 * possible VDD leakage currents in case the supply regulators
1233 * remain on
1234 */
1235 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
2a6fedec 1236 regcache_mark_dirty(aic3x->regmap);
6c1a7d40 1237 aic3x->power = 0;
5a895f8a 1238 /* HW writes are needless when bias is off */
2a6fedec 1239 regcache_cache_only(aic3x->regmap, true);
6c1a7d40
JN		 1240 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1241 aic3x->supplies);
1242 }
1243out:
1244 return ret;
1245}
1246
0be9898a
MB		 1247static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1248 enum snd_soc_bias_level level)
44d0a879 1249{
b2c812e2 1250 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1251
0be9898a
MB		 1252 switch (level) {
1253 case SND_SOC_BIAS_ON:
db13802e
JN		 1254 break;
1255 case SND_SOC_BIAS_PREPARE:
ce6120cc 1256 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1257 aic3x->master) {
44d0a879 1258 /* enable pll */
9c173d15
AL		 1259 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1260 PLL_ENABLE, PLL_ENABLE);
44d0a879
VB		 1261 }
1262 break;
0be9898a 1263 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1264 if (!aic3x->power)
1265 aic3x_set_power(codec, 1);
ce6120cc 1266 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1267 aic3x->master) {
44d0a879 1268 /* disable pll */
9c173d15
AL		 1269 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1270 PLL_ENABLE, 0);
44d0a879
VB		 1271 }
1272 break;
c23fd751 1273 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1274 if (aic3x->power)
1275 aic3x_set_power(codec, 0);
c23fd751 1276 break;
44d0a879 1277 }
ce6120cc 1278 codec->dapm.bias_level = level;
44d0a879
VB		 1279
1280 return 0;
1281}
1282
1283#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1284#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2a11a10a
PU		 1285 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1286 SNDRV_PCM_FMTBIT_S32_LE)
44d0a879 1287
85e7652d 1288static const struct snd_soc_dai_ops aic3x_dai_ops = {
6335d055 1289 .hw_params = aic3x_hw_params,
36849409 1290 .prepare = aic3x_prepare,
6335d055
EM		 1291 .digital_mute = aic3x_mute,
1292 .set_sysclk = aic3x_set_dai_sysclk,
1293 .set_fmt = aic3x_set_dai_fmt,
36849409 1294 .set_tdm_slot = aic3x_set_dai_tdm_slot,
6335d055
EM		 1295};
1296
f0fba2ad
LG		 1297static struct snd_soc_dai_driver aic3x_dai = {
1298 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1299 .playback = {
1300 .stream_name = "Playback",
06378da4 1301 .channels_min = 2,
44d0a879
VB		 1302 .channels_max = 2,
1303 .rates = AIC3X_RATES,
1304 .formats = AIC3X_FORMATS,},
1305 .capture = {
1306 .stream_name = "Capture",
06378da4 1307 .channels_min = 2,
44d0a879
VB		 1308 .channels_max = 2,
1309 .rates = AIC3X_RATES,
1310 .formats = AIC3X_FORMATS,},
6335d055 1311 .ops = &aic3x_dai_ops,
14017615 1312 .symmetric_rates = 1,
44d0a879 1313};
44d0a879 1314
58381da6
JW		 1315static void aic3x_mono_init(struct snd_soc_codec *codec)
1316{
1317 /* DAC to Mono Line Out default volume and route to Output mixer */
1318 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1319 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1320
1321 /* unmute all outputs */
1322 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1323
1324 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1325 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1326 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1327
1328 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1329 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1330 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1331}
1332
44d0a879
VB		 1333/*
1334 * initialise the AIC3X driver
1335 * register the mixer and dsp interfaces with the kernel
1336 */
cb3826f5 1337static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1338{
6184f105 1339 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5 1340
e18eca43
JN		 1341 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1342 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1343
44d0a879 1344 /* DAC default volume and mute */
e18eca43
JN		 1345 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1346 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1347
1348 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1349 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1350 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1351 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1352 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1353 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1354 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1355 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1356
1357 /* unmute all outputs */
9c173d15
AL		 1358 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1359 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
9c173d15
AL		 1360 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1361 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1362 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1363 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
44d0a879
VB		 1364
1365 /* ADC default volume and unmute */
e18eca43
JN		 1366 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1367 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1368 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1369 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1370 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1371
1372 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1373 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1374 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1375 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1376 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1377 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1378 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1379 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1380
1381 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1382 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1383 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1384 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1385 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1386 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1387 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1388 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1389
58381da6
JW		 1390 switch (aic3x->model) {
1391 case AIC3X_MODEL_3X:
1392 case AIC3X_MODEL_33:
1393 aic3x_mono_init(codec);
1394 break;
1395 case AIC3X_MODEL_3007:
e18eca43 1396 snd_soc_write(codec, CLASSD_CTRL, 0);
58381da6 1397 break;
6184f105
RC		 1398 }
1399
cb3826f5
BD		 1400 return 0;
1401}
54e7e616 1402
414c73ab
JN		 1403static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1404{
1405 struct aic3x_priv *a;
1406
1407 list_for_each_entry(a, &reset_list, list) {
1408 if (gpio_is_valid(aic3x->gpio_reset) &&
1409 aic3x->gpio_reset == a->gpio_reset)
1410 return true;
1411 }
1412
1413 return false;
1414}
1415
f0fba2ad 1416static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1417{
f0fba2ad 1418 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1419 int ret, i;
f0fba2ad 1420
414c73ab 1421 INIT_LIST_HEAD(&aic3x->list);
5a895f8a 1422 aic3x->codec = codec;
cb3826f5 1423
5a895f8a
JN		 1424 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1425 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1426 aic3x->disable_nb[i].aic3x = aic3x;
1427 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1428 &aic3x->disable_nb[i].nb);
1429 if (ret) {
1430 dev_err(codec->dev,
1431 "Failed to request regulator notifier: %d\n",
1432 ret);
1433 goto err_notif;
1434 }
1435 }
2f24111a 1436
2a6fedec 1437 regcache_mark_dirty(aic3x->regmap);
37b47656
JN		 1438 aic3x_init(codec);
1439
f0fba2ad
LG		 1440 if (aic3x->setup) {
1441 /* setup GPIO functions */
e18eca43
JN		 1442 snd_soc_write(codec, AIC3X_GPIO1_REG,
1443 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1444 snd_soc_write(codec, AIC3X_GPIO2_REG,
1445 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1446 }
1447
58381da6
JW		 1448 switch (aic3x->model) {
1449 case AIC3X_MODEL_3X:
1450 case AIC3X_MODEL_33:
1451 snd_soc_add_codec_controls(codec, aic3x_mono_controls,
1452 ARRAY_SIZE(aic3x_mono_controls));
1453 break;
1454 case AIC3X_MODEL_3007:
1455 snd_soc_add_codec_controls(codec,
1456 &aic3x_classd_amp_gain_ctrl, 1);
1457 break;
1458 }
cb3826f5 1459
e2e8bfdf
HG		 1460 /* set mic bias voltage */
1461 switch (aic3x->micbias_vg) {
1462 case AIC3X_MICBIAS_2_0V:
1463 case AIC3X_MICBIAS_2_5V:
1464 case AIC3X_MICBIAS_AVDDV:
1465 snd_soc_update_bits(codec, MICBIAS_CTRL,
1466 MICBIAS_LEVEL_MASK,
1467 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1468 break;
1469 case AIC3X_MICBIAS_OFF:
1470 /*
1471 * noting to do. target won't enter here. This is just to avoid
1472 * compile time warning "warning: enumeration value
1473 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1474 */
1475 break;
1476 }
1477
f0fba2ad 1478 aic3x_add_widgets(codec);
cb3826f5
BD		 1479
1480 return 0;
2f24111a 1481
5a895f8a
JN		 1482err_notif:
1483 while (i--)
1484 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1485 &aic3x->disable_nb[i].nb);
2f24111a 1486 return ret;
44d0a879
VB		 1487}
1488
f0fba2ad 1489static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1490{
2f24111a 1491 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1492 int i;
2f24111a 1493
414c73ab 1494 list_del(&aic3x->list);
5a895f8a
JN		 1495 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1496 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1497 &aic3x->disable_nb[i].nb);
2f24111a 1498
cb3826f5
BD		 1499 return 0;
1500}
44d0a879 1501
f0fba2ad 1502static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad 1503 .set_bias_level = aic3x_set_bias_level,
eb3032f8 1504 .idle_bias_off = true,
f0fba2ad
LG		 1505 .probe = aic3x_probe,
1506 .remove = aic3x_remove,
f9df1ae6
MB		 1507 .controls = aic3x_snd_controls,
1508 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
58a63fbd
MB		 1509 .dapm_widgets = aic3x_dapm_widgets,
1510 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1511 .dapm_routes = intercon,
1512 .num_dapm_routes = ARRAY_SIZE(intercon),
f0fba2ad
LG		 1513};
1514
44d0a879
VB		 1515/*
1516 * AIC3X 2 wire address can be up to 4 devices with device addresses
1517 * 0x18, 0x19, 0x1A, 0x1B
1518 */
44d0a879 1519
6184f105 1520static const struct i2c_device_id aic3x_i2c_id[] = {
177fdd89
AL		 1521 { "tlv320aic3x", AIC3X_MODEL_3X },
1522 { "tlv320aic33", AIC3X_MODEL_33 },
1523 { "tlv320aic3007", AIC3X_MODEL_3007 },
cbaa5689 1524 { "tlv320aic3106", AIC3X_MODEL_3X },
6184f105
RC		 1525 { }
1526};
1527MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1528
2a6fedec
MB		 1529static const struct reg_default aic3007_class_d[] = {
1530 /* Class-D speaker driver init; datasheet p. 46 */
1531 { AIC3X_PAGE_SELECT, 0x0D },
1532 { 0xD, 0x0D },
1533 { 0x8, 0x5C },
1534 { 0x8, 0x5D },
1535 { 0x8, 0x5C },
1536 { AIC3X_PAGE_SELECT, 0x00 },
1537};
1538
44d0a879
VB		 1539/*
1540 * If the i2c layer weren't so broken, we could pass this kind of data
1541 * around
1542 */
ba8ed121
JD		 1543static int aic3x_i2c_probe(struct i2c_client *i2c,
1544 const struct i2c_device_id *id)
44d0a879 1545{
5193d62f 1546 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1547 struct aic3x_priv *aic3x;
c24fdc88
HG		 1548 struct aic3x_setup_data *ai3x_setup;
1549 struct device_node *np = i2c->dev.of_node;
6f818e04 1550 int ret, i;
e2e8bfdf 1551 u32 value;
44d0a879 1552
e2257db3 1553 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
b1117f52 1554 if (!aic3x)
cb3826f5 1555 return -ENOMEM;
cb3826f5 1556
2a6fedec
MB		 1557 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1558 if (IS_ERR(aic3x->regmap)) {
1559 ret = PTR_ERR(aic3x->regmap);
1560 return ret;
1561 }
1562
1563 regcache_cache_only(aic3x->regmap, true);
a84a441b 1564
cb3826f5 1565 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1566 if (pdata) {
1567 aic3x->gpio_reset = pdata->gpio_reset;
1568 aic3x->setup = pdata->setup;
e2e8bfdf 1569 aic3x->micbias_vg = pdata->micbias_vg;
c24fdc88
HG		 1570 } else if (np) {
1571 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1572 GFP_KERNEL);
b1117f52 1573 if (!ai3x_setup)
c24fdc88 1574 return -ENOMEM;
c24fdc88
HG		 1575
1576 ret = of_get_named_gpio(np, "gpio-reset", 0);
1577 if (ret >= 0)
1578 aic3x->gpio_reset = ret;
1579 else
1580 aic3x->gpio_reset = -1;
1581
1582 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1583 ai3x_setup->gpio_func, 2) >= 0) {
1584 aic3x->setup = ai3x_setup;
1585 }
1586
e2e8bfdf
HG		 1587 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1588 switch (value) {
1589 case 1 :
1590 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1591 break;
1592 case 2 :
1593 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1594 break;
1595 case 3 :
1596 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1597 break;
1598 default :
1599 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1600 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1601 "found in DT\n");
1602 }
1603 } else {
1604 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1605 }
1606
c776357e
JN		 1607 } else {
1608 aic3x->gpio_reset = -1;
1609 }
cb3826f5 1610
177fdd89 1611 aic3x->model = id->driver_data;
6184f105 1612
6f818e04
MB		 1613 if (gpio_is_valid(aic3x->gpio_reset) &&
1614 !aic3x_is_shared_reset(aic3x)) {
1615 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1616 if (ret != 0)
1617 goto err;
1618 gpio_direction_output(aic3x->gpio_reset, 0);
1619 }
1620
1621 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1622 aic3x->supplies[i].supply = aic3x_supply_names[i];
1623
1624 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1625 aic3x->supplies);
1626 if (ret != 0) {
1627 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1628 goto err_gpio;
1629 }
1630
2a6fedec
MB		 1631 if (aic3x->model == AIC3X_MODEL_3007) {
1632 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1633 ARRAY_SIZE(aic3007_class_d));
1634 if (ret != 0)
1635 dev_err(&i2c->dev, "Failed to init class D: %d\n",
1636 ret);
1637 }
1638
f0fba2ad
LG		 1639 ret = snd_soc_register_codec(&i2c->dev,
1640 &soc_codec_dev_aic3x, &aic3x_dai, 1);
3b5b2431
SR		 1641
1642 if (ret != 0)
1643 goto err_gpio;
1644
1645 list_add(&aic3x->list, &reset_list);
1646
1647 return 0;
6f818e04
MB		 1648
1649err_gpio:
1650 if (gpio_is_valid(aic3x->gpio_reset) &&
1651 !aic3x_is_shared_reset(aic3x))
1652 gpio_free(aic3x->gpio_reset);
1653err:
1654 return ret;
44d0a879
VB		 1655}
1656
ba8ed121 1657static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1658{
6f818e04
MB		 1659 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1660
f0fba2ad 1661 snd_soc_unregister_codec(&client->dev);
6f818e04
MB		 1662 if (gpio_is_valid(aic3x->gpio_reset) &&
1663 !aic3x_is_shared_reset(aic3x)) {
1664 gpio_set_value(aic3x->gpio_reset, 0);
1665 gpio_free(aic3x->gpio_reset);
1666 }
f0fba2ad 1667 return 0;
44d0a879
VB		 1668}
1669
c24fdc88
HG		 1670#if defined(CONFIG_OF)
1671static const struct of_device_id tlv320aic3x_of_match[] = {
1672 { .compatible = "ti,tlv320aic3x", },
f2c4fa65
MB		 1673 { .compatible = "ti,tlv320aic33" },
1674 { .compatible = "ti,tlv320aic3007" },
cbaa5689 1675 { .compatible = "ti,tlv320aic3106" },
c24fdc88
HG		 1676 {},
1677};
1678MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1679#endif
1680
44d0a879
VB		 1681/* machine i2c codec control layer */
1682static struct i2c_driver aic3x_i2c_driver = {
1683 .driver = {
f0fba2ad 1684 .name = "tlv320aic3x-codec",
44d0a879 1685 .owner = THIS_MODULE,
c24fdc88 1686 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
44d0a879 1687 },
cb3826f5 1688 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1689 .remove = aic3x_i2c_remove,
1690 .id_table = aic3x_i2c_id,
44d0a879 1691};
44d0a879 1692
fd39d14b 1693module_i2c_driver(aic3x_i2c_driver);
64089b84 1694
44d0a879
VB		 1695MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1696MODULE_AUTHOR("Vladimir Barinov");
1697MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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