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ASoC: improve I2C initialization code in CS4270 driver
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
41#include <linux/platform_device.h>
44d0a879
VB		 42#include <sound/core.h>
43#include <sound/pcm.h>
44#include <sound/pcm_params.h>
45#include <sound/soc.h>
46#include <sound/soc-dapm.h>
47#include <sound/initval.h>
48
49#include "tlv320aic3x.h"
50
4f9c16cc 51#define AIC3X_VERSION "0.2"
44d0a879
VB		 52
53/* codec private data */
54struct aic3x_priv {
55 unsigned int sysclk;
56 int master;
57};
58
59/*
60 * AIC3X register cache
61 * We can't read the AIC3X register space when we are
62 * using 2 wire for device control, so we cache them instead.
63 * There is no point in caching the reset register
64 */
65static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
66 0x00, 0x00, 0x00, 0x10, /* 0 */
67 0x04, 0x00, 0x00, 0x00, /* 4 */
68 0x00, 0x00, 0x00, 0x01, /* 8 */
69 0x00, 0x00, 0x00, 0x80, /* 12 */
70 0x80, 0xff, 0xff, 0x78, /* 16 */
71 0x78, 0x78, 0x78, 0x78, /* 20 */
72 0x78, 0x00, 0x00, 0xfe, /* 24 */
73 0x00, 0x00, 0xfe, 0x00, /* 28 */
74 0x18, 0x18, 0x00, 0x00, /* 32 */
75 0x00, 0x00, 0x00, 0x00, /* 36 */
76 0x00, 0x00, 0x00, 0x80, /* 40 */
77 0x80, 0x00, 0x00, 0x00, /* 44 */
78 0x00, 0x00, 0x00, 0x04, /* 48 */
79 0x00, 0x00, 0x00, 0x00, /* 52 */
80 0x00, 0x00, 0x04, 0x00, /* 56 */
81 0x00, 0x00, 0x00, 0x00, /* 60 */
82 0x00, 0x04, 0x00, 0x00, /* 64 */
83 0x00, 0x00, 0x00, 0x00, /* 68 */
84 0x04, 0x00, 0x00, 0x00, /* 72 */
85 0x00, 0x00, 0x00, 0x00, /* 76 */
86 0x00, 0x00, 0x00, 0x00, /* 80 */
87 0x00, 0x00, 0x00, 0x00, /* 84 */
88 0x00, 0x00, 0x00, 0x00, /* 88 */
89 0x00, 0x00, 0x00, 0x00, /* 92 */
90 0x00, 0x00, 0x00, 0x00, /* 96 */
91 0x00, 0x00, 0x02, /* 100 */
92};
93
94/*
95 * read aic3x register cache
96 */
97static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
98 unsigned int reg)
99{
100 u8 *cache = codec->reg_cache;
101 if (reg >= AIC3X_CACHEREGNUM)
102 return -1;
103 return cache[reg];
104}
105
106/*
107 * write aic3x register cache
108 */
109static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
110 u8 reg, u8 value)
111{
112 u8 *cache = codec->reg_cache;
113 if (reg >= AIC3X_CACHEREGNUM)
114 return;
115 cache[reg] = value;
116}
117
118/*
119 * write to the aic3x register space
120 */
121static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
122 unsigned int value)
123{
124 u8 data[2];
125
126 /* data is
127 * D15..D8 aic3x register offset
128 * D7...D0 register data
129 */
130 data[0] = reg & 0xff;
131 data[1] = value & 0xff;
132
133 aic3x_write_reg_cache(codec, data[0], data[1]);
134 if (codec->hw_write(codec->control_data, data, 2) == 2)
135 return 0;
136 else
137 return -EIO;
138}
139
54e7e616
DM		 140/*
141 * read from the aic3x register space
142 */
143static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
144 u8 *value)
145{
146 *value = reg & 0xff;
147 if (codec->hw_read(codec->control_data, value, 1) != 1)
148 return -EIO;
149
150 aic3x_write_reg_cache(codec, reg, *value);
151 return 0;
152}
153
44d0a879
VB		 154#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
155{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
156 .info = snd_soc_info_volsw, \
157 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
158 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
159
160/*
161 * All input lines are connected when !0xf and disconnected with 0xf bit field,
162 * so we have to use specific dapm_put call for input mixer
163 */
164static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
165 struct snd_ctl_elem_value *ucontrol)
166{
167 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
168 int reg = kcontrol->private_value & 0xff;
169 int shift = (kcontrol->private_value >> 8) & 0x0f;
170 int mask = (kcontrol->private_value >> 16) & 0xff;
171 int invert = (kcontrol->private_value >> 24) & 0x01;
172 unsigned short val, val_mask;
173 int ret;
174 struct snd_soc_dapm_path *path;
175 int found = 0;
176
177 val = (ucontrol->value.integer.value[0] & mask);
178
179 mask = 0xf;
180 if (val)
181 val = mask;
182
183 if (invert)
184 val = mask - val;
185 val_mask = mask << shift;
186 val = val << shift;
187
188 mutex_lock(&widget->codec->mutex);
189
190 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
191 /* find dapm widget path assoc with kcontrol */
192 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
193 if (path->kcontrol != kcontrol)
194 continue;
195
196 /* found, now check type */
197 found = 1;
198 if (val)
199 /* new connection */
200 path->connect = invert ? 0 : 1;
201 else
202 /* old connection must be powered down */
203 path->connect = invert ? 1 : 0;
204 break;
205 }
206
207 if (found)
a5302181 208 snd_soc_dapm_sync(widget->codec);
44d0a879
VB		 209 }
210
211 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
212
213 mutex_unlock(&widget->codec->mutex);
214 return ret;
215}
216
217static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
218static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
219static const char *aic3x_left_hpcom_mux[] =
220 { "differential of HPLOUT", "constant VCM", "single-ended" };
221static const char *aic3x_right_hpcom_mux[] =
222 { "differential of HPROUT", "constant VCM", "single-ended",
223 "differential of HPLCOM", "external feedback" };
224static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 225static const char *aic3x_adc_hpf[] =
226 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 227
228#define LDAC_ENUM 0
229#define RDAC_ENUM 1
230#define LHPCOM_ENUM 2
231#define RHPCOM_ENUM 3
232#define LINE1L_ENUM 4
233#define LINE1R_ENUM 5
234#define LINE2L_ENUM 6
235#define LINE2R_ENUM 7
4d20f70a 236#define ADC_HPF_ENUM 8
44d0a879
VB		 237
238static const struct soc_enum aic3x_enum[] = {
239 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
240 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
241 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
242 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
243 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
244 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
245 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
246 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 247 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 248};
249
250static const struct snd_kcontrol_new aic3x_snd_controls[] = {
251 /* Output */
252 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1),
253
254 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL,
255 DACR1_2_RLOPM_VOL, 0, 0x7f, 1),
28a1d869
DM		 256 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
257 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
258 SOC_DOUBLE_R("LineL DAC Playback Volume", DACL1_2_LLOPM_VOL,
259 DACR1_2_LLOPM_VOL, 0, 0x7f, 1),
260 SOC_SINGLE("LineL Left PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL,
261 0, 0x7f, 1),
262 SOC_SINGLE("LineR Right PGA Bypass Playback Volume", PGAR_2_RLOPM_VOL,
263 0, 0x7f, 1),
264 SOC_DOUBLE_R("LineL Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL,
265 LINE2R_2_LLOPM_VOL, 0, 0x7f, 1),
266 SOC_DOUBLE_R("LineR Line2 Bypass Playback Volume", LINE2L_2_RLOPM_VOL,
44d0a879
VB		 267 LINE2R_2_RLOPM_VOL, 0, 0x7f, 1),
268
269 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL,
270 DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1),
271 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
272 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL,
273 PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1),
274 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL,
275 LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1),
276
277 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL,
278 DACR1_2_HPROUT_VOL, 0, 0x7f, 1),
279 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
280 0x01, 0),
28a1d869
DM		 281 SOC_DOUBLE_R("HP Right PGA Bypass Playback Volume", PGAR_2_HPLOUT_VOL,
282 PGAR_2_HPROUT_VOL, 0, 0x7f, 1),
54f01916
DM		 283 SOC_SINGLE("HPL PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL,
284 0, 0x7f, 1),
285 SOC_SINGLE("HPR PGA Bypass Playback Volume", PGAL_2_HPROUT_VOL,
286 0, 0x7f, 1),
44d0a879
VB		 287 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL,
288 LINE2R_2_HPROUT_VOL, 0, 0x7f, 1),
289
290 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL,
291 DACR1_2_HPRCOM_VOL, 0, 0x7f, 1),
292 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
293 0x01, 0),
54f01916
DM		 294 SOC_SINGLE("HPLCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL,
295 0, 0x7f, 1),
296 SOC_SINGLE("HPRCOM PGA Bypass Playback Volume", PGAL_2_HPRCOM_VOL,
297 0, 0x7f, 1),
44d0a879
VB		 298 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL,
299 LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1),
300
301 /*
302 * Note: enable Automatic input Gain Controller with care. It can
303 * adjust PGA to max value when ADC is on and will never go back.
304 */
305 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
306
307 /* Input */
308 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0),
309 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 310
311 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 312};
313
44d0a879
VB		 314/* Left DAC Mux */
315static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
316SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
317
318/* Right DAC Mux */
319static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
320SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
321
322/* Left HPCOM Mux */
323static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
324SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
325
326/* Right HPCOM Mux */
327static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
328SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
329
330/* Left DAC_L1 Mixer */
331static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
54f01916
DM		 332 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
333 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 334 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
335 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
336 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
337};
338
339/* Right DAC_R1 Mixer */
340static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
54f01916
DM		 341 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
342 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 343 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
344 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
345 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
346};
347
348/* Left PGA Mixer */
349static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
350 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 351 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 352 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
353 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 354 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 355};
356
357/* Right PGA Mixer */
358static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
359 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 360 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 361 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 362 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 363 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
364};
365
366/* Left Line1 Mux */
367static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
368SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
369
370/* Right Line1 Mux */
371static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
372SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
373
374/* Left Line2 Mux */
375static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
376SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
377
378/* Right Line2 Mux */
379static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
380SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
381
382/* Left PGA Bypass Mixer */
383static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
54f01916
DM		 384 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
385 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
44d0a879 386 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
54f01916
DM		 387 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
388 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
389 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
390 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 391};
392
393/* Right PGA Bypass Mixer */
394static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
54f01916
DM		 395 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
396 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
44d0a879 397 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
54f01916
DM		 398 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
399 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
400 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
401 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 402};
403
404/* Left Line2 Bypass Mixer */
405static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
54f01916
DM		 406 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 408 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
409 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
54f01916 410 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
44d0a879
VB		 411};
412
413/* Right Line2 Bypass Mixer */
414static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
54f01916
DM		 415 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 417 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
54f01916 419 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 420};
421
422static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
423 /* Left DAC to Left Outputs */
424 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
425 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
426 &aic3x_left_dac_mux_controls),
427 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
428 &aic3x_left_dac_mixer_controls[0],
429 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
430 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
431 &aic3x_left_hpcom_mux_controls),
432 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
433 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
434 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
435
436 /* Right DAC to Right Outputs */
437 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
438 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
439 &aic3x_right_dac_mux_controls),
440 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
441 &aic3x_right_dac_mixer_controls[0],
442 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
443 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
444 &aic3x_right_hpcom_mux_controls),
445 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
446 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
447 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
448
449 /* Mono Output */
450 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
451
54f01916 452 /* Inputs to Left ADC */
44d0a879
VB		 453 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
454 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
455 &aic3x_left_pga_mixer_controls[0],
456 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
457 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
458 &aic3x_left_line1_mux_controls),
54f01916
DM		 459 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
460 &aic3x_left_line1_mux_controls),
44d0a879
VB		 461 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
462 &aic3x_left_line2_mux_controls),
463
54f01916 464 /* Inputs to Right ADC */
44d0a879
VB		 465 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
466 LINE1R_2_RADC_CTRL, 2, 0),
467 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
468 &aic3x_right_pga_mixer_controls[0],
469 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 470 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
471 &aic3x_right_line1_mux_controls),
44d0a879
VB		 472 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
473 &aic3x_right_line1_mux_controls),
474 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
475 &aic3x_right_line2_mux_controls),
476
ee15ffdb
JN		 477 /*
478 * Not a real mic bias widget but similar function. This is for dynamic
479 * control of GPIO1 digital mic modulator clock output function when
480 * using digital mic.
481 */
482 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
483 AIC3X_GPIO1_REG, 4, 0xf,
484 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
485 AIC3X_GPIO1_FUNC_DISABLED),
486
487 /*
488 * Also similar function like mic bias. Selects digital mic with
489 * configurable oversampling rate instead of ADC converter.
490 */
491 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
492 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
493 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
494 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
495 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
496 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
497
44d0a879 498 /* Mic Bias */
0bd72a3d
JN		 499 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
500 MICBIAS_CTRL, 6, 3, 1, 0),
501 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
502 MICBIAS_CTRL, 6, 3, 2, 0),
503 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
504 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879
VB		 505
506 /* Left PGA to Left Output bypass */
507 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
508 &aic3x_left_pga_bp_mixer_controls[0],
509 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
510
511 /* Right PGA to Right Output bypass */
512 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
513 &aic3x_right_pga_bp_mixer_controls[0],
514 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
515
516 /* Left Line2 to Left Output bypass */
517 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
518 &aic3x_left_line2_bp_mixer_controls[0],
519 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
520
521 /* Right Line2 to Right Output bypass */
522 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
523 &aic3x_right_line2_bp_mixer_controls[0],
524 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
525
526 SND_SOC_DAPM_OUTPUT("LLOUT"),
527 SND_SOC_DAPM_OUTPUT("RLOUT"),
528 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
529 SND_SOC_DAPM_OUTPUT("HPLOUT"),
530 SND_SOC_DAPM_OUTPUT("HPROUT"),
531 SND_SOC_DAPM_OUTPUT("HPLCOM"),
532 SND_SOC_DAPM_OUTPUT("HPRCOM"),
533
534 SND_SOC_DAPM_INPUT("MIC3L"),
535 SND_SOC_DAPM_INPUT("MIC3R"),
536 SND_SOC_DAPM_INPUT("LINE1L"),
537 SND_SOC_DAPM_INPUT("LINE1R"),
538 SND_SOC_DAPM_INPUT("LINE2L"),
539 SND_SOC_DAPM_INPUT("LINE2R"),
540};
541
d0cc0d3a 542static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 543 /* Left Output */
544 {"Left DAC Mux", "DAC_L1", "Left DAC"},
545 {"Left DAC Mux", "DAC_L2", "Left DAC"},
546 {"Left DAC Mux", "DAC_L3", "Left DAC"},
547
54f01916
DM		 548 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
549 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
44d0a879
VB		 550 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
551 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
552 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
553 {"Left Line Out", NULL, "Left DAC Mux"},
554 {"Left HP Out", NULL, "Left DAC Mux"},
555
556 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
557 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
558 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
559
560 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
561 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
562 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
563 {"Left HP Com", NULL, "Left HPCOM Mux"},
564
565 {"LLOUT", NULL, "Left Line Out"},
566 {"LLOUT", NULL, "Left Line Out"},
567 {"HPLOUT", NULL, "Left HP Out"},
568 {"HPLCOM", NULL, "Left HP Com"},
569
570 /* Right Output */
571 {"Right DAC Mux", "DAC_R1", "Right DAC"},
572 {"Right DAC Mux", "DAC_R2", "Right DAC"},
573 {"Right DAC Mux", "DAC_R3", "Right DAC"},
574
54f01916
DM		 575 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
576 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
44d0a879
VB		 577 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
578 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
579 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
580 {"Right Line Out", NULL, "Right DAC Mux"},
581 {"Right HP Out", NULL, "Right DAC Mux"},
582
583 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
584 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
585 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
586 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
587 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
588
589 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
590 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
591 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
592 {"Right HP Com", NULL, "Right HPCOM Mux"},
593
594 {"RLOUT", NULL, "Right Line Out"},
595 {"RLOUT", NULL, "Right Line Out"},
596 {"HPROUT", NULL, "Right HP Out"},
597 {"HPRCOM", NULL, "Right HP Com"},
598
599 /* Mono Output */
5b006137
JN		 600 {"MONO_LOUT", NULL, "Mono Out"},
601 {"MONO_LOUT", NULL, "Mono Out"},
44d0a879
VB		 602
603 /* Left Input */
604 {"Left Line1L Mux", "single-ended", "LINE1L"},
605 {"Left Line1L Mux", "differential", "LINE1L"},
606
607 {"Left Line2L Mux", "single-ended", "LINE2L"},
608 {"Left Line2L Mux", "differential", "LINE2L"},
609
610 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 611 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 612 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
613 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 614 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 615
616 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 617 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 618
619 /* Right Input */
620 {"Right Line1R Mux", "single-ended", "LINE1R"},
621 {"Right Line1R Mux", "differential", "LINE1R"},
622
623 {"Right Line2R Mux", "single-ended", "LINE2R"},
624 {"Right Line2R Mux", "differential", "LINE2R"},
625
54f01916 626 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 627 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
628 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 629 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 630 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
631
632 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 633 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 634
635 /* Left PGA Bypass */
54f01916
DM		 636 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
637 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
44d0a879 638 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
54f01916
DM		 639 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
640 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
641 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
642 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
44d0a879
VB		 643
644 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
645 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
646 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
647
648 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
649 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
650 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
651
652 /* Right PGA Bypass */
54f01916
DM		 653 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
654 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
44d0a879 655 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
54f01916
DM		 656 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
657 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
658 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
659 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
44d0a879
VB		 660
661 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
662 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
663 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
664 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
665 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
666
667 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
668 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
669 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
670
671 /* Left Line2 Bypass */
54f01916
DM		 672 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
673 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
44d0a879
VB		 674 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
675 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
54f01916 676 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
44d0a879
VB		 677
678 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
679 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
680 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
681
682 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
683 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
684 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
685
686 /* Right Line2 Bypass */
54f01916
DM		 687 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
688 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
44d0a879
VB		 689 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
690 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
54f01916 691 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
44d0a879
VB		 692
693 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
694 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
695 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
696 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
697 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
698
699 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
700 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
701 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
ee15ffdb
JN		 702
703 /*
704 * Logical path between digital mic enable and GPIO1 modulator clock
705 * output function
706 */
707 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
708 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
709 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
44d0a879
VB		 710};
711
712static int aic3x_add_widgets(struct snd_soc_codec *codec)
713{
d0cc0d3a
MB		 714 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
715 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 716
717 /* set up audio path interconnects */
d0cc0d3a 718 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
44d0a879
VB		 719
720 snd_soc_dapm_new_widgets(codec);
721 return 0;
722}
723
44d0a879 724static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 725 struct snd_pcm_hw_params *params,
726 struct snd_soc_dai *dai)
44d0a879
VB		 727{
728 struct snd_soc_pcm_runtime *rtd = substream->private_data;
729 struct snd_soc_device *socdev = rtd->socdev;
730 struct snd_soc_codec *codec = socdev->codec;
731 struct aic3x_priv *aic3x = codec->private_data;
4f9c16cc
DM		 732 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
733 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
734 u16 pll_d = 1;
44d0a879 735
4f9c16cc
DM		 736 /* select data word length */
737 data =
738 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
739 switch (params_format(params)) {
740 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 741 break;
4f9c16cc
DM		 742 case SNDRV_PCM_FORMAT_S20_3LE:
743 data |= (0x01 << 4);
44d0a879 744 break;
4f9c16cc
DM		 745 case SNDRV_PCM_FORMAT_S24_LE:
746 data |= (0x02 << 4);
44d0a879 747 break;
4f9c16cc
DM		 748 case SNDRV_PCM_FORMAT_S32_LE:
749 data |= (0x03 << 4);
44d0a879
VB		 750 break;
751 }
4f9c16cc
DM		 752 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
753
754 /* Fsref can be 44100 or 48000 */
755 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
756
757 /* Try to find a value for Q which allows us to bypass the PLL and
758 * generate CODEC_CLK directly. */
759 for (pll_q = 2; pll_q < 18; pll_q++)
760 if (aic3x->sysclk / (128 * pll_q) == fsref) {
761 bypass_pll = 1;
762 break;
763 }
764
765 if (bypass_pll) {
766 pll_q &= 0xf;
767 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
768 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
769 } else
770 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
771
772 /* Route Left DAC to left channel input and
773 * right DAC to right channel input */
774 data = (LDAC2LCH | RDAC2RCH);
775 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
776 if (params_rate(params) >= 64000)
777 data |= DUAL_RATE_MODE;
44d0a879
VB		 778 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
779
780 /* codec sample rate select */
4f9c16cc
DM		 781 data = (fsref * 20) / params_rate(params);
782 if (params_rate(params) < 64000)
783 data /= 2;
784 data /= 5;
785 data -= 2;
44d0a879
VB		 786 data |= (data << 4);
787 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
788
4f9c16cc
DM		 789 if (bypass_pll)
790 return 0;
791
792 /* Use PLL
793 * find an apropriate setup for j, d, r and p by iterating over
794 * p and r - j and d are calculated for each fraction.
795 * Up to 128 values are probed, the closest one wins the game.
796 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 797 */
4f9c16cc
DM		 798 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
799
800 for (r = 1; r <= 16; r++)
801 for (p = 1; p <= 8; p++) {
802 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
803 u8 j = tmp / 10000;
804 u16 d = tmp % 10000;
805
806 if (j > 63)
807 continue;
808
809 if (d != 0 && aic3x->sysclk < 10000000)
810 continue;
811
812 /* This is actually 1000 * ((j + (d/10000)) * r) / p
813 * The term had to be converted to get rid of the
814 * division by 10000 */
815 clk = ((10000 * j * r) + (d * r)) / (10 * p);
816
817 /* check whether this values get closer than the best
818 * ones we had before */
819 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
820 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
821 last_clk = clk;
822 }
823
824 /* Early exit for exact matches */
825 if (clk == codec_clk)
826 break;
827 }
828
829 if (last_clk == 0) {
830 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
831 return -EINVAL;
832 }
44d0a879
VB		 833
834 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
835 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
836 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
837 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
838 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
839 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
840 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
841
44d0a879
VB		 842 return 0;
843}
844
e550e17f 845static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 846{
847 struct snd_soc_codec *codec = dai->codec;
848 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
849 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
850
851 if (mute) {
852 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
853 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
854 } else {
855 aic3x_write(codec, LDAC_VOL, ldac_reg);
856 aic3x_write(codec, RDAC_VOL, rdac_reg);
857 }
858
859 return 0;
860}
861
e550e17f 862static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 863 int clk_id, unsigned int freq, int dir)
864{
865 struct snd_soc_codec *codec = codec_dai->codec;
866 struct aic3x_priv *aic3x = codec->private_data;
867
4f9c16cc
DM		 868 aic3x->sysclk = freq;
869 return 0;
44d0a879
VB		 870}
871
e550e17f 872static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 873 unsigned int fmt)
874{
875 struct snd_soc_codec *codec = codec_dai->codec;
876 struct aic3x_priv *aic3x = codec->private_data;
81971a14 877 u8 iface_areg, iface_breg;
a24f4f68 878 int delay = 0;
81971a14
JN		 879
880 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
881 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 882
883 /* set master/slave audio interface */
884 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
885 case SND_SOC_DAIFMT_CBM_CFM:
886 aic3x->master = 1;
887 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
888 break;
889 case SND_SOC_DAIFMT_CBS_CFS:
890 aic3x->master = 0;
891 break;
892 default:
893 return -EINVAL;
894 }
895
4b7d2831
JN		 896 /*
897 * match both interface format and signal polarities since they
898 * are fixed
899 */
900 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
901 SND_SOC_DAIFMT_INV_MASK)) {
902 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 903 break;
a24f4f68
TK		 904 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
905 delay = 1;
4b7d2831 906 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 907 iface_breg |= (0x01 << 6);
908 break;
4b7d2831 909 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 910 iface_breg |= (0x02 << 6);
911 break;
4b7d2831 912 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 913 iface_breg |= (0x03 << 6);
914 break;
915 default:
916 return -EINVAL;
917 }
918
919 /* set iface */
920 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
921 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
a24f4f68 922 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 923
924 return 0;
925}
926
0be9898a
MB		 927static int aic3x_set_bias_level(struct snd_soc_codec *codec,
928 enum snd_soc_bias_level level)
44d0a879
VB		 929{
930 struct aic3x_priv *aic3x = codec->private_data;
931 u8 reg;
932
0be9898a
MB		 933 switch (level) {
934 case SND_SOC_BIAS_ON:
44d0a879
VB		 935 /* all power is driven by DAPM system */
936 if (aic3x->master) {
937 /* enable pll */
938 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
939 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
940 reg | PLL_ENABLE);
941 }
942 break;
0be9898a 943 case SND_SOC_BIAS_PREPARE:
44d0a879 944 break;
0be9898a 945 case SND_SOC_BIAS_STANDBY:
44d0a879
VB		 946 /*
947 * all power is driven by DAPM system,
948 * so output power is safe if bypass was set
949 */
950 if (aic3x->master) {
951 /* disable pll */
952 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
953 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
954 reg & ~PLL_ENABLE);
955 }
956 break;
0be9898a 957 case SND_SOC_BIAS_OFF:
44d0a879
VB		 958 /* force all power off */
959 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
960 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
961 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
962 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
963
964 reg = aic3x_read_reg_cache(codec, DAC_PWR);
965 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
966
967 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
968 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
969 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
970 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
971
972 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
973 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
974 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
975 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
976
977 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
978 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
979
980 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
981 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
982 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
983 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
984
985 if (aic3x->master) {
986 /* disable pll */
987 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
988 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
989 reg & ~PLL_ENABLE);
990 }
991 break;
992 }
0be9898a 993 codec->bias_level = level;
44d0a879
VB		 994
995 return 0;
996}
997
54e7e616
DM		 998void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
999{
1000 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1001 u8 bit = gpio ? 3: 0;
1002 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1003 aic3x_write(codec, reg, val | (!!state << bit));
1004}
1005EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1006
1007int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1008{
1009 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1010 u8 val, bit = gpio ? 2: 1;
1011
1012 aic3x_read(codec, reg, &val);
1013 return (val >> bit) & 1;
1014}
1015EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1016
6f2a974b
DM		 1017void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1018 int headset_debounce, int button_debounce)
1019{
1020 u8 val;
1021
1022 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1023 << AIC3X_HEADSET_DETECT_SHIFT) |
1024 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1025 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1026 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1027 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1028
1029 if (detect & AIC3X_HEADSET_DETECT_MASK)
1030 val |= AIC3X_HEADSET_DETECT_ENABLED;
1031
1032 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1033}
1034EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1035
54e7e616
DM		 1036int aic3x_headset_detected(struct snd_soc_codec *codec)
1037{
1038 u8 val;
6f2a974b
DM		 1039 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1040 return (val >> 4) & 1;
54e7e616
DM		 1041}
1042EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1043
6f2a974b
DM		 1044int aic3x_button_pressed(struct snd_soc_codec *codec)
1045{
1046 u8 val;
1047 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1048 return (val >> 5) & 1;
1049}
1050EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1051
44d0a879
VB		 1052#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1053#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1054 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1055
e550e17f 1056struct snd_soc_dai aic3x_dai = {
e78cc18d 1057 .name = "tlv320aic3x",
44d0a879
VB		 1058 .playback = {
1059 .stream_name = "Playback",
1060 .channels_min = 1,
1061 .channels_max = 2,
1062 .rates = AIC3X_RATES,
1063 .formats = AIC3X_FORMATS,},
1064 .capture = {
1065 .stream_name = "Capture",
1066 .channels_min = 1,
1067 .channels_max = 2,
1068 .rates = AIC3X_RATES,
1069 .formats = AIC3X_FORMATS,},
1070 .ops = {
1071 .hw_params = aic3x_hw_params,
44d0a879
VB		 1072 .digital_mute = aic3x_mute,
1073 .set_sysclk = aic3x_set_dai_sysclk,
1074 .set_fmt = aic3x_set_dai_fmt,
1075 }
1076};
1077EXPORT_SYMBOL_GPL(aic3x_dai);
1078
1079static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1080{
1081 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1082 struct snd_soc_codec *codec = socdev->codec;
1083
0be9898a 1084 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1085
1086 return 0;
1087}
1088
1089static int aic3x_resume(struct platform_device *pdev)
1090{
1091 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1092 struct snd_soc_codec *codec = socdev->codec;
1093 int i;
1094 u8 data[2];
1095 u8 *cache = codec->reg_cache;
1096
1097 /* Sync reg_cache with the hardware */
1098 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1099 data[0] = i;
1100 data[1] = cache[i];
1101 codec->hw_write(codec->control_data, data, 2);
1102 }
1103
0be9898a 1104 aic3x_set_bias_level(codec, codec->suspend_bias_level);
44d0a879
VB		 1105
1106 return 0;
1107}
1108
1109/*
1110 * initialise the AIC3X driver
1111 * register the mixer and dsp interfaces with the kernel
1112 */
1113static int aic3x_init(struct snd_soc_device *socdev)
1114{
1115 struct snd_soc_codec *codec = socdev->codec;
54e7e616 1116 struct aic3x_setup_data *setup = socdev->codec_data;
44d0a879
VB		 1117 int reg, ret = 0;
1118
e78cc18d 1119 codec->name = "tlv320aic3x";
44d0a879
VB		 1120 codec->owner = THIS_MODULE;
1121 codec->read = aic3x_read_reg_cache;
1122 codec->write = aic3x_write;
0be9898a 1123 codec->set_bias_level = aic3x_set_bias_level;
44d0a879
VB		 1124 codec->dai = &aic3x_dai;
1125 codec->num_dai = 1;
ae2ff191 1126 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
44d0a879
VB		 1127 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1128 if (codec->reg_cache == NULL)
1129 return -ENOMEM;
1130
1131 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1132 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1133
1134 /* register pcms */
1135 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1136 if (ret < 0) {
1137 printk(KERN_ERR "aic3x: failed to create pcms\n");
1138 goto pcm_err;
1139 }
1140
1141 /* DAC default volume and mute */
1142 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1143 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1144
1145 /* DAC to HP default volume and route to Output mixer */
1146 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1147 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1148 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1149 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1150 /* DAC to Line Out default volume and route to Output mixer */
1151 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1152 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1153 /* DAC to Mono Line Out default volume and route to Output mixer */
1154 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1155 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1156
1157 /* unmute all outputs */
1158 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1159 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1160 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1161 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1162 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1163 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1164 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1165 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1166 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1167 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1168 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1169 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1170 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1171 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1172
1173 /* ADC default volume and unmute */
1174 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1175 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1176 /* By default route Line1 to ADC PGA mixer */
1177 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1178 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1179
1180 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1181 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1182 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1183 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1184 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1185 /* PGA to Line Out default volume, disconnect from Output Mixer */
1186 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1187 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1188 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1189 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1190 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1191
1192 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1193 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1194 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1195 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1196 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1197 /* Line2 Line Out default volume, disconnect from Output Mixer */
1198 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1199 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1200 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1201 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1202 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1203
1204 /* off, with power on */
0be9898a 1205 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879 1206
54e7e616
DM		 1207 /* setup GPIO functions */
1208 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1209 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1210
3e8e1952
IM		 1211 snd_soc_add_controls(codec, aic3x_snd_controls,
1212 ARRAY_SIZE(aic3x_snd_controls));
44d0a879 1213 aic3x_add_widgets(codec);
968a6025 1214 ret = snd_soc_init_card(socdev);
44d0a879
VB		 1215 if (ret < 0) {
1216 printk(KERN_ERR "aic3x: failed to register card\n");
1217 goto card_err;
1218 }
1219
1220 return ret;
1221
1222card_err:
1223 snd_soc_free_pcms(socdev);
1224 snd_soc_dapm_free(socdev);
1225pcm_err:
1226 kfree(codec->reg_cache);
1227 return ret;
1228}
1229
1230static struct snd_soc_device *aic3x_socdev;
1231
1232#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1233/*
1234 * AIC3X 2 wire address can be up to 4 devices with device addresses
1235 * 0x18, 0x19, 0x1A, 0x1B
1236 */
44d0a879
VB		 1237
1238/*
1239 * If the i2c layer weren't so broken, we could pass this kind of data
1240 * around
1241 */
ba8ed121
JD		 1242static int aic3x_i2c_probe(struct i2c_client *i2c,
1243 const struct i2c_device_id *id)
44d0a879
VB		 1244{
1245 struct snd_soc_device *socdev = aic3x_socdev;
44d0a879 1246 struct snd_soc_codec *codec = socdev->codec;
44d0a879
VB		 1247 int ret;
1248
44d0a879
VB		 1249 i2c_set_clientdata(i2c, codec);
1250 codec->control_data = i2c;
1251
44d0a879 1252 ret = aic3x_init(socdev);
ba8ed121 1253 if (ret < 0)
44d0a879 1254 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
44d0a879
VB		 1255 return ret;
1256}
1257
ba8ed121 1258static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879
VB		 1259{
1260 struct snd_soc_codec *codec = i2c_get_clientdata(client);
44d0a879 1261 kfree(codec->reg_cache);
44d0a879
VB		 1262 return 0;
1263}
1264
ba8ed121
JD		 1265static const struct i2c_device_id aic3x_i2c_id[] = {
1266 { "tlv320aic3x", 0 },
1267 { }
1268};
1269MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
44d0a879
VB		 1270
1271/* machine i2c codec control layer */
1272static struct i2c_driver aic3x_i2c_driver = {
1273 .driver = {
1274 .name = "aic3x I2C Codec",
1275 .owner = THIS_MODULE,
1276 },
ba8ed121
JD		 1277 .probe = aic3x_i2c_probe,
1278 .remove = aic3x_i2c_remove,
1279 .id_table = aic3x_i2c_id,
44d0a879 1280};
54e7e616
DM		 1281
1282static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1283{
1284 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1285 return (len == 1);
1286}
ba8ed121
JD		 1287
1288static int aic3x_add_i2c_device(struct platform_device *pdev,
1289 const struct aic3x_setup_data *setup)
1290{
1291 struct i2c_board_info info;
1292 struct i2c_adapter *adapter;
1293 struct i2c_client *client;
1294 int ret;
1295
1296 ret = i2c_add_driver(&aic3x_i2c_driver);
1297 if (ret != 0) {
1298 dev_err(&pdev->dev, "can't add i2c driver\n");
1299 return ret;
1300 }
1301
1302 memset(&info, 0, sizeof(struct i2c_board_info));
1303 info.addr = setup->i2c_address;
1304 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1305
1306 adapter = i2c_get_adapter(setup->i2c_bus);
1307 if (!adapter) {
1308 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1309 setup->i2c_bus);
1310 goto err_driver;
1311 }
1312
1313 client = i2c_new_device(adapter, &info);
1314 i2c_put_adapter(adapter);
1315 if (!client) {
1316 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1317 (unsigned int)info.addr);
1318 goto err_driver;
1319 }
1320
1321 return 0;
1322
1323err_driver:
1324 i2c_del_driver(&aic3x_i2c_driver);
1325 return -ENODEV;
1326}
44d0a879
VB		 1327#endif
1328
1329static int aic3x_probe(struct platform_device *pdev)
1330{
1331 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1332 struct aic3x_setup_data *setup;
1333 struct snd_soc_codec *codec;
1334 struct aic3x_priv *aic3x;
1335 int ret = 0;
1336
1337 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1338
1339 setup = socdev->codec_data;
1340 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1341 if (codec == NULL)
1342 return -ENOMEM;
1343
1344 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1345 if (aic3x == NULL) {
1346 kfree(codec);
1347 return -ENOMEM;
1348 }
1349
1350 codec->private_data = aic3x;
1351 socdev->codec = codec;
1352 mutex_init(&codec->mutex);
1353 INIT_LIST_HEAD(&codec->dapm_widgets);
1354 INIT_LIST_HEAD(&codec->dapm_paths);
1355
1356 aic3x_socdev = socdev;
1357#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1358 if (setup->i2c_address) {
44d0a879 1359 codec->hw_write = (hw_write_t) i2c_master_send;
54e7e616 1360 codec->hw_read = (hw_read_t) aic3x_i2c_read;
ba8ed121 1361 ret = aic3x_add_i2c_device(pdev, setup);
44d0a879
VB		 1362 }
1363#else
1364 /* Add other interfaces here */
1365#endif
3051e41a
JD		 1366
1367 if (ret != 0) {
1368 kfree(codec->private_data);
1369 kfree(codec);
1370 }
44d0a879
VB		 1371 return ret;
1372}
1373
1374static int aic3x_remove(struct platform_device *pdev)
1375{
1376 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1377 struct snd_soc_codec *codec = socdev->codec;
1378
1379 /* power down chip */
1380 if (codec->control_data)
0be9898a 1381 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1382
1383 snd_soc_free_pcms(socdev);
1384 snd_soc_dapm_free(socdev);
1385#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
ba8ed121 1386 i2c_unregister_device(codec->control_data);
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VB		 1387 i2c_del_driver(&aic3x_i2c_driver);
1388#endif
1389 kfree(codec->private_data);
1390 kfree(codec);
1391
1392 return 0;
1393}
1394
1395struct snd_soc_codec_device soc_codec_dev_aic3x = {
1396 .probe = aic3x_probe,
1397 .remove = aic3x_remove,
1398 .suspend = aic3x_suspend,
1399 .resume = aic3x_resume,
1400};
1401EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1402
c9b3a40f 1403static int __init aic3x_modinit(void)
64089b84
MB		 1404{
1405 return snd_soc_register_dai(&aic3x_dai);
1406}
1407module_init(aic3x_modinit);
1408
1409static void __exit aic3x_exit(void)
1410{
1411 snd_soc_unregister_dai(&aic3x_dai);
1412}
1413module_exit(aic3x_exit);
1414
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VB		 1415MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1416MODULE_AUTHOR("Vladimir Barinov");
1417MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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