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ASoC: wm8940: Fix a typo for the mask of setting WM8940_BCLKDIV
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
44d0a879 43#include <linux/platform_device.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
44d0a879 49#include <sound/initval.h>
7565fc38 50#include <sound/tlv.h>
5193d62f 51#include <sound/tlv320aic3x.h>
44d0a879
VB		 52
53#include "tlv320aic3x.h"
54
07779fdd
JN		 55#define AIC3X_NUM_SUPPLIES 4
56static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD", /* I/O Voltage */
58 "DVDD", /* Digital Core Voltage */
59 "AVDD", /* Analog DAC Voltage */
60 "DRVDD", /* ADC Analog and Output Driver Voltage */
61};
44d0a879 62
414c73ab
JN		 63static LIST_HEAD(reset_list);
64
5a895f8a
JN		 65struct aic3x_priv;
66
67struct aic3x_disable_nb {
68 struct notifier_block nb;
69 struct aic3x_priv *aic3x;
70};
71
44d0a879
VB		 72/* codec private data */
73struct aic3x_priv {
5a895f8a 74 struct snd_soc_codec *codec;
07779fdd 75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 77 enum snd_soc_control_type control_type;
78 struct aic3x_setup_data *setup;
44d0a879 79 unsigned int sysclk;
414c73ab 80 struct list_head list;
44d0a879 81 int master;
5193d62f 82 int gpio_reset;
6c1a7d40 83 int power;
6184f105
RC		 84#define AIC3X_MODEL_3X 0
85#define AIC3X_MODEL_33 1
86#define AIC3X_MODEL_3007 2
87 u16 model;
44d0a879
VB		 88};
89
90/*
91 * AIC3X register cache
92 * We can't read the AIC3X register space when we are
93 * using 2 wire for device control, so we cache them instead.
94 * There is no point in caching the reset register
95 */
96static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
97 0x00, 0x00, 0x00, 0x10, /* 0 */
98 0x04, 0x00, 0x00, 0x00, /* 4 */
99 0x00, 0x00, 0x00, 0x01, /* 8 */
100 0x00, 0x00, 0x00, 0x80, /* 12 */
101 0x80, 0xff, 0xff, 0x78, /* 16 */
102 0x78, 0x78, 0x78, 0x78, /* 20 */
103 0x78, 0x00, 0x00, 0xfe, /* 24 */
104 0x00, 0x00, 0xfe, 0x00, /* 28 */
105 0x18, 0x18, 0x00, 0x00, /* 32 */
106 0x00, 0x00, 0x00, 0x00, /* 36 */
107 0x00, 0x00, 0x00, 0x80, /* 40 */
108 0x80, 0x00, 0x00, 0x00, /* 44 */
109 0x00, 0x00, 0x00, 0x04, /* 48 */
110 0x00, 0x00, 0x00, 0x00, /* 52 */
111 0x00, 0x00, 0x04, 0x00, /* 56 */
112 0x00, 0x00, 0x00, 0x00, /* 60 */
113 0x00, 0x04, 0x00, 0x00, /* 64 */
114 0x00, 0x00, 0x00, 0x00, /* 68 */
115 0x04, 0x00, 0x00, 0x00, /* 72 */
116 0x00, 0x00, 0x00, 0x00, /* 76 */
117 0x00, 0x00, 0x00, 0x00, /* 80 */
118 0x00, 0x00, 0x00, 0x00, /* 84 */
119 0x00, 0x00, 0x00, 0x00, /* 88 */
120 0x00, 0x00, 0x00, 0x00, /* 92 */
121 0x00, 0x00, 0x00, 0x00, /* 96 */
122 0x00, 0x00, 0x02, /* 100 */
123};
124
125/*
9900daa8
JN		 126 * read from the aic3x register space. Only use for this function is if
127 * wanting to read volatile bits from those registers that has both read-only
128 * and read/write bits. All other cases should use snd_soc_read.
44d0a879 129 */
54e7e616
DM		 130static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
131 u8 *value)
44d0a879
VB		 132{
133 u8 *cache = codec->reg_cache;
44d0a879 134
5a895f8a
JN		 135 if (codec->cache_only)
136 return -EINVAL;
44d0a879 137 if (reg >= AIC3X_CACHEREGNUM)
9900daa8 138 return -1;
5f345346 139
38c436aa
AL		 140 codec->cache_bypass = 1;
141 *value = snd_soc_read(codec, reg);
142 codec->cache_bypass = 0;
143
9900daa8 144 cache[reg] = *value;
54e7e616 145
54e7e616
DM		 146 return 0;
147}
148
44d0a879
VB		 149#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
150{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
151 .info = snd_soc_info_volsw, \
152 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
153 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
154
155/*
156 * All input lines are connected when !0xf and disconnected with 0xf bit field,
157 * so we have to use specific dapm_put call for input mixer
158 */
159static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
160 struct snd_ctl_elem_value *ucontrol)
161{
9d03545d
JN		 162 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
163 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
4453dba5
EN		 164 struct soc_mixer_control *mc =
165 (struct soc_mixer_control *)kcontrol->private_value;
166 unsigned int reg = mc->reg;
167 unsigned int shift = mc->shift;
168 int max = mc->max;
169 unsigned int mask = (1 << fls(max)) - 1;
170 unsigned int invert = mc->invert;
44d0a879
VB		 171 unsigned short val, val_mask;
172 int ret;
173 struct snd_soc_dapm_path *path;
174 int found = 0;
175
176 val = (ucontrol->value.integer.value[0] & mask);
177
178 mask = 0xf;
179 if (val)
180 val = mask;
181
182 if (invert)
183 val = mask - val;
184 val_mask = mask << shift;
185 val = val << shift;
186
187 mutex_lock(&widget->codec->mutex);
188
189 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
190 /* find dapm widget path assoc with kcontrol */
8ddab3f5 191 list_for_each_entry(path, &widget->dapm->card->paths, list) {
44d0a879
VB		 192 if (path->kcontrol != kcontrol)
193 continue;
194
195 /* found, now check type */
196 found = 1;
197 if (val)
198 /* new connection */
199 path->connect = invert ? 0 : 1;
200 else
201 /* old connection must be powered down */
202 path->connect = invert ? 1 : 0;
25c77c5f
MB		 203
204 dapm_mark_dirty(path->source, "tlv320aic3x source");
205 dapm_mark_dirty(path->sink, "tlv320aic3x sink");
206
44d0a879
VB		 207 break;
208 }
209
210 if (found)
ce6120cc 211 snd_soc_dapm_sync(widget->dapm);
44d0a879
VB		 212 }
213
214 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
215
216 mutex_unlock(&widget->codec->mutex);
217 return ret;
218}
219
220static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
221static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
222static const char *aic3x_left_hpcom_mux[] =
223 { "differential of HPLOUT", "constant VCM", "single-ended" };
224static const char *aic3x_right_hpcom_mux[] =
225 { "differential of HPROUT", "constant VCM", "single-ended",
226 "differential of HPLCOM", "external feedback" };
227static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 228static const char *aic3x_adc_hpf[] =
229 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 230
231#define LDAC_ENUM 0
232#define RDAC_ENUM 1
233#define LHPCOM_ENUM 2
234#define RHPCOM_ENUM 3
404b5665
JN		 235#define LINE1L_2_L_ENUM 4
236#define LINE1L_2_R_ENUM 5
237#define LINE1R_2_L_ENUM 6
238#define LINE1R_2_R_ENUM 7
239#define LINE2L_ENUM 8
240#define LINE2R_ENUM 9
241#define ADC_HPF_ENUM 10
44d0a879
VB		 242
243static const struct soc_enum aic3x_enum[] = {
244 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
245 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
246 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
247 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
248 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
404b5665
JN		 249 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
250 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
44d0a879
VB		 251 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
252 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
253 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 254 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 255};
256
7565fc38
JN		 257/*
258 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
259 */
260static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
261/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
262static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
263/*
264 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
265 * Step size is approximately 0.5 dB over most of the scale but increasing
266 * near the very low levels.
267 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
268 * but having increasing dB difference below that (and where it doesn't count
269 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
270 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
271 */
272static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
273
44d0a879
VB		 274static const struct snd_kcontrol_new aic3x_snd_controls[] = {
275 /* Output */
7565fc38
JN		 276 SOC_DOUBLE_R_TLV("PCM Playback Volume",
277 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 278
098b1718
JN		 279 /*
280 * Output controls that map to output mixer switches. Note these are
281 * only for swapped L-to-R and R-to-L routes. See below stereo controls
282 * for direct L-to-L and R-to-R routes.
283 */
284 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
285 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
286 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
287 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
288 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
289 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
290
291 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
292 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
293 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
294 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
295 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
296 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
297
298 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
299 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
300 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
301 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
302 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
303 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
304
305 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
306 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
307 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
308 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
309 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
310 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
311
312 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
313 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
314 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
315 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
316 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
317 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
318
319 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
320 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
321 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
322 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
323 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
324 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
325
326 /* Stereo output controls for direct L-to-L and R-to-R routes */
327 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
328 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
329 0, 118, 1, output_stage_tlv),
330 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
331 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
332 0, 118, 1, output_stage_tlv),
7565fc38
JN		 333 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
334 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
335 0, 118, 1, output_stage_tlv),
098b1718
JN		 336
337 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
338 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 339 0, 118, 1, output_stage_tlv),
098b1718
JN		 340 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
341 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 342 0, 118, 1, output_stage_tlv),
7565fc38
JN		 343 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
344 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
345 0, 118, 1, output_stage_tlv),
098b1718
JN		 346
347 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
348 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 349 0, 118, 1, output_stage_tlv),
098b1718
JN		 350 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
351 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 352 0, 118, 1, output_stage_tlv),
7565fc38
JN		 353 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
354 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
355 0, 118, 1, output_stage_tlv),
098b1718
JN		 356
357 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
358 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 359 0, 118, 1, output_stage_tlv),
098b1718
JN		 360 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
361 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 362 0, 118, 1, output_stage_tlv),
7565fc38
JN		 363 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
364 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
365 0, 118, 1, output_stage_tlv),
098b1718
JN		 366
367 /* Output pin mute controls */
368 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
369 0x01, 0),
370 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
371 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
372 0x01, 0),
f9bc0297 373 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 374 0x01, 0),
44d0a879
VB		 375
376 /*
377 * Note: enable Automatic input Gain Controller with care. It can
378 * adjust PGA to max value when ADC is on and will never go back.
379 */
380 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
381
382 /* Input */
7565fc38
JN		 383 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
384 0, 119, 0, adc_tlv),
44d0a879 385 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 386
387 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 388};
389
6184f105
RC		 390/*
391 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
392 */
393static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
394
395static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
396 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
397
44d0a879
VB		 398/* Left DAC Mux */
399static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
400SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
401
402/* Right DAC Mux */
403static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
404SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
405
406/* Left HPCOM Mux */
407static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
408SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
409
410/* Right HPCOM Mux */
411static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
412SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
413
c3b79e05
JN		 414/* Left Line Mixer */
415static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
416 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
419 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
420 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
421 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 422};
423
c3b79e05
JN		 424/* Right Line Mixer */
425static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
426 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
428 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
429 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
430 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
431 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
432};
433
434/* Mono Mixer */
435static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
436 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
439 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
440 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
441 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
442};
443
444/* Left HP Mixer */
445static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
446 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
450 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
452};
453
454/* Right HP Mixer */
455static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
456 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
462};
463
464/* Left HPCOM Mixer */
465static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
466 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
472};
473
474/* Right HPCOM Mixer */
475static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
476 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
480 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
481 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 482};
483
484/* Left PGA Mixer */
485static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
486 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 487 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 488 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
489 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 490 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 491};
492
493/* Right PGA Mixer */
494static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
495 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 496 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 497 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 498 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 499 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
500};
501
502/* Left Line1 Mux */
404b5665
JN		 503static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
504SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
505static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
506SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
44d0a879
VB		 507
508/* Right Line1 Mux */
404b5665
JN		 509static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
510SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
511static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
512SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
44d0a879
VB		 513
514/* Left Line2 Mux */
515static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
516SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
517
518/* Right Line2 Mux */
519static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
520SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
521
44d0a879
VB		 522static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
523 /* Left DAC to Left Outputs */
524 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
525 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
526 &aic3x_left_dac_mux_controls),
44d0a879
VB		 527 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
528 &aic3x_left_hpcom_mux_controls),
529 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
530 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
531 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
532
533 /* Right DAC to Right Outputs */
534 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
535 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
536 &aic3x_right_dac_mux_controls),
44d0a879
VB		 537 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
538 &aic3x_right_hpcom_mux_controls),
539 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
540 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
541 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
542
543 /* Mono Output */
544 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
545
54f01916 546 /* Inputs to Left ADC */
44d0a879
VB		 547 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
548 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
549 &aic3x_left_pga_mixer_controls[0],
550 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
551 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 552 &aic3x_left_line1l_mux_controls),
54f01916 553 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 554 &aic3x_left_line1r_mux_controls),
44d0a879
VB		 555 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
556 &aic3x_left_line2_mux_controls),
557
54f01916 558 /* Inputs to Right ADC */
44d0a879
VB		 559 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
560 LINE1R_2_RADC_CTRL, 2, 0),
561 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
562 &aic3x_right_pga_mixer_controls[0],
563 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916 564 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 565 &aic3x_right_line1l_mux_controls),
44d0a879 566 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 567 &aic3x_right_line1r_mux_controls),
44d0a879
VB		 568 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
569 &aic3x_right_line2_mux_controls),
570
ee15ffdb
JN		 571 /*
572 * Not a real mic bias widget but similar function. This is for dynamic
573 * control of GPIO1 digital mic modulator clock output function when
574 * using digital mic.
575 */
576 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
577 AIC3X_GPIO1_REG, 4, 0xf,
578 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
579 AIC3X_GPIO1_FUNC_DISABLED),
580
581 /*
582 * Also similar function like mic bias. Selects digital mic with
583 * configurable oversampling rate instead of ADC converter.
584 */
585 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
586 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
587 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
588 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
589 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
590 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
591
44d0a879 592 /* Mic Bias */
0bd72a3d
JN		 593 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
594 MICBIAS_CTRL, 6, 3, 1, 0),
595 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
596 MICBIAS_CTRL, 6, 3, 2, 0),
597 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
598 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 599
c3b79e05
JN		 600 /* Output mixers */
601 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
602 &aic3x_left_line_mixer_controls[0],
603 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
604 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
605 &aic3x_right_line_mixer_controls[0],
606 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
607 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
608 &aic3x_mono_mixer_controls[0],
609 ARRAY_SIZE(aic3x_mono_mixer_controls)),
610 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
611 &aic3x_left_hp_mixer_controls[0],
612 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
613 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
614 &aic3x_right_hp_mixer_controls[0],
615 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
616 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
617 &aic3x_left_hpcom_mixer_controls[0],
618 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
619 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
620 &aic3x_right_hpcom_mixer_controls[0],
621 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 622
623 SND_SOC_DAPM_OUTPUT("LLOUT"),
624 SND_SOC_DAPM_OUTPUT("RLOUT"),
625 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
626 SND_SOC_DAPM_OUTPUT("HPLOUT"),
627 SND_SOC_DAPM_OUTPUT("HPROUT"),
628 SND_SOC_DAPM_OUTPUT("HPLCOM"),
629 SND_SOC_DAPM_OUTPUT("HPRCOM"),
630
631 SND_SOC_DAPM_INPUT("MIC3L"),
632 SND_SOC_DAPM_INPUT("MIC3R"),
633 SND_SOC_DAPM_INPUT("LINE1L"),
634 SND_SOC_DAPM_INPUT("LINE1R"),
635 SND_SOC_DAPM_INPUT("LINE2L"),
636 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 637
638 /*
639 * Virtual output pin to detection block inside codec. This can be
640 * used to keep codec bias on if gpio or detection features are needed.
641 * Force pin on or construct a path with an input jack and mic bias
642 * widgets.
643 */
644 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 645};
646
6184f105
RC		 647static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
648 /* Class-D outputs */
649 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
650 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
651
652 SND_SOC_DAPM_OUTPUT("SPOP"),
653 SND_SOC_DAPM_OUTPUT("SPOM"),
654};
655
d0cc0d3a 656static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 657 /* Left Input */
658 {"Left Line1L Mux", "single-ended", "LINE1L"},
659 {"Left Line1L Mux", "differential", "LINE1L"},
660
661 {"Left Line2L Mux", "single-ended", "LINE2L"},
662 {"Left Line2L Mux", "differential", "LINE2L"},
663
664 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 665 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 666 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
667 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 668 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 669
670 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 671 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 672
673 /* Right Input */
674 {"Right Line1R Mux", "single-ended", "LINE1R"},
675 {"Right Line1R Mux", "differential", "LINE1R"},
676
677 {"Right Line2R Mux", "single-ended", "LINE2R"},
678 {"Right Line2R Mux", "differential", "LINE2R"},
679
54f01916 680 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 681 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
682 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 683 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 684 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
685
686 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 687 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 688
ee15ffdb
JN		 689 /*
690 * Logical path between digital mic enable and GPIO1 modulator clock
691 * output function
692 */
693 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
694 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
695 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 696
697 /* Left DAC Output */
698 {"Left DAC Mux", "DAC_L1", "Left DAC"},
699 {"Left DAC Mux", "DAC_L2", "Left DAC"},
700 {"Left DAC Mux", "DAC_L3", "Left DAC"},
701
702 /* Right DAC Output */
703 {"Right DAC Mux", "DAC_R1", "Right DAC"},
704 {"Right DAC Mux", "DAC_R2", "Right DAC"},
705 {"Right DAC Mux", "DAC_R3", "Right DAC"},
706
707 /* Left Line Output */
708 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
709 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
710 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
711 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
712 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
713 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
714
715 {"Left Line Out", NULL, "Left Line Mixer"},
716 {"Left Line Out", NULL, "Left DAC Mux"},
717 {"LLOUT", NULL, "Left Line Out"},
718
719 /* Right Line Output */
720 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
721 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
722 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
723 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
724 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
725 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
726
727 {"Right Line Out", NULL, "Right Line Mixer"},
728 {"Right Line Out", NULL, "Right DAC Mux"},
729 {"RLOUT", NULL, "Right Line Out"},
730
731 /* Mono Output */
732 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
733 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
734 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
735 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
736 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
737 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
738
739 {"Mono Out", NULL, "Mono Mixer"},
740 {"MONO_LOUT", NULL, "Mono Out"},
741
742 /* Left HP Output */
743 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
744 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
745 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
746 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
747 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
748 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
749
750 {"Left HP Out", NULL, "Left HP Mixer"},
751 {"Left HP Out", NULL, "Left DAC Mux"},
752 {"HPLOUT", NULL, "Left HP Out"},
753
754 /* Right HP Output */
755 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
756 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
757 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
758 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
759 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
760 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
761
762 {"Right HP Out", NULL, "Right HP Mixer"},
763 {"Right HP Out", NULL, "Right DAC Mux"},
764 {"HPROUT", NULL, "Right HP Out"},
765
766 /* Left HPCOM Output */
767 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
768 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
769 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
770 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
771 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
772 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
773
774 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
775 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
776 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
777 {"Left HP Com", NULL, "Left HPCOM Mux"},
778 {"HPLCOM", NULL, "Left HP Com"},
779
780 /* Right HPCOM Output */
781 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
782 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
783 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
784 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
785 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
786 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
787
788 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
789 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
790 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
791 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
792 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
793 {"Right HP Com", NULL, "Right HPCOM Mux"},
794 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 795};
796
6184f105
RC		 797static const struct snd_soc_dapm_route intercon_3007[] = {
798 /* Class-D outputs */
799 {"Left Class-D Out", NULL, "Left Line Out"},
800 {"Right Class-D Out", NULL, "Left Line Out"},
801 {"SPOP", NULL, "Left Class-D Out"},
802 {"SPOM", NULL, "Right Class-D Out"},
803};
804
44d0a879
VB		 805static int aic3x_add_widgets(struct snd_soc_codec *codec)
806{
6184f105 807 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 808 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 809
ce6120cc 810 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
d0cc0d3a 811 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 812
813 /* set up audio path interconnects */
ce6120cc 814 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
44d0a879 815
6184f105 816 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 817 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 818 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 819 snd_soc_dapm_add_routes(dapm, intercon_3007,
820 ARRAY_SIZE(intercon_3007));
6184f105
RC		 821 }
822
44d0a879
VB		 823 return 0;
824}
825
44d0a879 826static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 827 struct snd_pcm_hw_params *params,
828 struct snd_soc_dai *dai)
44d0a879
VB		 829{
830 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 831 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 832 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 833 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 834 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
835 u16 d, pll_d = 1;
06c71282 836 u8 reg;
255173b4 837 int clk;
44d0a879 838
4f9c16cc 839 /* select data word length */
e18eca43 840 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 841 switch (params_format(params)) {
842 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 843 break;
4f9c16cc
DM		 844 case SNDRV_PCM_FORMAT_S20_3LE:
845 data |= (0x01 << 4);
44d0a879 846 break;
4f9c16cc
DM		 847 case SNDRV_PCM_FORMAT_S24_LE:
848 data |= (0x02 << 4);
44d0a879 849 break;
4f9c16cc
DM		 850 case SNDRV_PCM_FORMAT_S32_LE:
851 data |= (0x03 << 4);
44d0a879
VB		 852 break;
853 }
e18eca43 854 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 855
856 /* Fsref can be 44100 or 48000 */
857 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
858
859 /* Try to find a value for Q which allows us to bypass the PLL and
860 * generate CODEC_CLK directly. */
861 for (pll_q = 2; pll_q < 18; pll_q++)
862 if (aic3x->sysclk / (128 * pll_q) == fsref) {
863 bypass_pll = 1;
864 break;
865 }
866
867 if (bypass_pll) {
868 pll_q &= 0xf;
e18eca43
JN		 869 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
870 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 871 /* disable PLL if it is bypassed */
e18eca43
JN		 872 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
873 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
06c71282
C		 874
875 } else {
e18eca43 876 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 877 /* enable PLL when it is used */
e18eca43
JN		 878 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
879 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
06c71282 880 }
4f9c16cc
DM		 881
882 /* Route Left DAC to left channel input and
883 * right DAC to right channel input */
884 data = (LDAC2LCH | RDAC2RCH);
885 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
886 if (params_rate(params) >= 64000)
887 data |= DUAL_RATE_MODE;
e18eca43 888 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 889
890 /* codec sample rate select */
4f9c16cc
DM		 891 data = (fsref * 20) / params_rate(params);
892 if (params_rate(params) < 64000)
893 data /= 2;
894 data /= 5;
895 data -= 2;
44d0a879 896 data |= (data << 4);
e18eca43 897 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 898
4f9c16cc
DM		 899 if (bypass_pll)
900 return 0;
901
25985edc 902 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 903 * one wins the game. Try with d==0 first, next with d!=0.
904 * Constraints for j are according to the datasheet.
4f9c16cc 905 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 906 */
255173b4 907
4f9c16cc
DM		 908 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
909
910 for (r = 1; r <= 16; r++)
911 for (p = 1; p <= 8; p++) {
255173b4
PM		 912 for (j = 4; j <= 55; j++) {
913 /* This is actually 1000*((j+(d/10000))*r)/p
914 * The term had to be converted to get
915 * rid of the division by 10000; d = 0 here
916 */
5baf8315 917 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 918
919 /* Check whether this values get closer than
920 * the best ones we had before
921 */
5baf8315 922 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 923 abs(codec_clk - last_clk)) {
924 pll_j = j; pll_d = 0;
925 pll_r = r; pll_p = p;
5baf8315 926 last_clk = tmp_clk;
255173b4
PM		 927 }
928
929 /* Early exit for exact matches */
5baf8315 930 if (tmp_clk == codec_clk)
255173b4
PM		 931 goto found;
932 }
933 }
4f9c16cc 934
255173b4
PM		 935 /* try with d != 0 */
936 for (p = 1; p <= 8; p++) {
937 j = codec_clk * p / 1000;
4f9c16cc 938
255173b4
PM		 939 if (j < 4 || j > 11)
940 continue;
4f9c16cc 941
255173b4
PM		 942 /* do not use codec_clk here since we'd loose precision */
943 d = ((2048 * p * fsref) - j * aic3x->sysclk)
944 * 100 / (aic3x->sysclk/100);
4f9c16cc 945
255173b4 946 clk = (10000 * j + d) / (10 * p);
4f9c16cc 947
255173b4
PM		 948 /* check whether this values get closer than the best
949 * ones we had before */
950 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
951 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
952 last_clk = clk;
4f9c16cc
DM		 953 }
954
255173b4
PM		 955 /* Early exit for exact matches */
956 if (clk == codec_clk)
957 goto found;
958 }
959
4f9c16cc
DM		 960 if (last_clk == 0) {
961 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
962 return -EINVAL;
963 }
44d0a879 964
255173b4 965found:
e18eca43
JN		 966 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
967 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
968 data | (pll_p << PLLP_SHIFT));
969 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
970 pll_r << PLLR_SHIFT);
971 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
972 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
973 (pll_d >> 6) << PLLD_MSB_SHIFT);
974 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
975 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 976
44d0a879
VB		 977 return 0;
978}
979
e550e17f 980static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 981{
982 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 983 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
984 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 985
986 if (mute) {
e18eca43
JN		 987 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
988 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 989 } else {
e18eca43
JN		 990 snd_soc_write(codec, LDAC_VOL, ldac_reg);
991 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 992 }
993
994 return 0;
995}
996
e550e17f 997static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 998 int clk_id, unsigned int freq, int dir)
999{
1000 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1001 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1002
4f9c16cc
DM		 1003 aic3x->sysclk = freq;
1004 return 0;
44d0a879
VB		 1005}
1006
e550e17f 1007static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1008 unsigned int fmt)
1009{
1010 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1011 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 1012 u8 iface_areg, iface_breg;
a24f4f68 1013 int delay = 0;
81971a14 1014
e18eca43
JN		 1015 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1016 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1017
1018 /* set master/slave audio interface */
1019 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1020 case SND_SOC_DAIFMT_CBM_CFM:
1021 aic3x->master = 1;
1022 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1023 break;
1024 case SND_SOC_DAIFMT_CBS_CFS:
1025 aic3x->master = 0;
1026 break;
1027 default:
1028 return -EINVAL;
1029 }
1030
4b7d2831
JN		 1031 /*
1032 * match both interface format and signal polarities since they
1033 * are fixed
1034 */
1035 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1036 SND_SOC_DAIFMT_INV_MASK)) {
1037 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1038 break;
a24f4f68
TK		 1039 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1040 delay = 1;
4b7d2831 1041 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1042 iface_breg |= (0x01 << 6);
1043 break;
4b7d2831 1044 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1045 iface_breg |= (0x02 << 6);
1046 break;
4b7d2831 1047 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1048 iface_breg |= (0x03 << 6);
1049 break;
1050 default:
1051 return -EINVAL;
1052 }
1053
1054 /* set iface */
e18eca43
JN		 1055 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1056 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1057 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1058
1059 return 0;
1060}
1061
6c1a7d40
JN		 1062static int aic3x_init_3007(struct snd_soc_codec *codec)
1063{
1064 u8 tmp1, tmp2, *cache = codec->reg_cache;
1065
1066 /*
1067 * There is no need to cache writes to undocumented page 0xD but
1068 * respective page 0 register cache entries must be preserved
1069 */
1070 tmp1 = cache[0xD];
1071 tmp2 = cache[0x8];
1072 /* Class-D speaker driver init; datasheet p. 46 */
1073 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1074 snd_soc_write(codec, 0xD, 0x0D);
1075 snd_soc_write(codec, 0x8, 0x5C);
1076 snd_soc_write(codec, 0x8, 0x5D);
1077 snd_soc_write(codec, 0x8, 0x5C);
1078 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1079 cache[0xD] = tmp1;
1080 cache[0x8] = tmp2;
1081
1082 return 0;
1083}
1084
5a895f8a
JN		 1085static int aic3x_regulator_event(struct notifier_block *nb,
1086 unsigned long event, void *data)
1087{
1088 struct aic3x_disable_nb *disable_nb =
1089 container_of(nb, struct aic3x_disable_nb, nb);
1090 struct aic3x_priv *aic3x = disable_nb->aic3x;
1091
1092 if (event & REGULATOR_EVENT_DISABLE) {
1093 /*
1094 * Put codec to reset and require cache sync as at least one
1095 * of the supplies was disabled
1096 */
79ee820d 1097 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a
JN		 1098 gpio_set_value(aic3x->gpio_reset, 0);
1099 aic3x->codec->cache_sync = 1;
1100 }
1101
1102 return 0;
1103}
1104
6c1a7d40
JN		 1105static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1106{
1107 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1108 int i, ret;
1109 u8 *cache = codec->reg_cache;
1110
1111 if (power) {
1112 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1113 aic3x->supplies);
1114 if (ret)
1115 goto out;
1116 aic3x->power = 1;
5a895f8a
JN		 1117 /*
1118 * Reset release and cache sync is necessary only if some
1119 * supply was off or if there were cached writes
1120 */
1121 if (!codec->cache_sync)
1122 goto out;
1123
79ee820d 1124 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1125 udelay(1);
1126 gpio_set_value(aic3x->gpio_reset, 1);
1127 }
1128
1129 /* Sync reg_cache with the hardware */
1130 codec->cache_only = 0;
508b7686 1131 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
6c1a7d40
JN		 1132 snd_soc_write(codec, i, cache[i]);
1133 if (aic3x->model == AIC3X_MODEL_3007)
1134 aic3x_init_3007(codec);
1135 codec->cache_sync = 0;
1136 } else {
9fb352b1
JN		 1137 /*
1138 * Do soft reset to this codec instance in order to clear
1139 * possible VDD leakage currents in case the supply regulators
1140 * remain on
1141 */
1142 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1143 codec->cache_sync = 1;
6c1a7d40 1144 aic3x->power = 0;
5a895f8a
JN		 1145 /* HW writes are needless when bias is off */
1146 codec->cache_only = 1;
6c1a7d40
JN		 1147 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1148 aic3x->supplies);
1149 }
1150out:
1151 return ret;
1152}
1153
0be9898a
MB		 1154static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1155 enum snd_soc_bias_level level)
44d0a879 1156{
b2c812e2 1157 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 1158 u8 reg;
1159
0be9898a
MB		 1160 switch (level) {
1161 case SND_SOC_BIAS_ON:
db13802e
JN		 1162 break;
1163 case SND_SOC_BIAS_PREPARE:
ce6120cc 1164 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1165 aic3x->master) {
44d0a879 1166 /* enable pll */
e18eca43
JN		 1167 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1168 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1169 reg | PLL_ENABLE);
44d0a879
VB		 1170 }
1171 break;
0be9898a 1172 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1173 if (!aic3x->power)
1174 aic3x_set_power(codec, 1);
ce6120cc 1175 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1176 aic3x->master) {
44d0a879 1177 /* disable pll */
e18eca43
JN		 1178 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1179 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1180 reg & ~PLL_ENABLE);
44d0a879
VB		 1181 }
1182 break;
c23fd751 1183 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1184 if (aic3x->power)
1185 aic3x_set_power(codec, 0);
c23fd751 1186 break;
44d0a879 1187 }
ce6120cc 1188 codec->dapm.bias_level = level;
44d0a879
VB		 1189
1190 return 0;
1191}
1192
54e7e616
DM		 1193void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1194{
1195 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1196 u8 bit = gpio ? 3: 0;
e18eca43
JN		 1197 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1198 snd_soc_write(codec, reg, val | (!!state << bit));
54e7e616
DM		 1199}
1200EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1201
1202int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1203{
1204 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
fe99b559 1205 u8 val = 0, bit = gpio ? 2 : 1;
54e7e616
DM		 1206
1207 aic3x_read(codec, reg, &val);
1208 return (val >> bit) & 1;
1209}
1210EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1211
6f2a974b
DM		 1212void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1213 int headset_debounce, int button_debounce)
1214{
1215 u8 val;
1216
1217 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1218 << AIC3X_HEADSET_DETECT_SHIFT) |
1219 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1220 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1221 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1222 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1223
1224 if (detect & AIC3X_HEADSET_DETECT_MASK)
1225 val |= AIC3X_HEADSET_DETECT_ENABLED;
1226
e18eca43 1227 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
6f2a974b
DM		 1228}
1229EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1230
54e7e616
DM		 1231int aic3x_headset_detected(struct snd_soc_codec *codec)
1232{
fe99b559 1233 u8 val = 0;
6f2a974b
DM		 1234 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1235 return (val >> 4) & 1;
54e7e616
DM		 1236}
1237EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1238
6f2a974b
DM		 1239int aic3x_button_pressed(struct snd_soc_codec *codec)
1240{
fe99b559 1241 u8 val = 0;
6f2a974b
DM		 1242 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1243 return (val >> 5) & 1;
1244}
1245EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1246
44d0a879
VB		 1247#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1248#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1249 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1250
6335d055
EM		 1251static struct snd_soc_dai_ops aic3x_dai_ops = {
1252 .hw_params = aic3x_hw_params,
1253 .digital_mute = aic3x_mute,
1254 .set_sysclk = aic3x_set_dai_sysclk,
1255 .set_fmt = aic3x_set_dai_fmt,
1256};
1257
f0fba2ad
LG		 1258static struct snd_soc_dai_driver aic3x_dai = {
1259 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1260 .playback = {
1261 .stream_name = "Playback",
1262 .channels_min = 1,
1263 .channels_max = 2,
1264 .rates = AIC3X_RATES,
1265 .formats = AIC3X_FORMATS,},
1266 .capture = {
1267 .stream_name = "Capture",
1268 .channels_min = 1,
1269 .channels_max = 2,
1270 .rates = AIC3X_RATES,
1271 .formats = AIC3X_FORMATS,},
6335d055 1272 .ops = &aic3x_dai_ops,
14017615 1273 .symmetric_rates = 1,
44d0a879 1274};
44d0a879 1275
f0fba2ad 1276static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
44d0a879 1277{
0be9898a 1278 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1279
1280 return 0;
1281}
1282
f0fba2ad 1283static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1284{
29e189c2 1285 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1286
1287 return 0;
1288}
1289
1290/*
1291 * initialise the AIC3X driver
1292 * register the mixer and dsp interfaces with the kernel
1293 */
cb3826f5 1294static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1295{
6184f105 1296 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5
BD		 1297 int reg;
1298
e18eca43
JN		 1299 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1300 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1301
44d0a879 1302 /* DAC default volume and mute */
e18eca43
JN		 1303 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1304 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1305
1306 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1307 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1308 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1309 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1310 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1311 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1312 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1313 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1314 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1315 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1316 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1317
1318 /* unmute all outputs */
e18eca43
JN		 1319 reg = snd_soc_read(codec, LLOPM_CTRL);
1320 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
1321 reg = snd_soc_read(codec, RLOPM_CTRL);
1322 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
1323 reg = snd_soc_read(codec, MONOLOPM_CTRL);
1324 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1325 reg = snd_soc_read(codec, HPLOUT_CTRL);
1326 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1327 reg = snd_soc_read(codec, HPROUT_CTRL);
1328 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
1329 reg = snd_soc_read(codec, HPLCOM_CTRL);
1330 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1331 reg = snd_soc_read(codec, HPRCOM_CTRL);
1332 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
44d0a879
VB		 1333
1334 /* ADC default volume and unmute */
e18eca43
JN		 1335 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1336 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1337 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1338 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1339 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1340
1341 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1342 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1343 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1344 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1345 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1346 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1347 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1348 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1349 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1350 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1351 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1352
1353 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1354 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1355 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1356 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1357 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1358 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1359 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1360 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1361 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1362 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1363 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1364
6184f105 1365 if (aic3x->model == AIC3X_MODEL_3007) {
6c1a7d40 1366 aic3x_init_3007(codec);
e18eca43 1367 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1368 }
1369
cb3826f5
BD		 1370 return 0;
1371}
54e7e616 1372
414c73ab
JN		 1373static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1374{
1375 struct aic3x_priv *a;
1376
1377 list_for_each_entry(a, &reset_list, list) {
1378 if (gpio_is_valid(aic3x->gpio_reset) &&
1379 aic3x->gpio_reset == a->gpio_reset)
1380 return true;
1381 }
1382
1383 return false;
1384}
1385
f0fba2ad 1386static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1387{
f0fba2ad 1388 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1389 int ret, i;
f0fba2ad 1390
414c73ab 1391 INIT_LIST_HEAD(&aic3x->list);
5a895f8a 1392 aic3x->codec = codec;
ce6120cc 1393 codec->dapm.idle_bias_off = 1;
cb3826f5 1394
a84a441b
JN		 1395 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1396 if (ret != 0) {
1397 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1398 return ret;
1399 }
1400
414c73ab
JN		 1401 if (gpio_is_valid(aic3x->gpio_reset) &&
1402 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1403 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1404 if (ret != 0)
1405 goto err_gpio;
1406 gpio_direction_output(aic3x->gpio_reset, 0);
1407 }
1408
1409 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1410 aic3x->supplies[i].supply = aic3x_supply_names[i];
1411
1412 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1413 aic3x->supplies);
1414 if (ret != 0) {
1415 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1416 goto err_get;
1417 }
5a895f8a
JN		 1418 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1419 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1420 aic3x->disable_nb[i].aic3x = aic3x;
1421 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1422 &aic3x->disable_nb[i].nb);
1423 if (ret) {
1424 dev_err(codec->dev,
1425 "Failed to request regulator notifier: %d\n",
1426 ret);
1427 goto err_notif;
1428 }
1429 }
2f24111a 1430
7d1be0a6 1431 codec->cache_only = 1;
37b47656
JN		 1432 aic3x_init(codec);
1433
f0fba2ad
LG		 1434 if (aic3x->setup) {
1435 /* setup GPIO functions */
e18eca43
JN		 1436 snd_soc_write(codec, AIC3X_GPIO1_REG,
1437 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1438 snd_soc_write(codec, AIC3X_GPIO2_REG,
1439 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1440 }
1441
f0fba2ad
LG		 1442 snd_soc_add_controls(codec, aic3x_snd_controls,
1443 ARRAY_SIZE(aic3x_snd_controls));
6184f105
RC		 1444 if (aic3x->model == AIC3X_MODEL_3007)
1445 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1446
f0fba2ad 1447 aic3x_add_widgets(codec);
414c73ab 1448 list_add(&aic3x->list, &reset_list);
cb3826f5
BD		 1449
1450 return 0;
2f24111a 1451
5a895f8a
JN		 1452err_notif:
1453 while (i--)
1454 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1455 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1456 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1457err_get:
414c73ab
JN		 1458 if (gpio_is_valid(aic3x->gpio_reset) &&
1459 !aic3x_is_shared_reset(aic3x))
2f24111a
JN		 1460 gpio_free(aic3x->gpio_reset);
1461err_gpio:
2f24111a 1462 return ret;
44d0a879
VB		 1463}
1464
f0fba2ad 1465static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1466{
2f24111a 1467 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1468 int i;
2f24111a 1469
f0fba2ad 1470 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
414c73ab
JN		 1471 list_del(&aic3x->list);
1472 if (gpio_is_valid(aic3x->gpio_reset) &&
1473 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1474 gpio_set_value(aic3x->gpio_reset, 0);
1475 gpio_free(aic3x->gpio_reset);
1476 }
5a895f8a
JN		 1477 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1478 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1479 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1480 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1481
cb3826f5
BD		 1482 return 0;
1483}
44d0a879 1484
f0fba2ad 1485static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad
LG		 1486 .set_bias_level = aic3x_set_bias_level,
1487 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1488 .reg_word_size = sizeof(u8),
1489 .reg_cache_default = aic3x_reg,
1490 .probe = aic3x_probe,
1491 .remove = aic3x_remove,
1492 .suspend = aic3x_suspend,
1493 .resume = aic3x_resume,
1494};
1495
44d0a879
VB		 1496#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1497/*
1498 * AIC3X 2 wire address can be up to 4 devices with device addresses
1499 * 0x18, 0x19, 0x1A, 0x1B
1500 */
44d0a879 1501
6184f105 1502static const struct i2c_device_id aic3x_i2c_id[] = {
177fdd89
AL		 1503 { "tlv320aic3x", AIC3X_MODEL_3X },
1504 { "tlv320aic33", AIC3X_MODEL_33 },
1505 { "tlv320aic3007", AIC3X_MODEL_3007 },
6184f105
RC		 1506 { }
1507};
1508MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1509
44d0a879
VB		 1510/*
1511 * If the i2c layer weren't so broken, we could pass this kind of data
1512 * around
1513 */
ba8ed121
JD		 1514static int aic3x_i2c_probe(struct i2c_client *i2c,
1515 const struct i2c_device_id *id)
44d0a879 1516{
5193d62f 1517 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1518 struct aic3x_priv *aic3x;
2f24111a 1519 int ret;
44d0a879 1520
cb3826f5
BD		 1521 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1522 if (aic3x == NULL) {
1523 dev_err(&i2c->dev, "failed to create private data\n");
1524 return -ENOMEM;
1525 }
1526
a84a441b
JN		 1527 aic3x->control_type = SND_SOC_I2C;
1528
cb3826f5 1529 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1530 if (pdata) {
1531 aic3x->gpio_reset = pdata->gpio_reset;
1532 aic3x->setup = pdata->setup;
1533 } else {
1534 aic3x->gpio_reset = -1;
1535 }
cb3826f5 1536
177fdd89 1537 aic3x->model = id->driver_data;
6184f105 1538
f0fba2ad
LG		 1539 ret = snd_soc_register_codec(&i2c->dev,
1540 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1541 if (ret < 0)
2f24111a 1542 kfree(aic3x);
07779fdd 1543 return ret;
44d0a879
VB		 1544}
1545
ba8ed121 1546static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1547{
f0fba2ad
LG		 1548 snd_soc_unregister_codec(&client->dev);
1549 kfree(i2c_get_clientdata(client));
1550 return 0;
44d0a879
VB		 1551}
1552
44d0a879
VB		 1553/* machine i2c codec control layer */
1554static struct i2c_driver aic3x_i2c_driver = {
1555 .driver = {
f0fba2ad 1556 .name = "tlv320aic3x-codec",
44d0a879
VB		 1557 .owner = THIS_MODULE,
1558 },
cb3826f5 1559 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1560 .remove = aic3x_i2c_remove,
1561 .id_table = aic3x_i2c_id,
44d0a879
VB		 1562};
1563#endif
1564
f0fba2ad 1565static int __init aic3x_modinit(void)
44d0a879 1566{
44d0a879 1567 int ret = 0;
f0fba2ad
LG		 1568#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1569 ret = i2c_add_driver(&aic3x_i2c_driver);
1570 if (ret != 0) {
1571 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1572 ret);
44d0a879 1573 }
f0fba2ad 1574#endif
44d0a879
VB		 1575 return ret;
1576}
64089b84
MB		 1577module_init(aic3x_modinit);
1578
1579static void __exit aic3x_exit(void)
1580{
f0fba2ad
LG		 1581#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1582 i2c_del_driver(&aic3x_i2c_driver);
1583#endif
64089b84
MB		 1584}
1585module_exit(aic3x_exit);
1586
44d0a879
VB		 1587MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1588MODULE_AUTHOR("Vladimir Barinov");
1589MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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