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44d0a879 VB |
1 | /* |
2 | * ALSA SoC TLV320AIC3X codec driver | |
3 | * | |
4 | * Author: Vladimir Barinov, <vbarinov@ru.mvista.com> | |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> | |
6 | * | |
7 | * Based on sound/soc/codecs/wm8753.c by Liam Girdwood | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * Notes: | |
14 | * The AIC3X is a driver for a low power stereo audio | |
15 | * codecs aic31, aic32, aic33. | |
16 | * | |
17 | * It supports full aic33 codec functionality. | |
18 | * The compatibility with aic32, aic31 is as follows: | |
19 | * aic32 | aic31 | |
20 | * --------------------------------------- | |
21 | * MONO_LOUT -> N/A | MONO_LOUT -> N/A | |
22 | * | IN1L -> LINE1L | |
23 | * | IN1R -> LINE1R | |
24 | * | IN2L -> LINE2L | |
25 | * | IN2R -> LINE2R | |
26 | * | MIC3L/R -> N/A | |
27 | * truncated internal functionality in | |
28 | * accordance with documentation | |
29 | * --------------------------------------- | |
30 | * | |
31 | * Hence the machine layer should disable unsupported inputs/outputs by | |
32 | * snd_soc_dapm_set_endpoint(codec, "MONO_LOUT", 0), etc. | |
33 | */ | |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/pm.h> | |
40 | #include <linux/i2c.h> | |
41 | #include <linux/platform_device.h> | |
44d0a879 VB |
42 | #include <sound/core.h> |
43 | #include <sound/pcm.h> | |
44 | #include <sound/pcm_params.h> | |
45 | #include <sound/soc.h> | |
46 | #include <sound/soc-dapm.h> | |
47 | #include <sound/initval.h> | |
48 | ||
49 | #include "tlv320aic3x.h" | |
50 | ||
51 | #define AUDIO_NAME "aic3x" | |
4f9c16cc | 52 | #define AIC3X_VERSION "0.2" |
44d0a879 VB |
53 | |
54 | /* codec private data */ | |
55 | struct aic3x_priv { | |
56 | unsigned int sysclk; | |
57 | int master; | |
58 | }; | |
59 | ||
60 | /* | |
61 | * AIC3X register cache | |
62 | * We can't read the AIC3X register space when we are | |
63 | * using 2 wire for device control, so we cache them instead. | |
64 | * There is no point in caching the reset register | |
65 | */ | |
66 | static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { | |
67 | 0x00, 0x00, 0x00, 0x10, /* 0 */ | |
68 | 0x04, 0x00, 0x00, 0x00, /* 4 */ | |
69 | 0x00, 0x00, 0x00, 0x01, /* 8 */ | |
70 | 0x00, 0x00, 0x00, 0x80, /* 12 */ | |
71 | 0x80, 0xff, 0xff, 0x78, /* 16 */ | |
72 | 0x78, 0x78, 0x78, 0x78, /* 20 */ | |
73 | 0x78, 0x00, 0x00, 0xfe, /* 24 */ | |
74 | 0x00, 0x00, 0xfe, 0x00, /* 28 */ | |
75 | 0x18, 0x18, 0x00, 0x00, /* 32 */ | |
76 | 0x00, 0x00, 0x00, 0x00, /* 36 */ | |
77 | 0x00, 0x00, 0x00, 0x80, /* 40 */ | |
78 | 0x80, 0x00, 0x00, 0x00, /* 44 */ | |
79 | 0x00, 0x00, 0x00, 0x04, /* 48 */ | |
80 | 0x00, 0x00, 0x00, 0x00, /* 52 */ | |
81 | 0x00, 0x00, 0x04, 0x00, /* 56 */ | |
82 | 0x00, 0x00, 0x00, 0x00, /* 60 */ | |
83 | 0x00, 0x04, 0x00, 0x00, /* 64 */ | |
84 | 0x00, 0x00, 0x00, 0x00, /* 68 */ | |
85 | 0x04, 0x00, 0x00, 0x00, /* 72 */ | |
86 | 0x00, 0x00, 0x00, 0x00, /* 76 */ | |
87 | 0x00, 0x00, 0x00, 0x00, /* 80 */ | |
88 | 0x00, 0x00, 0x00, 0x00, /* 84 */ | |
89 | 0x00, 0x00, 0x00, 0x00, /* 88 */ | |
90 | 0x00, 0x00, 0x00, 0x00, /* 92 */ | |
91 | 0x00, 0x00, 0x00, 0x00, /* 96 */ | |
92 | 0x00, 0x00, 0x02, /* 100 */ | |
93 | }; | |
94 | ||
95 | /* | |
96 | * read aic3x register cache | |
97 | */ | |
98 | static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec, | |
99 | unsigned int reg) | |
100 | { | |
101 | u8 *cache = codec->reg_cache; | |
102 | if (reg >= AIC3X_CACHEREGNUM) | |
103 | return -1; | |
104 | return cache[reg]; | |
105 | } | |
106 | ||
107 | /* | |
108 | * write aic3x register cache | |
109 | */ | |
110 | static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec, | |
111 | u8 reg, u8 value) | |
112 | { | |
113 | u8 *cache = codec->reg_cache; | |
114 | if (reg >= AIC3X_CACHEREGNUM) | |
115 | return; | |
116 | cache[reg] = value; | |
117 | } | |
118 | ||
119 | /* | |
120 | * write to the aic3x register space | |
121 | */ | |
122 | static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg, | |
123 | unsigned int value) | |
124 | { | |
125 | u8 data[2]; | |
126 | ||
127 | /* data is | |
128 | * D15..D8 aic3x register offset | |
129 | * D7...D0 register data | |
130 | */ | |
131 | data[0] = reg & 0xff; | |
132 | data[1] = value & 0xff; | |
133 | ||
134 | aic3x_write_reg_cache(codec, data[0], data[1]); | |
135 | if (codec->hw_write(codec->control_data, data, 2) == 2) | |
136 | return 0; | |
137 | else | |
138 | return -EIO; | |
139 | } | |
140 | ||
54e7e616 DM |
141 | /* |
142 | * read from the aic3x register space | |
143 | */ | |
144 | static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg, | |
145 | u8 *value) | |
146 | { | |
147 | *value = reg & 0xff; | |
148 | if (codec->hw_read(codec->control_data, value, 1) != 1) | |
149 | return -EIO; | |
150 | ||
151 | aic3x_write_reg_cache(codec, reg, *value); | |
152 | return 0; | |
153 | } | |
154 | ||
44d0a879 VB |
155 | #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ |
156 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
157 | .info = snd_soc_info_volsw, \ | |
158 | .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ | |
159 | .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } | |
160 | ||
161 | /* | |
162 | * All input lines are connected when !0xf and disconnected with 0xf bit field, | |
163 | * so we have to use specific dapm_put call for input mixer | |
164 | */ | |
165 | static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, | |
166 | struct snd_ctl_elem_value *ucontrol) | |
167 | { | |
168 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); | |
169 | int reg = kcontrol->private_value & 0xff; | |
170 | int shift = (kcontrol->private_value >> 8) & 0x0f; | |
171 | int mask = (kcontrol->private_value >> 16) & 0xff; | |
172 | int invert = (kcontrol->private_value >> 24) & 0x01; | |
173 | unsigned short val, val_mask; | |
174 | int ret; | |
175 | struct snd_soc_dapm_path *path; | |
176 | int found = 0; | |
177 | ||
178 | val = (ucontrol->value.integer.value[0] & mask); | |
179 | ||
180 | mask = 0xf; | |
181 | if (val) | |
182 | val = mask; | |
183 | ||
184 | if (invert) | |
185 | val = mask - val; | |
186 | val_mask = mask << shift; | |
187 | val = val << shift; | |
188 | ||
189 | mutex_lock(&widget->codec->mutex); | |
190 | ||
191 | if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { | |
192 | /* find dapm widget path assoc with kcontrol */ | |
193 | list_for_each_entry(path, &widget->codec->dapm_paths, list) { | |
194 | if (path->kcontrol != kcontrol) | |
195 | continue; | |
196 | ||
197 | /* found, now check type */ | |
198 | found = 1; | |
199 | if (val) | |
200 | /* new connection */ | |
201 | path->connect = invert ? 0 : 1; | |
202 | else | |
203 | /* old connection must be powered down */ | |
204 | path->connect = invert ? 1 : 0; | |
205 | break; | |
206 | } | |
207 | ||
208 | if (found) | |
209 | snd_soc_dapm_sync_endpoints(widget->codec); | |
210 | } | |
211 | ||
212 | ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); | |
213 | ||
214 | mutex_unlock(&widget->codec->mutex); | |
215 | return ret; | |
216 | } | |
217 | ||
218 | static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; | |
219 | static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; | |
220 | static const char *aic3x_left_hpcom_mux[] = | |
221 | { "differential of HPLOUT", "constant VCM", "single-ended" }; | |
222 | static const char *aic3x_right_hpcom_mux[] = | |
223 | { "differential of HPROUT", "constant VCM", "single-ended", | |
224 | "differential of HPLCOM", "external feedback" }; | |
225 | static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; | |
226 | ||
227 | #define LDAC_ENUM 0 | |
228 | #define RDAC_ENUM 1 | |
229 | #define LHPCOM_ENUM 2 | |
230 | #define RHPCOM_ENUM 3 | |
231 | #define LINE1L_ENUM 4 | |
232 | #define LINE1R_ENUM 5 | |
233 | #define LINE2L_ENUM 6 | |
234 | #define LINE2R_ENUM 7 | |
235 | ||
236 | static const struct soc_enum aic3x_enum[] = { | |
237 | SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), | |
238 | SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), | |
239 | SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), | |
240 | SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), | |
241 | SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
242 | SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
243 | SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
244 | SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
245 | }; | |
246 | ||
247 | static const struct snd_kcontrol_new aic3x_snd_controls[] = { | |
248 | /* Output */ | |
249 | SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1), | |
250 | ||
251 | SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL, | |
252 | DACR1_2_RLOPM_VOL, 0, 0x7f, 1), | |
253 | SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, | |
254 | 0x01, 0), | |
255 | SOC_DOUBLE_R("Line PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL, | |
256 | PGAR_2_RLOPM_VOL, 0, 0x7f, 1), | |
257 | SOC_DOUBLE_R("Line Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL, | |
258 | LINE2R_2_RLOPM_VOL, 0, 0x7f, 1), | |
259 | ||
260 | SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL, | |
261 | DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1), | |
262 | SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), | |
263 | SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL, | |
264 | PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1), | |
265 | SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL, | |
266 | LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1), | |
267 | ||
268 | SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL, | |
269 | DACR1_2_HPROUT_VOL, 0, 0x7f, 1), | |
270 | SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, | |
271 | 0x01, 0), | |
272 | SOC_DOUBLE_R("HP PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL, | |
273 | PGAR_2_HPROUT_VOL, 0, 0x7f, 1), | |
274 | SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL, | |
275 | LINE2R_2_HPROUT_VOL, 0, 0x7f, 1), | |
276 | ||
277 | SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL, | |
278 | DACR1_2_HPRCOM_VOL, 0, 0x7f, 1), | |
279 | SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, | |
280 | 0x01, 0), | |
281 | SOC_DOUBLE_R("HPCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL, | |
282 | PGAR_2_HPRCOM_VOL, 0, 0x7f, 1), | |
283 | SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL, | |
284 | LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1), | |
285 | ||
286 | /* | |
287 | * Note: enable Automatic input Gain Controller with care. It can | |
288 | * adjust PGA to max value when ADC is on and will never go back. | |
289 | */ | |
290 | SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), | |
291 | ||
292 | /* Input */ | |
293 | SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0), | |
294 | SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), | |
295 | }; | |
296 | ||
297 | /* add non dapm controls */ | |
298 | static int aic3x_add_controls(struct snd_soc_codec *codec) | |
299 | { | |
300 | int err, i; | |
301 | ||
302 | for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) { | |
303 | err = snd_ctl_add(codec->card, | |
304 | snd_soc_cnew(&aic3x_snd_controls[i], | |
305 | codec, NULL)); | |
306 | if (err < 0) | |
307 | return err; | |
308 | } | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | /* Left DAC Mux */ | |
314 | static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = | |
315 | SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); | |
316 | ||
317 | /* Right DAC Mux */ | |
318 | static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = | |
319 | SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); | |
320 | ||
321 | /* Left HPCOM Mux */ | |
322 | static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = | |
323 | SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); | |
324 | ||
325 | /* Right HPCOM Mux */ | |
326 | static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = | |
327 | SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); | |
328 | ||
329 | /* Left DAC_L1 Mixer */ | |
330 | static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = { | |
331 | SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), | |
332 | SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), | |
333 | SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), | |
334 | SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), | |
335 | }; | |
336 | ||
337 | /* Right DAC_R1 Mixer */ | |
338 | static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = { | |
339 | SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), | |
340 | SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), | |
341 | SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), | |
342 | SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), | |
343 | }; | |
344 | ||
345 | /* Left PGA Mixer */ | |
346 | static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { | |
347 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), | |
348 | SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), | |
349 | SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), | |
350 | }; | |
351 | ||
352 | /* Right PGA Mixer */ | |
353 | static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { | |
354 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), | |
355 | SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), | |
356 | SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), | |
357 | }; | |
358 | ||
359 | /* Left Line1 Mux */ | |
360 | static const struct snd_kcontrol_new aic3x_left_line1_mux_controls = | |
361 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]); | |
362 | ||
363 | /* Right Line1 Mux */ | |
364 | static const struct snd_kcontrol_new aic3x_right_line1_mux_controls = | |
365 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]); | |
366 | ||
367 | /* Left Line2 Mux */ | |
368 | static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = | |
369 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); | |
370 | ||
371 | /* Right Line2 Mux */ | |
372 | static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = | |
373 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); | |
374 | ||
375 | /* Left PGA Bypass Mixer */ | |
376 | static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = { | |
377 | SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), | |
378 | SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), | |
379 | SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), | |
380 | SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), | |
381 | }; | |
382 | ||
383 | /* Right PGA Bypass Mixer */ | |
384 | static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = { | |
385 | SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), | |
386 | SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), | |
387 | SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), | |
388 | SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), | |
389 | }; | |
390 | ||
391 | /* Left Line2 Bypass Mixer */ | |
392 | static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = { | |
393 | SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), | |
394 | SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), | |
395 | SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), | |
396 | SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), | |
397 | }; | |
398 | ||
399 | /* Right Line2 Bypass Mixer */ | |
400 | static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = { | |
401 | SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), | |
402 | SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), | |
403 | SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), | |
404 | SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), | |
405 | }; | |
406 | ||
407 | static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { | |
408 | /* Left DAC to Left Outputs */ | |
409 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), | |
410 | SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, | |
411 | &aic3x_left_dac_mux_controls), | |
412 | SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0, | |
413 | &aic3x_left_dac_mixer_controls[0], | |
414 | ARRAY_SIZE(aic3x_left_dac_mixer_controls)), | |
415 | SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, | |
416 | &aic3x_left_hpcom_mux_controls), | |
417 | SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), | |
418 | SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), | |
419 | SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), | |
420 | ||
421 | /* Right DAC to Right Outputs */ | |
422 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), | |
423 | SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, | |
424 | &aic3x_right_dac_mux_controls), | |
425 | SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0, | |
426 | &aic3x_right_dac_mixer_controls[0], | |
427 | ARRAY_SIZE(aic3x_right_dac_mixer_controls)), | |
428 | SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, | |
429 | &aic3x_right_hpcom_mux_controls), | |
430 | SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), | |
431 | SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), | |
432 | SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), | |
433 | ||
434 | /* Mono Output */ | |
435 | SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), | |
436 | ||
437 | /* Left Inputs to Left ADC */ | |
438 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), | |
439 | SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, | |
440 | &aic3x_left_pga_mixer_controls[0], | |
441 | ARRAY_SIZE(aic3x_left_pga_mixer_controls)), | |
442 | SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, | |
443 | &aic3x_left_line1_mux_controls), | |
444 | SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, | |
445 | &aic3x_left_line2_mux_controls), | |
446 | ||
447 | /* Right Inputs to Right ADC */ | |
448 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", | |
449 | LINE1R_2_RADC_CTRL, 2, 0), | |
450 | SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, | |
451 | &aic3x_right_pga_mixer_controls[0], | |
452 | ARRAY_SIZE(aic3x_right_pga_mixer_controls)), | |
453 | SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, | |
454 | &aic3x_right_line1_mux_controls), | |
455 | SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, | |
456 | &aic3x_right_line2_mux_controls), | |
457 | ||
458 | /* Mic Bias */ | |
459 | SND_SOC_DAPM_MICBIAS("Mic Bias 2V", MICBIAS_CTRL, 6, 0), | |
460 | SND_SOC_DAPM_MICBIAS("Mic Bias 2.5V", MICBIAS_CTRL, 7, 0), | |
461 | SND_SOC_DAPM_MICBIAS("Mic Bias AVDD", MICBIAS_CTRL, 6, 0), | |
462 | SND_SOC_DAPM_MICBIAS("Mic Bias AVDD", MICBIAS_CTRL, 7, 0), | |
463 | ||
464 | /* Left PGA to Left Output bypass */ | |
465 | SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
466 | &aic3x_left_pga_bp_mixer_controls[0], | |
467 | ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)), | |
468 | ||
469 | /* Right PGA to Right Output bypass */ | |
470 | SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
471 | &aic3x_right_pga_bp_mixer_controls[0], | |
472 | ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)), | |
473 | ||
474 | /* Left Line2 to Left Output bypass */ | |
475 | SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
476 | &aic3x_left_line2_bp_mixer_controls[0], | |
477 | ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)), | |
478 | ||
479 | /* Right Line2 to Right Output bypass */ | |
480 | SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
481 | &aic3x_right_line2_bp_mixer_controls[0], | |
482 | ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)), | |
483 | ||
484 | SND_SOC_DAPM_OUTPUT("LLOUT"), | |
485 | SND_SOC_DAPM_OUTPUT("RLOUT"), | |
486 | SND_SOC_DAPM_OUTPUT("MONO_LOUT"), | |
487 | SND_SOC_DAPM_OUTPUT("HPLOUT"), | |
488 | SND_SOC_DAPM_OUTPUT("HPROUT"), | |
489 | SND_SOC_DAPM_OUTPUT("HPLCOM"), | |
490 | SND_SOC_DAPM_OUTPUT("HPRCOM"), | |
491 | ||
492 | SND_SOC_DAPM_INPUT("MIC3L"), | |
493 | SND_SOC_DAPM_INPUT("MIC3R"), | |
494 | SND_SOC_DAPM_INPUT("LINE1L"), | |
495 | SND_SOC_DAPM_INPUT("LINE1R"), | |
496 | SND_SOC_DAPM_INPUT("LINE2L"), | |
497 | SND_SOC_DAPM_INPUT("LINE2R"), | |
498 | }; | |
499 | ||
d0cc0d3a | 500 | static const struct snd_soc_dapm_route intercon[] = { |
44d0a879 VB |
501 | /* Left Output */ |
502 | {"Left DAC Mux", "DAC_L1", "Left DAC"}, | |
503 | {"Left DAC Mux", "DAC_L2", "Left DAC"}, | |
504 | {"Left DAC Mux", "DAC_L3", "Left DAC"}, | |
505 | ||
506 | {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"}, | |
507 | {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"}, | |
508 | {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"}, | |
509 | {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"}, | |
510 | {"Left Line Out", NULL, "Left DAC Mux"}, | |
511 | {"Left HP Out", NULL, "Left DAC Mux"}, | |
512 | ||
513 | {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"}, | |
514 | {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"}, | |
515 | {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"}, | |
516 | ||
517 | {"Left Line Out", NULL, "Left DAC_L1 Mixer"}, | |
518 | {"Mono Out", NULL, "Left DAC_L1 Mixer"}, | |
519 | {"Left HP Out", NULL, "Left DAC_L1 Mixer"}, | |
520 | {"Left HP Com", NULL, "Left HPCOM Mux"}, | |
521 | ||
522 | {"LLOUT", NULL, "Left Line Out"}, | |
523 | {"LLOUT", NULL, "Left Line Out"}, | |
524 | {"HPLOUT", NULL, "Left HP Out"}, | |
525 | {"HPLCOM", NULL, "Left HP Com"}, | |
526 | ||
527 | /* Right Output */ | |
528 | {"Right DAC Mux", "DAC_R1", "Right DAC"}, | |
529 | {"Right DAC Mux", "DAC_R2", "Right DAC"}, | |
530 | {"Right DAC Mux", "DAC_R3", "Right DAC"}, | |
531 | ||
532 | {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"}, | |
533 | {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"}, | |
534 | {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"}, | |
535 | {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"}, | |
536 | {"Right Line Out", NULL, "Right DAC Mux"}, | |
537 | {"Right HP Out", NULL, "Right DAC Mux"}, | |
538 | ||
539 | {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"}, | |
540 | {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"}, | |
541 | {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"}, | |
542 | {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"}, | |
543 | {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"}, | |
544 | ||
545 | {"Right Line Out", NULL, "Right DAC_R1 Mixer"}, | |
546 | {"Mono Out", NULL, "Right DAC_R1 Mixer"}, | |
547 | {"Right HP Out", NULL, "Right DAC_R1 Mixer"}, | |
548 | {"Right HP Com", NULL, "Right HPCOM Mux"}, | |
549 | ||
550 | {"RLOUT", NULL, "Right Line Out"}, | |
551 | {"RLOUT", NULL, "Right Line Out"}, | |
552 | {"HPROUT", NULL, "Right HP Out"}, | |
553 | {"HPRCOM", NULL, "Right HP Com"}, | |
554 | ||
555 | /* Mono Output */ | |
5b006137 JN |
556 | {"MONO_LOUT", NULL, "Mono Out"}, |
557 | {"MONO_LOUT", NULL, "Mono Out"}, | |
44d0a879 VB |
558 | |
559 | /* Left Input */ | |
560 | {"Left Line1L Mux", "single-ended", "LINE1L"}, | |
561 | {"Left Line1L Mux", "differential", "LINE1L"}, | |
562 | ||
563 | {"Left Line2L Mux", "single-ended", "LINE2L"}, | |
564 | {"Left Line2L Mux", "differential", "LINE2L"}, | |
565 | ||
566 | {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, | |
567 | {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, | |
568 | {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, | |
569 | ||
570 | {"Left ADC", NULL, "Left PGA Mixer"}, | |
571 | ||
572 | /* Right Input */ | |
573 | {"Right Line1R Mux", "single-ended", "LINE1R"}, | |
574 | {"Right Line1R Mux", "differential", "LINE1R"}, | |
575 | ||
576 | {"Right Line2R Mux", "single-ended", "LINE2R"}, | |
577 | {"Right Line2R Mux", "differential", "LINE2R"}, | |
578 | ||
579 | {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, | |
580 | {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, | |
581 | {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, | |
582 | ||
583 | {"Right ADC", NULL, "Right PGA Mixer"}, | |
584 | ||
585 | /* Left PGA Bypass */ | |
586 | {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"}, | |
587 | {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"}, | |
588 | {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"}, | |
589 | {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"}, | |
590 | ||
591 | {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"}, | |
592 | {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"}, | |
593 | {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"}, | |
594 | ||
595 | {"Left Line Out", NULL, "Left PGA Bypass Mixer"}, | |
596 | {"Mono Out", NULL, "Left PGA Bypass Mixer"}, | |
597 | {"Left HP Out", NULL, "Left PGA Bypass Mixer"}, | |
598 | ||
599 | /* Right PGA Bypass */ | |
600 | {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"}, | |
601 | {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"}, | |
602 | {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"}, | |
603 | {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"}, | |
604 | ||
605 | {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"}, | |
606 | {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"}, | |
607 | {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"}, | |
608 | {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"}, | |
609 | {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"}, | |
610 | ||
611 | {"Right Line Out", NULL, "Right PGA Bypass Mixer"}, | |
612 | {"Mono Out", NULL, "Right PGA Bypass Mixer"}, | |
613 | {"Right HP Out", NULL, "Right PGA Bypass Mixer"}, | |
614 | ||
615 | /* Left Line2 Bypass */ | |
616 | {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"}, | |
617 | {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"}, | |
618 | {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"}, | |
619 | {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"}, | |
620 | ||
621 | {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"}, | |
622 | {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"}, | |
623 | {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"}, | |
624 | ||
625 | {"Left Line Out", NULL, "Left Line2 Bypass Mixer"}, | |
626 | {"Mono Out", NULL, "Left Line2 Bypass Mixer"}, | |
627 | {"Left HP Out", NULL, "Left Line2 Bypass Mixer"}, | |
628 | ||
629 | /* Right Line2 Bypass */ | |
630 | {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"}, | |
631 | {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"}, | |
632 | {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"}, | |
633 | {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"}, | |
634 | ||
635 | {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"}, | |
636 | {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"}, | |
637 | {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"}, | |
638 | {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"}, | |
639 | {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"}, | |
640 | ||
641 | {"Right Line Out", NULL, "Right Line2 Bypass Mixer"}, | |
642 | {"Mono Out", NULL, "Right Line2 Bypass Mixer"}, | |
643 | {"Right HP Out", NULL, "Right Line2 Bypass Mixer"}, | |
44d0a879 VB |
644 | }; |
645 | ||
646 | static int aic3x_add_widgets(struct snd_soc_codec *codec) | |
647 | { | |
d0cc0d3a MB |
648 | snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets, |
649 | ARRAY_SIZE(aic3x_dapm_widgets)); | |
44d0a879 VB |
650 | |
651 | /* set up audio path interconnects */ | |
d0cc0d3a | 652 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); |
44d0a879 VB |
653 | |
654 | snd_soc_dapm_new_widgets(codec); | |
655 | return 0; | |
656 | } | |
657 | ||
44d0a879 VB |
658 | static int aic3x_hw_params(struct snd_pcm_substream *substream, |
659 | struct snd_pcm_hw_params *params) | |
660 | { | |
661 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
662 | struct snd_soc_device *socdev = rtd->socdev; | |
663 | struct snd_soc_codec *codec = socdev->codec; | |
664 | struct aic3x_priv *aic3x = codec->private_data; | |
4f9c16cc DM |
665 | int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; |
666 | u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; | |
667 | u16 pll_d = 1; | |
44d0a879 | 668 | |
4f9c16cc DM |
669 | /* select data word length */ |
670 | data = | |
671 | aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); | |
672 | switch (params_format(params)) { | |
673 | case SNDRV_PCM_FORMAT_S16_LE: | |
44d0a879 | 674 | break; |
4f9c16cc DM |
675 | case SNDRV_PCM_FORMAT_S20_3LE: |
676 | data |= (0x01 << 4); | |
44d0a879 | 677 | break; |
4f9c16cc DM |
678 | case SNDRV_PCM_FORMAT_S24_LE: |
679 | data |= (0x02 << 4); | |
44d0a879 | 680 | break; |
4f9c16cc DM |
681 | case SNDRV_PCM_FORMAT_S32_LE: |
682 | data |= (0x03 << 4); | |
44d0a879 VB |
683 | break; |
684 | } | |
4f9c16cc DM |
685 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data); |
686 | ||
687 | /* Fsref can be 44100 or 48000 */ | |
688 | fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; | |
689 | ||
690 | /* Try to find a value for Q which allows us to bypass the PLL and | |
691 | * generate CODEC_CLK directly. */ | |
692 | for (pll_q = 2; pll_q < 18; pll_q++) | |
693 | if (aic3x->sysclk / (128 * pll_q) == fsref) { | |
694 | bypass_pll = 1; | |
695 | break; | |
696 | } | |
697 | ||
698 | if (bypass_pll) { | |
699 | pll_q &= 0xf; | |
700 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); | |
701 | aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); | |
702 | } else | |
703 | aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); | |
704 | ||
705 | /* Route Left DAC to left channel input and | |
706 | * right DAC to right channel input */ | |
707 | data = (LDAC2LCH | RDAC2RCH); | |
708 | data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; | |
709 | if (params_rate(params) >= 64000) | |
710 | data |= DUAL_RATE_MODE; | |
44d0a879 VB |
711 | aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data); |
712 | ||
713 | /* codec sample rate select */ | |
4f9c16cc DM |
714 | data = (fsref * 20) / params_rate(params); |
715 | if (params_rate(params) < 64000) | |
716 | data /= 2; | |
717 | data /= 5; | |
718 | data -= 2; | |
44d0a879 VB |
719 | data |= (data << 4); |
720 | aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); | |
721 | ||
4f9c16cc DM |
722 | if (bypass_pll) |
723 | return 0; | |
724 | ||
725 | /* Use PLL | |
726 | * find an apropriate setup for j, d, r and p by iterating over | |
727 | * p and r - j and d are calculated for each fraction. | |
728 | * Up to 128 values are probed, the closest one wins the game. | |
729 | * The sysclk is divided by 1000 to prevent integer overflows. | |
44d0a879 | 730 | */ |
4f9c16cc DM |
731 | codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); |
732 | ||
733 | for (r = 1; r <= 16; r++) | |
734 | for (p = 1; p <= 8; p++) { | |
735 | int clk, tmp = (codec_clk * pll_r * 10) / pll_p; | |
736 | u8 j = tmp / 10000; | |
737 | u16 d = tmp % 10000; | |
738 | ||
739 | if (j > 63) | |
740 | continue; | |
741 | ||
742 | if (d != 0 && aic3x->sysclk < 10000000) | |
743 | continue; | |
744 | ||
745 | /* This is actually 1000 * ((j + (d/10000)) * r) / p | |
746 | * The term had to be converted to get rid of the | |
747 | * division by 10000 */ | |
748 | clk = ((10000 * j * r) + (d * r)) / (10 * p); | |
749 | ||
750 | /* check whether this values get closer than the best | |
751 | * ones we had before */ | |
752 | if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { | |
753 | pll_j = j; pll_d = d; pll_r = r; pll_p = p; | |
754 | last_clk = clk; | |
755 | } | |
756 | ||
757 | /* Early exit for exact matches */ | |
758 | if (clk == codec_clk) | |
759 | break; | |
760 | } | |
761 | ||
762 | if (last_clk == 0) { | |
763 | printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); | |
764 | return -EINVAL; | |
765 | } | |
44d0a879 VB |
766 | |
767 | data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
768 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT)); | |
769 | aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT); | |
770 | aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); | |
771 | aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT); | |
772 | aic3x_write(codec, AIC3X_PLL_PROGD_REG, | |
773 | (pll_d & 0x3F) << PLLD_LSB_SHIFT); | |
774 | ||
44d0a879 VB |
775 | return 0; |
776 | } | |
777 | ||
778 | static int aic3x_mute(struct snd_soc_codec_dai *dai, int mute) | |
779 | { | |
780 | struct snd_soc_codec *codec = dai->codec; | |
781 | u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON; | |
782 | u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON; | |
783 | ||
784 | if (mute) { | |
785 | aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); | |
786 | aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); | |
787 | } else { | |
788 | aic3x_write(codec, LDAC_VOL, ldac_reg); | |
789 | aic3x_write(codec, RDAC_VOL, rdac_reg); | |
790 | } | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
795 | static int aic3x_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai, | |
796 | int clk_id, unsigned int freq, int dir) | |
797 | { | |
798 | struct snd_soc_codec *codec = codec_dai->codec; | |
799 | struct aic3x_priv *aic3x = codec->private_data; | |
800 | ||
4f9c16cc DM |
801 | aic3x->sysclk = freq; |
802 | return 0; | |
44d0a879 VB |
803 | } |
804 | ||
805 | static int aic3x_set_dai_fmt(struct snd_soc_codec_dai *codec_dai, | |
806 | unsigned int fmt) | |
807 | { | |
808 | struct snd_soc_codec *codec = codec_dai->codec; | |
809 | struct aic3x_priv *aic3x = codec->private_data; | |
810 | u8 iface_areg = 0; | |
811 | u8 iface_breg = 0; | |
812 | ||
813 | /* set master/slave audio interface */ | |
814 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
815 | case SND_SOC_DAIFMT_CBM_CFM: | |
816 | aic3x->master = 1; | |
817 | iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; | |
818 | break; | |
819 | case SND_SOC_DAIFMT_CBS_CFS: | |
820 | aic3x->master = 0; | |
821 | break; | |
822 | default: | |
823 | return -EINVAL; | |
824 | } | |
825 | ||
826 | /* interface format */ | |
827 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
828 | case SND_SOC_DAIFMT_I2S: | |
829 | break; | |
830 | case SND_SOC_DAIFMT_DSP_A: | |
831 | iface_breg |= (0x01 << 6); | |
832 | break; | |
833 | case SND_SOC_DAIFMT_RIGHT_J: | |
834 | iface_breg |= (0x02 << 6); | |
835 | break; | |
836 | case SND_SOC_DAIFMT_LEFT_J: | |
837 | iface_breg |= (0x03 << 6); | |
838 | break; | |
839 | default: | |
840 | return -EINVAL; | |
841 | } | |
842 | ||
843 | /* set iface */ | |
844 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); | |
845 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
0be9898a MB |
850 | static int aic3x_set_bias_level(struct snd_soc_codec *codec, |
851 | enum snd_soc_bias_level level) | |
44d0a879 VB |
852 | { |
853 | struct aic3x_priv *aic3x = codec->private_data; | |
854 | u8 reg; | |
855 | ||
0be9898a MB |
856 | switch (level) { |
857 | case SND_SOC_BIAS_ON: | |
44d0a879 VB |
858 | /* all power is driven by DAPM system */ |
859 | if (aic3x->master) { | |
860 | /* enable pll */ | |
861 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
862 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | |
863 | reg | PLL_ENABLE); | |
864 | } | |
865 | break; | |
0be9898a | 866 | case SND_SOC_BIAS_PREPARE: |
44d0a879 | 867 | break; |
0be9898a | 868 | case SND_SOC_BIAS_STANDBY: |
44d0a879 VB |
869 | /* |
870 | * all power is driven by DAPM system, | |
871 | * so output power is safe if bypass was set | |
872 | */ | |
873 | if (aic3x->master) { | |
874 | /* disable pll */ | |
875 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
876 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | |
877 | reg & ~PLL_ENABLE); | |
878 | } | |
879 | break; | |
0be9898a | 880 | case SND_SOC_BIAS_OFF: |
44d0a879 VB |
881 | /* force all power off */ |
882 | reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL); | |
883 | aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON); | |
884 | reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL); | |
885 | aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON); | |
886 | ||
887 | reg = aic3x_read_reg_cache(codec, DAC_PWR); | |
888 | aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON)); | |
889 | ||
890 | reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); | |
891 | aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON); | |
892 | reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); | |
893 | aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON); | |
894 | ||
895 | reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); | |
896 | aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON); | |
897 | reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); | |
898 | aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON); | |
899 | ||
900 | reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); | |
901 | aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON); | |
902 | ||
903 | reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); | |
904 | aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON); | |
905 | reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); | |
906 | aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON); | |
907 | ||
908 | if (aic3x->master) { | |
909 | /* disable pll */ | |
910 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
911 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | |
912 | reg & ~PLL_ENABLE); | |
913 | } | |
914 | break; | |
915 | } | |
0be9898a | 916 | codec->bias_level = level; |
44d0a879 VB |
917 | |
918 | return 0; | |
919 | } | |
920 | ||
54e7e616 DM |
921 | void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state) |
922 | { | |
923 | u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; | |
924 | u8 bit = gpio ? 3: 0; | |
925 | u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit); | |
926 | aic3x_write(codec, reg, val | (!!state << bit)); | |
927 | } | |
928 | EXPORT_SYMBOL_GPL(aic3x_set_gpio); | |
929 | ||
930 | int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio) | |
931 | { | |
932 | u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; | |
933 | u8 val, bit = gpio ? 2: 1; | |
934 | ||
935 | aic3x_read(codec, reg, &val); | |
936 | return (val >> bit) & 1; | |
937 | } | |
938 | EXPORT_SYMBOL_GPL(aic3x_get_gpio); | |
939 | ||
940 | int aic3x_headset_detected(struct snd_soc_codec *codec) | |
941 | { | |
942 | u8 val; | |
943 | aic3x_read(codec, AIC3X_RT_IRQ_FLAGS_REG, &val); | |
944 | return (val >> 2) & 1; | |
945 | } | |
946 | EXPORT_SYMBOL_GPL(aic3x_headset_detected); | |
947 | ||
44d0a879 VB |
948 | #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 |
949 | #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
950 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) | |
951 | ||
952 | struct snd_soc_codec_dai aic3x_dai = { | |
953 | .name = "aic3x", | |
954 | .playback = { | |
955 | .stream_name = "Playback", | |
956 | .channels_min = 1, | |
957 | .channels_max = 2, | |
958 | .rates = AIC3X_RATES, | |
959 | .formats = AIC3X_FORMATS,}, | |
960 | .capture = { | |
961 | .stream_name = "Capture", | |
962 | .channels_min = 1, | |
963 | .channels_max = 2, | |
964 | .rates = AIC3X_RATES, | |
965 | .formats = AIC3X_FORMATS,}, | |
966 | .ops = { | |
967 | .hw_params = aic3x_hw_params, | |
968 | }, | |
969 | .dai_ops = { | |
970 | .digital_mute = aic3x_mute, | |
971 | .set_sysclk = aic3x_set_dai_sysclk, | |
972 | .set_fmt = aic3x_set_dai_fmt, | |
973 | } | |
974 | }; | |
975 | EXPORT_SYMBOL_GPL(aic3x_dai); | |
976 | ||
977 | static int aic3x_suspend(struct platform_device *pdev, pm_message_t state) | |
978 | { | |
979 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
980 | struct snd_soc_codec *codec = socdev->codec; | |
981 | ||
0be9898a | 982 | aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); |
44d0a879 VB |
983 | |
984 | return 0; | |
985 | } | |
986 | ||
987 | static int aic3x_resume(struct platform_device *pdev) | |
988 | { | |
989 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
990 | struct snd_soc_codec *codec = socdev->codec; | |
991 | int i; | |
992 | u8 data[2]; | |
993 | u8 *cache = codec->reg_cache; | |
994 | ||
995 | /* Sync reg_cache with the hardware */ | |
996 | for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) { | |
997 | data[0] = i; | |
998 | data[1] = cache[i]; | |
999 | codec->hw_write(codec->control_data, data, 2); | |
1000 | } | |
1001 | ||
0be9898a | 1002 | aic3x_set_bias_level(codec, codec->suspend_bias_level); |
44d0a879 VB |
1003 | |
1004 | return 0; | |
1005 | } | |
1006 | ||
1007 | /* | |
1008 | * initialise the AIC3X driver | |
1009 | * register the mixer and dsp interfaces with the kernel | |
1010 | */ | |
1011 | static int aic3x_init(struct snd_soc_device *socdev) | |
1012 | { | |
1013 | struct snd_soc_codec *codec = socdev->codec; | |
54e7e616 | 1014 | struct aic3x_setup_data *setup = socdev->codec_data; |
44d0a879 VB |
1015 | int reg, ret = 0; |
1016 | ||
1017 | codec->name = "aic3x"; | |
1018 | codec->owner = THIS_MODULE; | |
1019 | codec->read = aic3x_read_reg_cache; | |
1020 | codec->write = aic3x_write; | |
0be9898a | 1021 | codec->set_bias_level = aic3x_set_bias_level; |
44d0a879 VB |
1022 | codec->dai = &aic3x_dai; |
1023 | codec->num_dai = 1; | |
ae2ff191 | 1024 | codec->reg_cache_size = ARRAY_SIZE(aic3x_reg); |
44d0a879 VB |
1025 | codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL); |
1026 | if (codec->reg_cache == NULL) | |
1027 | return -ENOMEM; | |
1028 | ||
1029 | aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); | |
1030 | aic3x_write(codec, AIC3X_RESET, SOFT_RESET); | |
1031 | ||
1032 | /* register pcms */ | |
1033 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
1034 | if (ret < 0) { | |
1035 | printk(KERN_ERR "aic3x: failed to create pcms\n"); | |
1036 | goto pcm_err; | |
1037 | } | |
1038 | ||
1039 | /* DAC default volume and mute */ | |
1040 | aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); | |
1041 | aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); | |
1042 | ||
1043 | /* DAC to HP default volume and route to Output mixer */ | |
1044 | aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); | |
1045 | aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); | |
1046 | aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1047 | aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1048 | /* DAC to Line Out default volume and route to Output mixer */ | |
1049 | aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1050 | aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1051 | /* DAC to Mono Line Out default volume and route to Output mixer */ | |
1052 | aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1053 | aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1054 | ||
1055 | /* unmute all outputs */ | |
1056 | reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); | |
1057 | aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE); | |
1058 | reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); | |
1059 | aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE); | |
1060 | reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); | |
1061 | aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE); | |
1062 | reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); | |
1063 | aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE); | |
1064 | reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); | |
1065 | aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE); | |
1066 | reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); | |
1067 | aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE); | |
1068 | reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); | |
1069 | aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE); | |
1070 | ||
1071 | /* ADC default volume and unmute */ | |
1072 | aic3x_write(codec, LADC_VOL, DEFAULT_GAIN); | |
1073 | aic3x_write(codec, RADC_VOL, DEFAULT_GAIN); | |
1074 | /* By default route Line1 to ADC PGA mixer */ | |
1075 | aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0); | |
1076 | aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0); | |
1077 | ||
1078 | /* PGA to HP Bypass default volume, disconnect from Output Mixer */ | |
1079 | aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); | |
1080 | aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); | |
1081 | aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); | |
1082 | aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); | |
1083 | /* PGA to Line Out default volume, disconnect from Output Mixer */ | |
1084 | aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); | |
1085 | aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); | |
1086 | /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ | |
1087 | aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1088 | aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1089 | ||
1090 | /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ | |
1091 | aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); | |
1092 | aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); | |
1093 | aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); | |
1094 | aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); | |
1095 | /* Line2 Line Out default volume, disconnect from Output Mixer */ | |
1096 | aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); | |
1097 | aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); | |
1098 | /* Line2 to Mono Out default volume, disconnect from Output Mixer */ | |
1099 | aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1100 | aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1101 | ||
1102 | /* off, with power on */ | |
0be9898a | 1103 | aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
44d0a879 | 1104 | |
54e7e616 DM |
1105 | /* setup GPIO functions */ |
1106 | aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4); | |
1107 | aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4); | |
1108 | ||
44d0a879 VB |
1109 | aic3x_add_controls(codec); |
1110 | aic3x_add_widgets(codec); | |
1111 | ret = snd_soc_register_card(socdev); | |
1112 | if (ret < 0) { | |
1113 | printk(KERN_ERR "aic3x: failed to register card\n"); | |
1114 | goto card_err; | |
1115 | } | |
1116 | ||
1117 | return ret; | |
1118 | ||
1119 | card_err: | |
1120 | snd_soc_free_pcms(socdev); | |
1121 | snd_soc_dapm_free(socdev); | |
1122 | pcm_err: | |
1123 | kfree(codec->reg_cache); | |
1124 | return ret; | |
1125 | } | |
1126 | ||
1127 | static struct snd_soc_device *aic3x_socdev; | |
1128 | ||
1129 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1130 | /* | |
1131 | * AIC3X 2 wire address can be up to 4 devices with device addresses | |
1132 | * 0x18, 0x19, 0x1A, 0x1B | |
1133 | */ | |
1134 | static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; | |
1135 | ||
1136 | /* Magic definition of all other variables and things */ | |
1137 | I2C_CLIENT_INSMOD; | |
1138 | ||
1139 | static struct i2c_driver aic3x_i2c_driver; | |
1140 | static struct i2c_client client_template; | |
1141 | ||
1142 | /* | |
1143 | * If the i2c layer weren't so broken, we could pass this kind of data | |
1144 | * around | |
1145 | */ | |
1146 | static int aic3x_codec_probe(struct i2c_adapter *adap, int addr, int kind) | |
1147 | { | |
1148 | struct snd_soc_device *socdev = aic3x_socdev; | |
1149 | struct aic3x_setup_data *setup = socdev->codec_data; | |
1150 | struct snd_soc_codec *codec = socdev->codec; | |
1151 | struct i2c_client *i2c; | |
1152 | int ret; | |
1153 | ||
1154 | if (addr != setup->i2c_address) | |
1155 | return -ENODEV; | |
1156 | ||
1157 | client_template.adapter = adap; | |
1158 | client_template.addr = addr; | |
1159 | ||
1160 | i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); | |
1161 | if (i2c == NULL) { | |
1162 | kfree(codec); | |
1163 | return -ENOMEM; | |
1164 | } | |
1165 | i2c_set_clientdata(i2c, codec); | |
1166 | codec->control_data = i2c; | |
1167 | ||
1168 | ret = i2c_attach_client(i2c); | |
1169 | if (ret < 0) { | |
1170 | printk(KERN_ERR "aic3x: failed to attach codec at addr %x\n", | |
1171 | addr); | |
1172 | goto err; | |
1173 | } | |
1174 | ||
1175 | ret = aic3x_init(socdev); | |
1176 | if (ret < 0) { | |
1177 | printk(KERN_ERR "aic3x: failed to initialise AIC3X\n"); | |
1178 | goto err; | |
1179 | } | |
1180 | return ret; | |
1181 | ||
1182 | err: | |
1183 | kfree(codec); | |
1184 | kfree(i2c); | |
1185 | return ret; | |
1186 | } | |
1187 | ||
1188 | static int aic3x_i2c_detach(struct i2c_client *client) | |
1189 | { | |
1190 | struct snd_soc_codec *codec = i2c_get_clientdata(client); | |
1191 | i2c_detach_client(client); | |
1192 | kfree(codec->reg_cache); | |
1193 | kfree(client); | |
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static int aic3x_i2c_attach(struct i2c_adapter *adap) | |
1198 | { | |
1199 | return i2c_probe(adap, &addr_data, aic3x_codec_probe); | |
1200 | } | |
1201 | ||
1202 | /* machine i2c codec control layer */ | |
1203 | static struct i2c_driver aic3x_i2c_driver = { | |
1204 | .driver = { | |
1205 | .name = "aic3x I2C Codec", | |
1206 | .owner = THIS_MODULE, | |
1207 | }, | |
44d0a879 VB |
1208 | .attach_adapter = aic3x_i2c_attach, |
1209 | .detach_client = aic3x_i2c_detach, | |
44d0a879 VB |
1210 | }; |
1211 | ||
1212 | static struct i2c_client client_template = { | |
1213 | .name = "AIC3X", | |
1214 | .driver = &aic3x_i2c_driver, | |
1215 | }; | |
54e7e616 DM |
1216 | |
1217 | static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len) | |
1218 | { | |
1219 | value[0] = i2c_smbus_read_byte_data(client, value[0]); | |
1220 | return (len == 1); | |
1221 | } | |
44d0a879 VB |
1222 | #endif |
1223 | ||
1224 | static int aic3x_probe(struct platform_device *pdev) | |
1225 | { | |
1226 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1227 | struct aic3x_setup_data *setup; | |
1228 | struct snd_soc_codec *codec; | |
1229 | struct aic3x_priv *aic3x; | |
1230 | int ret = 0; | |
1231 | ||
1232 | printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION); | |
1233 | ||
1234 | setup = socdev->codec_data; | |
1235 | codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); | |
1236 | if (codec == NULL) | |
1237 | return -ENOMEM; | |
1238 | ||
1239 | aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL); | |
1240 | if (aic3x == NULL) { | |
1241 | kfree(codec); | |
1242 | return -ENOMEM; | |
1243 | } | |
1244 | ||
1245 | codec->private_data = aic3x; | |
1246 | socdev->codec = codec; | |
1247 | mutex_init(&codec->mutex); | |
1248 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
1249 | INIT_LIST_HEAD(&codec->dapm_paths); | |
1250 | ||
1251 | aic3x_socdev = socdev; | |
1252 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1253 | if (setup->i2c_address) { | |
1254 | normal_i2c[0] = setup->i2c_address; | |
1255 | codec->hw_write = (hw_write_t) i2c_master_send; | |
54e7e616 | 1256 | codec->hw_read = (hw_read_t) aic3x_i2c_read; |
44d0a879 VB |
1257 | ret = i2c_add_driver(&aic3x_i2c_driver); |
1258 | if (ret != 0) | |
1259 | printk(KERN_ERR "can't add i2c driver"); | |
1260 | } | |
1261 | #else | |
1262 | /* Add other interfaces here */ | |
1263 | #endif | |
1264 | return ret; | |
1265 | } | |
1266 | ||
1267 | static int aic3x_remove(struct platform_device *pdev) | |
1268 | { | |
1269 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1270 | struct snd_soc_codec *codec = socdev->codec; | |
1271 | ||
1272 | /* power down chip */ | |
1273 | if (codec->control_data) | |
0be9898a | 1274 | aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); |
44d0a879 VB |
1275 | |
1276 | snd_soc_free_pcms(socdev); | |
1277 | snd_soc_dapm_free(socdev); | |
1278 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1279 | i2c_del_driver(&aic3x_i2c_driver); | |
1280 | #endif | |
1281 | kfree(codec->private_data); | |
1282 | kfree(codec); | |
1283 | ||
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | struct snd_soc_codec_device soc_codec_dev_aic3x = { | |
1288 | .probe = aic3x_probe, | |
1289 | .remove = aic3x_remove, | |
1290 | .suspend = aic3x_suspend, | |
1291 | .resume = aic3x_resume, | |
1292 | }; | |
1293 | EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x); | |
1294 | ||
1295 | MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); | |
1296 | MODULE_AUTHOR("Vladimir Barinov"); | |
1297 | MODULE_LICENSE("GPL"); |