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ASoC: Don't restart an already running WM8958 DSP2
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
44d0a879 43#include <linux/platform_device.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
44d0a879 49#include <sound/initval.h>
7565fc38 50#include <sound/tlv.h>
5193d62f 51#include <sound/tlv320aic3x.h>
44d0a879
VB		 52
53#include "tlv320aic3x.h"
54
07779fdd
JN		 55#define AIC3X_NUM_SUPPLIES 4
56static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD", /* I/O Voltage */
58 "DVDD", /* Digital Core Voltage */
59 "AVDD", /* Analog DAC Voltage */
60 "DRVDD", /* ADC Analog and Output Driver Voltage */
61};
44d0a879 62
414c73ab
JN		 63static LIST_HEAD(reset_list);
64
5a895f8a
JN		 65struct aic3x_priv;
66
67struct aic3x_disable_nb {
68 struct notifier_block nb;
69 struct aic3x_priv *aic3x;
70};
71
44d0a879
VB		 72/* codec private data */
73struct aic3x_priv {
5a895f8a 74 struct snd_soc_codec *codec;
07779fdd 75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 77 enum snd_soc_control_type control_type;
78 struct aic3x_setup_data *setup;
79 void *control_data;
44d0a879 80 unsigned int sysclk;
414c73ab 81 struct list_head list;
44d0a879 82 int master;
5193d62f 83 int gpio_reset;
6c1a7d40 84 int power;
6184f105
RC		 85#define AIC3X_MODEL_3X 0
86#define AIC3X_MODEL_33 1
87#define AIC3X_MODEL_3007 2
88 u16 model;
44d0a879
VB		 89};
90
91/*
92 * AIC3X register cache
93 * We can't read the AIC3X register space when we are
94 * using 2 wire for device control, so we cache them instead.
95 * There is no point in caching the reset register
96 */
97static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
98 0x00, 0x00, 0x00, 0x10, /* 0 */
99 0x04, 0x00, 0x00, 0x00, /* 4 */
100 0x00, 0x00, 0x00, 0x01, /* 8 */
101 0x00, 0x00, 0x00, 0x80, /* 12 */
102 0x80, 0xff, 0xff, 0x78, /* 16 */
103 0x78, 0x78, 0x78, 0x78, /* 20 */
104 0x78, 0x00, 0x00, 0xfe, /* 24 */
105 0x00, 0x00, 0xfe, 0x00, /* 28 */
106 0x18, 0x18, 0x00, 0x00, /* 32 */
107 0x00, 0x00, 0x00, 0x00, /* 36 */
108 0x00, 0x00, 0x00, 0x80, /* 40 */
109 0x80, 0x00, 0x00, 0x00, /* 44 */
110 0x00, 0x00, 0x00, 0x04, /* 48 */
111 0x00, 0x00, 0x00, 0x00, /* 52 */
112 0x00, 0x00, 0x04, 0x00, /* 56 */
113 0x00, 0x00, 0x00, 0x00, /* 60 */
114 0x00, 0x04, 0x00, 0x00, /* 64 */
115 0x00, 0x00, 0x00, 0x00, /* 68 */
116 0x04, 0x00, 0x00, 0x00, /* 72 */
117 0x00, 0x00, 0x00, 0x00, /* 76 */
118 0x00, 0x00, 0x00, 0x00, /* 80 */
119 0x00, 0x00, 0x00, 0x00, /* 84 */
120 0x00, 0x00, 0x00, 0x00, /* 88 */
121 0x00, 0x00, 0x00, 0x00, /* 92 */
122 0x00, 0x00, 0x00, 0x00, /* 96 */
123 0x00, 0x00, 0x02, /* 100 */
124};
125
126/*
9900daa8
JN		 127 * read from the aic3x register space. Only use for this function is if
128 * wanting to read volatile bits from those registers that has both read-only
129 * and read/write bits. All other cases should use snd_soc_read.
44d0a879 130 */
54e7e616
DM		 131static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
132 u8 *value)
44d0a879
VB		 133{
134 u8 *cache = codec->reg_cache;
44d0a879 135
5a895f8a
JN		 136 if (codec->cache_only)
137 return -EINVAL;
44d0a879 138 if (reg >= AIC3X_CACHEREGNUM)
9900daa8 139 return -1;
5f345346 140
9900daa8
JN		 141 *value = codec->hw_read(codec, reg);
142 cache[reg] = *value;
54e7e616 143
54e7e616
DM		 144 return 0;
145}
146
44d0a879
VB		 147#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
148{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
149 .info = snd_soc_info_volsw, \
150 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
151 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
152
153/*
154 * All input lines are connected when !0xf and disconnected with 0xf bit field,
155 * so we have to use specific dapm_put call for input mixer
156 */
157static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
158 struct snd_ctl_elem_value *ucontrol)
159{
160 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
4453dba5
EN		 161 struct soc_mixer_control *mc =
162 (struct soc_mixer_control *)kcontrol->private_value;
163 unsigned int reg = mc->reg;
164 unsigned int shift = mc->shift;
165 int max = mc->max;
166 unsigned int mask = (1 << fls(max)) - 1;
167 unsigned int invert = mc->invert;
44d0a879
VB		 168 unsigned short val, val_mask;
169 int ret;
170 struct snd_soc_dapm_path *path;
171 int found = 0;
172
173 val = (ucontrol->value.integer.value[0] & mask);
174
175 mask = 0xf;
176 if (val)
177 val = mask;
178
179 if (invert)
180 val = mask - val;
181 val_mask = mask << shift;
182 val = val << shift;
183
184 mutex_lock(&widget->codec->mutex);
185
186 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
187 /* find dapm widget path assoc with kcontrol */
8ddab3f5 188 list_for_each_entry(path, &widget->dapm->card->paths, list) {
44d0a879
VB		 189 if (path->kcontrol != kcontrol)
190 continue;
191
192 /* found, now check type */
193 found = 1;
194 if (val)
195 /* new connection */
196 path->connect = invert ? 0 : 1;
197 else
198 /* old connection must be powered down */
199 path->connect = invert ? 1 : 0;
200 break;
201 }
202
203 if (found)
ce6120cc 204 snd_soc_dapm_sync(widget->dapm);
44d0a879
VB		 205 }
206
207 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
208
209 mutex_unlock(&widget->codec->mutex);
210 return ret;
211}
212
213static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
214static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
215static const char *aic3x_left_hpcom_mux[] =
216 { "differential of HPLOUT", "constant VCM", "single-ended" };
217static const char *aic3x_right_hpcom_mux[] =
218 { "differential of HPROUT", "constant VCM", "single-ended",
219 "differential of HPLCOM", "external feedback" };
220static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 221static const char *aic3x_adc_hpf[] =
222 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 223
224#define LDAC_ENUM 0
225#define RDAC_ENUM 1
226#define LHPCOM_ENUM 2
227#define RHPCOM_ENUM 3
228#define LINE1L_ENUM 4
229#define LINE1R_ENUM 5
230#define LINE2L_ENUM 6
231#define LINE2R_ENUM 7
4d20f70a 232#define ADC_HPF_ENUM 8
44d0a879
VB		 233
234static const struct soc_enum aic3x_enum[] = {
235 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
236 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
237 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
238 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
239 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
240 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
241 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
242 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 243 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 244};
245
7565fc38
JN		 246/*
247 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
248 */
249static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
250/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
251static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
252/*
253 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
254 * Step size is approximately 0.5 dB over most of the scale but increasing
255 * near the very low levels.
256 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
257 * but having increasing dB difference below that (and where it doesn't count
258 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
259 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
260 */
261static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
262
44d0a879
VB		 263static const struct snd_kcontrol_new aic3x_snd_controls[] = {
264 /* Output */
7565fc38
JN		 265 SOC_DOUBLE_R_TLV("PCM Playback Volume",
266 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 267
098b1718
JN		 268 /*
269 * Output controls that map to output mixer switches. Note these are
270 * only for swapped L-to-R and R-to-L routes. See below stereo controls
271 * for direct L-to-L and R-to-R routes.
272 */
273 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
274 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
275 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
276 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
277 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
278 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
279
280 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
281 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
282 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
283 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
284 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
285 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
286
287 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
288 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
289 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
290 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
291 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
292 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
293
294 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
295 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
296 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
297 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
299 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
300
301 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
302 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
303 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
304 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
305 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
306 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
307
308 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
309 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
310 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
311 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
312 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
313 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
314
315 /* Stereo output controls for direct L-to-L and R-to-R routes */
316 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
317 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
318 0, 118, 1, output_stage_tlv),
319 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
320 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
321 0, 118, 1, output_stage_tlv),
7565fc38
JN		 322 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
323 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
324 0, 118, 1, output_stage_tlv),
098b1718
JN		 325
326 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
327 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 328 0, 118, 1, output_stage_tlv),
098b1718
JN		 329 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
330 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 331 0, 118, 1, output_stage_tlv),
7565fc38
JN		 332 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
333 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
334 0, 118, 1, output_stage_tlv),
098b1718
JN		 335
336 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
337 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 338 0, 118, 1, output_stage_tlv),
098b1718
JN		 339 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
340 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 341 0, 118, 1, output_stage_tlv),
7565fc38
JN		 342 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
343 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
344 0, 118, 1, output_stage_tlv),
098b1718
JN		 345
346 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
347 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 348 0, 118, 1, output_stage_tlv),
098b1718
JN		 349 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
350 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 351 0, 118, 1, output_stage_tlv),
7565fc38
JN		 352 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
353 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
354 0, 118, 1, output_stage_tlv),
098b1718
JN		 355
356 /* Output pin mute controls */
357 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
358 0x01, 0),
359 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
360 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
361 0x01, 0),
f9bc0297 362 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 363 0x01, 0),
44d0a879
VB		 364
365 /*
366 * Note: enable Automatic input Gain Controller with care. It can
367 * adjust PGA to max value when ADC is on and will never go back.
368 */
369 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
370
371 /* Input */
7565fc38
JN		 372 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
373 0, 119, 0, adc_tlv),
44d0a879 374 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 375
376 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 377};
378
6184f105
RC		 379/*
380 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
381 */
382static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
383
384static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
385 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
386
44d0a879
VB		 387/* Left DAC Mux */
388static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
389SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
390
391/* Right DAC Mux */
392static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
393SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
394
395/* Left HPCOM Mux */
396static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
397SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
398
399/* Right HPCOM Mux */
400static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
401SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
402
c3b79e05
JN		 403/* Left Line Mixer */
404static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
405 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
408 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
409 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
410 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 411};
412
c3b79e05
JN		 413/* Right Line Mixer */
414static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
415 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
419 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
420 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
421};
422
423/* Mono Mixer */
424static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
425 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
428 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
429 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
430 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
431};
432
433/* Left HP Mixer */
434static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
435 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
439 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
440 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
441};
442
443/* Right HP Mixer */
444static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
445 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
450 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
451};
452
453/* Left HPCOM Mixer */
454static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
455 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
461};
462
463/* Right HPCOM Mixer */
464static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
465 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 471};
472
473/* Left PGA Mixer */
474static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
475 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 476 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 477 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
478 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 479 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 480};
481
482/* Right PGA Mixer */
483static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
484 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 485 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 486 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 487 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 488 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
489};
490
491/* Left Line1 Mux */
492static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
493SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
494
495/* Right Line1 Mux */
496static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
497SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
498
499/* Left Line2 Mux */
500static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
501SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
502
503/* Right Line2 Mux */
504static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
505SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
506
44d0a879
VB		 507static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
508 /* Left DAC to Left Outputs */
509 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
510 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
511 &aic3x_left_dac_mux_controls),
44d0a879
VB		 512 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
513 &aic3x_left_hpcom_mux_controls),
514 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
515 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
516 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
517
518 /* Right DAC to Right Outputs */
519 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
520 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
521 &aic3x_right_dac_mux_controls),
44d0a879
VB		 522 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
523 &aic3x_right_hpcom_mux_controls),
524 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
525 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
526 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
527
528 /* Mono Output */
529 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
530
54f01916 531 /* Inputs to Left ADC */
44d0a879
VB		 532 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
533 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
534 &aic3x_left_pga_mixer_controls[0],
535 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
536 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
537 &aic3x_left_line1_mux_controls),
54f01916
DM		 538 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
539 &aic3x_left_line1_mux_controls),
44d0a879
VB		 540 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
541 &aic3x_left_line2_mux_controls),
542
54f01916 543 /* Inputs to Right ADC */
44d0a879
VB		 544 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
545 LINE1R_2_RADC_CTRL, 2, 0),
546 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
547 &aic3x_right_pga_mixer_controls[0],
548 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 549 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
550 &aic3x_right_line1_mux_controls),
44d0a879
VB		 551 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
552 &aic3x_right_line1_mux_controls),
553 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
554 &aic3x_right_line2_mux_controls),
555
ee15ffdb
JN		 556 /*
557 * Not a real mic bias widget but similar function. This is for dynamic
558 * control of GPIO1 digital mic modulator clock output function when
559 * using digital mic.
560 */
561 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
562 AIC3X_GPIO1_REG, 4, 0xf,
563 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
564 AIC3X_GPIO1_FUNC_DISABLED),
565
566 /*
567 * Also similar function like mic bias. Selects digital mic with
568 * configurable oversampling rate instead of ADC converter.
569 */
570 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
571 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
572 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
573 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
574 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
575 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
576
44d0a879 577 /* Mic Bias */
0bd72a3d
JN		 578 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
579 MICBIAS_CTRL, 6, 3, 1, 0),
580 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
581 MICBIAS_CTRL, 6, 3, 2, 0),
582 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
583 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 584
c3b79e05
JN		 585 /* Output mixers */
586 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
587 &aic3x_left_line_mixer_controls[0],
588 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
589 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
590 &aic3x_right_line_mixer_controls[0],
591 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
592 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
593 &aic3x_mono_mixer_controls[0],
594 ARRAY_SIZE(aic3x_mono_mixer_controls)),
595 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
596 &aic3x_left_hp_mixer_controls[0],
597 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
598 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
599 &aic3x_right_hp_mixer_controls[0],
600 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
601 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
602 &aic3x_left_hpcom_mixer_controls[0],
603 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
604 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
605 &aic3x_right_hpcom_mixer_controls[0],
606 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 607
608 SND_SOC_DAPM_OUTPUT("LLOUT"),
609 SND_SOC_DAPM_OUTPUT("RLOUT"),
610 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
611 SND_SOC_DAPM_OUTPUT("HPLOUT"),
612 SND_SOC_DAPM_OUTPUT("HPROUT"),
613 SND_SOC_DAPM_OUTPUT("HPLCOM"),
614 SND_SOC_DAPM_OUTPUT("HPRCOM"),
615
616 SND_SOC_DAPM_INPUT("MIC3L"),
617 SND_SOC_DAPM_INPUT("MIC3R"),
618 SND_SOC_DAPM_INPUT("LINE1L"),
619 SND_SOC_DAPM_INPUT("LINE1R"),
620 SND_SOC_DAPM_INPUT("LINE2L"),
621 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 622
623 /*
624 * Virtual output pin to detection block inside codec. This can be
625 * used to keep codec bias on if gpio or detection features are needed.
626 * Force pin on or construct a path with an input jack and mic bias
627 * widgets.
628 */
629 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 630};
631
6184f105
RC		 632static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
633 /* Class-D outputs */
634 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
635 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
636
637 SND_SOC_DAPM_OUTPUT("SPOP"),
638 SND_SOC_DAPM_OUTPUT("SPOM"),
639};
640
d0cc0d3a 641static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 642 /* Left Input */
643 {"Left Line1L Mux", "single-ended", "LINE1L"},
644 {"Left Line1L Mux", "differential", "LINE1L"},
645
646 {"Left Line2L Mux", "single-ended", "LINE2L"},
647 {"Left Line2L Mux", "differential", "LINE2L"},
648
649 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 650 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 651 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
652 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 653 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 654
655 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 656 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 657
658 /* Right Input */
659 {"Right Line1R Mux", "single-ended", "LINE1R"},
660 {"Right Line1R Mux", "differential", "LINE1R"},
661
662 {"Right Line2R Mux", "single-ended", "LINE2R"},
663 {"Right Line2R Mux", "differential", "LINE2R"},
664
54f01916 665 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 666 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
667 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 668 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 669 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
670
671 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 672 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 673
ee15ffdb
JN		 674 /*
675 * Logical path between digital mic enable and GPIO1 modulator clock
676 * output function
677 */
678 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
679 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
680 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 681
682 /* Left DAC Output */
683 {"Left DAC Mux", "DAC_L1", "Left DAC"},
684 {"Left DAC Mux", "DAC_L2", "Left DAC"},
685 {"Left DAC Mux", "DAC_L3", "Left DAC"},
686
687 /* Right DAC Output */
688 {"Right DAC Mux", "DAC_R1", "Right DAC"},
689 {"Right DAC Mux", "DAC_R2", "Right DAC"},
690 {"Right DAC Mux", "DAC_R3", "Right DAC"},
691
692 /* Left Line Output */
693 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
694 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
695 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
696 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
697 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
698 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
699
700 {"Left Line Out", NULL, "Left Line Mixer"},
701 {"Left Line Out", NULL, "Left DAC Mux"},
702 {"LLOUT", NULL, "Left Line Out"},
703
704 /* Right Line Output */
705 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
706 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
707 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
708 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
709 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
710 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
711
712 {"Right Line Out", NULL, "Right Line Mixer"},
713 {"Right Line Out", NULL, "Right DAC Mux"},
714 {"RLOUT", NULL, "Right Line Out"},
715
716 /* Mono Output */
717 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
718 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
719 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
720 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
721 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
722 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
723
724 {"Mono Out", NULL, "Mono Mixer"},
725 {"MONO_LOUT", NULL, "Mono Out"},
726
727 /* Left HP Output */
728 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
729 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
730 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
731 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
732 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
733 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
734
735 {"Left HP Out", NULL, "Left HP Mixer"},
736 {"Left HP Out", NULL, "Left DAC Mux"},
737 {"HPLOUT", NULL, "Left HP Out"},
738
739 /* Right HP Output */
740 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
741 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
742 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
743 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
744 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
745 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
746
747 {"Right HP Out", NULL, "Right HP Mixer"},
748 {"Right HP Out", NULL, "Right DAC Mux"},
749 {"HPROUT", NULL, "Right HP Out"},
750
751 /* Left HPCOM Output */
752 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
753 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
754 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
755 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
756 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
757 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
758
759 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
760 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
761 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
762 {"Left HP Com", NULL, "Left HPCOM Mux"},
763 {"HPLCOM", NULL, "Left HP Com"},
764
765 /* Right HPCOM Output */
766 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
767 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
768 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
769 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
770 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
771 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
772
773 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
774 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
775 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
776 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
777 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
778 {"Right HP Com", NULL, "Right HPCOM Mux"},
779 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 780};
781
6184f105
RC		 782static const struct snd_soc_dapm_route intercon_3007[] = {
783 /* Class-D outputs */
784 {"Left Class-D Out", NULL, "Left Line Out"},
785 {"Right Class-D Out", NULL, "Left Line Out"},
786 {"SPOP", NULL, "Left Class-D Out"},
787 {"SPOM", NULL, "Right Class-D Out"},
788};
789
44d0a879
VB		 790static int aic3x_add_widgets(struct snd_soc_codec *codec)
791{
6184f105 792 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 793 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 794
ce6120cc 795 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
d0cc0d3a 796 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 797
798 /* set up audio path interconnects */
ce6120cc 799 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
44d0a879 800
6184f105 801 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 802 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 803 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 804 snd_soc_dapm_add_routes(dapm, intercon_3007,
805 ARRAY_SIZE(intercon_3007));
6184f105
RC		 806 }
807
44d0a879
VB		 808 return 0;
809}
810
44d0a879 811static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 812 struct snd_pcm_hw_params *params,
813 struct snd_soc_dai *dai)
44d0a879
VB		 814{
815 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 816 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 817 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 818 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 819 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
820 u16 d, pll_d = 1;
06c71282 821 u8 reg;
255173b4 822 int clk;
44d0a879 823
4f9c16cc 824 /* select data word length */
e18eca43 825 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 826 switch (params_format(params)) {
827 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 828 break;
4f9c16cc
DM		 829 case SNDRV_PCM_FORMAT_S20_3LE:
830 data |= (0x01 << 4);
44d0a879 831 break;
4f9c16cc
DM		 832 case SNDRV_PCM_FORMAT_S24_LE:
833 data |= (0x02 << 4);
44d0a879 834 break;
4f9c16cc
DM		 835 case SNDRV_PCM_FORMAT_S32_LE:
836 data |= (0x03 << 4);
44d0a879
VB		 837 break;
838 }
e18eca43 839 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 840
841 /* Fsref can be 44100 or 48000 */
842 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
843
844 /* Try to find a value for Q which allows us to bypass the PLL and
845 * generate CODEC_CLK directly. */
846 for (pll_q = 2; pll_q < 18; pll_q++)
847 if (aic3x->sysclk / (128 * pll_q) == fsref) {
848 bypass_pll = 1;
849 break;
850 }
851
852 if (bypass_pll) {
853 pll_q &= 0xf;
e18eca43
JN		 854 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
855 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 856 /* disable PLL if it is bypassed */
e18eca43
JN		 857 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
858 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
06c71282
C		 859
860 } else {
e18eca43 861 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 862 /* enable PLL when it is used */
e18eca43
JN		 863 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
864 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
06c71282 865 }
4f9c16cc
DM		 866
867 /* Route Left DAC to left channel input and
868 * right DAC to right channel input */
869 data = (LDAC2LCH | RDAC2RCH);
870 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
871 if (params_rate(params) >= 64000)
872 data |= DUAL_RATE_MODE;
e18eca43 873 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 874
875 /* codec sample rate select */
4f9c16cc
DM		 876 data = (fsref * 20) / params_rate(params);
877 if (params_rate(params) < 64000)
878 data /= 2;
879 data /= 5;
880 data -= 2;
44d0a879 881 data |= (data << 4);
e18eca43 882 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 883
4f9c16cc
DM		 884 if (bypass_pll)
885 return 0;
886
25985edc 887 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 888 * one wins the game. Try with d==0 first, next with d!=0.
889 * Constraints for j are according to the datasheet.
4f9c16cc 890 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 891 */
255173b4 892
4f9c16cc
DM		 893 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
894
895 for (r = 1; r <= 16; r++)
896 for (p = 1; p <= 8; p++) {
255173b4
PM		 897 for (j = 4; j <= 55; j++) {
898 /* This is actually 1000*((j+(d/10000))*r)/p
899 * The term had to be converted to get
900 * rid of the division by 10000; d = 0 here
901 */
5baf8315 902 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 903
904 /* Check whether this values get closer than
905 * the best ones we had before
906 */
5baf8315 907 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 908 abs(codec_clk - last_clk)) {
909 pll_j = j; pll_d = 0;
910 pll_r = r; pll_p = p;
5baf8315 911 last_clk = tmp_clk;
255173b4
PM		 912 }
913
914 /* Early exit for exact matches */
5baf8315 915 if (tmp_clk == codec_clk)
255173b4
PM		 916 goto found;
917 }
918 }
4f9c16cc 919
255173b4
PM		 920 /* try with d != 0 */
921 for (p = 1; p <= 8; p++) {
922 j = codec_clk * p / 1000;
4f9c16cc 923
255173b4
PM		 924 if (j < 4 || j > 11)
925 continue;
4f9c16cc 926
255173b4
PM		 927 /* do not use codec_clk here since we'd loose precision */
928 d = ((2048 * p * fsref) - j * aic3x->sysclk)
929 * 100 / (aic3x->sysclk/100);
4f9c16cc 930
255173b4 931 clk = (10000 * j + d) / (10 * p);
4f9c16cc 932
255173b4
PM		 933 /* check whether this values get closer than the best
934 * ones we had before */
935 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
936 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
937 last_clk = clk;
4f9c16cc
DM		 938 }
939
255173b4
PM		 940 /* Early exit for exact matches */
941 if (clk == codec_clk)
942 goto found;
943 }
944
4f9c16cc
DM		 945 if (last_clk == 0) {
946 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
947 return -EINVAL;
948 }
44d0a879 949
255173b4 950found:
e18eca43
JN		 951 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
952 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
953 data | (pll_p << PLLP_SHIFT));
954 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
955 pll_r << PLLR_SHIFT);
956 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
957 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
958 (pll_d >> 6) << PLLD_MSB_SHIFT);
959 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
960 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 961
44d0a879
VB		 962 return 0;
963}
964
e550e17f 965static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 966{
967 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 968 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
969 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 970
971 if (mute) {
e18eca43
JN		 972 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
973 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 974 } else {
e18eca43
JN		 975 snd_soc_write(codec, LDAC_VOL, ldac_reg);
976 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 977 }
978
979 return 0;
980}
981
e550e17f 982static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 983 int clk_id, unsigned int freq, int dir)
984{
985 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 986 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 987
4f9c16cc
DM		 988 aic3x->sysclk = freq;
989 return 0;
44d0a879
VB		 990}
991
e550e17f 992static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 993 unsigned int fmt)
994{
995 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 996 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 997 u8 iface_areg, iface_breg;
a24f4f68 998 int delay = 0;
81971a14 999
e18eca43
JN		 1000 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1001 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1002
1003 /* set master/slave audio interface */
1004 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1005 case SND_SOC_DAIFMT_CBM_CFM:
1006 aic3x->master = 1;
1007 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1008 break;
1009 case SND_SOC_DAIFMT_CBS_CFS:
1010 aic3x->master = 0;
1011 break;
1012 default:
1013 return -EINVAL;
1014 }
1015
4b7d2831
JN		 1016 /*
1017 * match both interface format and signal polarities since they
1018 * are fixed
1019 */
1020 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1021 SND_SOC_DAIFMT_INV_MASK)) {
1022 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1023 break;
a24f4f68
TK		 1024 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1025 delay = 1;
4b7d2831 1026 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1027 iface_breg |= (0x01 << 6);
1028 break;
4b7d2831 1029 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1030 iface_breg |= (0x02 << 6);
1031 break;
4b7d2831 1032 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1033 iface_breg |= (0x03 << 6);
1034 break;
1035 default:
1036 return -EINVAL;
1037 }
1038
1039 /* set iface */
e18eca43
JN		 1040 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1041 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1042 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1043
1044 return 0;
1045}
1046
6c1a7d40
JN		 1047static int aic3x_init_3007(struct snd_soc_codec *codec)
1048{
1049 u8 tmp1, tmp2, *cache = codec->reg_cache;
1050
1051 /*
1052 * There is no need to cache writes to undocumented page 0xD but
1053 * respective page 0 register cache entries must be preserved
1054 */
1055 tmp1 = cache[0xD];
1056 tmp2 = cache[0x8];
1057 /* Class-D speaker driver init; datasheet p. 46 */
1058 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1059 snd_soc_write(codec, 0xD, 0x0D);
1060 snd_soc_write(codec, 0x8, 0x5C);
1061 snd_soc_write(codec, 0x8, 0x5D);
1062 snd_soc_write(codec, 0x8, 0x5C);
1063 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1064 cache[0xD] = tmp1;
1065 cache[0x8] = tmp2;
1066
1067 return 0;
1068}
1069
5a895f8a
JN		 1070static int aic3x_regulator_event(struct notifier_block *nb,
1071 unsigned long event, void *data)
1072{
1073 struct aic3x_disable_nb *disable_nb =
1074 container_of(nb, struct aic3x_disable_nb, nb);
1075 struct aic3x_priv *aic3x = disable_nb->aic3x;
1076
1077 if (event & REGULATOR_EVENT_DISABLE) {
1078 /*
1079 * Put codec to reset and require cache sync as at least one
1080 * of the supplies was disabled
1081 */
79ee820d 1082 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a
JN		 1083 gpio_set_value(aic3x->gpio_reset, 0);
1084 aic3x->codec->cache_sync = 1;
1085 }
1086
1087 return 0;
1088}
1089
6c1a7d40
JN		 1090static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1091{
1092 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1093 int i, ret;
1094 u8 *cache = codec->reg_cache;
1095
1096 if (power) {
1097 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1098 aic3x->supplies);
1099 if (ret)
1100 goto out;
1101 aic3x->power = 1;
5a895f8a
JN		 1102 /*
1103 * Reset release and cache sync is necessary only if some
1104 * supply was off or if there were cached writes
1105 */
1106 if (!codec->cache_sync)
1107 goto out;
1108
79ee820d 1109 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1110 udelay(1);
1111 gpio_set_value(aic3x->gpio_reset, 1);
1112 }
1113
1114 /* Sync reg_cache with the hardware */
1115 codec->cache_only = 0;
1116 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++)
1117 snd_soc_write(codec, i, cache[i]);
1118 if (aic3x->model == AIC3X_MODEL_3007)
1119 aic3x_init_3007(codec);
1120 codec->cache_sync = 0;
1121 } else {
1122 aic3x->power = 0;
5a895f8a
JN		 1123 /* HW writes are needless when bias is off */
1124 codec->cache_only = 1;
6c1a7d40
JN		 1125 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1126 aic3x->supplies);
1127 }
1128out:
1129 return ret;
1130}
1131
0be9898a
MB		 1132static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1133 enum snd_soc_bias_level level)
44d0a879 1134{
b2c812e2 1135 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 1136 u8 reg;
1137
0be9898a
MB		 1138 switch (level) {
1139 case SND_SOC_BIAS_ON:
db13802e
JN		 1140 break;
1141 case SND_SOC_BIAS_PREPARE:
ce6120cc 1142 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1143 aic3x->master) {
44d0a879 1144 /* enable pll */
e18eca43
JN		 1145 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1146 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1147 reg | PLL_ENABLE);
44d0a879
VB		 1148 }
1149 break;
0be9898a 1150 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1151 if (!aic3x->power)
1152 aic3x_set_power(codec, 1);
ce6120cc 1153 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1154 aic3x->master) {
44d0a879 1155 /* disable pll */
e18eca43
JN		 1156 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1157 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1158 reg & ~PLL_ENABLE);
44d0a879
VB		 1159 }
1160 break;
c23fd751 1161 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1162 if (aic3x->power)
1163 aic3x_set_power(codec, 0);
c23fd751 1164 break;
44d0a879 1165 }
ce6120cc 1166 codec->dapm.bias_level = level;
44d0a879
VB		 1167
1168 return 0;
1169}
1170
54e7e616
DM		 1171void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1172{
1173 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1174 u8 bit = gpio ? 3: 0;
e18eca43
JN		 1175 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1176 snd_soc_write(codec, reg, val | (!!state << bit));
54e7e616
DM		 1177}
1178EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1179
1180int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1181{
1182 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
fe99b559 1183 u8 val = 0, bit = gpio ? 2 : 1;
54e7e616
DM		 1184
1185 aic3x_read(codec, reg, &val);
1186 return (val >> bit) & 1;
1187}
1188EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1189
6f2a974b
DM		 1190void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1191 int headset_debounce, int button_debounce)
1192{
1193 u8 val;
1194
1195 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1196 << AIC3X_HEADSET_DETECT_SHIFT) |
1197 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1198 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1199 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1200 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1201
1202 if (detect & AIC3X_HEADSET_DETECT_MASK)
1203 val |= AIC3X_HEADSET_DETECT_ENABLED;
1204
e18eca43 1205 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
6f2a974b
DM		 1206}
1207EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1208
54e7e616
DM		 1209int aic3x_headset_detected(struct snd_soc_codec *codec)
1210{
fe99b559 1211 u8 val = 0;
6f2a974b
DM		 1212 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1213 return (val >> 4) & 1;
54e7e616
DM		 1214}
1215EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1216
6f2a974b
DM		 1217int aic3x_button_pressed(struct snd_soc_codec *codec)
1218{
fe99b559 1219 u8 val = 0;
6f2a974b
DM		 1220 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1221 return (val >> 5) & 1;
1222}
1223EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1224
44d0a879
VB		 1225#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1226#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1227 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1228
6335d055
EM		 1229static struct snd_soc_dai_ops aic3x_dai_ops = {
1230 .hw_params = aic3x_hw_params,
1231 .digital_mute = aic3x_mute,
1232 .set_sysclk = aic3x_set_dai_sysclk,
1233 .set_fmt = aic3x_set_dai_fmt,
1234};
1235
f0fba2ad
LG		 1236static struct snd_soc_dai_driver aic3x_dai = {
1237 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1238 .playback = {
1239 .stream_name = "Playback",
1240 .channels_min = 1,
1241 .channels_max = 2,
1242 .rates = AIC3X_RATES,
1243 .formats = AIC3X_FORMATS,},
1244 .capture = {
1245 .stream_name = "Capture",
1246 .channels_min = 1,
1247 .channels_max = 2,
1248 .rates = AIC3X_RATES,
1249 .formats = AIC3X_FORMATS,},
6335d055 1250 .ops = &aic3x_dai_ops,
14017615 1251 .symmetric_rates = 1,
44d0a879 1252};
44d0a879 1253
f0fba2ad 1254static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
44d0a879 1255{
0be9898a 1256 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1257
1258 return 0;
1259}
1260
f0fba2ad 1261static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1262{
29e189c2 1263 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1264
1265 return 0;
1266}
1267
1268/*
1269 * initialise the AIC3X driver
1270 * register the mixer and dsp interfaces with the kernel
1271 */
cb3826f5 1272static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1273{
6184f105 1274 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5
BD		 1275 int reg;
1276
e18eca43
JN		 1277 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1278 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1279
44d0a879 1280 /* DAC default volume and mute */
e18eca43
JN		 1281 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1282 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1283
1284 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1285 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1286 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1287 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1288 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1289 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1290 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1291 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1292 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1293 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1294 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1295
1296 /* unmute all outputs */
e18eca43
JN		 1297 reg = snd_soc_read(codec, LLOPM_CTRL);
1298 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
1299 reg = snd_soc_read(codec, RLOPM_CTRL);
1300 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
1301 reg = snd_soc_read(codec, MONOLOPM_CTRL);
1302 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1303 reg = snd_soc_read(codec, HPLOUT_CTRL);
1304 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1305 reg = snd_soc_read(codec, HPROUT_CTRL);
1306 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
1307 reg = snd_soc_read(codec, HPLCOM_CTRL);
1308 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1309 reg = snd_soc_read(codec, HPRCOM_CTRL);
1310 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
44d0a879
VB		 1311
1312 /* ADC default volume and unmute */
e18eca43
JN		 1313 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1314 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1315 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1316 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1317 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1318
1319 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1320 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1321 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1322 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1323 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1324 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1325 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1326 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1327 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1328 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1329 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1330
1331 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1332 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1333 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1334 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1335 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1336 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1337 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1338 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1339 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1340 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1341 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1342
6184f105 1343 if (aic3x->model == AIC3X_MODEL_3007) {
6c1a7d40 1344 aic3x_init_3007(codec);
e18eca43 1345 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1346 }
1347
cb3826f5
BD		 1348 return 0;
1349}
54e7e616 1350
414c73ab
JN		 1351static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1352{
1353 struct aic3x_priv *a;
1354
1355 list_for_each_entry(a, &reset_list, list) {
1356 if (gpio_is_valid(aic3x->gpio_reset) &&
1357 aic3x->gpio_reset == a->gpio_reset)
1358 return true;
1359 }
1360
1361 return false;
1362}
1363
f0fba2ad 1364static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1365{
f0fba2ad 1366 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1367 int ret, i;
f0fba2ad 1368
414c73ab 1369 INIT_LIST_HEAD(&aic3x->list);
f0fba2ad 1370 codec->control_data = aic3x->control_data;
5a895f8a 1371 aic3x->codec = codec;
ce6120cc 1372 codec->dapm.idle_bias_off = 1;
cb3826f5 1373
a84a441b
JN		 1374 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1375 if (ret != 0) {
1376 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1377 return ret;
1378 }
1379
414c73ab
JN		 1380 if (gpio_is_valid(aic3x->gpio_reset) &&
1381 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1382 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1383 if (ret != 0)
1384 goto err_gpio;
1385 gpio_direction_output(aic3x->gpio_reset, 0);
1386 }
1387
1388 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1389 aic3x->supplies[i].supply = aic3x_supply_names[i];
1390
1391 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1392 aic3x->supplies);
1393 if (ret != 0) {
1394 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1395 goto err_get;
1396 }
5a895f8a
JN		 1397 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1398 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1399 aic3x->disable_nb[i].aic3x = aic3x;
1400 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1401 &aic3x->disable_nb[i].nb);
1402 if (ret) {
1403 dev_err(codec->dev,
1404 "Failed to request regulator notifier: %d\n",
1405 ret);
1406 goto err_notif;
1407 }
1408 }
2f24111a 1409
7d1be0a6 1410 codec->cache_only = 1;
37b47656
JN		 1411 aic3x_init(codec);
1412
f0fba2ad
LG		 1413 if (aic3x->setup) {
1414 /* setup GPIO functions */
e18eca43
JN		 1415 snd_soc_write(codec, AIC3X_GPIO1_REG,
1416 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1417 snd_soc_write(codec, AIC3X_GPIO2_REG,
1418 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1419 }
1420
f0fba2ad
LG		 1421 snd_soc_add_controls(codec, aic3x_snd_controls,
1422 ARRAY_SIZE(aic3x_snd_controls));
6184f105
RC		 1423 if (aic3x->model == AIC3X_MODEL_3007)
1424 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1425
f0fba2ad 1426 aic3x_add_widgets(codec);
414c73ab 1427 list_add(&aic3x->list, &reset_list);
cb3826f5
BD		 1428
1429 return 0;
2f24111a 1430
5a895f8a
JN		 1431err_notif:
1432 while (i--)
1433 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1434 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1435 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1436err_get:
414c73ab
JN		 1437 if (gpio_is_valid(aic3x->gpio_reset) &&
1438 !aic3x_is_shared_reset(aic3x))
2f24111a
JN		 1439 gpio_free(aic3x->gpio_reset);
1440err_gpio:
2f24111a 1441 return ret;
44d0a879
VB		 1442}
1443
f0fba2ad 1444static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1445{
2f24111a 1446 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1447 int i;
2f24111a 1448
f0fba2ad 1449 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
414c73ab
JN		 1450 list_del(&aic3x->list);
1451 if (gpio_is_valid(aic3x->gpio_reset) &&
1452 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1453 gpio_set_value(aic3x->gpio_reset, 0);
1454 gpio_free(aic3x->gpio_reset);
1455 }
5a895f8a
JN		 1456 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1457 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1458 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1459 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1460
cb3826f5
BD		 1461 return 0;
1462}
44d0a879 1463
f0fba2ad 1464static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad
LG		 1465 .set_bias_level = aic3x_set_bias_level,
1466 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1467 .reg_word_size = sizeof(u8),
1468 .reg_cache_default = aic3x_reg,
1469 .probe = aic3x_probe,
1470 .remove = aic3x_remove,
1471 .suspend = aic3x_suspend,
1472 .resume = aic3x_resume,
1473};
1474
44d0a879
VB		 1475#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1476/*
1477 * AIC3X 2 wire address can be up to 4 devices with device addresses
1478 * 0x18, 0x19, 0x1A, 0x1B
1479 */
44d0a879 1480
6184f105
RC		 1481static const struct i2c_device_id aic3x_i2c_id[] = {
1482 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1483 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1484 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1485 { }
1486};
1487MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1488
44d0a879
VB		 1489/*
1490 * If the i2c layer weren't so broken, we could pass this kind of data
1491 * around
1492 */
ba8ed121
JD		 1493static int aic3x_i2c_probe(struct i2c_client *i2c,
1494 const struct i2c_device_id *id)
44d0a879 1495{
5193d62f 1496 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1497 struct aic3x_priv *aic3x;
2f24111a 1498 int ret;
6184f105 1499 const struct i2c_device_id *tbl;
44d0a879 1500
cb3826f5
BD		 1501 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1502 if (aic3x == NULL) {
1503 dev_err(&i2c->dev, "failed to create private data\n");
1504 return -ENOMEM;
1505 }
1506
f0fba2ad 1507 aic3x->control_data = i2c;
a84a441b
JN		 1508 aic3x->control_type = SND_SOC_I2C;
1509
cb3826f5 1510 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1511 if (pdata) {
1512 aic3x->gpio_reset = pdata->gpio_reset;
1513 aic3x->setup = pdata->setup;
1514 } else {
1515 aic3x->gpio_reset = -1;
1516 }
cb3826f5 1517
6184f105
RC		 1518 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1519 if (!strcmp(tbl->name, id->name))
1520 break;
1521 }
1522 aic3x->model = tbl - aic3x_i2c_id;
1523
f0fba2ad
LG		 1524 ret = snd_soc_register_codec(&i2c->dev,
1525 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1526 if (ret < 0)
2f24111a 1527 kfree(aic3x);
07779fdd 1528 return ret;
44d0a879
VB		 1529}
1530
ba8ed121 1531static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1532{
f0fba2ad
LG		 1533 snd_soc_unregister_codec(&client->dev);
1534 kfree(i2c_get_clientdata(client));
1535 return 0;
44d0a879
VB		 1536}
1537
44d0a879
VB		 1538/* machine i2c codec control layer */
1539static struct i2c_driver aic3x_i2c_driver = {
1540 .driver = {
f0fba2ad 1541 .name = "tlv320aic3x-codec",
44d0a879
VB		 1542 .owner = THIS_MODULE,
1543 },
cb3826f5 1544 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1545 .remove = aic3x_i2c_remove,
1546 .id_table = aic3x_i2c_id,
44d0a879
VB		 1547};
1548#endif
1549
f0fba2ad 1550static int __init aic3x_modinit(void)
44d0a879 1551{
44d0a879 1552 int ret = 0;
f0fba2ad
LG		 1553#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1554 ret = i2c_add_driver(&aic3x_i2c_driver);
1555 if (ret != 0) {
1556 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1557 ret);
44d0a879 1558 }
f0fba2ad 1559#endif
44d0a879
VB		 1560 return ret;
1561}
64089b84
MB		 1562module_init(aic3x_modinit);
1563
1564static void __exit aic3x_exit(void)
1565{
f0fba2ad
LG		 1566#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1567 i2c_del_driver(&aic3x_i2c_driver);
1568#endif
64089b84
MB		 1569}
1570module_exit(aic3x_exit);
1571
44d0a879
VB		 1572MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1573MODULE_AUTHOR("Vladimir Barinov");
1574MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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