Commit | Line | Data |
---|---|---|
c8bf93f0 PU |
1 | /* |
2 | * ALSA SoC Texas Instruments TLV320DAC33 codec driver | |
3 | * | |
93864cf0 | 4 | * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> |
c8bf93f0 PU |
5 | * |
6 | * Copyright: (C) 2009 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/moduleparam.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/pm.h> | |
29 | #include <linux/i2c.h> | |
c8bf93f0 PU |
30 | #include <linux/interrupt.h> |
31 | #include <linux/gpio.h> | |
3a7aaed7 | 32 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
c8bf93f0 PU |
34 | #include <sound/core.h> |
35 | #include <sound/pcm.h> | |
36 | #include <sound/pcm_params.h> | |
37 | #include <sound/soc.h> | |
c8bf93f0 PU |
38 | #include <sound/initval.h> |
39 | #include <sound/tlv.h> | |
40 | ||
41 | #include <sound/tlv320dac33-plat.h> | |
42 | #include "tlv320dac33.h" | |
43 | ||
549675ed PU |
44 | /* |
45 | * The internal FIFO is 24576 bytes long | |
46 | * It can be configured to hold 16bit or 24bit samples | |
47 | * In 16bit configuration the FIFO can hold 6144 stereo samples | |
48 | * In 24bit configuration the FIFO can hold 4096 stereo samples | |
49 | */ | |
50 | #define DAC33_FIFO_SIZE_16BIT 6144 | |
51 | #define DAC33_FIFO_SIZE_24BIT 4096 | |
52 | #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ | |
4260393e | 53 | |
76f47127 PU |
54 | #define BURST_BASEFREQ_HZ 49152000 |
55 | ||
f57d2cfa | 56 | #define SAMPLES_TO_US(rate, samples) \ |
c29429f3 | 57 | (1000000000 / (((rate) * 1000) / (samples))) |
f57d2cfa PU |
58 | |
59 | #define US_TO_SAMPLES(rate, us) \ | |
c29429f3 | 60 | ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000))) |
f57d2cfa | 61 | |
a577b318 | 62 | #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ |
c29429f3 | 63 | (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate)))) |
a577b318 | 64 | |
e6968a17 MB |
65 | static void dac33_calculate_times(struct snd_pcm_substream *substream, |
66 | struct snd_soc_codec *codec); | |
67 | static int dac33_prepare_chip(struct snd_pcm_substream *substream, | |
68 | struct snd_soc_codec *codec); | |
f57d2cfa | 69 | |
c8bf93f0 PU |
70 | enum dac33_state { |
71 | DAC33_IDLE = 0, | |
72 | DAC33_PREFILL, | |
73 | DAC33_PLAYBACK, | |
74 | DAC33_FLUSH, | |
75 | }; | |
76 | ||
7427b4b9 PU |
77 | enum dac33_fifo_modes { |
78 | DAC33_FIFO_BYPASS = 0, | |
79 | DAC33_FIFO_MODE1, | |
28e05d98 | 80 | DAC33_FIFO_MODE7, |
7427b4b9 PU |
81 | DAC33_FIFO_LAST_MODE, |
82 | }; | |
83 | ||
3a7aaed7 IK |
84 | #define DAC33_NUM_SUPPLIES 3 |
85 | static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { | |
86 | "AVDD", | |
87 | "DVDD", | |
88 | "IOVDD", | |
89 | }; | |
90 | ||
c8bf93f0 PU |
91 | struct tlv320dac33_priv { |
92 | struct mutex mutex; | |
93 | struct workqueue_struct *dac33_wq; | |
94 | struct work_struct work; | |
f0fba2ad | 95 | struct snd_soc_codec *codec; |
3a7aaed7 | 96 | struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; |
0b61d2b9 | 97 | struct snd_pcm_substream *substream; |
c8bf93f0 PU |
98 | int power_gpio; |
99 | int chip_power; | |
100 | int irq; | |
101 | unsigned int refclk; | |
102 | ||
103 | unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ | |
7427b4b9 | 104 | enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ |
549675ed | 105 | unsigned int fifo_size; /* Size of the FIFO in samples */ |
c8bf93f0 | 106 | unsigned int nsample; /* burst read amount from host */ |
f430a27f PU |
107 | int mode1_latency; /* latency caused by the i2c writes in |
108 | * us */ | |
6aceabb4 | 109 | u8 burst_bclkdiv; /* BCLK divider value in burst mode */ |
76f47127 | 110 | unsigned int burst_rate; /* Interface speed in Burst modes */ |
c8bf93f0 | 111 | |
eeb309a8 PU |
112 | int keep_bclk; /* Keep the BCLK continuously running |
113 | * in FIFO modes */ | |
f57d2cfa PU |
114 | spinlock_t lock; |
115 | unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ | |
116 | unsigned long long t_stamp2; /* calculate the FIFO caused delay */ | |
117 | ||
118 | unsigned int mode1_us_burst; /* Time to burst read n number of | |
119 | * samples */ | |
120 | unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ | |
c8bf93f0 | 121 | |
9d7db2b2 PU |
122 | unsigned int uthr; |
123 | ||
c8bf93f0 | 124 | enum dac33_state state; |
f0fba2ad | 125 | void *control_data; |
c8bf93f0 PU |
126 | }; |
127 | ||
128 | static const u8 dac33_reg[DAC33_CACHEREGNUM] = { | |
129 | 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ | |
130 | 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ | |
131 | 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ | |
132 | 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ | |
133 | 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ | |
134 | 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ | |
135 | 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ | |
136 | 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ | |
137 | 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ | |
138 | 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ | |
139 | 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ | |
140 | 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ | |
141 | 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ | |
142 | 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ | |
143 | 0x00, 0x00, /* 0x38 - 0x39 */ | |
144 | /* Registers 0x3a - 0x3f are reserved */ | |
145 | 0x00, 0x00, /* 0x3a - 0x3b */ | |
146 | 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ | |
147 | ||
148 | 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ | |
149 | 0x00, 0x80, /* 0x44 - 0x45 */ | |
150 | /* Registers 0x46 - 0x47 are reserved */ | |
151 | 0x80, 0x80, /* 0x46 - 0x47 */ | |
152 | ||
153 | 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ | |
154 | /* Registers 0x4b - 0x7c are reserved */ | |
155 | 0x00, /* 0x4b */ | |
156 | 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ | |
157 | 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ | |
158 | 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ | |
159 | 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ | |
160 | 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ | |
161 | 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ | |
162 | 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ | |
163 | 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ | |
164 | 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ | |
165 | 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ | |
166 | 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ | |
167 | 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ | |
168 | 0x00, /* 0x7c */ | |
169 | ||
170 | 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ | |
171 | }; | |
172 | ||
173 | /* Register read and write */ | |
174 | static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec, | |
175 | unsigned reg) | |
176 | { | |
177 | u8 *cache = codec->reg_cache; | |
178 | if (reg >= DAC33_CACHEREGNUM) | |
179 | return 0; | |
180 | ||
181 | return cache[reg]; | |
182 | } | |
183 | ||
184 | static inline void dac33_write_reg_cache(struct snd_soc_codec *codec, | |
185 | u8 reg, u8 value) | |
186 | { | |
187 | u8 *cache = codec->reg_cache; | |
188 | if (reg >= DAC33_CACHEREGNUM) | |
189 | return; | |
190 | ||
191 | cache[reg] = value; | |
192 | } | |
193 | ||
194 | static int dac33_read(struct snd_soc_codec *codec, unsigned int reg, | |
195 | u8 *value) | |
196 | { | |
b2c812e2 | 197 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
911a0f0b | 198 | int val, ret = 0; |
c8bf93f0 PU |
199 | |
200 | *value = reg & 0xff; | |
201 | ||
202 | /* If powered off, return the cached value */ | |
203 | if (dac33->chip_power) { | |
204 | val = i2c_smbus_read_byte_data(codec->control_data, value[0]); | |
205 | if (val < 0) { | |
206 | dev_err(codec->dev, "Read failed (%d)\n", val); | |
207 | value[0] = dac33_read_reg_cache(codec, reg); | |
911a0f0b | 208 | ret = val; |
c8bf93f0 PU |
209 | } else { |
210 | value[0] = val; | |
211 | dac33_write_reg_cache(codec, reg, val); | |
212 | } | |
213 | } else { | |
214 | value[0] = dac33_read_reg_cache(codec, reg); | |
215 | } | |
216 | ||
911a0f0b | 217 | return ret; |
c8bf93f0 PU |
218 | } |
219 | ||
220 | static int dac33_write(struct snd_soc_codec *codec, unsigned int reg, | |
221 | unsigned int value) | |
222 | { | |
b2c812e2 | 223 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
224 | u8 data[2]; |
225 | int ret = 0; | |
226 | ||
227 | /* | |
228 | * data is | |
229 | * D15..D8 dac33 register offset | |
230 | * D7...D0 register data | |
231 | */ | |
232 | data[0] = reg & 0xff; | |
233 | data[1] = value & 0xff; | |
234 | ||
235 | dac33_write_reg_cache(codec, data[0], data[1]); | |
236 | if (dac33->chip_power) { | |
237 | ret = codec->hw_write(codec->control_data, data, 2); | |
238 | if (ret != 2) | |
239 | dev_err(codec->dev, "Write failed (%d)\n", ret); | |
240 | else | |
241 | ret = 0; | |
242 | } | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
247 | static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg, | |
248 | unsigned int value) | |
249 | { | |
b2c812e2 | 250 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
251 | int ret; |
252 | ||
253 | mutex_lock(&dac33->mutex); | |
254 | ret = dac33_write(codec, reg, value); | |
255 | mutex_unlock(&dac33->mutex); | |
256 | ||
257 | return ret; | |
258 | } | |
259 | ||
260 | #define DAC33_I2C_ADDR_AUTOINC 0x80 | |
261 | static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg, | |
262 | unsigned int value) | |
263 | { | |
b2c812e2 | 264 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
265 | u8 data[3]; |
266 | int ret = 0; | |
267 | ||
268 | /* | |
269 | * data is | |
270 | * D23..D16 dac33 register offset | |
271 | * D15..D8 register data MSB | |
272 | * D7...D0 register data LSB | |
273 | */ | |
274 | data[0] = reg & 0xff; | |
275 | data[1] = (value >> 8) & 0xff; | |
276 | data[2] = value & 0xff; | |
277 | ||
278 | dac33_write_reg_cache(codec, data[0], data[1]); | |
279 | dac33_write_reg_cache(codec, data[0] + 1, data[2]); | |
280 | ||
281 | if (dac33->chip_power) { | |
282 | /* We need to set autoincrement mode for 16 bit writes */ | |
283 | data[0] |= DAC33_I2C_ADDR_AUTOINC; | |
284 | ret = codec->hw_write(codec->control_data, data, 3); | |
285 | if (ret != 3) | |
286 | dev_err(codec->dev, "Write failed (%d)\n", ret); | |
287 | else | |
288 | ret = 0; | |
289 | } | |
290 | ||
291 | return ret; | |
292 | } | |
293 | ||
ef909d67 | 294 | static void dac33_init_chip(struct snd_soc_codec *codec) |
c8bf93f0 | 295 | { |
b2c812e2 | 296 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 297 | |
ef909d67 | 298 | if (unlikely(!dac33->chip_power)) |
c8bf93f0 PU |
299 | return; |
300 | ||
ef909d67 PU |
301 | /* A : DAC sample rate Fsref/1.5 */ |
302 | dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); | |
303 | /* B : DAC src=normal, not muted */ | |
304 | dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | | |
305 | DAC33_DACSRCL_LEFT); | |
306 | /* C : (defaults) */ | |
307 | dac33_write(codec, DAC33_DAC_CTRL_C, 0x00); | |
308 | ||
ef909d67 PU |
309 | /* 73 : volume soft stepping control, |
310 | clock source = internal osc (?) */ | |
311 | dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); | |
312 | ||
ef909d67 PU |
313 | /* Restore only selected registers (gains mostly) */ |
314 | dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, | |
315 | dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); | |
316 | dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL, | |
317 | dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL)); | |
318 | ||
319 | dac33_write(codec, DAC33_LINEL_TO_LLO_VOL, | |
320 | dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); | |
321 | dac33_write(codec, DAC33_LINER_TO_RLO_VOL, | |
322 | dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); | |
399b82e4 PU |
323 | |
324 | dac33_write(codec, DAC33_OUT_AMP_CTRL, | |
325 | dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL)); | |
326 | ||
56a3536c PU |
327 | dac33_write(codec, DAC33_LDAC_PWR_CTRL, |
328 | dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL)); | |
329 | dac33_write(codec, DAC33_RDAC_PWR_CTRL, | |
330 | dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL)); | |
c8bf93f0 PU |
331 | } |
332 | ||
911a0f0b | 333 | static inline int dac33_read_id(struct snd_soc_codec *codec) |
239fe55c | 334 | { |
911a0f0b | 335 | int i, ret = 0; |
239fe55c PU |
336 | u8 reg; |
337 | ||
911a0f0b PU |
338 | for (i = 0; i < 3; i++) { |
339 | ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, ®); | |
340 | if (ret < 0) | |
341 | break; | |
342 | } | |
343 | ||
344 | return ret; | |
c8bf93f0 PU |
345 | } |
346 | ||
347 | static inline void dac33_soft_power(struct snd_soc_codec *codec, int power) | |
348 | { | |
349 | u8 reg; | |
350 | ||
351 | reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
352 | if (power) | |
353 | reg |= DAC33_PDNALLB; | |
354 | else | |
c3746a07 PU |
355 | reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | |
356 | DAC33_DACRPDNB | DAC33_DACLPDNB); | |
c8bf93f0 PU |
357 | dac33_write(codec, DAC33_PWR_CTRL, reg); |
358 | } | |
359 | ||
a6cea965 PU |
360 | static inline void dac33_disable_digital(struct snd_soc_codec *codec) |
361 | { | |
362 | u8 reg; | |
363 | ||
364 | /* Stop the DAI clock */ | |
365 | reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
366 | reg &= ~DAC33_BCLKON; | |
367 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg); | |
368 | ||
369 | /* Power down the Oscillator, and DACs */ | |
370 | reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
371 | reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); | |
372 | dac33_write(codec, DAC33_PWR_CTRL, reg); | |
373 | } | |
374 | ||
3a7aaed7 | 375 | static int dac33_hard_power(struct snd_soc_codec *codec, int power) |
c8bf93f0 | 376 | { |
b2c812e2 | 377 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
ad05c03b | 378 | int ret = 0; |
c8bf93f0 PU |
379 | |
380 | mutex_lock(&dac33->mutex); | |
ad05c03b PU |
381 | |
382 | /* Safety check */ | |
383 | if (unlikely(power == dac33->chip_power)) { | |
7fd1d74b | 384 | dev_dbg(codec->dev, "Trying to set the same power state: %s\n", |
ad05c03b PU |
385 | power ? "ON" : "OFF"); |
386 | goto exit; | |
387 | } | |
388 | ||
c8bf93f0 | 389 | if (power) { |
3a7aaed7 IK |
390 | ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), |
391 | dac33->supplies); | |
392 | if (ret != 0) { | |
393 | dev_err(codec->dev, | |
394 | "Failed to enable supplies: %d\n", ret); | |
395 | goto exit; | |
c8bf93f0 | 396 | } |
3a7aaed7 IK |
397 | |
398 | if (dac33->power_gpio >= 0) | |
399 | gpio_set_value(dac33->power_gpio, 1); | |
400 | ||
401 | dac33->chip_power = 1; | |
c8bf93f0 PU |
402 | } else { |
403 | dac33_soft_power(codec, 0); | |
3a7aaed7 | 404 | if (dac33->power_gpio >= 0) |
c8bf93f0 | 405 | gpio_set_value(dac33->power_gpio, 0); |
3a7aaed7 IK |
406 | |
407 | ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), | |
408 | dac33->supplies); | |
409 | if (ret != 0) { | |
410 | dev_err(codec->dev, | |
411 | "Failed to disable supplies: %d\n", ret); | |
412 | goto exit; | |
c8bf93f0 | 413 | } |
3a7aaed7 IK |
414 | |
415 | dac33->chip_power = 0; | |
c8bf93f0 | 416 | } |
c8bf93f0 | 417 | |
3a7aaed7 IK |
418 | exit: |
419 | mutex_unlock(&dac33->mutex); | |
420 | return ret; | |
c8bf93f0 PU |
421 | } |
422 | ||
a6cea965 | 423 | static int dac33_playback_event(struct snd_soc_dapm_widget *w, |
ad05c03b PU |
424 | struct snd_kcontrol *kcontrol, int event) |
425 | { | |
c61ac6b7 LPC |
426 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
427 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); | |
ad05c03b PU |
428 | |
429 | switch (event) { | |
430 | case SND_SOC_DAPM_PRE_PMU: | |
431 | if (likely(dac33->substream)) { | |
c61ac6b7 LPC |
432 | dac33_calculate_times(dac33->substream, codec); |
433 | dac33_prepare_chip(dac33->substream, codec); | |
ad05c03b PU |
434 | } |
435 | break; | |
a6cea965 | 436 | case SND_SOC_DAPM_POST_PMD: |
c61ac6b7 | 437 | dac33_disable_digital(codec); |
a6cea965 | 438 | break; |
ad05c03b PU |
439 | } |
440 | return 0; | |
441 | } | |
442 | ||
7427b4b9 | 443 | static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, |
c8bf93f0 PU |
444 | struct snd_ctl_elem_value *ucontrol) |
445 | { | |
ea53bf77 | 446 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
b2c812e2 | 447 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 448 | |
7427b4b9 | 449 | ucontrol->value.integer.value[0] = dac33->fifo_mode; |
c8bf93f0 PU |
450 | |
451 | return 0; | |
452 | } | |
453 | ||
7427b4b9 | 454 | static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, |
c8bf93f0 PU |
455 | struct snd_ctl_elem_value *ucontrol) |
456 | { | |
ea53bf77 | 457 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
b2c812e2 | 458 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
459 | int ret = 0; |
460 | ||
7427b4b9 | 461 | if (dac33->fifo_mode == ucontrol->value.integer.value[0]) |
c8bf93f0 PU |
462 | return 0; |
463 | /* Do not allow changes while stream is running*/ | |
5c898e74 | 464 | if (snd_soc_codec_is_active(codec)) |
c8bf93f0 PU |
465 | return -EPERM; |
466 | ||
467 | if (ucontrol->value.integer.value[0] < 0 || | |
7427b4b9 | 468 | ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE) |
c8bf93f0 PU |
469 | ret = -EINVAL; |
470 | else | |
7427b4b9 | 471 | dac33->fifo_mode = ucontrol->value.integer.value[0]; |
c8bf93f0 PU |
472 | |
473 | return ret; | |
474 | } | |
475 | ||
7427b4b9 PU |
476 | /* Codec operation modes */ |
477 | static const char *dac33_fifo_mode_texts[] = { | |
28e05d98 | 478 | "Bypass", "Mode 1", "Mode 7" |
7427b4b9 PU |
479 | }; |
480 | ||
d77c290a | 481 | static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts); |
7427b4b9 | 482 | |
cf4bb698 PU |
483 | /* L/R Line Output Gain */ |
484 | static const char *lr_lineout_gain_texts[] = { | |
485 | "Line -12dB DAC 0dB", "Line -6dB DAC 6dB", | |
486 | "Line 0dB DAC 12dB", "Line 6dB DAC 18dB", | |
487 | }; | |
488 | ||
d77c290a TI |
489 | static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum, |
490 | DAC33_LDAC_PWR_CTRL, 0, | |
491 | lr_lineout_gain_texts); | |
cf4bb698 | 492 | |
d77c290a TI |
493 | static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum, |
494 | DAC33_RDAC_PWR_CTRL, 0, | |
495 | lr_lineout_gain_texts); | |
cf4bb698 | 496 | |
c8bf93f0 PU |
497 | /* |
498 | * DACL/R digital volume control: | |
499 | * from 0 dB to -63.5 in 0.5 dB steps | |
500 | * Need to be inverted later on: | |
501 | * 0x00 == 0 dB | |
502 | * 0x7f == -63.5 dB | |
503 | */ | |
504 | static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); | |
505 | ||
506 | static const struct snd_kcontrol_new dac33_snd_controls[] = { | |
507 | SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", | |
508 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, | |
509 | 0, 0x7f, 1, dac_digivol_tlv), | |
510 | SOC_DOUBLE_R("DAC Digital Playback Switch", | |
511 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), | |
512 | SOC_DOUBLE_R("Line to Line Out Volume", | |
513 | DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), | |
cf4bb698 PU |
514 | SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum), |
515 | SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum), | |
c8bf93f0 PU |
516 | }; |
517 | ||
a577b318 PU |
518 | static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { |
519 | SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, | |
520 | dac33_get_fifo_mode, dac33_set_fifo_mode), | |
521 | }; | |
522 | ||
c8bf93f0 PU |
523 | /* Analog bypass */ |
524 | static const struct snd_kcontrol_new dac33_dapm_abypassl_control = | |
525 | SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); | |
526 | ||
527 | static const struct snd_kcontrol_new dac33_dapm_abypassr_control = | |
528 | SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); | |
529 | ||
399b82e4 PU |
530 | /* LOP L/R invert selection */ |
531 | static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"}; | |
532 | ||
d77c290a TI |
533 | static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum, |
534 | DAC33_OUT_AMP_CTRL, 3, | |
535 | dac33_lr_lom_texts); | |
399b82e4 PU |
536 | |
537 | static const struct snd_kcontrol_new dac33_dapm_left_lom_control = | |
538 | SOC_DAPM_ENUM("Route", dac33_left_lom_enum); | |
539 | ||
d77c290a TI |
540 | static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum, |
541 | DAC33_OUT_AMP_CTRL, 2, | |
542 | dac33_lr_lom_texts); | |
399b82e4 PU |
543 | |
544 | static const struct snd_kcontrol_new dac33_dapm_right_lom_control = | |
545 | SOC_DAPM_ENUM("Route", dac33_right_lom_enum); | |
546 | ||
c8bf93f0 PU |
547 | static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { |
548 | SND_SOC_DAPM_OUTPUT("LEFT_LO"), | |
549 | SND_SOC_DAPM_OUTPUT("RIGHT_LO"), | |
550 | ||
551 | SND_SOC_DAPM_INPUT("LINEL"), | |
552 | SND_SOC_DAPM_INPUT("LINER"), | |
553 | ||
76eac39c PU |
554 | SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), |
555 | SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), | |
c8bf93f0 PU |
556 | |
557 | /* Analog bypass */ | |
558 | SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, | |
559 | &dac33_dapm_abypassl_control), | |
560 | SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, | |
561 | &dac33_dapm_abypassr_control), | |
562 | ||
399b82e4 PU |
563 | SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0, |
564 | &dac33_dapm_left_lom_control), | |
565 | SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0, | |
566 | &dac33_dapm_right_lom_control), | |
567 | /* | |
568 | * For DAPM path, when only the anlog bypass path is enabled, and the | |
569 | * LOP inverted from the corresponding DAC side. | |
570 | * This is needed, so we can attach the DAC power supply in this case. | |
571 | */ | |
572 | SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
573 | SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
574 | ||
9e87186f | 575 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", |
c8bf93f0 | 576 | DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), |
9e87186f | 577 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", |
c8bf93f0 | 578 | DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), |
ad05c03b | 579 | |
76eac39c PU |
580 | SND_SOC_DAPM_SUPPLY("Left DAC Power", |
581 | DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), | |
582 | SND_SOC_DAPM_SUPPLY("Right DAC Power", | |
583 | DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), | |
584 | ||
4b8ffdb9 PU |
585 | SND_SOC_DAPM_SUPPLY("Codec Power", |
586 | DAC33_PWR_CTRL, 4, 0, NULL, 0), | |
587 | ||
a6cea965 PU |
588 | SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event), |
589 | SND_SOC_DAPM_POST("Post Playback", dac33_playback_event), | |
c8bf93f0 PU |
590 | }; |
591 | ||
592 | static const struct snd_soc_dapm_route audio_map[] = { | |
593 | /* Analog bypass */ | |
594 | {"Analog Left Bypass", "Switch", "LINEL"}, | |
595 | {"Analog Right Bypass", "Switch", "LINER"}, | |
596 | ||
9e87186f PU |
597 | {"Output Left Amplifier", NULL, "DACL"}, |
598 | {"Output Right Amplifier", NULL, "DACR"}, | |
c8bf93f0 | 599 | |
399b82e4 PU |
600 | {"Left Bypass PGA", NULL, "Analog Left Bypass"}, |
601 | {"Right Bypass PGA", NULL, "Analog Right Bypass"}, | |
602 | ||
603 | {"Left LOM Inverted From", "DAC", "Left Bypass PGA"}, | |
604 | {"Right LOM Inverted From", "DAC", "Right Bypass PGA"}, | |
605 | {"Left LOM Inverted From", "LOP", "Analog Left Bypass"}, | |
606 | {"Right LOM Inverted From", "LOP", "Analog Right Bypass"}, | |
607 | ||
608 | {"Output Left Amplifier", NULL, "Left LOM Inverted From"}, | |
609 | {"Output Right Amplifier", NULL, "Right LOM Inverted From"}, | |
610 | ||
611 | {"DACL", NULL, "Left DAC Power"}, | |
612 | {"DACR", NULL, "Right DAC Power"}, | |
c8bf93f0 | 613 | |
399b82e4 PU |
614 | {"Left Bypass PGA", NULL, "Left DAC Power"}, |
615 | {"Right Bypass PGA", NULL, "Right DAC Power"}, | |
76eac39c | 616 | |
c8bf93f0 | 617 | /* output */ |
9e87186f PU |
618 | {"LEFT_LO", NULL, "Output Left Amplifier"}, |
619 | {"RIGHT_LO", NULL, "Output Right Amplifier"}, | |
4b8ffdb9 PU |
620 | |
621 | {"LEFT_LO", NULL, "Codec Power"}, | |
622 | {"RIGHT_LO", NULL, "Codec Power"}, | |
c8bf93f0 PU |
623 | }; |
624 | ||
c8bf93f0 PU |
625 | static int dac33_set_bias_level(struct snd_soc_codec *codec, |
626 | enum snd_soc_bias_level level) | |
627 | { | |
3a7aaed7 IK |
628 | int ret; |
629 | ||
c8bf93f0 PU |
630 | switch (level) { |
631 | case SND_SOC_BIAS_ON: | |
c8bf93f0 PU |
632 | break; |
633 | case SND_SOC_BIAS_PREPARE: | |
634 | break; | |
635 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 636 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
ad05c03b | 637 | /* Coming from OFF, switch on the codec */ |
3a7aaed7 IK |
638 | ret = dac33_hard_power(codec, 1); |
639 | if (ret != 0) | |
640 | return ret; | |
3a7aaed7 | 641 | |
ad05c03b PU |
642 | dac33_init_chip(codec); |
643 | } | |
c8bf93f0 PU |
644 | break; |
645 | case SND_SOC_BIAS_OFF: | |
2d4cdd6f | 646 | /* Do not power off, when the codec is already off */ |
ce6120cc | 647 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) |
2d4cdd6f | 648 | return 0; |
3a7aaed7 IK |
649 | ret = dac33_hard_power(codec, 0); |
650 | if (ret != 0) | |
651 | return ret; | |
c8bf93f0 PU |
652 | break; |
653 | } | |
ce6120cc | 654 | codec->dapm.bias_level = level; |
c8bf93f0 PU |
655 | |
656 | return 0; | |
657 | } | |
658 | ||
d4f102d4 PU |
659 | static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) |
660 | { | |
f0fba2ad | 661 | struct snd_soc_codec *codec = dac33->codec; |
84eae18c | 662 | unsigned int delay; |
a3b55791 | 663 | unsigned long flags; |
d4f102d4 PU |
664 | |
665 | switch (dac33->fifo_mode) { | |
666 | case DAC33_FIFO_MODE1: | |
667 | dac33_write16(codec, DAC33_NSAMPLE_MSB, | |
f430a27f | 668 | DAC33_THRREG(dac33->nsample)); |
f57d2cfa PU |
669 | |
670 | /* Take the timestamps */ | |
a3b55791 | 671 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa PU |
672 | dac33->t_stamp2 = ktime_to_us(ktime_get()); |
673 | dac33->t_stamp1 = dac33->t_stamp2; | |
a3b55791 | 674 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa | 675 | |
d4f102d4 PU |
676 | dac33_write16(codec, DAC33_PREFILL_MSB, |
677 | DAC33_THRREG(dac33->alarm_threshold)); | |
f4d59328 | 678 | /* Enable Alarm Threshold IRQ with a delay */ |
84eae18c PU |
679 | delay = SAMPLES_TO_US(dac33->burst_rate, |
680 | dac33->alarm_threshold) + 1000; | |
681 | usleep_range(delay, delay + 500); | |
f4d59328 | 682 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT); |
d4f102d4 | 683 | break; |
28e05d98 | 684 | case DAC33_FIFO_MODE7: |
f57d2cfa | 685 | /* Take the timestamp */ |
a3b55791 | 686 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa PU |
687 | dac33->t_stamp1 = ktime_to_us(ktime_get()); |
688 | /* Move back the timestamp with drain time */ | |
689 | dac33->t_stamp1 -= dac33->mode7_us_to_lthr; | |
a3b55791 | 690 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa | 691 | |
28e05d98 | 692 | dac33_write16(codec, DAC33_PREFILL_MSB, |
549675ed | 693 | DAC33_THRREG(DAC33_MODE7_MARGIN)); |
f57d2cfa PU |
694 | |
695 | /* Enable Upper Threshold IRQ */ | |
696 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); | |
28e05d98 | 697 | break; |
d4f102d4 PU |
698 | default: |
699 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
700 | dac33->fifo_mode); | |
701 | break; | |
702 | } | |
703 | } | |
704 | ||
705 | static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) | |
706 | { | |
f0fba2ad | 707 | struct snd_soc_codec *codec = dac33->codec; |
a3b55791 | 708 | unsigned long flags; |
d4f102d4 PU |
709 | |
710 | switch (dac33->fifo_mode) { | |
711 | case DAC33_FIFO_MODE1: | |
f57d2cfa | 712 | /* Take the timestamp */ |
a3b55791 | 713 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa | 714 | dac33->t_stamp2 = ktime_to_us(ktime_get()); |
a3b55791 | 715 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa | 716 | |
d4f102d4 PU |
717 | dac33_write16(codec, DAC33_NSAMPLE_MSB, |
718 | DAC33_THRREG(dac33->nsample)); | |
719 | break; | |
28e05d98 PU |
720 | case DAC33_FIFO_MODE7: |
721 | /* At the moment we are not using interrupts in mode7 */ | |
722 | break; | |
d4f102d4 PU |
723 | default: |
724 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
725 | dac33->fifo_mode); | |
726 | break; | |
727 | } | |
728 | } | |
729 | ||
c8bf93f0 PU |
730 | static void dac33_work(struct work_struct *work) |
731 | { | |
732 | struct snd_soc_codec *codec; | |
733 | struct tlv320dac33_priv *dac33; | |
734 | u8 reg; | |
735 | ||
736 | dac33 = container_of(work, struct tlv320dac33_priv, work); | |
f0fba2ad | 737 | codec = dac33->codec; |
c8bf93f0 PU |
738 | |
739 | mutex_lock(&dac33->mutex); | |
740 | switch (dac33->state) { | |
741 | case DAC33_PREFILL: | |
742 | dac33->state = DAC33_PLAYBACK; | |
d4f102d4 | 743 | dac33_prefill_handler(dac33); |
c8bf93f0 PU |
744 | break; |
745 | case DAC33_PLAYBACK: | |
d4f102d4 | 746 | dac33_playback_handler(dac33); |
c8bf93f0 PU |
747 | break; |
748 | case DAC33_IDLE: | |
749 | break; | |
750 | case DAC33_FLUSH: | |
751 | dac33->state = DAC33_IDLE; | |
752 | /* Mask all interrupts from dac33 */ | |
753 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); | |
754 | ||
755 | /* flush fifo */ | |
756 | reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); | |
757 | reg |= DAC33_FIFOFLUSH; | |
758 | dac33_write(codec, DAC33_FIFO_CTRL_A, reg); | |
759 | break; | |
760 | } | |
761 | mutex_unlock(&dac33->mutex); | |
762 | } | |
763 | ||
764 | static irqreturn_t dac33_interrupt_handler(int irq, void *dev) | |
765 | { | |
766 | struct snd_soc_codec *codec = dev; | |
b2c812e2 | 767 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
a3b55791 | 768 | unsigned long flags; |
c8bf93f0 | 769 | |
a3b55791 | 770 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa | 771 | dac33->t_stamp1 = ktime_to_us(ktime_get()); |
a3b55791 | 772 | spin_unlock_irqrestore(&dac33->lock, flags); |
c8bf93f0 | 773 | |
f57d2cfa PU |
774 | /* Do not schedule the workqueue in Mode7 */ |
775 | if (dac33->fifo_mode != DAC33_FIFO_MODE7) | |
776 | queue_work(dac33->dac33_wq, &dac33->work); | |
c8bf93f0 | 777 | |
c8bf93f0 | 778 | return IRQ_HANDLED; |
c8bf93f0 PU |
779 | } |
780 | ||
781 | static void dac33_oscwait(struct snd_soc_codec *codec) | |
782 | { | |
84eae18c | 783 | int timeout = 60; |
c8bf93f0 PU |
784 | u8 reg; |
785 | ||
786 | do { | |
84eae18c | 787 | usleep_range(1000, 2000); |
c8bf93f0 PU |
788 | dac33_read(codec, DAC33_INT_OSC_STATUS, ®); |
789 | } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); | |
790 | if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) | |
791 | dev_err(codec->dev, | |
792 | "internal oscillator calibration failed\n"); | |
793 | } | |
794 | ||
0b61d2b9 PU |
795 | static int dac33_startup(struct snd_pcm_substream *substream, |
796 | struct snd_soc_dai *dai) | |
797 | { | |
e6968a17 | 798 | struct snd_soc_codec *codec = dai->codec; |
0b61d2b9 PU |
799 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
800 | ||
801 | /* Stream started, save the substream pointer */ | |
802 | dac33->substream = substream; | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
807 | static void dac33_shutdown(struct snd_pcm_substream *substream, | |
808 | struct snd_soc_dai *dai) | |
809 | { | |
e6968a17 | 810 | struct snd_soc_codec *codec = dai->codec; |
0b61d2b9 PU |
811 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
812 | ||
813 | dac33->substream = NULL; | |
814 | } | |
815 | ||
549675ed PU |
816 | #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ |
817 | (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) | |
c8bf93f0 PU |
818 | static int dac33_hw_params(struct snd_pcm_substream *substream, |
819 | struct snd_pcm_hw_params *params, | |
820 | struct snd_soc_dai *dai) | |
821 | { | |
e6968a17 | 822 | struct snd_soc_codec *codec = dai->codec; |
549675ed | 823 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
824 | |
825 | /* Check parameters for validity */ | |
826 | switch (params_rate(params)) { | |
827 | case 44100: | |
828 | case 48000: | |
829 | break; | |
830 | default: | |
831 | dev_err(codec->dev, "unsupported rate %d\n", | |
832 | params_rate(params)); | |
833 | return -EINVAL; | |
834 | } | |
835 | ||
c60f23cb MB |
836 | switch (params_width(params)) { |
837 | case 16: | |
549675ed PU |
838 | dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; |
839 | dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); | |
c8bf93f0 | 840 | break; |
c60f23cb | 841 | case 32: |
0d99d2b0 PU |
842 | dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; |
843 | dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); | |
844 | break; | |
c8bf93f0 | 845 | default: |
c60f23cb MB |
846 | dev_err(codec->dev, "unsupported width %d\n", |
847 | params_width(params)); | |
c8bf93f0 PU |
848 | return -EINVAL; |
849 | } | |
850 | ||
851 | return 0; | |
852 | } | |
853 | ||
854 | #define CALC_OSCSET(rate, refclk) ( \ | |
7833ae0e | 855 | ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) |
c8bf93f0 PU |
856 | #define CALC_RATIOSET(rate, refclk) ( \ |
857 | ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) | |
858 | ||
859 | /* | |
860 | * tlv320dac33 is strict on the sequence of the register writes, if the register | |
861 | * writes happens in different order, than dac33 might end up in unknown state. | |
862 | * Use the known, working sequence of register writes to initialize the dac33. | |
863 | */ | |
e6968a17 MB |
864 | static int dac33_prepare_chip(struct snd_pcm_substream *substream, |
865 | struct snd_soc_codec *codec) | |
c8bf93f0 | 866 | { |
b2c812e2 | 867 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 868 | unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; |
aec242dc | 869 | u8 aictrl_a, aictrl_b, fifoctrl_a; |
c8bf93f0 PU |
870 | |
871 | switch (substream->runtime->rate) { | |
872 | case 44100: | |
873 | case 48000: | |
874 | oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); | |
875 | ratioset = CALC_RATIOSET(substream->runtime->rate, | |
876 | dac33->refclk); | |
877 | break; | |
878 | default: | |
879 | dev_err(codec->dev, "unsupported rate %d\n", | |
880 | substream->runtime->rate); | |
881 | return -EINVAL; | |
882 | } | |
883 | ||
884 | ||
885 | aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); | |
886 | aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); | |
e5e878c1 | 887 | /* Read FIFO control A, and clear FIFO flush bit */ |
c8bf93f0 | 888 | fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); |
e5e878c1 PU |
889 | fifoctrl_a &= ~DAC33_FIFOFLUSH; |
890 | ||
c8bf93f0 PU |
891 | fifoctrl_a &= ~DAC33_WIDTH; |
892 | switch (substream->runtime->format) { | |
893 | case SNDRV_PCM_FORMAT_S16_LE: | |
894 | aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); | |
895 | fifoctrl_a |= DAC33_WIDTH; | |
896 | break; | |
0d99d2b0 PU |
897 | case SNDRV_PCM_FORMAT_S32_LE: |
898 | aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); | |
899 | break; | |
c8bf93f0 PU |
900 | default: |
901 | dev_err(codec->dev, "unsupported format %d\n", | |
902 | substream->runtime->format); | |
903 | return -EINVAL; | |
904 | } | |
905 | ||
906 | mutex_lock(&dac33->mutex); | |
ad05c03b PU |
907 | |
908 | if (!dac33->chip_power) { | |
909 | /* | |
910 | * Chip is not powered yet. | |
911 | * Do the init in the dac33_set_bias_level later. | |
912 | */ | |
913 | mutex_unlock(&dac33->mutex); | |
914 | return 0; | |
915 | } | |
916 | ||
c3746a07 | 917 | dac33_soft_power(codec, 0); |
c8bf93f0 PU |
918 | dac33_soft_power(codec, 1); |
919 | ||
920 | reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); | |
921 | dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp); | |
922 | ||
923 | /* Write registers 0x08 and 0x09 (MSB, LSB) */ | |
924 | dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset); | |
925 | ||
82a58a8b PU |
926 | /* OSC calibration time */ |
927 | dac33_write(codec, DAC33_CALIB_TIME, 96); | |
c8bf93f0 PU |
928 | |
929 | /* adjustment treshold & step */ | |
930 | dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | | |
931 | DAC33_ADJSTEP(1)); | |
932 | ||
933 | /* div=4 / gain=1 / div */ | |
934 | dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); | |
935 | ||
936 | pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
937 | pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; | |
938 | dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl); | |
939 | ||
940 | dac33_oscwait(codec); | |
941 | ||
7427b4b9 | 942 | if (dac33->fifo_mode) { |
aec242dc | 943 | /* Generic for all FIFO modes */ |
c8bf93f0 | 944 | /* 50-51 : ASRC Control registers */ |
fdb6b1e1 | 945 | dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); |
c8bf93f0 PU |
946 | dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */ |
947 | ||
948 | /* Write registers 0x34 and 0x35 (MSB, LSB) */ | |
949 | dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset); | |
950 | ||
951 | /* Set interrupts to high active */ | |
952 | dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); | |
c8bf93f0 | 953 | } else { |
aec242dc | 954 | /* FIFO bypass mode */ |
c8bf93f0 PU |
955 | /* 50-51 : ASRC Control registers */ |
956 | dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); | |
957 | dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */ | |
958 | } | |
959 | ||
aec242dc PU |
960 | /* Interrupt behaviour configuration */ |
961 | switch (dac33->fifo_mode) { | |
962 | case DAC33_FIFO_MODE1: | |
963 | dac33_write(codec, DAC33_FIFO_IRQ_MODE_B, | |
964 | DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); | |
aec242dc | 965 | break; |
28e05d98 | 966 | case DAC33_FIFO_MODE7: |
f57d2cfa PU |
967 | dac33_write(codec, DAC33_FIFO_IRQ_MODE_A, |
968 | DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); | |
28e05d98 | 969 | break; |
aec242dc PU |
970 | default: |
971 | /* in FIFO bypass mode, the interrupts are not used */ | |
972 | break; | |
973 | } | |
974 | ||
975 | aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
976 | ||
977 | switch (dac33->fifo_mode) { | |
978 | case DAC33_FIFO_MODE1: | |
979 | /* | |
980 | * For mode1: | |
981 | * Disable the FIFO bypass (Enable the use of FIFO) | |
982 | * Select nSample mode | |
983 | * BCLK is only running when data is needed by DAC33 | |
984 | */ | |
c8bf93f0 | 985 | fifoctrl_a &= ~DAC33_FBYPAS; |
aec242dc | 986 | fifoctrl_a &= ~DAC33_FAUTO; |
eeb309a8 PU |
987 | if (dac33->keep_bclk) |
988 | aictrl_b |= DAC33_BCLKON; | |
989 | else | |
990 | aictrl_b &= ~DAC33_BCLKON; | |
aec242dc | 991 | break; |
28e05d98 PU |
992 | case DAC33_FIFO_MODE7: |
993 | /* | |
994 | * For mode1: | |
995 | * Disable the FIFO bypass (Enable the use of FIFO) | |
996 | * Select Threshold mode | |
997 | * BCLK is only running when data is needed by DAC33 | |
998 | */ | |
999 | fifoctrl_a &= ~DAC33_FBYPAS; | |
1000 | fifoctrl_a |= DAC33_FAUTO; | |
eeb309a8 PU |
1001 | if (dac33->keep_bclk) |
1002 | aictrl_b |= DAC33_BCLKON; | |
1003 | else | |
1004 | aictrl_b &= ~DAC33_BCLKON; | |
28e05d98 | 1005 | break; |
aec242dc PU |
1006 | default: |
1007 | /* | |
1008 | * For FIFO bypass mode: | |
1009 | * Enable the FIFO bypass (Disable the FIFO use) | |
25985edc | 1010 | * Set the BCLK as continuous |
aec242dc | 1011 | */ |
c8bf93f0 | 1012 | fifoctrl_a |= DAC33_FBYPAS; |
aec242dc PU |
1013 | aictrl_b |= DAC33_BCLKON; |
1014 | break; | |
1015 | } | |
c8bf93f0 | 1016 | |
aec242dc | 1017 | dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a); |
c8bf93f0 | 1018 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); |
aec242dc | 1019 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); |
c8bf93f0 | 1020 | |
6aceabb4 PU |
1021 | /* |
1022 | * BCLK divide ratio | |
1023 | * 0: 1.5 | |
1024 | * 1: 1 | |
1025 | * 2: 2 | |
1026 | * ... | |
1027 | * 254: 254 | |
1028 | * 255: 255 | |
1029 | */ | |
6cd6cede | 1030 | if (dac33->fifo_mode) |
6aceabb4 PU |
1031 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, |
1032 | dac33->burst_bclkdiv); | |
6cd6cede | 1033 | else |
0d99d2b0 PU |
1034 | if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) |
1035 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); | |
1036 | else | |
1037 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16); | |
c8bf93f0 | 1038 | |
6cd6cede PU |
1039 | switch (dac33->fifo_mode) { |
1040 | case DAC33_FIFO_MODE1: | |
c8bf93f0 PU |
1041 | dac33_write16(codec, DAC33_ATHR_MSB, |
1042 | DAC33_THRREG(dac33->alarm_threshold)); | |
aec242dc | 1043 | break; |
28e05d98 PU |
1044 | case DAC33_FIFO_MODE7: |
1045 | /* | |
1046 | * Configure the threshold levels, and leave 10 sample space | |
1047 | * at the bottom, and also at the top of the FIFO | |
1048 | */ | |
9d7db2b2 | 1049 | dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); |
549675ed PU |
1050 | dac33_write16(codec, DAC33_LTHR_MSB, |
1051 | DAC33_THRREG(DAC33_MODE7_MARGIN)); | |
28e05d98 | 1052 | break; |
aec242dc | 1053 | default: |
aec242dc | 1054 | break; |
c8bf93f0 PU |
1055 | } |
1056 | ||
1057 | mutex_unlock(&dac33->mutex); | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
e6968a17 MB |
1062 | static void dac33_calculate_times(struct snd_pcm_substream *substream, |
1063 | struct snd_soc_codec *codec) | |
c8bf93f0 | 1064 | { |
b2c812e2 | 1065 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
f430a27f PU |
1066 | unsigned int period_size = substream->runtime->period_size; |
1067 | unsigned int rate = substream->runtime->rate; | |
c8bf93f0 PU |
1068 | unsigned int nsample_limit; |
1069 | ||
55abb59c PU |
1070 | /* In bypass mode we don't need to calculate */ |
1071 | if (!dac33->fifo_mode) | |
1072 | return; | |
1073 | ||
f57d2cfa PU |
1074 | switch (dac33->fifo_mode) { |
1075 | case DAC33_FIFO_MODE1: | |
f430a27f PU |
1076 | /* Number of samples under i2c latency */ |
1077 | dac33->alarm_threshold = US_TO_SAMPLES(rate, | |
1078 | dac33->mode1_latency); | |
549675ed | 1079 | nsample_limit = dac33->fifo_size - dac33->alarm_threshold; |
1bc13b2e | 1080 | |
3591f4cd | 1081 | if (period_size <= dac33->alarm_threshold) |
a577b318 | 1082 | /* |
3591f4cd PU |
1083 | * Configure nSamaple to number of periods, |
1084 | * which covers the latency requironment. | |
a577b318 | 1085 | */ |
3591f4cd PU |
1086 | dac33->nsample = period_size * |
1087 | ((dac33->alarm_threshold / period_size) + | |
1088 | (dac33->alarm_threshold % period_size ? | |
1089 | 1 : 0)); | |
1090 | else if (period_size > nsample_limit) | |
1091 | dac33->nsample = nsample_limit; | |
1092 | else | |
1093 | dac33->nsample = period_size; | |
f430a27f | 1094 | |
f57d2cfa PU |
1095 | dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, |
1096 | dac33->nsample); | |
1097 | dac33->t_stamp1 = 0; | |
1098 | dac33->t_stamp2 = 0; | |
1099 | break; | |
1100 | case DAC33_FIFO_MODE7: | |
3591f4cd PU |
1101 | dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, |
1102 | dac33->burst_rate) + 9; | |
549675ed PU |
1103 | if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) |
1104 | dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; | |
1105 | if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) | |
1106 | dac33->uthr = (DAC33_MODE7_MARGIN + 10); | |
3591f4cd | 1107 | |
f57d2cfa | 1108 | dac33->mode7_us_to_lthr = |
9d7db2b2 | 1109 | SAMPLES_TO_US(substream->runtime->rate, |
549675ed | 1110 | dac33->uthr - DAC33_MODE7_MARGIN + 1); |
f57d2cfa PU |
1111 | dac33->t_stamp1 = 0; |
1112 | break; | |
1113 | default: | |
1114 | break; | |
1115 | } | |
c8bf93f0 | 1116 | |
c8bf93f0 PU |
1117 | } |
1118 | ||
1119 | static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, | |
1120 | struct snd_soc_dai *dai) | |
1121 | { | |
e6968a17 | 1122 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1123 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1124 | int ret = 0; |
1125 | ||
1126 | switch (cmd) { | |
1127 | case SNDRV_PCM_TRIGGER_START: | |
1128 | case SNDRV_PCM_TRIGGER_RESUME: | |
1129 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
7427b4b9 | 1130 | if (dac33->fifo_mode) { |
c8bf93f0 PU |
1131 | dac33->state = DAC33_PREFILL; |
1132 | queue_work(dac33->dac33_wq, &dac33->work); | |
1133 | } | |
1134 | break; | |
1135 | case SNDRV_PCM_TRIGGER_STOP: | |
1136 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
1137 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
7427b4b9 | 1138 | if (dac33->fifo_mode) { |
c8bf93f0 PU |
1139 | dac33->state = DAC33_FLUSH; |
1140 | queue_work(dac33->dac33_wq, &dac33->work); | |
1141 | } | |
1142 | break; | |
1143 | default: | |
1144 | ret = -EINVAL; | |
1145 | } | |
1146 | ||
1147 | return ret; | |
1148 | } | |
1149 | ||
f57d2cfa PU |
1150 | static snd_pcm_sframes_t dac33_dai_delay( |
1151 | struct snd_pcm_substream *substream, | |
1152 | struct snd_soc_dai *dai) | |
1153 | { | |
e6968a17 | 1154 | struct snd_soc_codec *codec = dai->codec; |
f57d2cfa PU |
1155 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
1156 | unsigned long long t0, t1, t_now; | |
9d7db2b2 | 1157 | unsigned int time_delta, uthr; |
f57d2cfa PU |
1158 | int samples_out, samples_in, samples; |
1159 | snd_pcm_sframes_t delay = 0; | |
a3b55791 | 1160 | unsigned long flags; |
f57d2cfa PU |
1161 | |
1162 | switch (dac33->fifo_mode) { | |
1163 | case DAC33_FIFO_BYPASS: | |
1164 | break; | |
1165 | case DAC33_FIFO_MODE1: | |
a3b55791 | 1166 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa PU |
1167 | t0 = dac33->t_stamp1; |
1168 | t1 = dac33->t_stamp2; | |
a3b55791 | 1169 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa PU |
1170 | t_now = ktime_to_us(ktime_get()); |
1171 | ||
1172 | /* We have not started to fill the FIFO yet, delay is 0 */ | |
1173 | if (!t1) | |
1174 | goto out; | |
1175 | ||
1176 | if (t0 > t1) { | |
1177 | /* | |
1178 | * Phase 1: | |
1179 | * After Alarm threshold, and before nSample write | |
1180 | */ | |
1181 | time_delta = t_now - t0; | |
1182 | samples_out = time_delta ? US_TO_SAMPLES( | |
1183 | substream->runtime->rate, | |
1184 | time_delta) : 0; | |
1185 | ||
1186 | if (likely(dac33->alarm_threshold > samples_out)) | |
1187 | delay = dac33->alarm_threshold - samples_out; | |
1188 | else | |
1189 | delay = 0; | |
1190 | } else if ((t_now - t1) <= dac33->mode1_us_burst) { | |
1191 | /* | |
1192 | * Phase 2: | |
1193 | * After nSample write (during burst operation) | |
1194 | */ | |
1195 | time_delta = t_now - t0; | |
1196 | samples_out = time_delta ? US_TO_SAMPLES( | |
1197 | substream->runtime->rate, | |
1198 | time_delta) : 0; | |
1199 | ||
1200 | time_delta = t_now - t1; | |
1201 | samples_in = time_delta ? US_TO_SAMPLES( | |
1202 | dac33->burst_rate, | |
1203 | time_delta) : 0; | |
1204 | ||
1205 | samples = dac33->alarm_threshold; | |
1206 | samples += (samples_in - samples_out); | |
1207 | ||
1208 | if (likely(samples > 0)) | |
1209 | delay = samples; | |
1210 | else | |
1211 | delay = 0; | |
1212 | } else { | |
1213 | /* | |
1214 | * Phase 3: | |
1215 | * After burst operation, before next alarm threshold | |
1216 | */ | |
1217 | time_delta = t_now - t0; | |
1218 | samples_out = time_delta ? US_TO_SAMPLES( | |
1219 | substream->runtime->rate, | |
1220 | time_delta) : 0; | |
1221 | ||
1222 | samples_in = dac33->nsample; | |
1223 | samples = dac33->alarm_threshold; | |
1224 | samples += (samples_in - samples_out); | |
1225 | ||
1226 | if (likely(samples > 0)) | |
549675ed PU |
1227 | delay = samples > dac33->fifo_size ? |
1228 | dac33->fifo_size : samples; | |
f57d2cfa PU |
1229 | else |
1230 | delay = 0; | |
1231 | } | |
1232 | break; | |
1233 | case DAC33_FIFO_MODE7: | |
a3b55791 | 1234 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa | 1235 | t0 = dac33->t_stamp1; |
9d7db2b2 | 1236 | uthr = dac33->uthr; |
a3b55791 | 1237 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa PU |
1238 | t_now = ktime_to_us(ktime_get()); |
1239 | ||
1240 | /* We have not started to fill the FIFO yet, delay is 0 */ | |
1241 | if (!t0) | |
1242 | goto out; | |
1243 | ||
1244 | if (t_now <= t0) { | |
1245 | /* | |
1246 | * Either the timestamps are messed or equal. Report | |
1247 | * maximum delay | |
1248 | */ | |
9d7db2b2 | 1249 | delay = uthr; |
f57d2cfa PU |
1250 | goto out; |
1251 | } | |
1252 | ||
1253 | time_delta = t_now - t0; | |
1254 | if (time_delta <= dac33->mode7_us_to_lthr) { | |
1255 | /* | |
1256 | * Phase 1: | |
1257 | * After burst (draining phase) | |
1258 | */ | |
1259 | samples_out = US_TO_SAMPLES( | |
1260 | substream->runtime->rate, | |
1261 | time_delta); | |
1262 | ||
9d7db2b2 PU |
1263 | if (likely(uthr > samples_out)) |
1264 | delay = uthr - samples_out; | |
f57d2cfa PU |
1265 | else |
1266 | delay = 0; | |
1267 | } else { | |
1268 | /* | |
1269 | * Phase 2: | |
1270 | * During burst operation | |
1271 | */ | |
1272 | time_delta = time_delta - dac33->mode7_us_to_lthr; | |
1273 | ||
1274 | samples_out = US_TO_SAMPLES( | |
1275 | substream->runtime->rate, | |
1276 | time_delta); | |
1277 | samples_in = US_TO_SAMPLES( | |
1278 | dac33->burst_rate, | |
1279 | time_delta); | |
549675ed | 1280 | delay = DAC33_MODE7_MARGIN + samples_in - samples_out; |
f57d2cfa | 1281 | |
9d7db2b2 PU |
1282 | if (unlikely(delay > uthr)) |
1283 | delay = uthr; | |
f57d2cfa PU |
1284 | } |
1285 | break; | |
1286 | default: | |
1287 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
1288 | dac33->fifo_mode); | |
1289 | break; | |
1290 | } | |
1291 | out: | |
1292 | return delay; | |
1293 | } | |
1294 | ||
c8bf93f0 PU |
1295 | static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
1296 | int clk_id, unsigned int freq, int dir) | |
1297 | { | |
1298 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1299 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1300 | u8 ioc_reg, asrcb_reg; |
1301 | ||
1302 | ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); | |
1303 | asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B); | |
1304 | switch (clk_id) { | |
1305 | case TLV320DAC33_MCLK: | |
1306 | ioc_reg |= DAC33_REFSEL; | |
1307 | asrcb_reg |= DAC33_SRCREFSEL; | |
1308 | break; | |
1309 | case TLV320DAC33_SLEEPCLK: | |
1310 | ioc_reg &= ~DAC33_REFSEL; | |
1311 | asrcb_reg &= ~DAC33_SRCREFSEL; | |
1312 | break; | |
1313 | default: | |
1314 | dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id); | |
1315 | break; | |
1316 | } | |
1317 | dac33->refclk = freq; | |
1318 | ||
1319 | dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg); | |
1320 | dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg); | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
1325 | static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1326 | unsigned int fmt) | |
1327 | { | |
1328 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1329 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1330 | u8 aictrl_a, aictrl_b; |
1331 | ||
1332 | aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); | |
1333 | aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
1334 | /* set master/slave audio interface */ | |
1335 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1336 | case SND_SOC_DAIFMT_CBM_CFM: | |
1337 | /* Codec Master */ | |
1338 | aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); | |
1339 | break; | |
1340 | case SND_SOC_DAIFMT_CBS_CFS: | |
1341 | /* Codec Slave */ | |
adcb8bc0 PU |
1342 | if (dac33->fifo_mode) { |
1343 | dev_err(codec->dev, "FIFO mode requires master mode\n"); | |
1344 | return -EINVAL; | |
1345 | } else | |
1346 | aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); | |
c8bf93f0 PU |
1347 | break; |
1348 | default: | |
1349 | return -EINVAL; | |
1350 | } | |
1351 | ||
1352 | aictrl_a &= ~DAC33_AFMT_MASK; | |
1353 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1354 | case SND_SOC_DAIFMT_I2S: | |
1355 | aictrl_a |= DAC33_AFMT_I2S; | |
1356 | break; | |
1357 | case SND_SOC_DAIFMT_DSP_A: | |
1358 | aictrl_a |= DAC33_AFMT_DSP; | |
1359 | aictrl_b &= ~DAC33_DATA_DELAY_MASK; | |
44f497b4 | 1360 | aictrl_b |= DAC33_DATA_DELAY(0); |
c8bf93f0 PU |
1361 | break; |
1362 | case SND_SOC_DAIFMT_RIGHT_J: | |
1363 | aictrl_a |= DAC33_AFMT_RIGHT_J; | |
1364 | break; | |
1365 | case SND_SOC_DAIFMT_LEFT_J: | |
1366 | aictrl_a |= DAC33_AFMT_LEFT_J; | |
1367 | break; | |
1368 | default: | |
1369 | dev_err(codec->dev, "Unsupported format (%u)\n", | |
1370 | fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1371 | return -EINVAL; | |
1372 | } | |
1373 | ||
1374 | dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); | |
1375 | dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); | |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
f0fba2ad | 1380 | static int dac33_soc_probe(struct snd_soc_codec *codec) |
c8bf93f0 | 1381 | { |
f0fba2ad | 1382 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1383 | int ret = 0; |
1384 | ||
f0fba2ad LG |
1385 | codec->control_data = dac33->control_data; |
1386 | codec->hw_write = (hw_write_t) i2c_master_send; | |
f0fba2ad | 1387 | dac33->codec = codec; |
c8bf93f0 | 1388 | |
f0fba2ad LG |
1389 | /* Read the tlv320dac33 ID registers */ |
1390 | ret = dac33_hard_power(codec, 1); | |
1391 | if (ret != 0) { | |
1392 | dev_err(codec->dev, "Failed to power up codec: %d\n", ret); | |
1393 | goto err_power; | |
1394 | } | |
911a0f0b | 1395 | ret = dac33_read_id(codec); |
f0fba2ad | 1396 | dac33_hard_power(codec, 0); |
c8bf93f0 | 1397 | |
911a0f0b PU |
1398 | if (ret < 0) { |
1399 | dev_err(codec->dev, "Failed to read chip ID: %d\n", ret); | |
1400 | ret = -ENODEV; | |
1401 | goto err_power; | |
1402 | } | |
1403 | ||
f0fba2ad LG |
1404 | /* Check if the IRQ number is valid and request it */ |
1405 | if (dac33->irq >= 0) { | |
1406 | ret = request_irq(dac33->irq, dac33_interrupt_handler, | |
88e24c3a | 1407 | IRQF_TRIGGER_RISING, |
f4333203 | 1408 | codec->component.name, codec); |
f0fba2ad LG |
1409 | if (ret < 0) { |
1410 | dev_err(codec->dev, "Could not request IRQ%d (%d)\n", | |
1411 | dac33->irq, ret); | |
1412 | dac33->irq = -1; | |
1413 | } | |
1414 | if (dac33->irq != -1) { | |
1415 | /* Setup work queue */ | |
1416 | dac33->dac33_wq = | |
1417 | create_singlethread_workqueue("tlv320dac33"); | |
1418 | if (dac33->dac33_wq == NULL) { | |
1419 | free_irq(dac33->irq, codec); | |
1420 | return -ENOMEM; | |
1421 | } | |
1422 | ||
1423 | INIT_WORK(&dac33->work, dac33_work); | |
1424 | } | |
c8bf93f0 PU |
1425 | } |
1426 | ||
a577b318 | 1427 | /* Only add the FIFO controls, if we have valid IRQ number */ |
3591f4cd | 1428 | if (dac33->irq >= 0) |
022658be | 1429 | snd_soc_add_codec_controls(codec, dac33_mode_snd_controls, |
a577b318 | 1430 | ARRAY_SIZE(dac33_mode_snd_controls)); |
3591f4cd | 1431 | |
f0fba2ad | 1432 | err_power: |
c8bf93f0 PU |
1433 | return ret; |
1434 | } | |
1435 | ||
f0fba2ad | 1436 | static int dac33_soc_remove(struct snd_soc_codec *codec) |
c8bf93f0 | 1437 | { |
f0fba2ad | 1438 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 1439 | |
f0fba2ad LG |
1440 | if (dac33->irq >= 0) { |
1441 | free_irq(dac33->irq, dac33->codec); | |
1442 | destroy_workqueue(dac33->dac33_wq); | |
1443 | } | |
c8bf93f0 PU |
1444 | return 0; |
1445 | } | |
1446 | ||
f0fba2ad LG |
1447 | static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { |
1448 | .read = dac33_read_reg_cache, | |
1449 | .write = dac33_write_locked, | |
1450 | .set_bias_level = dac33_set_bias_level, | |
eb3032f8 | 1451 | .idle_bias_off = true, |
f0fba2ad LG |
1452 | .reg_cache_size = ARRAY_SIZE(dac33_reg), |
1453 | .reg_word_size = sizeof(u8), | |
1454 | .reg_cache_default = dac33_reg, | |
c8bf93f0 PU |
1455 | .probe = dac33_soc_probe, |
1456 | .remove = dac33_soc_remove, | |
8066eb55 PU |
1457 | |
1458 | .controls = dac33_snd_controls, | |
1459 | .num_controls = ARRAY_SIZE(dac33_snd_controls), | |
1460 | .dapm_widgets = dac33_dapm_widgets, | |
1461 | .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets), | |
1462 | .dapm_routes = audio_map, | |
1463 | .num_dapm_routes = ARRAY_SIZE(audio_map), | |
c8bf93f0 | 1464 | }; |
c8bf93f0 PU |
1465 | |
1466 | #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ | |
1467 | SNDRV_PCM_RATE_48000) | |
0d99d2b0 | 1468 | #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) |
c8bf93f0 | 1469 | |
85e7652d | 1470 | static const struct snd_soc_dai_ops dac33_dai_ops = { |
0b61d2b9 | 1471 | .startup = dac33_startup, |
c8bf93f0 PU |
1472 | .shutdown = dac33_shutdown, |
1473 | .hw_params = dac33_hw_params, | |
c8bf93f0 | 1474 | .trigger = dac33_pcm_trigger, |
f57d2cfa | 1475 | .delay = dac33_dai_delay, |
c8bf93f0 PU |
1476 | .set_sysclk = dac33_set_dai_sysclk, |
1477 | .set_fmt = dac33_set_dai_fmt, | |
1478 | }; | |
1479 | ||
f0fba2ad LG |
1480 | static struct snd_soc_dai_driver dac33_dai = { |
1481 | .name = "tlv320dac33-hifi", | |
c8bf93f0 PU |
1482 | .playback = { |
1483 | .stream_name = "Playback", | |
1484 | .channels_min = 2, | |
1485 | .channels_max = 2, | |
1486 | .rates = DAC33_RATES, | |
3a4cbf88 | 1487 | .formats = DAC33_FORMATS, |
8d725b2b | 1488 | .sig_bits = 24, |
3a4cbf88 | 1489 | }, |
c8bf93f0 PU |
1490 | .ops = &dac33_dai_ops, |
1491 | }; | |
c8bf93f0 | 1492 | |
7a79e94e BP |
1493 | static int dac33_i2c_probe(struct i2c_client *client, |
1494 | const struct i2c_device_id *id) | |
c8bf93f0 PU |
1495 | { |
1496 | struct tlv320dac33_platform_data *pdata; | |
1497 | struct tlv320dac33_priv *dac33; | |
3a7aaed7 | 1498 | int ret, i; |
c8bf93f0 PU |
1499 | |
1500 | if (client->dev.platform_data == NULL) { | |
1501 | dev_err(&client->dev, "Platform data not set\n"); | |
1502 | return -ENODEV; | |
1503 | } | |
1504 | pdata = client->dev.platform_data; | |
1505 | ||
a54877d7 AL |
1506 | dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv), |
1507 | GFP_KERNEL); | |
c8bf93f0 PU |
1508 | if (dac33 == NULL) |
1509 | return -ENOMEM; | |
1510 | ||
f0fba2ad | 1511 | dac33->control_data = client; |
c8bf93f0 | 1512 | mutex_init(&dac33->mutex); |
f57d2cfa | 1513 | spin_lock_init(&dac33->lock); |
c8bf93f0 PU |
1514 | |
1515 | i2c_set_clientdata(client, dac33); | |
1516 | ||
1517 | dac33->power_gpio = pdata->power_gpio; | |
6aceabb4 | 1518 | dac33->burst_bclkdiv = pdata->burst_bclkdiv; |
eeb309a8 | 1519 | dac33->keep_bclk = pdata->keep_bclk; |
f430a27f PU |
1520 | dac33->mode1_latency = pdata->mode1_latency; |
1521 | if (!dac33->mode1_latency) | |
1522 | dac33->mode1_latency = 10000; /* 10ms */ | |
c8bf93f0 | 1523 | dac33->irq = client->irq; |
c8bf93f0 | 1524 | /* Disable FIFO use by default */ |
7427b4b9 | 1525 | dac33->fifo_mode = DAC33_FIFO_BYPASS; |
c8bf93f0 | 1526 | |
c8bf93f0 PU |
1527 | /* Check if the reset GPIO number is valid and request it */ |
1528 | if (dac33->power_gpio >= 0) { | |
1529 | ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset"); | |
1530 | if (ret < 0) { | |
f0fba2ad | 1531 | dev_err(&client->dev, |
c8bf93f0 PU |
1532 | "Failed to request reset GPIO (%d)\n", |
1533 | dac33->power_gpio); | |
f0fba2ad | 1534 | goto err_gpio; |
c8bf93f0 PU |
1535 | } |
1536 | gpio_direction_output(dac33->power_gpio, 0); | |
c8bf93f0 PU |
1537 | } |
1538 | ||
3a7aaed7 IK |
1539 | for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) |
1540 | dac33->supplies[i].supply = dac33_supply_names[i]; | |
1541 | ||
e9382e3b | 1542 | ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), |
3a7aaed7 IK |
1543 | dac33->supplies); |
1544 | ||
1545 | if (ret != 0) { | |
f0fba2ad | 1546 | dev_err(&client->dev, "Failed to request supplies: %d\n", ret); |
3a7aaed7 IK |
1547 | goto err_get; |
1548 | } | |
1549 | ||
f0fba2ad LG |
1550 | ret = snd_soc_register_codec(&client->dev, |
1551 | &soc_codec_dev_tlv320dac33, &dac33_dai, 1); | |
1552 | if (ret < 0) | |
e9382e3b | 1553 | goto err_get; |
c8bf93f0 | 1554 | |
c8bf93f0 | 1555 | return ret; |
3a7aaed7 | 1556 | err_get: |
c8bf93f0 PU |
1557 | if (dac33->power_gpio >= 0) |
1558 | gpio_free(dac33->power_gpio); | |
f0fba2ad | 1559 | err_gpio: |
c8bf93f0 PU |
1560 | return ret; |
1561 | } | |
1562 | ||
7a79e94e | 1563 | static int dac33_i2c_remove(struct i2c_client *client) |
c8bf93f0 | 1564 | { |
f0fba2ad | 1565 | struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); |
239fe55c PU |
1566 | |
1567 | if (unlikely(dac33->chip_power)) | |
f0fba2ad | 1568 | dac33_hard_power(dac33->codec, 0); |
c8bf93f0 PU |
1569 | |
1570 | if (dac33->power_gpio >= 0) | |
1571 | gpio_free(dac33->power_gpio); | |
c8bf93f0 | 1572 | |
f0fba2ad | 1573 | snd_soc_unregister_codec(&client->dev); |
c8bf93f0 PU |
1574 | return 0; |
1575 | } | |
1576 | ||
1577 | static const struct i2c_device_id tlv320dac33_i2c_id[] = { | |
1578 | { | |
1579 | .name = "tlv320dac33", | |
1580 | .driver_data = 0, | |
1581 | }, | |
1582 | { }, | |
1583 | }; | |
573f26e3 | 1584 | MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id); |
c8bf93f0 PU |
1585 | |
1586 | static struct i2c_driver tlv320dac33_i2c_driver = { | |
1587 | .driver = { | |
f0fba2ad | 1588 | .name = "tlv320dac33-codec", |
c8bf93f0 PU |
1589 | .owner = THIS_MODULE, |
1590 | }, | |
1591 | .probe = dac33_i2c_probe, | |
7a79e94e | 1592 | .remove = dac33_i2c_remove, |
c8bf93f0 PU |
1593 | .id_table = tlv320dac33_i2c_id, |
1594 | }; | |
1595 | ||
63a47a75 | 1596 | module_i2c_driver(tlv320dac33_i2c_driver); |
c8bf93f0 PU |
1597 | |
1598 | MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); | |
93864cf0 | 1599 | MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); |
c8bf93f0 | 1600 | MODULE_LICENSE("GPL"); |