Commit | Line | Data |
---|---|---|
c8bf93f0 PU |
1 | /* |
2 | * ALSA SoC Texas Instruments TLV320DAC33 codec driver | |
3 | * | |
93864cf0 | 4 | * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> |
c8bf93f0 PU |
5 | * |
6 | * Copyright: (C) 2009 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/moduleparam.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/pm.h> | |
29 | #include <linux/i2c.h> | |
c8bf93f0 PU |
30 | #include <linux/interrupt.h> |
31 | #include <linux/gpio.h> | |
3a7aaed7 | 32 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
c8bf93f0 PU |
34 | #include <sound/core.h> |
35 | #include <sound/pcm.h> | |
36 | #include <sound/pcm_params.h> | |
37 | #include <sound/soc.h> | |
c8bf93f0 PU |
38 | #include <sound/initval.h> |
39 | #include <sound/tlv.h> | |
40 | ||
41 | #include <sound/tlv320dac33-plat.h> | |
42 | #include "tlv320dac33.h" | |
43 | ||
549675ed PU |
44 | /* |
45 | * The internal FIFO is 24576 bytes long | |
46 | * It can be configured to hold 16bit or 24bit samples | |
47 | * In 16bit configuration the FIFO can hold 6144 stereo samples | |
48 | * In 24bit configuration the FIFO can hold 4096 stereo samples | |
49 | */ | |
50 | #define DAC33_FIFO_SIZE_16BIT 6144 | |
51 | #define DAC33_FIFO_SIZE_24BIT 4096 | |
52 | #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ | |
4260393e | 53 | |
76f47127 PU |
54 | #define BURST_BASEFREQ_HZ 49152000 |
55 | ||
f57d2cfa | 56 | #define SAMPLES_TO_US(rate, samples) \ |
c29429f3 | 57 | (1000000000 / (((rate) * 1000) / (samples))) |
f57d2cfa PU |
58 | |
59 | #define US_TO_SAMPLES(rate, us) \ | |
c29429f3 | 60 | ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000))) |
f57d2cfa | 61 | |
a577b318 | 62 | #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ |
c29429f3 | 63 | (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate)))) |
a577b318 | 64 | |
e6968a17 MB |
65 | static void dac33_calculate_times(struct snd_pcm_substream *substream, |
66 | struct snd_soc_codec *codec); | |
67 | static int dac33_prepare_chip(struct snd_pcm_substream *substream, | |
68 | struct snd_soc_codec *codec); | |
f57d2cfa | 69 | |
c8bf93f0 PU |
70 | enum dac33_state { |
71 | DAC33_IDLE = 0, | |
72 | DAC33_PREFILL, | |
73 | DAC33_PLAYBACK, | |
74 | DAC33_FLUSH, | |
75 | }; | |
76 | ||
7427b4b9 PU |
77 | enum dac33_fifo_modes { |
78 | DAC33_FIFO_BYPASS = 0, | |
79 | DAC33_FIFO_MODE1, | |
28e05d98 | 80 | DAC33_FIFO_MODE7, |
7427b4b9 PU |
81 | DAC33_FIFO_LAST_MODE, |
82 | }; | |
83 | ||
3a7aaed7 IK |
84 | #define DAC33_NUM_SUPPLIES 3 |
85 | static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { | |
86 | "AVDD", | |
87 | "DVDD", | |
88 | "IOVDD", | |
89 | }; | |
90 | ||
c8bf93f0 PU |
91 | struct tlv320dac33_priv { |
92 | struct mutex mutex; | |
93 | struct workqueue_struct *dac33_wq; | |
94 | struct work_struct work; | |
f0fba2ad | 95 | struct snd_soc_codec *codec; |
3a7aaed7 | 96 | struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; |
0b61d2b9 | 97 | struct snd_pcm_substream *substream; |
c8bf93f0 PU |
98 | int power_gpio; |
99 | int chip_power; | |
100 | int irq; | |
101 | unsigned int refclk; | |
102 | ||
103 | unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ | |
7427b4b9 | 104 | enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ |
549675ed | 105 | unsigned int fifo_size; /* Size of the FIFO in samples */ |
c8bf93f0 | 106 | unsigned int nsample; /* burst read amount from host */ |
f430a27f PU |
107 | int mode1_latency; /* latency caused by the i2c writes in |
108 | * us */ | |
6aceabb4 | 109 | u8 burst_bclkdiv; /* BCLK divider value in burst mode */ |
76f47127 | 110 | unsigned int burst_rate; /* Interface speed in Burst modes */ |
c8bf93f0 | 111 | |
eeb309a8 PU |
112 | int keep_bclk; /* Keep the BCLK continuously running |
113 | * in FIFO modes */ | |
f57d2cfa PU |
114 | spinlock_t lock; |
115 | unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ | |
116 | unsigned long long t_stamp2; /* calculate the FIFO caused delay */ | |
117 | ||
118 | unsigned int mode1_us_burst; /* Time to burst read n number of | |
119 | * samples */ | |
120 | unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ | |
c8bf93f0 | 121 | |
9d7db2b2 PU |
122 | unsigned int uthr; |
123 | ||
c8bf93f0 | 124 | enum dac33_state state; |
f0fba2ad LG |
125 | enum snd_soc_control_type control_type; |
126 | void *control_data; | |
c8bf93f0 PU |
127 | }; |
128 | ||
129 | static const u8 dac33_reg[DAC33_CACHEREGNUM] = { | |
130 | 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ | |
131 | 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ | |
132 | 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ | |
133 | 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ | |
134 | 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ | |
135 | 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ | |
136 | 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ | |
137 | 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ | |
138 | 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ | |
139 | 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ | |
140 | 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ | |
141 | 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ | |
142 | 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ | |
143 | 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ | |
144 | 0x00, 0x00, /* 0x38 - 0x39 */ | |
145 | /* Registers 0x3a - 0x3f are reserved */ | |
146 | 0x00, 0x00, /* 0x3a - 0x3b */ | |
147 | 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ | |
148 | ||
149 | 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ | |
150 | 0x00, 0x80, /* 0x44 - 0x45 */ | |
151 | /* Registers 0x46 - 0x47 are reserved */ | |
152 | 0x80, 0x80, /* 0x46 - 0x47 */ | |
153 | ||
154 | 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ | |
155 | /* Registers 0x4b - 0x7c are reserved */ | |
156 | 0x00, /* 0x4b */ | |
157 | 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ | |
158 | 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ | |
159 | 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ | |
160 | 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ | |
161 | 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ | |
162 | 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ | |
163 | 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ | |
164 | 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ | |
165 | 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ | |
166 | 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ | |
167 | 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ | |
168 | 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ | |
169 | 0x00, /* 0x7c */ | |
170 | ||
171 | 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ | |
172 | }; | |
173 | ||
174 | /* Register read and write */ | |
175 | static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec, | |
176 | unsigned reg) | |
177 | { | |
178 | u8 *cache = codec->reg_cache; | |
179 | if (reg >= DAC33_CACHEREGNUM) | |
180 | return 0; | |
181 | ||
182 | return cache[reg]; | |
183 | } | |
184 | ||
185 | static inline void dac33_write_reg_cache(struct snd_soc_codec *codec, | |
186 | u8 reg, u8 value) | |
187 | { | |
188 | u8 *cache = codec->reg_cache; | |
189 | if (reg >= DAC33_CACHEREGNUM) | |
190 | return; | |
191 | ||
192 | cache[reg] = value; | |
193 | } | |
194 | ||
195 | static int dac33_read(struct snd_soc_codec *codec, unsigned int reg, | |
196 | u8 *value) | |
197 | { | |
b2c812e2 | 198 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
911a0f0b | 199 | int val, ret = 0; |
c8bf93f0 PU |
200 | |
201 | *value = reg & 0xff; | |
202 | ||
203 | /* If powered off, return the cached value */ | |
204 | if (dac33->chip_power) { | |
205 | val = i2c_smbus_read_byte_data(codec->control_data, value[0]); | |
206 | if (val < 0) { | |
207 | dev_err(codec->dev, "Read failed (%d)\n", val); | |
208 | value[0] = dac33_read_reg_cache(codec, reg); | |
911a0f0b | 209 | ret = val; |
c8bf93f0 PU |
210 | } else { |
211 | value[0] = val; | |
212 | dac33_write_reg_cache(codec, reg, val); | |
213 | } | |
214 | } else { | |
215 | value[0] = dac33_read_reg_cache(codec, reg); | |
216 | } | |
217 | ||
911a0f0b | 218 | return ret; |
c8bf93f0 PU |
219 | } |
220 | ||
221 | static int dac33_write(struct snd_soc_codec *codec, unsigned int reg, | |
222 | unsigned int value) | |
223 | { | |
b2c812e2 | 224 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
225 | u8 data[2]; |
226 | int ret = 0; | |
227 | ||
228 | /* | |
229 | * data is | |
230 | * D15..D8 dac33 register offset | |
231 | * D7...D0 register data | |
232 | */ | |
233 | data[0] = reg & 0xff; | |
234 | data[1] = value & 0xff; | |
235 | ||
236 | dac33_write_reg_cache(codec, data[0], data[1]); | |
237 | if (dac33->chip_power) { | |
238 | ret = codec->hw_write(codec->control_data, data, 2); | |
239 | if (ret != 2) | |
240 | dev_err(codec->dev, "Write failed (%d)\n", ret); | |
241 | else | |
242 | ret = 0; | |
243 | } | |
244 | ||
245 | return ret; | |
246 | } | |
247 | ||
248 | static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg, | |
249 | unsigned int value) | |
250 | { | |
b2c812e2 | 251 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
252 | int ret; |
253 | ||
254 | mutex_lock(&dac33->mutex); | |
255 | ret = dac33_write(codec, reg, value); | |
256 | mutex_unlock(&dac33->mutex); | |
257 | ||
258 | return ret; | |
259 | } | |
260 | ||
261 | #define DAC33_I2C_ADDR_AUTOINC 0x80 | |
262 | static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg, | |
263 | unsigned int value) | |
264 | { | |
b2c812e2 | 265 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
266 | u8 data[3]; |
267 | int ret = 0; | |
268 | ||
269 | /* | |
270 | * data is | |
271 | * D23..D16 dac33 register offset | |
272 | * D15..D8 register data MSB | |
273 | * D7...D0 register data LSB | |
274 | */ | |
275 | data[0] = reg & 0xff; | |
276 | data[1] = (value >> 8) & 0xff; | |
277 | data[2] = value & 0xff; | |
278 | ||
279 | dac33_write_reg_cache(codec, data[0], data[1]); | |
280 | dac33_write_reg_cache(codec, data[0] + 1, data[2]); | |
281 | ||
282 | if (dac33->chip_power) { | |
283 | /* We need to set autoincrement mode for 16 bit writes */ | |
284 | data[0] |= DAC33_I2C_ADDR_AUTOINC; | |
285 | ret = codec->hw_write(codec->control_data, data, 3); | |
286 | if (ret != 3) | |
287 | dev_err(codec->dev, "Write failed (%d)\n", ret); | |
288 | else | |
289 | ret = 0; | |
290 | } | |
291 | ||
292 | return ret; | |
293 | } | |
294 | ||
ef909d67 | 295 | static void dac33_init_chip(struct snd_soc_codec *codec) |
c8bf93f0 | 296 | { |
b2c812e2 | 297 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 298 | |
ef909d67 | 299 | if (unlikely(!dac33->chip_power)) |
c8bf93f0 PU |
300 | return; |
301 | ||
ef909d67 PU |
302 | /* A : DAC sample rate Fsref/1.5 */ |
303 | dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); | |
304 | /* B : DAC src=normal, not muted */ | |
305 | dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | | |
306 | DAC33_DACSRCL_LEFT); | |
307 | /* C : (defaults) */ | |
308 | dac33_write(codec, DAC33_DAC_CTRL_C, 0x00); | |
309 | ||
ef909d67 PU |
310 | /* 73 : volume soft stepping control, |
311 | clock source = internal osc (?) */ | |
312 | dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); | |
313 | ||
ef909d67 PU |
314 | /* Restore only selected registers (gains mostly) */ |
315 | dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, | |
316 | dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); | |
317 | dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL, | |
318 | dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL)); | |
319 | ||
320 | dac33_write(codec, DAC33_LINEL_TO_LLO_VOL, | |
321 | dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); | |
322 | dac33_write(codec, DAC33_LINER_TO_RLO_VOL, | |
323 | dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); | |
399b82e4 PU |
324 | |
325 | dac33_write(codec, DAC33_OUT_AMP_CTRL, | |
326 | dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL)); | |
327 | ||
56a3536c PU |
328 | dac33_write(codec, DAC33_LDAC_PWR_CTRL, |
329 | dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL)); | |
330 | dac33_write(codec, DAC33_RDAC_PWR_CTRL, | |
331 | dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL)); | |
c8bf93f0 PU |
332 | } |
333 | ||
911a0f0b | 334 | static inline int dac33_read_id(struct snd_soc_codec *codec) |
239fe55c | 335 | { |
911a0f0b | 336 | int i, ret = 0; |
239fe55c PU |
337 | u8 reg; |
338 | ||
911a0f0b PU |
339 | for (i = 0; i < 3; i++) { |
340 | ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, ®); | |
341 | if (ret < 0) | |
342 | break; | |
343 | } | |
344 | ||
345 | return ret; | |
c8bf93f0 PU |
346 | } |
347 | ||
348 | static inline void dac33_soft_power(struct snd_soc_codec *codec, int power) | |
349 | { | |
350 | u8 reg; | |
351 | ||
352 | reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
353 | if (power) | |
354 | reg |= DAC33_PDNALLB; | |
355 | else | |
c3746a07 PU |
356 | reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | |
357 | DAC33_DACRPDNB | DAC33_DACLPDNB); | |
c8bf93f0 PU |
358 | dac33_write(codec, DAC33_PWR_CTRL, reg); |
359 | } | |
360 | ||
a6cea965 PU |
361 | static inline void dac33_disable_digital(struct snd_soc_codec *codec) |
362 | { | |
363 | u8 reg; | |
364 | ||
365 | /* Stop the DAI clock */ | |
366 | reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
367 | reg &= ~DAC33_BCLKON; | |
368 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg); | |
369 | ||
370 | /* Power down the Oscillator, and DACs */ | |
371 | reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
372 | reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); | |
373 | dac33_write(codec, DAC33_PWR_CTRL, reg); | |
374 | } | |
375 | ||
3a7aaed7 | 376 | static int dac33_hard_power(struct snd_soc_codec *codec, int power) |
c8bf93f0 | 377 | { |
b2c812e2 | 378 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
ad05c03b | 379 | int ret = 0; |
c8bf93f0 PU |
380 | |
381 | mutex_lock(&dac33->mutex); | |
ad05c03b PU |
382 | |
383 | /* Safety check */ | |
384 | if (unlikely(power == dac33->chip_power)) { | |
7fd1d74b | 385 | dev_dbg(codec->dev, "Trying to set the same power state: %s\n", |
ad05c03b PU |
386 | power ? "ON" : "OFF"); |
387 | goto exit; | |
388 | } | |
389 | ||
c8bf93f0 | 390 | if (power) { |
3a7aaed7 IK |
391 | ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), |
392 | dac33->supplies); | |
393 | if (ret != 0) { | |
394 | dev_err(codec->dev, | |
395 | "Failed to enable supplies: %d\n", ret); | |
396 | goto exit; | |
c8bf93f0 | 397 | } |
3a7aaed7 IK |
398 | |
399 | if (dac33->power_gpio >= 0) | |
400 | gpio_set_value(dac33->power_gpio, 1); | |
401 | ||
402 | dac33->chip_power = 1; | |
c8bf93f0 PU |
403 | } else { |
404 | dac33_soft_power(codec, 0); | |
3a7aaed7 | 405 | if (dac33->power_gpio >= 0) |
c8bf93f0 | 406 | gpio_set_value(dac33->power_gpio, 0); |
3a7aaed7 IK |
407 | |
408 | ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), | |
409 | dac33->supplies); | |
410 | if (ret != 0) { | |
411 | dev_err(codec->dev, | |
412 | "Failed to disable supplies: %d\n", ret); | |
413 | goto exit; | |
c8bf93f0 | 414 | } |
3a7aaed7 IK |
415 | |
416 | dac33->chip_power = 0; | |
c8bf93f0 | 417 | } |
c8bf93f0 | 418 | |
3a7aaed7 IK |
419 | exit: |
420 | mutex_unlock(&dac33->mutex); | |
421 | return ret; | |
c8bf93f0 PU |
422 | } |
423 | ||
a6cea965 | 424 | static int dac33_playback_event(struct snd_soc_dapm_widget *w, |
ad05c03b PU |
425 | struct snd_kcontrol *kcontrol, int event) |
426 | { | |
427 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec); | |
428 | ||
429 | switch (event) { | |
430 | case SND_SOC_DAPM_PRE_PMU: | |
431 | if (likely(dac33->substream)) { | |
e6968a17 MB |
432 | dac33_calculate_times(dac33->substream, w->codec); |
433 | dac33_prepare_chip(dac33->substream, w->codec); | |
ad05c03b PU |
434 | } |
435 | break; | |
a6cea965 PU |
436 | case SND_SOC_DAPM_POST_PMD: |
437 | dac33_disable_digital(w->codec); | |
438 | break; | |
ad05c03b PU |
439 | } |
440 | return 0; | |
441 | } | |
442 | ||
7427b4b9 | 443 | static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, |
c8bf93f0 PU |
444 | struct snd_ctl_elem_value *ucontrol) |
445 | { | |
446 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 447 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 448 | |
7427b4b9 | 449 | ucontrol->value.integer.value[0] = dac33->fifo_mode; |
c8bf93f0 PU |
450 | |
451 | return 0; | |
452 | } | |
453 | ||
7427b4b9 | 454 | static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, |
c8bf93f0 PU |
455 | struct snd_ctl_elem_value *ucontrol) |
456 | { | |
457 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 458 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
459 | int ret = 0; |
460 | ||
7427b4b9 | 461 | if (dac33->fifo_mode == ucontrol->value.integer.value[0]) |
c8bf93f0 PU |
462 | return 0; |
463 | /* Do not allow changes while stream is running*/ | |
464 | if (codec->active) | |
465 | return -EPERM; | |
466 | ||
467 | if (ucontrol->value.integer.value[0] < 0 || | |
7427b4b9 | 468 | ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE) |
c8bf93f0 PU |
469 | ret = -EINVAL; |
470 | else | |
7427b4b9 | 471 | dac33->fifo_mode = ucontrol->value.integer.value[0]; |
c8bf93f0 PU |
472 | |
473 | return ret; | |
474 | } | |
475 | ||
7427b4b9 PU |
476 | /* Codec operation modes */ |
477 | static const char *dac33_fifo_mode_texts[] = { | |
28e05d98 | 478 | "Bypass", "Mode 1", "Mode 7" |
7427b4b9 PU |
479 | }; |
480 | ||
481 | static const struct soc_enum dac33_fifo_mode_enum = | |
482 | SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts), | |
483 | dac33_fifo_mode_texts); | |
484 | ||
cf4bb698 PU |
485 | /* L/R Line Output Gain */ |
486 | static const char *lr_lineout_gain_texts[] = { | |
487 | "Line -12dB DAC 0dB", "Line -6dB DAC 6dB", | |
488 | "Line 0dB DAC 12dB", "Line 6dB DAC 18dB", | |
489 | }; | |
490 | ||
491 | static const struct soc_enum l_lineout_gain_enum = | |
492 | SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0, | |
493 | ARRAY_SIZE(lr_lineout_gain_texts), | |
494 | lr_lineout_gain_texts); | |
495 | ||
496 | static const struct soc_enum r_lineout_gain_enum = | |
497 | SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0, | |
498 | ARRAY_SIZE(lr_lineout_gain_texts), | |
499 | lr_lineout_gain_texts); | |
500 | ||
c8bf93f0 PU |
501 | /* |
502 | * DACL/R digital volume control: | |
503 | * from 0 dB to -63.5 in 0.5 dB steps | |
504 | * Need to be inverted later on: | |
505 | * 0x00 == 0 dB | |
506 | * 0x7f == -63.5 dB | |
507 | */ | |
508 | static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); | |
509 | ||
510 | static const struct snd_kcontrol_new dac33_snd_controls[] = { | |
511 | SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", | |
512 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, | |
513 | 0, 0x7f, 1, dac_digivol_tlv), | |
514 | SOC_DOUBLE_R("DAC Digital Playback Switch", | |
515 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), | |
516 | SOC_DOUBLE_R("Line to Line Out Volume", | |
517 | DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), | |
cf4bb698 PU |
518 | SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum), |
519 | SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum), | |
c8bf93f0 PU |
520 | }; |
521 | ||
a577b318 PU |
522 | static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { |
523 | SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, | |
524 | dac33_get_fifo_mode, dac33_set_fifo_mode), | |
525 | }; | |
526 | ||
c8bf93f0 PU |
527 | /* Analog bypass */ |
528 | static const struct snd_kcontrol_new dac33_dapm_abypassl_control = | |
529 | SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); | |
530 | ||
531 | static const struct snd_kcontrol_new dac33_dapm_abypassr_control = | |
532 | SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); | |
533 | ||
399b82e4 PU |
534 | /* LOP L/R invert selection */ |
535 | static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"}; | |
536 | ||
537 | static const struct soc_enum dac33_left_lom_enum = | |
538 | SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3, | |
539 | ARRAY_SIZE(dac33_lr_lom_texts), | |
540 | dac33_lr_lom_texts); | |
541 | ||
542 | static const struct snd_kcontrol_new dac33_dapm_left_lom_control = | |
543 | SOC_DAPM_ENUM("Route", dac33_left_lom_enum); | |
544 | ||
545 | static const struct soc_enum dac33_right_lom_enum = | |
546 | SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2, | |
547 | ARRAY_SIZE(dac33_lr_lom_texts), | |
548 | dac33_lr_lom_texts); | |
549 | ||
550 | static const struct snd_kcontrol_new dac33_dapm_right_lom_control = | |
551 | SOC_DAPM_ENUM("Route", dac33_right_lom_enum); | |
552 | ||
c8bf93f0 PU |
553 | static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { |
554 | SND_SOC_DAPM_OUTPUT("LEFT_LO"), | |
555 | SND_SOC_DAPM_OUTPUT("RIGHT_LO"), | |
556 | ||
557 | SND_SOC_DAPM_INPUT("LINEL"), | |
558 | SND_SOC_DAPM_INPUT("LINER"), | |
559 | ||
76eac39c PU |
560 | SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), |
561 | SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), | |
c8bf93f0 PU |
562 | |
563 | /* Analog bypass */ | |
564 | SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, | |
565 | &dac33_dapm_abypassl_control), | |
566 | SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, | |
567 | &dac33_dapm_abypassr_control), | |
568 | ||
399b82e4 PU |
569 | SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0, |
570 | &dac33_dapm_left_lom_control), | |
571 | SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0, | |
572 | &dac33_dapm_right_lom_control), | |
573 | /* | |
574 | * For DAPM path, when only the anlog bypass path is enabled, and the | |
575 | * LOP inverted from the corresponding DAC side. | |
576 | * This is needed, so we can attach the DAC power supply in this case. | |
577 | */ | |
578 | SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
579 | SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
580 | ||
9e87186f | 581 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", |
c8bf93f0 | 582 | DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), |
9e87186f | 583 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", |
c8bf93f0 | 584 | DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), |
ad05c03b | 585 | |
76eac39c PU |
586 | SND_SOC_DAPM_SUPPLY("Left DAC Power", |
587 | DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), | |
588 | SND_SOC_DAPM_SUPPLY("Right DAC Power", | |
589 | DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), | |
590 | ||
4b8ffdb9 PU |
591 | SND_SOC_DAPM_SUPPLY("Codec Power", |
592 | DAC33_PWR_CTRL, 4, 0, NULL, 0), | |
593 | ||
a6cea965 PU |
594 | SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event), |
595 | SND_SOC_DAPM_POST("Post Playback", dac33_playback_event), | |
c8bf93f0 PU |
596 | }; |
597 | ||
598 | static const struct snd_soc_dapm_route audio_map[] = { | |
599 | /* Analog bypass */ | |
600 | {"Analog Left Bypass", "Switch", "LINEL"}, | |
601 | {"Analog Right Bypass", "Switch", "LINER"}, | |
602 | ||
9e87186f PU |
603 | {"Output Left Amplifier", NULL, "DACL"}, |
604 | {"Output Right Amplifier", NULL, "DACR"}, | |
c8bf93f0 | 605 | |
399b82e4 PU |
606 | {"Left Bypass PGA", NULL, "Analog Left Bypass"}, |
607 | {"Right Bypass PGA", NULL, "Analog Right Bypass"}, | |
608 | ||
609 | {"Left LOM Inverted From", "DAC", "Left Bypass PGA"}, | |
610 | {"Right LOM Inverted From", "DAC", "Right Bypass PGA"}, | |
611 | {"Left LOM Inverted From", "LOP", "Analog Left Bypass"}, | |
612 | {"Right LOM Inverted From", "LOP", "Analog Right Bypass"}, | |
613 | ||
614 | {"Output Left Amplifier", NULL, "Left LOM Inverted From"}, | |
615 | {"Output Right Amplifier", NULL, "Right LOM Inverted From"}, | |
616 | ||
617 | {"DACL", NULL, "Left DAC Power"}, | |
618 | {"DACR", NULL, "Right DAC Power"}, | |
c8bf93f0 | 619 | |
399b82e4 PU |
620 | {"Left Bypass PGA", NULL, "Left DAC Power"}, |
621 | {"Right Bypass PGA", NULL, "Right DAC Power"}, | |
76eac39c | 622 | |
c8bf93f0 | 623 | /* output */ |
9e87186f PU |
624 | {"LEFT_LO", NULL, "Output Left Amplifier"}, |
625 | {"RIGHT_LO", NULL, "Output Right Amplifier"}, | |
4b8ffdb9 PU |
626 | |
627 | {"LEFT_LO", NULL, "Codec Power"}, | |
628 | {"RIGHT_LO", NULL, "Codec Power"}, | |
c8bf93f0 PU |
629 | }; |
630 | ||
c8bf93f0 PU |
631 | static int dac33_set_bias_level(struct snd_soc_codec *codec, |
632 | enum snd_soc_bias_level level) | |
633 | { | |
3a7aaed7 IK |
634 | int ret; |
635 | ||
c8bf93f0 PU |
636 | switch (level) { |
637 | case SND_SOC_BIAS_ON: | |
c8bf93f0 PU |
638 | break; |
639 | case SND_SOC_BIAS_PREPARE: | |
640 | break; | |
641 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 642 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
ad05c03b | 643 | /* Coming from OFF, switch on the codec */ |
3a7aaed7 IK |
644 | ret = dac33_hard_power(codec, 1); |
645 | if (ret != 0) | |
646 | return ret; | |
3a7aaed7 | 647 | |
ad05c03b PU |
648 | dac33_init_chip(codec); |
649 | } | |
c8bf93f0 PU |
650 | break; |
651 | case SND_SOC_BIAS_OFF: | |
2d4cdd6f | 652 | /* Do not power off, when the codec is already off */ |
ce6120cc | 653 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) |
2d4cdd6f | 654 | return 0; |
3a7aaed7 IK |
655 | ret = dac33_hard_power(codec, 0); |
656 | if (ret != 0) | |
657 | return ret; | |
c8bf93f0 PU |
658 | break; |
659 | } | |
ce6120cc | 660 | codec->dapm.bias_level = level; |
c8bf93f0 PU |
661 | |
662 | return 0; | |
663 | } | |
664 | ||
d4f102d4 PU |
665 | static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) |
666 | { | |
f0fba2ad | 667 | struct snd_soc_codec *codec = dac33->codec; |
84eae18c | 668 | unsigned int delay; |
a3b55791 | 669 | unsigned long flags; |
d4f102d4 PU |
670 | |
671 | switch (dac33->fifo_mode) { | |
672 | case DAC33_FIFO_MODE1: | |
673 | dac33_write16(codec, DAC33_NSAMPLE_MSB, | |
f430a27f | 674 | DAC33_THRREG(dac33->nsample)); |
f57d2cfa PU |
675 | |
676 | /* Take the timestamps */ | |
a3b55791 | 677 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa PU |
678 | dac33->t_stamp2 = ktime_to_us(ktime_get()); |
679 | dac33->t_stamp1 = dac33->t_stamp2; | |
a3b55791 | 680 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa | 681 | |
d4f102d4 PU |
682 | dac33_write16(codec, DAC33_PREFILL_MSB, |
683 | DAC33_THRREG(dac33->alarm_threshold)); | |
f4d59328 | 684 | /* Enable Alarm Threshold IRQ with a delay */ |
84eae18c PU |
685 | delay = SAMPLES_TO_US(dac33->burst_rate, |
686 | dac33->alarm_threshold) + 1000; | |
687 | usleep_range(delay, delay + 500); | |
f4d59328 | 688 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT); |
d4f102d4 | 689 | break; |
28e05d98 | 690 | case DAC33_FIFO_MODE7: |
f57d2cfa | 691 | /* Take the timestamp */ |
a3b55791 | 692 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa PU |
693 | dac33->t_stamp1 = ktime_to_us(ktime_get()); |
694 | /* Move back the timestamp with drain time */ | |
695 | dac33->t_stamp1 -= dac33->mode7_us_to_lthr; | |
a3b55791 | 696 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa | 697 | |
28e05d98 | 698 | dac33_write16(codec, DAC33_PREFILL_MSB, |
549675ed | 699 | DAC33_THRREG(DAC33_MODE7_MARGIN)); |
f57d2cfa PU |
700 | |
701 | /* Enable Upper Threshold IRQ */ | |
702 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); | |
28e05d98 | 703 | break; |
d4f102d4 PU |
704 | default: |
705 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
706 | dac33->fifo_mode); | |
707 | break; | |
708 | } | |
709 | } | |
710 | ||
711 | static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) | |
712 | { | |
f0fba2ad | 713 | struct snd_soc_codec *codec = dac33->codec; |
a3b55791 | 714 | unsigned long flags; |
d4f102d4 PU |
715 | |
716 | switch (dac33->fifo_mode) { | |
717 | case DAC33_FIFO_MODE1: | |
f57d2cfa | 718 | /* Take the timestamp */ |
a3b55791 | 719 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa | 720 | dac33->t_stamp2 = ktime_to_us(ktime_get()); |
a3b55791 | 721 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa | 722 | |
d4f102d4 PU |
723 | dac33_write16(codec, DAC33_NSAMPLE_MSB, |
724 | DAC33_THRREG(dac33->nsample)); | |
725 | break; | |
28e05d98 PU |
726 | case DAC33_FIFO_MODE7: |
727 | /* At the moment we are not using interrupts in mode7 */ | |
728 | break; | |
d4f102d4 PU |
729 | default: |
730 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
731 | dac33->fifo_mode); | |
732 | break; | |
733 | } | |
734 | } | |
735 | ||
c8bf93f0 PU |
736 | static void dac33_work(struct work_struct *work) |
737 | { | |
738 | struct snd_soc_codec *codec; | |
739 | struct tlv320dac33_priv *dac33; | |
740 | u8 reg; | |
741 | ||
742 | dac33 = container_of(work, struct tlv320dac33_priv, work); | |
f0fba2ad | 743 | codec = dac33->codec; |
c8bf93f0 PU |
744 | |
745 | mutex_lock(&dac33->mutex); | |
746 | switch (dac33->state) { | |
747 | case DAC33_PREFILL: | |
748 | dac33->state = DAC33_PLAYBACK; | |
d4f102d4 | 749 | dac33_prefill_handler(dac33); |
c8bf93f0 PU |
750 | break; |
751 | case DAC33_PLAYBACK: | |
d4f102d4 | 752 | dac33_playback_handler(dac33); |
c8bf93f0 PU |
753 | break; |
754 | case DAC33_IDLE: | |
755 | break; | |
756 | case DAC33_FLUSH: | |
757 | dac33->state = DAC33_IDLE; | |
758 | /* Mask all interrupts from dac33 */ | |
759 | dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); | |
760 | ||
761 | /* flush fifo */ | |
762 | reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); | |
763 | reg |= DAC33_FIFOFLUSH; | |
764 | dac33_write(codec, DAC33_FIFO_CTRL_A, reg); | |
765 | break; | |
766 | } | |
767 | mutex_unlock(&dac33->mutex); | |
768 | } | |
769 | ||
770 | static irqreturn_t dac33_interrupt_handler(int irq, void *dev) | |
771 | { | |
772 | struct snd_soc_codec *codec = dev; | |
b2c812e2 | 773 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
a3b55791 | 774 | unsigned long flags; |
c8bf93f0 | 775 | |
a3b55791 | 776 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa | 777 | dac33->t_stamp1 = ktime_to_us(ktime_get()); |
a3b55791 | 778 | spin_unlock_irqrestore(&dac33->lock, flags); |
c8bf93f0 | 779 | |
f57d2cfa PU |
780 | /* Do not schedule the workqueue in Mode7 */ |
781 | if (dac33->fifo_mode != DAC33_FIFO_MODE7) | |
782 | queue_work(dac33->dac33_wq, &dac33->work); | |
c8bf93f0 | 783 | |
c8bf93f0 | 784 | return IRQ_HANDLED; |
c8bf93f0 PU |
785 | } |
786 | ||
787 | static void dac33_oscwait(struct snd_soc_codec *codec) | |
788 | { | |
84eae18c | 789 | int timeout = 60; |
c8bf93f0 PU |
790 | u8 reg; |
791 | ||
792 | do { | |
84eae18c | 793 | usleep_range(1000, 2000); |
c8bf93f0 PU |
794 | dac33_read(codec, DAC33_INT_OSC_STATUS, ®); |
795 | } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); | |
796 | if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) | |
797 | dev_err(codec->dev, | |
798 | "internal oscillator calibration failed\n"); | |
799 | } | |
800 | ||
0b61d2b9 PU |
801 | static int dac33_startup(struct snd_pcm_substream *substream, |
802 | struct snd_soc_dai *dai) | |
803 | { | |
e6968a17 | 804 | struct snd_soc_codec *codec = dai->codec; |
0b61d2b9 PU |
805 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
806 | ||
807 | /* Stream started, save the substream pointer */ | |
808 | dac33->substream = substream; | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | static void dac33_shutdown(struct snd_pcm_substream *substream, | |
814 | struct snd_soc_dai *dai) | |
815 | { | |
e6968a17 | 816 | struct snd_soc_codec *codec = dai->codec; |
0b61d2b9 PU |
817 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
818 | ||
819 | dac33->substream = NULL; | |
820 | } | |
821 | ||
549675ed PU |
822 | #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ |
823 | (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) | |
c8bf93f0 PU |
824 | static int dac33_hw_params(struct snd_pcm_substream *substream, |
825 | struct snd_pcm_hw_params *params, | |
826 | struct snd_soc_dai *dai) | |
827 | { | |
e6968a17 | 828 | struct snd_soc_codec *codec = dai->codec; |
549675ed | 829 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
830 | |
831 | /* Check parameters for validity */ | |
832 | switch (params_rate(params)) { | |
833 | case 44100: | |
834 | case 48000: | |
835 | break; | |
836 | default: | |
837 | dev_err(codec->dev, "unsupported rate %d\n", | |
838 | params_rate(params)); | |
839 | return -EINVAL; | |
840 | } | |
841 | ||
842 | switch (params_format(params)) { | |
843 | case SNDRV_PCM_FORMAT_S16_LE: | |
549675ed PU |
844 | dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; |
845 | dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); | |
c8bf93f0 | 846 | break; |
0d99d2b0 PU |
847 | case SNDRV_PCM_FORMAT_S32_LE: |
848 | dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; | |
849 | dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); | |
850 | break; | |
c8bf93f0 PU |
851 | default: |
852 | dev_err(codec->dev, "unsupported format %d\n", | |
853 | params_format(params)); | |
854 | return -EINVAL; | |
855 | } | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
860 | #define CALC_OSCSET(rate, refclk) ( \ | |
7833ae0e | 861 | ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) |
c8bf93f0 PU |
862 | #define CALC_RATIOSET(rate, refclk) ( \ |
863 | ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) | |
864 | ||
865 | /* | |
866 | * tlv320dac33 is strict on the sequence of the register writes, if the register | |
867 | * writes happens in different order, than dac33 might end up in unknown state. | |
868 | * Use the known, working sequence of register writes to initialize the dac33. | |
869 | */ | |
e6968a17 MB |
870 | static int dac33_prepare_chip(struct snd_pcm_substream *substream, |
871 | struct snd_soc_codec *codec) | |
c8bf93f0 | 872 | { |
b2c812e2 | 873 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 | 874 | unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; |
aec242dc | 875 | u8 aictrl_a, aictrl_b, fifoctrl_a; |
c8bf93f0 PU |
876 | |
877 | switch (substream->runtime->rate) { | |
878 | case 44100: | |
879 | case 48000: | |
880 | oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); | |
881 | ratioset = CALC_RATIOSET(substream->runtime->rate, | |
882 | dac33->refclk); | |
883 | break; | |
884 | default: | |
885 | dev_err(codec->dev, "unsupported rate %d\n", | |
886 | substream->runtime->rate); | |
887 | return -EINVAL; | |
888 | } | |
889 | ||
890 | ||
891 | aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); | |
892 | aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); | |
e5e878c1 | 893 | /* Read FIFO control A, and clear FIFO flush bit */ |
c8bf93f0 | 894 | fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); |
e5e878c1 PU |
895 | fifoctrl_a &= ~DAC33_FIFOFLUSH; |
896 | ||
c8bf93f0 PU |
897 | fifoctrl_a &= ~DAC33_WIDTH; |
898 | switch (substream->runtime->format) { | |
899 | case SNDRV_PCM_FORMAT_S16_LE: | |
900 | aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); | |
901 | fifoctrl_a |= DAC33_WIDTH; | |
902 | break; | |
0d99d2b0 PU |
903 | case SNDRV_PCM_FORMAT_S32_LE: |
904 | aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); | |
905 | break; | |
c8bf93f0 PU |
906 | default: |
907 | dev_err(codec->dev, "unsupported format %d\n", | |
908 | substream->runtime->format); | |
909 | return -EINVAL; | |
910 | } | |
911 | ||
912 | mutex_lock(&dac33->mutex); | |
ad05c03b PU |
913 | |
914 | if (!dac33->chip_power) { | |
915 | /* | |
916 | * Chip is not powered yet. | |
917 | * Do the init in the dac33_set_bias_level later. | |
918 | */ | |
919 | mutex_unlock(&dac33->mutex); | |
920 | return 0; | |
921 | } | |
922 | ||
c3746a07 | 923 | dac33_soft_power(codec, 0); |
c8bf93f0 PU |
924 | dac33_soft_power(codec, 1); |
925 | ||
926 | reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); | |
927 | dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp); | |
928 | ||
929 | /* Write registers 0x08 and 0x09 (MSB, LSB) */ | |
930 | dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset); | |
931 | ||
82a58a8b PU |
932 | /* OSC calibration time */ |
933 | dac33_write(codec, DAC33_CALIB_TIME, 96); | |
c8bf93f0 PU |
934 | |
935 | /* adjustment treshold & step */ | |
936 | dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | | |
937 | DAC33_ADJSTEP(1)); | |
938 | ||
939 | /* div=4 / gain=1 / div */ | |
940 | dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); | |
941 | ||
942 | pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); | |
943 | pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; | |
944 | dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl); | |
945 | ||
946 | dac33_oscwait(codec); | |
947 | ||
7427b4b9 | 948 | if (dac33->fifo_mode) { |
aec242dc | 949 | /* Generic for all FIFO modes */ |
c8bf93f0 | 950 | /* 50-51 : ASRC Control registers */ |
fdb6b1e1 | 951 | dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); |
c8bf93f0 PU |
952 | dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */ |
953 | ||
954 | /* Write registers 0x34 and 0x35 (MSB, LSB) */ | |
955 | dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset); | |
956 | ||
957 | /* Set interrupts to high active */ | |
958 | dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); | |
c8bf93f0 | 959 | } else { |
aec242dc | 960 | /* FIFO bypass mode */ |
c8bf93f0 PU |
961 | /* 50-51 : ASRC Control registers */ |
962 | dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); | |
963 | dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */ | |
964 | } | |
965 | ||
aec242dc PU |
966 | /* Interrupt behaviour configuration */ |
967 | switch (dac33->fifo_mode) { | |
968 | case DAC33_FIFO_MODE1: | |
969 | dac33_write(codec, DAC33_FIFO_IRQ_MODE_B, | |
970 | DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); | |
aec242dc | 971 | break; |
28e05d98 | 972 | case DAC33_FIFO_MODE7: |
f57d2cfa PU |
973 | dac33_write(codec, DAC33_FIFO_IRQ_MODE_A, |
974 | DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); | |
28e05d98 | 975 | break; |
aec242dc PU |
976 | default: |
977 | /* in FIFO bypass mode, the interrupts are not used */ | |
978 | break; | |
979 | } | |
980 | ||
981 | aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
982 | ||
983 | switch (dac33->fifo_mode) { | |
984 | case DAC33_FIFO_MODE1: | |
985 | /* | |
986 | * For mode1: | |
987 | * Disable the FIFO bypass (Enable the use of FIFO) | |
988 | * Select nSample mode | |
989 | * BCLK is only running when data is needed by DAC33 | |
990 | */ | |
c8bf93f0 | 991 | fifoctrl_a &= ~DAC33_FBYPAS; |
aec242dc | 992 | fifoctrl_a &= ~DAC33_FAUTO; |
eeb309a8 PU |
993 | if (dac33->keep_bclk) |
994 | aictrl_b |= DAC33_BCLKON; | |
995 | else | |
996 | aictrl_b &= ~DAC33_BCLKON; | |
aec242dc | 997 | break; |
28e05d98 PU |
998 | case DAC33_FIFO_MODE7: |
999 | /* | |
1000 | * For mode1: | |
1001 | * Disable the FIFO bypass (Enable the use of FIFO) | |
1002 | * Select Threshold mode | |
1003 | * BCLK is only running when data is needed by DAC33 | |
1004 | */ | |
1005 | fifoctrl_a &= ~DAC33_FBYPAS; | |
1006 | fifoctrl_a |= DAC33_FAUTO; | |
eeb309a8 PU |
1007 | if (dac33->keep_bclk) |
1008 | aictrl_b |= DAC33_BCLKON; | |
1009 | else | |
1010 | aictrl_b &= ~DAC33_BCLKON; | |
28e05d98 | 1011 | break; |
aec242dc PU |
1012 | default: |
1013 | /* | |
1014 | * For FIFO bypass mode: | |
1015 | * Enable the FIFO bypass (Disable the FIFO use) | |
25985edc | 1016 | * Set the BCLK as continuous |
aec242dc | 1017 | */ |
c8bf93f0 | 1018 | fifoctrl_a |= DAC33_FBYPAS; |
aec242dc PU |
1019 | aictrl_b |= DAC33_BCLKON; |
1020 | break; | |
1021 | } | |
c8bf93f0 | 1022 | |
aec242dc | 1023 | dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a); |
c8bf93f0 | 1024 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); |
aec242dc | 1025 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); |
c8bf93f0 | 1026 | |
6aceabb4 PU |
1027 | /* |
1028 | * BCLK divide ratio | |
1029 | * 0: 1.5 | |
1030 | * 1: 1 | |
1031 | * 2: 2 | |
1032 | * ... | |
1033 | * 254: 254 | |
1034 | * 255: 255 | |
1035 | */ | |
6cd6cede | 1036 | if (dac33->fifo_mode) |
6aceabb4 PU |
1037 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, |
1038 | dac33->burst_bclkdiv); | |
6cd6cede | 1039 | else |
0d99d2b0 PU |
1040 | if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) |
1041 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); | |
1042 | else | |
1043 | dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16); | |
c8bf93f0 | 1044 | |
6cd6cede PU |
1045 | switch (dac33->fifo_mode) { |
1046 | case DAC33_FIFO_MODE1: | |
c8bf93f0 PU |
1047 | dac33_write16(codec, DAC33_ATHR_MSB, |
1048 | DAC33_THRREG(dac33->alarm_threshold)); | |
aec242dc | 1049 | break; |
28e05d98 PU |
1050 | case DAC33_FIFO_MODE7: |
1051 | /* | |
1052 | * Configure the threshold levels, and leave 10 sample space | |
1053 | * at the bottom, and also at the top of the FIFO | |
1054 | */ | |
9d7db2b2 | 1055 | dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); |
549675ed PU |
1056 | dac33_write16(codec, DAC33_LTHR_MSB, |
1057 | DAC33_THRREG(DAC33_MODE7_MARGIN)); | |
28e05d98 | 1058 | break; |
aec242dc | 1059 | default: |
aec242dc | 1060 | break; |
c8bf93f0 PU |
1061 | } |
1062 | ||
1063 | mutex_unlock(&dac33->mutex); | |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
e6968a17 MB |
1068 | static void dac33_calculate_times(struct snd_pcm_substream *substream, |
1069 | struct snd_soc_codec *codec) | |
c8bf93f0 | 1070 | { |
b2c812e2 | 1071 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
f430a27f PU |
1072 | unsigned int period_size = substream->runtime->period_size; |
1073 | unsigned int rate = substream->runtime->rate; | |
c8bf93f0 PU |
1074 | unsigned int nsample_limit; |
1075 | ||
55abb59c PU |
1076 | /* In bypass mode we don't need to calculate */ |
1077 | if (!dac33->fifo_mode) | |
1078 | return; | |
1079 | ||
f57d2cfa PU |
1080 | switch (dac33->fifo_mode) { |
1081 | case DAC33_FIFO_MODE1: | |
f430a27f PU |
1082 | /* Number of samples under i2c latency */ |
1083 | dac33->alarm_threshold = US_TO_SAMPLES(rate, | |
1084 | dac33->mode1_latency); | |
549675ed | 1085 | nsample_limit = dac33->fifo_size - dac33->alarm_threshold; |
1bc13b2e | 1086 | |
3591f4cd | 1087 | if (period_size <= dac33->alarm_threshold) |
a577b318 | 1088 | /* |
3591f4cd PU |
1089 | * Configure nSamaple to number of periods, |
1090 | * which covers the latency requironment. | |
a577b318 | 1091 | */ |
3591f4cd PU |
1092 | dac33->nsample = period_size * |
1093 | ((dac33->alarm_threshold / period_size) + | |
1094 | (dac33->alarm_threshold % period_size ? | |
1095 | 1 : 0)); | |
1096 | else if (period_size > nsample_limit) | |
1097 | dac33->nsample = nsample_limit; | |
1098 | else | |
1099 | dac33->nsample = period_size; | |
f430a27f | 1100 | |
f57d2cfa PU |
1101 | dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, |
1102 | dac33->nsample); | |
1103 | dac33->t_stamp1 = 0; | |
1104 | dac33->t_stamp2 = 0; | |
1105 | break; | |
1106 | case DAC33_FIFO_MODE7: | |
3591f4cd PU |
1107 | dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, |
1108 | dac33->burst_rate) + 9; | |
549675ed PU |
1109 | if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) |
1110 | dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; | |
1111 | if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) | |
1112 | dac33->uthr = (DAC33_MODE7_MARGIN + 10); | |
3591f4cd | 1113 | |
f57d2cfa | 1114 | dac33->mode7_us_to_lthr = |
9d7db2b2 | 1115 | SAMPLES_TO_US(substream->runtime->rate, |
549675ed | 1116 | dac33->uthr - DAC33_MODE7_MARGIN + 1); |
f57d2cfa PU |
1117 | dac33->t_stamp1 = 0; |
1118 | break; | |
1119 | default: | |
1120 | break; | |
1121 | } | |
c8bf93f0 | 1122 | |
c8bf93f0 PU |
1123 | } |
1124 | ||
1125 | static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, | |
1126 | struct snd_soc_dai *dai) | |
1127 | { | |
e6968a17 | 1128 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1129 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1130 | int ret = 0; |
1131 | ||
1132 | switch (cmd) { | |
1133 | case SNDRV_PCM_TRIGGER_START: | |
1134 | case SNDRV_PCM_TRIGGER_RESUME: | |
1135 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
7427b4b9 | 1136 | if (dac33->fifo_mode) { |
c8bf93f0 PU |
1137 | dac33->state = DAC33_PREFILL; |
1138 | queue_work(dac33->dac33_wq, &dac33->work); | |
1139 | } | |
1140 | break; | |
1141 | case SNDRV_PCM_TRIGGER_STOP: | |
1142 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
1143 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
7427b4b9 | 1144 | if (dac33->fifo_mode) { |
c8bf93f0 PU |
1145 | dac33->state = DAC33_FLUSH; |
1146 | queue_work(dac33->dac33_wq, &dac33->work); | |
1147 | } | |
1148 | break; | |
1149 | default: | |
1150 | ret = -EINVAL; | |
1151 | } | |
1152 | ||
1153 | return ret; | |
1154 | } | |
1155 | ||
f57d2cfa PU |
1156 | static snd_pcm_sframes_t dac33_dai_delay( |
1157 | struct snd_pcm_substream *substream, | |
1158 | struct snd_soc_dai *dai) | |
1159 | { | |
e6968a17 | 1160 | struct snd_soc_codec *codec = dai->codec; |
f57d2cfa PU |
1161 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
1162 | unsigned long long t0, t1, t_now; | |
9d7db2b2 | 1163 | unsigned int time_delta, uthr; |
f57d2cfa PU |
1164 | int samples_out, samples_in, samples; |
1165 | snd_pcm_sframes_t delay = 0; | |
a3b55791 | 1166 | unsigned long flags; |
f57d2cfa PU |
1167 | |
1168 | switch (dac33->fifo_mode) { | |
1169 | case DAC33_FIFO_BYPASS: | |
1170 | break; | |
1171 | case DAC33_FIFO_MODE1: | |
a3b55791 | 1172 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa PU |
1173 | t0 = dac33->t_stamp1; |
1174 | t1 = dac33->t_stamp2; | |
a3b55791 | 1175 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa PU |
1176 | t_now = ktime_to_us(ktime_get()); |
1177 | ||
1178 | /* We have not started to fill the FIFO yet, delay is 0 */ | |
1179 | if (!t1) | |
1180 | goto out; | |
1181 | ||
1182 | if (t0 > t1) { | |
1183 | /* | |
1184 | * Phase 1: | |
1185 | * After Alarm threshold, and before nSample write | |
1186 | */ | |
1187 | time_delta = t_now - t0; | |
1188 | samples_out = time_delta ? US_TO_SAMPLES( | |
1189 | substream->runtime->rate, | |
1190 | time_delta) : 0; | |
1191 | ||
1192 | if (likely(dac33->alarm_threshold > samples_out)) | |
1193 | delay = dac33->alarm_threshold - samples_out; | |
1194 | else | |
1195 | delay = 0; | |
1196 | } else if ((t_now - t1) <= dac33->mode1_us_burst) { | |
1197 | /* | |
1198 | * Phase 2: | |
1199 | * After nSample write (during burst operation) | |
1200 | */ | |
1201 | time_delta = t_now - t0; | |
1202 | samples_out = time_delta ? US_TO_SAMPLES( | |
1203 | substream->runtime->rate, | |
1204 | time_delta) : 0; | |
1205 | ||
1206 | time_delta = t_now - t1; | |
1207 | samples_in = time_delta ? US_TO_SAMPLES( | |
1208 | dac33->burst_rate, | |
1209 | time_delta) : 0; | |
1210 | ||
1211 | samples = dac33->alarm_threshold; | |
1212 | samples += (samples_in - samples_out); | |
1213 | ||
1214 | if (likely(samples > 0)) | |
1215 | delay = samples; | |
1216 | else | |
1217 | delay = 0; | |
1218 | } else { | |
1219 | /* | |
1220 | * Phase 3: | |
1221 | * After burst operation, before next alarm threshold | |
1222 | */ | |
1223 | time_delta = t_now - t0; | |
1224 | samples_out = time_delta ? US_TO_SAMPLES( | |
1225 | substream->runtime->rate, | |
1226 | time_delta) : 0; | |
1227 | ||
1228 | samples_in = dac33->nsample; | |
1229 | samples = dac33->alarm_threshold; | |
1230 | samples += (samples_in - samples_out); | |
1231 | ||
1232 | if (likely(samples > 0)) | |
549675ed PU |
1233 | delay = samples > dac33->fifo_size ? |
1234 | dac33->fifo_size : samples; | |
f57d2cfa PU |
1235 | else |
1236 | delay = 0; | |
1237 | } | |
1238 | break; | |
1239 | case DAC33_FIFO_MODE7: | |
a3b55791 | 1240 | spin_lock_irqsave(&dac33->lock, flags); |
f57d2cfa | 1241 | t0 = dac33->t_stamp1; |
9d7db2b2 | 1242 | uthr = dac33->uthr; |
a3b55791 | 1243 | spin_unlock_irqrestore(&dac33->lock, flags); |
f57d2cfa PU |
1244 | t_now = ktime_to_us(ktime_get()); |
1245 | ||
1246 | /* We have not started to fill the FIFO yet, delay is 0 */ | |
1247 | if (!t0) | |
1248 | goto out; | |
1249 | ||
1250 | if (t_now <= t0) { | |
1251 | /* | |
1252 | * Either the timestamps are messed or equal. Report | |
1253 | * maximum delay | |
1254 | */ | |
9d7db2b2 | 1255 | delay = uthr; |
f57d2cfa PU |
1256 | goto out; |
1257 | } | |
1258 | ||
1259 | time_delta = t_now - t0; | |
1260 | if (time_delta <= dac33->mode7_us_to_lthr) { | |
1261 | /* | |
1262 | * Phase 1: | |
1263 | * After burst (draining phase) | |
1264 | */ | |
1265 | samples_out = US_TO_SAMPLES( | |
1266 | substream->runtime->rate, | |
1267 | time_delta); | |
1268 | ||
9d7db2b2 PU |
1269 | if (likely(uthr > samples_out)) |
1270 | delay = uthr - samples_out; | |
f57d2cfa PU |
1271 | else |
1272 | delay = 0; | |
1273 | } else { | |
1274 | /* | |
1275 | * Phase 2: | |
1276 | * During burst operation | |
1277 | */ | |
1278 | time_delta = time_delta - dac33->mode7_us_to_lthr; | |
1279 | ||
1280 | samples_out = US_TO_SAMPLES( | |
1281 | substream->runtime->rate, | |
1282 | time_delta); | |
1283 | samples_in = US_TO_SAMPLES( | |
1284 | dac33->burst_rate, | |
1285 | time_delta); | |
549675ed | 1286 | delay = DAC33_MODE7_MARGIN + samples_in - samples_out; |
f57d2cfa | 1287 | |
9d7db2b2 PU |
1288 | if (unlikely(delay > uthr)) |
1289 | delay = uthr; | |
f57d2cfa PU |
1290 | } |
1291 | break; | |
1292 | default: | |
1293 | dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", | |
1294 | dac33->fifo_mode); | |
1295 | break; | |
1296 | } | |
1297 | out: | |
1298 | return delay; | |
1299 | } | |
1300 | ||
c8bf93f0 PU |
1301 | static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
1302 | int clk_id, unsigned int freq, int dir) | |
1303 | { | |
1304 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1305 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1306 | u8 ioc_reg, asrcb_reg; |
1307 | ||
1308 | ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); | |
1309 | asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B); | |
1310 | switch (clk_id) { | |
1311 | case TLV320DAC33_MCLK: | |
1312 | ioc_reg |= DAC33_REFSEL; | |
1313 | asrcb_reg |= DAC33_SRCREFSEL; | |
1314 | break; | |
1315 | case TLV320DAC33_SLEEPCLK: | |
1316 | ioc_reg &= ~DAC33_REFSEL; | |
1317 | asrcb_reg &= ~DAC33_SRCREFSEL; | |
1318 | break; | |
1319 | default: | |
1320 | dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id); | |
1321 | break; | |
1322 | } | |
1323 | dac33->refclk = freq; | |
1324 | ||
1325 | dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg); | |
1326 | dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg); | |
1327 | ||
1328 | return 0; | |
1329 | } | |
1330 | ||
1331 | static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1332 | unsigned int fmt) | |
1333 | { | |
1334 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1335 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1336 | u8 aictrl_a, aictrl_b; |
1337 | ||
1338 | aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); | |
1339 | aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); | |
1340 | /* set master/slave audio interface */ | |
1341 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1342 | case SND_SOC_DAIFMT_CBM_CFM: | |
1343 | /* Codec Master */ | |
1344 | aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); | |
1345 | break; | |
1346 | case SND_SOC_DAIFMT_CBS_CFS: | |
1347 | /* Codec Slave */ | |
adcb8bc0 PU |
1348 | if (dac33->fifo_mode) { |
1349 | dev_err(codec->dev, "FIFO mode requires master mode\n"); | |
1350 | return -EINVAL; | |
1351 | } else | |
1352 | aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); | |
c8bf93f0 PU |
1353 | break; |
1354 | default: | |
1355 | return -EINVAL; | |
1356 | } | |
1357 | ||
1358 | aictrl_a &= ~DAC33_AFMT_MASK; | |
1359 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1360 | case SND_SOC_DAIFMT_I2S: | |
1361 | aictrl_a |= DAC33_AFMT_I2S; | |
1362 | break; | |
1363 | case SND_SOC_DAIFMT_DSP_A: | |
1364 | aictrl_a |= DAC33_AFMT_DSP; | |
1365 | aictrl_b &= ~DAC33_DATA_DELAY_MASK; | |
44f497b4 | 1366 | aictrl_b |= DAC33_DATA_DELAY(0); |
c8bf93f0 PU |
1367 | break; |
1368 | case SND_SOC_DAIFMT_RIGHT_J: | |
1369 | aictrl_a |= DAC33_AFMT_RIGHT_J; | |
1370 | break; | |
1371 | case SND_SOC_DAIFMT_LEFT_J: | |
1372 | aictrl_a |= DAC33_AFMT_LEFT_J; | |
1373 | break; | |
1374 | default: | |
1375 | dev_err(codec->dev, "Unsupported format (%u)\n", | |
1376 | fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
1377 | return -EINVAL; | |
1378 | } | |
1379 | ||
1380 | dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); | |
1381 | dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); | |
1382 | ||
1383 | return 0; | |
1384 | } | |
1385 | ||
f0fba2ad | 1386 | static int dac33_soc_probe(struct snd_soc_codec *codec) |
c8bf93f0 | 1387 | { |
f0fba2ad | 1388 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1389 | int ret = 0; |
1390 | ||
f0fba2ad LG |
1391 | codec->control_data = dac33->control_data; |
1392 | codec->hw_write = (hw_write_t) i2c_master_send; | |
f0fba2ad | 1393 | dac33->codec = codec; |
c8bf93f0 | 1394 | |
f0fba2ad LG |
1395 | /* Read the tlv320dac33 ID registers */ |
1396 | ret = dac33_hard_power(codec, 1); | |
1397 | if (ret != 0) { | |
1398 | dev_err(codec->dev, "Failed to power up codec: %d\n", ret); | |
1399 | goto err_power; | |
1400 | } | |
911a0f0b | 1401 | ret = dac33_read_id(codec); |
f0fba2ad | 1402 | dac33_hard_power(codec, 0); |
c8bf93f0 | 1403 | |
911a0f0b PU |
1404 | if (ret < 0) { |
1405 | dev_err(codec->dev, "Failed to read chip ID: %d\n", ret); | |
1406 | ret = -ENODEV; | |
1407 | goto err_power; | |
1408 | } | |
1409 | ||
f0fba2ad LG |
1410 | /* Check if the IRQ number is valid and request it */ |
1411 | if (dac33->irq >= 0) { | |
1412 | ret = request_irq(dac33->irq, dac33_interrupt_handler, | |
88e24c3a | 1413 | IRQF_TRIGGER_RISING, |
f0fba2ad LG |
1414 | codec->name, codec); |
1415 | if (ret < 0) { | |
1416 | dev_err(codec->dev, "Could not request IRQ%d (%d)\n", | |
1417 | dac33->irq, ret); | |
1418 | dac33->irq = -1; | |
1419 | } | |
1420 | if (dac33->irq != -1) { | |
1421 | /* Setup work queue */ | |
1422 | dac33->dac33_wq = | |
1423 | create_singlethread_workqueue("tlv320dac33"); | |
1424 | if (dac33->dac33_wq == NULL) { | |
1425 | free_irq(dac33->irq, codec); | |
1426 | return -ENOMEM; | |
1427 | } | |
1428 | ||
1429 | INIT_WORK(&dac33->work, dac33_work); | |
1430 | } | |
c8bf93f0 PU |
1431 | } |
1432 | ||
a577b318 | 1433 | /* Only add the FIFO controls, if we have valid IRQ number */ |
3591f4cd | 1434 | if (dac33->irq >= 0) |
022658be | 1435 | snd_soc_add_codec_controls(codec, dac33_mode_snd_controls, |
a577b318 | 1436 | ARRAY_SIZE(dac33_mode_snd_controls)); |
3591f4cd | 1437 | |
f0fba2ad | 1438 | err_power: |
c8bf93f0 PU |
1439 | return ret; |
1440 | } | |
1441 | ||
f0fba2ad | 1442 | static int dac33_soc_remove(struct snd_soc_codec *codec) |
c8bf93f0 | 1443 | { |
f0fba2ad | 1444 | struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); |
c8bf93f0 PU |
1445 | |
1446 | dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1447 | ||
f0fba2ad LG |
1448 | if (dac33->irq >= 0) { |
1449 | free_irq(dac33->irq, dac33->codec); | |
1450 | destroy_workqueue(dac33->dac33_wq); | |
1451 | } | |
c8bf93f0 PU |
1452 | return 0; |
1453 | } | |
1454 | ||
f0fba2ad LG |
1455 | static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { |
1456 | .read = dac33_read_reg_cache, | |
1457 | .write = dac33_write_locked, | |
1458 | .set_bias_level = dac33_set_bias_level, | |
eb3032f8 | 1459 | .idle_bias_off = true, |
f0fba2ad LG |
1460 | .reg_cache_size = ARRAY_SIZE(dac33_reg), |
1461 | .reg_word_size = sizeof(u8), | |
1462 | .reg_cache_default = dac33_reg, | |
c8bf93f0 PU |
1463 | .probe = dac33_soc_probe, |
1464 | .remove = dac33_soc_remove, | |
8066eb55 PU |
1465 | |
1466 | .controls = dac33_snd_controls, | |
1467 | .num_controls = ARRAY_SIZE(dac33_snd_controls), | |
1468 | .dapm_widgets = dac33_dapm_widgets, | |
1469 | .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets), | |
1470 | .dapm_routes = audio_map, | |
1471 | .num_dapm_routes = ARRAY_SIZE(audio_map), | |
c8bf93f0 | 1472 | }; |
c8bf93f0 PU |
1473 | |
1474 | #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ | |
1475 | SNDRV_PCM_RATE_48000) | |
0d99d2b0 | 1476 | #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) |
c8bf93f0 | 1477 | |
85e7652d | 1478 | static const struct snd_soc_dai_ops dac33_dai_ops = { |
0b61d2b9 | 1479 | .startup = dac33_startup, |
c8bf93f0 PU |
1480 | .shutdown = dac33_shutdown, |
1481 | .hw_params = dac33_hw_params, | |
c8bf93f0 | 1482 | .trigger = dac33_pcm_trigger, |
f57d2cfa | 1483 | .delay = dac33_dai_delay, |
c8bf93f0 PU |
1484 | .set_sysclk = dac33_set_dai_sysclk, |
1485 | .set_fmt = dac33_set_dai_fmt, | |
1486 | }; | |
1487 | ||
f0fba2ad LG |
1488 | static struct snd_soc_dai_driver dac33_dai = { |
1489 | .name = "tlv320dac33-hifi", | |
c8bf93f0 PU |
1490 | .playback = { |
1491 | .stream_name = "Playback", | |
1492 | .channels_min = 2, | |
1493 | .channels_max = 2, | |
1494 | .rates = DAC33_RATES, | |
3a4cbf88 | 1495 | .formats = DAC33_FORMATS, |
8d725b2b | 1496 | .sig_bits = 24, |
3a4cbf88 | 1497 | }, |
c8bf93f0 PU |
1498 | .ops = &dac33_dai_ops, |
1499 | }; | |
c8bf93f0 | 1500 | |
7a79e94e BP |
1501 | static int dac33_i2c_probe(struct i2c_client *client, |
1502 | const struct i2c_device_id *id) | |
c8bf93f0 PU |
1503 | { |
1504 | struct tlv320dac33_platform_data *pdata; | |
1505 | struct tlv320dac33_priv *dac33; | |
3a7aaed7 | 1506 | int ret, i; |
c8bf93f0 PU |
1507 | |
1508 | if (client->dev.platform_data == NULL) { | |
1509 | dev_err(&client->dev, "Platform data not set\n"); | |
1510 | return -ENODEV; | |
1511 | } | |
1512 | pdata = client->dev.platform_data; | |
1513 | ||
a54877d7 AL |
1514 | dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv), |
1515 | GFP_KERNEL); | |
c8bf93f0 PU |
1516 | if (dac33 == NULL) |
1517 | return -ENOMEM; | |
1518 | ||
f0fba2ad | 1519 | dac33->control_data = client; |
c8bf93f0 | 1520 | mutex_init(&dac33->mutex); |
f57d2cfa | 1521 | spin_lock_init(&dac33->lock); |
c8bf93f0 PU |
1522 | |
1523 | i2c_set_clientdata(client, dac33); | |
1524 | ||
1525 | dac33->power_gpio = pdata->power_gpio; | |
6aceabb4 | 1526 | dac33->burst_bclkdiv = pdata->burst_bclkdiv; |
eeb309a8 | 1527 | dac33->keep_bclk = pdata->keep_bclk; |
f430a27f PU |
1528 | dac33->mode1_latency = pdata->mode1_latency; |
1529 | if (!dac33->mode1_latency) | |
1530 | dac33->mode1_latency = 10000; /* 10ms */ | |
c8bf93f0 | 1531 | dac33->irq = client->irq; |
c8bf93f0 | 1532 | /* Disable FIFO use by default */ |
7427b4b9 | 1533 | dac33->fifo_mode = DAC33_FIFO_BYPASS; |
c8bf93f0 | 1534 | |
c8bf93f0 PU |
1535 | /* Check if the reset GPIO number is valid and request it */ |
1536 | if (dac33->power_gpio >= 0) { | |
1537 | ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset"); | |
1538 | if (ret < 0) { | |
f0fba2ad | 1539 | dev_err(&client->dev, |
c8bf93f0 PU |
1540 | "Failed to request reset GPIO (%d)\n", |
1541 | dac33->power_gpio); | |
f0fba2ad | 1542 | goto err_gpio; |
c8bf93f0 PU |
1543 | } |
1544 | gpio_direction_output(dac33->power_gpio, 0); | |
c8bf93f0 PU |
1545 | } |
1546 | ||
3a7aaed7 IK |
1547 | for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) |
1548 | dac33->supplies[i].supply = dac33_supply_names[i]; | |
1549 | ||
f0fba2ad | 1550 | ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), |
3a7aaed7 IK |
1551 | dac33->supplies); |
1552 | ||
1553 | if (ret != 0) { | |
f0fba2ad | 1554 | dev_err(&client->dev, "Failed to request supplies: %d\n", ret); |
3a7aaed7 IK |
1555 | goto err_get; |
1556 | } | |
1557 | ||
f0fba2ad LG |
1558 | ret = snd_soc_register_codec(&client->dev, |
1559 | &soc_codec_dev_tlv320dac33, &dac33_dai, 1); | |
1560 | if (ret < 0) | |
1561 | goto err_register; | |
c8bf93f0 | 1562 | |
c8bf93f0 | 1563 | return ret; |
f0fba2ad | 1564 | err_register: |
3a7aaed7 IK |
1565 | regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); |
1566 | err_get: | |
c8bf93f0 PU |
1567 | if (dac33->power_gpio >= 0) |
1568 | gpio_free(dac33->power_gpio); | |
f0fba2ad | 1569 | err_gpio: |
c8bf93f0 PU |
1570 | return ret; |
1571 | } | |
1572 | ||
7a79e94e | 1573 | static int dac33_i2c_remove(struct i2c_client *client) |
c8bf93f0 | 1574 | { |
f0fba2ad | 1575 | struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); |
239fe55c PU |
1576 | |
1577 | if (unlikely(dac33->chip_power)) | |
f0fba2ad | 1578 | dac33_hard_power(dac33->codec, 0); |
c8bf93f0 PU |
1579 | |
1580 | if (dac33->power_gpio >= 0) | |
1581 | gpio_free(dac33->power_gpio); | |
c8bf93f0 | 1582 | |
3a7aaed7 IK |
1583 | regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); |
1584 | ||
f0fba2ad | 1585 | snd_soc_unregister_codec(&client->dev); |
c8bf93f0 PU |
1586 | return 0; |
1587 | } | |
1588 | ||
1589 | static const struct i2c_device_id tlv320dac33_i2c_id[] = { | |
1590 | { | |
1591 | .name = "tlv320dac33", | |
1592 | .driver_data = 0, | |
1593 | }, | |
1594 | { }, | |
1595 | }; | |
573f26e3 | 1596 | MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id); |
c8bf93f0 PU |
1597 | |
1598 | static struct i2c_driver tlv320dac33_i2c_driver = { | |
1599 | .driver = { | |
f0fba2ad | 1600 | .name = "tlv320dac33-codec", |
c8bf93f0 PU |
1601 | .owner = THIS_MODULE, |
1602 | }, | |
1603 | .probe = dac33_i2c_probe, | |
7a79e94e | 1604 | .remove = dac33_i2c_remove, |
c8bf93f0 PU |
1605 | .id_table = tlv320dac33_i2c_id, |
1606 | }; | |
1607 | ||
63a47a75 | 1608 | module_i2c_driver(tlv320dac33_i2c_driver); |
c8bf93f0 PU |
1609 | |
1610 | MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); | |
93864cf0 | 1611 | MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); |
c8bf93f0 | 1612 | MODULE_LICENSE("GPL"); |