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ASoC: TWL4030: Remove OUTL/R outputs
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
4260393e
PU		 53#define MODE7_LTHR 10
54#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55
76f47127
PU		 56#define BURST_BASEFREQ_HZ 49152000
57
f57d2cfa
PU		 58#define SAMPLES_TO_US(rate, samples) \
59 (1000000000 / ((rate * 1000) / samples))
60
61#define US_TO_SAMPLES(rate, us) \
62 (rate / (1000000 / us))
63
64
c8bf93f0
PU		 65static struct snd_soc_codec *tlv320dac33_codec;
66
67enum dac33_state {
68 DAC33_IDLE = 0,
69 DAC33_PREFILL,
70 DAC33_PLAYBACK,
71 DAC33_FLUSH,
72};
73
7427b4b9
PU		 74enum dac33_fifo_modes {
75 DAC33_FIFO_BYPASS = 0,
76 DAC33_FIFO_MODE1,
28e05d98 77 DAC33_FIFO_MODE7,
7427b4b9
PU		 78 DAC33_FIFO_LAST_MODE,
79};
80
3a7aaed7
IK		 81#define DAC33_NUM_SUPPLIES 3
82static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
83 "AVDD",
84 "DVDD",
85 "IOVDD",
86};
87
c8bf93f0
PU		 88struct tlv320dac33_priv {
89 struct mutex mutex;
90 struct workqueue_struct *dac33_wq;
91 struct work_struct work;
92 struct snd_soc_codec codec;
3a7aaed7 93 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
c8bf93f0
PU		 94 int power_gpio;
95 int chip_power;
96 int irq;
97 unsigned int refclk;
98
99 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
100 unsigned int nsample_min; /* nsample should not be lower than
101 * this */
102 unsigned int nsample_max; /* nsample should not be higher than
103 * this */
7427b4b9 104 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 105 unsigned int nsample; /* burst read amount from host */
6aceabb4 106 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 107 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 108
eeb309a8
PU		 109 int keep_bclk; /* Keep the BCLK continuously running
110 * in FIFO modes */
f57d2cfa
PU		 111 spinlock_t lock;
112 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
113 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
114
115 unsigned int mode1_us_burst; /* Time to burst read n number of
116 * samples */
117 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
118
c8bf93f0
PU		 119 enum dac33_state state;
120};
121
122static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1230x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1240x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1250x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1260x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1270x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1280x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1290x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1300x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1310x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1320x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1330x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1340x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1350x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1360x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1370x00, 0x00, /* 0x38 - 0x39 */
138/* Registers 0x3a - 0x3f are reserved */
139 0x00, 0x00, /* 0x3a - 0x3b */
1400x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
141
1420x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1430x00, 0x80, /* 0x44 - 0x45 */
144/* Registers 0x46 - 0x47 are reserved */
145 0x80, 0x80, /* 0x46 - 0x47 */
146
1470x80, 0x00, 0x00, /* 0x48 - 0x4a */
148/* Registers 0x4b - 0x7c are reserved */
149 0x00, /* 0x4b */
1500x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1510x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1520x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1530x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1540x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1550x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1560x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1570x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1580x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1590x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1600x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1610x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1620x00, /* 0x7c */
163
164 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
165};
166
167/* Register read and write */
168static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
169 unsigned reg)
170{
171 u8 *cache = codec->reg_cache;
172 if (reg >= DAC33_CACHEREGNUM)
173 return 0;
174
175 return cache[reg];
176}
177
178static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
179 u8 reg, u8 value)
180{
181 u8 *cache = codec->reg_cache;
182 if (reg >= DAC33_CACHEREGNUM)
183 return;
184
185 cache[reg] = value;
186}
187
188static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
189 u8 *value)
190{
b2c812e2 191 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 192 int val;
193
194 *value = reg & 0xff;
195
196 /* If powered off, return the cached value */
197 if (dac33->chip_power) {
198 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
199 if (val < 0) {
200 dev_err(codec->dev, "Read failed (%d)\n", val);
201 value[0] = dac33_read_reg_cache(codec, reg);
202 } else {
203 value[0] = val;
204 dac33_write_reg_cache(codec, reg, val);
205 }
206 } else {
207 value[0] = dac33_read_reg_cache(codec, reg);
208 }
209
210 return 0;
211}
212
213static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
214 unsigned int value)
215{
b2c812e2 216 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 217 u8 data[2];
218 int ret = 0;
219
220 /*
221 * data is
222 * D15..D8 dac33 register offset
223 * D7...D0 register data
224 */
225 data[0] = reg & 0xff;
226 data[1] = value & 0xff;
227
228 dac33_write_reg_cache(codec, data[0], data[1]);
229 if (dac33->chip_power) {
230 ret = codec->hw_write(codec->control_data, data, 2);
231 if (ret != 2)
232 dev_err(codec->dev, "Write failed (%d)\n", ret);
233 else
234 ret = 0;
235 }
236
237 return ret;
238}
239
240static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
241 unsigned int value)
242{
b2c812e2 243 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 244 int ret;
245
246 mutex_lock(&dac33->mutex);
247 ret = dac33_write(codec, reg, value);
248 mutex_unlock(&dac33->mutex);
249
250 return ret;
251}
252
253#define DAC33_I2C_ADDR_AUTOINC 0x80
254static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
255 unsigned int value)
256{
b2c812e2 257 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 258 u8 data[3];
259 int ret = 0;
260
261 /*
262 * data is
263 * D23..D16 dac33 register offset
264 * D15..D8 register data MSB
265 * D7...D0 register data LSB
266 */
267 data[0] = reg & 0xff;
268 data[1] = (value >> 8) & 0xff;
269 data[2] = value & 0xff;
270
271 dac33_write_reg_cache(codec, data[0], data[1]);
272 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
273
274 if (dac33->chip_power) {
275 /* We need to set autoincrement mode for 16 bit writes */
276 data[0] |= DAC33_I2C_ADDR_AUTOINC;
277 ret = codec->hw_write(codec->control_data, data, 3);
278 if (ret != 3)
279 dev_err(codec->dev, "Write failed (%d)\n", ret);
280 else
281 ret = 0;
282 }
283
284 return ret;
285}
286
287static void dac33_restore_regs(struct snd_soc_codec *codec)
288{
b2c812e2 289 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 290 u8 *cache = codec->reg_cache;
291 u8 data[2];
292 int i, ret;
293
294 if (!dac33->chip_power)
295 return;
296
297 for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
298 data[0] = i;
299 data[1] = cache[i];
300 /* Skip the read only registers */
301 if ((i >= DAC33_INT_OSC_STATUS &&
302 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
303 (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
304 i == DAC33_DAC_STATUS_FLAGS ||
305 i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
306 i == DAC33_SRC_EST_REF_CLK_RATIO_B)
307 continue;
308 ret = codec->hw_write(codec->control_data, data, 2);
309 if (ret != 2)
310 dev_err(codec->dev, "Write failed (%d)\n", ret);
311 }
312 for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
313 data[0] = i;
314 data[1] = cache[i];
315 ret = codec->hw_write(codec->control_data, data, 2);
316 if (ret != 2)
317 dev_err(codec->dev, "Write failed (%d)\n", ret);
318 }
319 for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
320 data[0] = i;
321 data[1] = cache[i];
322 ret = codec->hw_write(codec->control_data, data, 2);
323 if (ret != 2)
324 dev_err(codec->dev, "Write failed (%d)\n", ret);
325 }
326}
327
328static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
329{
330 u8 reg;
331
332 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
333 if (power)
334 reg |= DAC33_PDNALLB;
335 else
c3746a07
PU		 336 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
337 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 338 dac33_write(codec, DAC33_PWR_CTRL, reg);
339}
340
3a7aaed7 341static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 342{
b2c812e2 343 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7 344 int ret;
c8bf93f0
PU		 345
346 mutex_lock(&dac33->mutex);
347 if (power) {
3a7aaed7
IK		 348 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
349 dac33->supplies);
350 if (ret != 0) {
351 dev_err(codec->dev,
352 "Failed to enable supplies: %d\n", ret);
353 goto exit;
c8bf93f0 354 }
3a7aaed7
IK		 355
356 if (dac33->power_gpio >= 0)
357 gpio_set_value(dac33->power_gpio, 1);
358
359 dac33->chip_power = 1;
360
361 /* Restore registers */
362 dac33_restore_regs(codec);
363
c8bf93f0
PU		 364 dac33_soft_power(codec, 1);
365 } else {
366 dac33_soft_power(codec, 0);
3a7aaed7 367 if (dac33->power_gpio >= 0)
c8bf93f0 368 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 369
370 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
371 dac33->supplies);
372 if (ret != 0) {
373 dev_err(codec->dev,
374 "Failed to disable supplies: %d\n", ret);
375 goto exit;
c8bf93f0 376 }
3a7aaed7
IK		 377
378 dac33->chip_power = 0;
c8bf93f0 379 }
c8bf93f0 380
3a7aaed7
IK		 381exit:
382 mutex_unlock(&dac33->mutex);
383 return ret;
c8bf93f0
PU		 384}
385
386static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
387 struct snd_ctl_elem_value *ucontrol)
388{
389 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 390 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 391
392 ucontrol->value.integer.value[0] = dac33->nsample;
393
394 return 0;
395}
396
397static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
398 struct snd_ctl_elem_value *ucontrol)
399{
400 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 401 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 402 int ret = 0;
403
404 if (dac33->nsample == ucontrol->value.integer.value[0])
405 return 0;
406
407 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
f57d2cfa 408 ucontrol->value.integer.value[0] > dac33->nsample_max) {
c8bf93f0 409 ret = -EINVAL;
f57d2cfa 410 } else {
c8bf93f0 411 dac33->nsample = ucontrol->value.integer.value[0];
f57d2cfa
PU		 412 /* Re calculate the burst time */
413 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
414 dac33->nsample);
415 }
c8bf93f0
PU		 416
417 return ret;
418}
419
7427b4b9 420static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 421 struct snd_ctl_elem_value *ucontrol)
422{
423 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 424 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 425
7427b4b9 426 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 427
428 return 0;
429}
430
7427b4b9 431static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 432 struct snd_ctl_elem_value *ucontrol)
433{
434 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 435 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 436 int ret = 0;
437
7427b4b9 438 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 439 return 0;
440 /* Do not allow changes while stream is running*/
441 if (codec->active)
442 return -EPERM;
443
444 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 445 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 446 ret = -EINVAL;
447 else
7427b4b9 448 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 449
450 return ret;
451}
452
7427b4b9
PU		 453/* Codec operation modes */
454static const char *dac33_fifo_mode_texts[] = {
28e05d98 455 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 456};
457
458static const struct soc_enum dac33_fifo_mode_enum =
459 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
460 dac33_fifo_mode_texts);
461
c8bf93f0
PU		 462/*
463 * DACL/R digital volume control:
464 * from 0 dB to -63.5 in 0.5 dB steps
465 * Need to be inverted later on:
466 * 0x00 == 0 dB
467 * 0x7f == -63.5 dB
468 */
469static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
470
471static const struct snd_kcontrol_new dac33_snd_controls[] = {
472 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
473 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
474 0, 0x7f, 1, dac_digivol_tlv),
475 SOC_DOUBLE_R("DAC Digital Playback Switch",
476 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
477 SOC_DOUBLE_R("Line to Line Out Volume",
478 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
479};
480
481static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
482 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
483 dac33_get_nsample, dac33_set_nsample),
7427b4b9
PU		 484 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
485 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 486};
487
488/* Analog bypass */
489static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
490 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
491
492static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
493 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
494
495static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
496 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
497 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
498
499 SND_SOC_DAPM_INPUT("LINEL"),
500 SND_SOC_DAPM_INPUT("LINER"),
501
502 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
503 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
504
505 /* Analog bypass */
506 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
507 &dac33_dapm_abypassl_control),
508 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
509 &dac33_dapm_abypassr_control),
510
511 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
512 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
513 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
514 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
515};
516
517static const struct snd_soc_dapm_route audio_map[] = {
518 /* Analog bypass */
519 {"Analog Left Bypass", "Switch", "LINEL"},
520 {"Analog Right Bypass", "Switch", "LINER"},
521
522 {"Output Left Amp Power", NULL, "DACL"},
523 {"Output Right Amp Power", NULL, "DACR"},
524
525 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
526 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
527
528 /* output */
529 {"LEFT_LO", NULL, "Output Left Amp Power"},
530 {"RIGHT_LO", NULL, "Output Right Amp Power"},
531};
532
533static int dac33_add_widgets(struct snd_soc_codec *codec)
534{
535 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
536 ARRAY_SIZE(dac33_dapm_widgets));
537
538 /* set up audio path interconnects */
539 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 540
541 return 0;
542}
543
544static int dac33_set_bias_level(struct snd_soc_codec *codec,
545 enum snd_soc_bias_level level)
546{
3a7aaed7
IK		 547 int ret;
548
c8bf93f0
PU		 549 switch (level) {
550 case SND_SOC_BIAS_ON:
551 dac33_soft_power(codec, 1);
552 break;
553 case SND_SOC_BIAS_PREPARE:
554 break;
555 case SND_SOC_BIAS_STANDBY:
3a7aaed7
IK		 556 if (codec->bias_level == SND_SOC_BIAS_OFF) {
557 ret = dac33_hard_power(codec, 1);
558 if (ret != 0)
559 return ret;
560 }
561
c8bf93f0
PU		 562 dac33_soft_power(codec, 0);
563 break;
564 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 565 ret = dac33_hard_power(codec, 0);
566 if (ret != 0)
567 return ret;
568
c8bf93f0
PU		 569 break;
570 }
571 codec->bias_level = level;
572
573 return 0;
574}
575
d4f102d4
PU		 576static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
577{
578 struct snd_soc_codec *codec;
579
580 codec = &dac33->codec;
581
582 switch (dac33->fifo_mode) {
583 case DAC33_FIFO_MODE1:
584 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f4d59328 585 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
f57d2cfa
PU		 586
587 /* Take the timestamps */
588 spin_lock_irq(&dac33->lock);
589 dac33->t_stamp2 = ktime_to_us(ktime_get());
590 dac33->t_stamp1 = dac33->t_stamp2;
591 spin_unlock_irq(&dac33->lock);
592
d4f102d4
PU		 593 dac33_write16(codec, DAC33_PREFILL_MSB,
594 DAC33_THRREG(dac33->alarm_threshold));
f4d59328
PU		 595 /* Enable Alarm Threshold IRQ with a delay */
596 udelay(SAMPLES_TO_US(dac33->burst_rate,
597 dac33->alarm_threshold));
598 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 599 break;
28e05d98 600 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 601 /* Take the timestamp */
602 spin_lock_irq(&dac33->lock);
603 dac33->t_stamp1 = ktime_to_us(ktime_get());
604 /* Move back the timestamp with drain time */
605 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
606 spin_unlock_irq(&dac33->lock);
607
28e05d98 608 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 609 DAC33_THRREG(MODE7_LTHR));
f57d2cfa
PU		 610
611 /* Enable Upper Threshold IRQ */
612 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 613 break;
d4f102d4
PU		 614 default:
615 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
616 dac33->fifo_mode);
617 break;
618 }
619}
620
621static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
622{
623 struct snd_soc_codec *codec;
624
625 codec = &dac33->codec;
626
627 switch (dac33->fifo_mode) {
628 case DAC33_FIFO_MODE1:
f57d2cfa
PU		 629 /* Take the timestamp */
630 spin_lock_irq(&dac33->lock);
631 dac33->t_stamp2 = ktime_to_us(ktime_get());
632 spin_unlock_irq(&dac33->lock);
633
d4f102d4
PU		 634 dac33_write16(codec, DAC33_NSAMPLE_MSB,
635 DAC33_THRREG(dac33->nsample));
636 break;
28e05d98
PU		 637 case DAC33_FIFO_MODE7:
638 /* At the moment we are not using interrupts in mode7 */
639 break;
d4f102d4
PU		 640 default:
641 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
642 dac33->fifo_mode);
643 break;
644 }
645}
646
c8bf93f0
PU		 647static void dac33_work(struct work_struct *work)
648{
649 struct snd_soc_codec *codec;
650 struct tlv320dac33_priv *dac33;
651 u8 reg;
652
653 dac33 = container_of(work, struct tlv320dac33_priv, work);
654 codec = &dac33->codec;
655
656 mutex_lock(&dac33->mutex);
657 switch (dac33->state) {
658 case DAC33_PREFILL:
659 dac33->state = DAC33_PLAYBACK;
d4f102d4 660 dac33_prefill_handler(dac33);
c8bf93f0
PU		 661 break;
662 case DAC33_PLAYBACK:
d4f102d4 663 dac33_playback_handler(dac33);
c8bf93f0
PU		 664 break;
665 case DAC33_IDLE:
666 break;
667 case DAC33_FLUSH:
668 dac33->state = DAC33_IDLE;
669 /* Mask all interrupts from dac33 */
670 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
671
672 /* flush fifo */
673 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
674 reg |= DAC33_FIFOFLUSH;
675 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
676 break;
677 }
678 mutex_unlock(&dac33->mutex);
679}
680
681static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
682{
683 struct snd_soc_codec *codec = dev;
b2c812e2 684 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 685
f57d2cfa
PU		 686 spin_lock(&dac33->lock);
687 dac33->t_stamp1 = ktime_to_us(ktime_get());
688 spin_unlock(&dac33->lock);
689
690 /* Do not schedule the workqueue in Mode7 */
691 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
692 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0
PU		 693
694 return IRQ_HANDLED;
695}
696
c8bf93f0
PU		 697static void dac33_oscwait(struct snd_soc_codec *codec)
698{
699 int timeout = 20;
700 u8 reg;
701
702 do {
703 msleep(1);
704 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
705 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
706 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
707 dev_err(codec->dev,
708 "internal oscillator calibration failed\n");
709}
710
711static int dac33_hw_params(struct snd_pcm_substream *substream,
712 struct snd_pcm_hw_params *params,
713 struct snd_soc_dai *dai)
714{
715 struct snd_soc_pcm_runtime *rtd = substream->private_data;
716 struct snd_soc_device *socdev = rtd->socdev;
717 struct snd_soc_codec *codec = socdev->card->codec;
718
719 /* Check parameters for validity */
720 switch (params_rate(params)) {
721 case 44100:
722 case 48000:
723 break;
724 default:
725 dev_err(codec->dev, "unsupported rate %d\n",
726 params_rate(params));
727 return -EINVAL;
728 }
729
730 switch (params_format(params)) {
731 case SNDRV_PCM_FORMAT_S16_LE:
732 break;
733 default:
734 dev_err(codec->dev, "unsupported format %d\n",
735 params_format(params));
736 return -EINVAL;
737 }
738
739 return 0;
740}
741
742#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 743 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 744#define CALC_RATIOSET(rate, refclk) ( \
745 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
746
747/*
748 * tlv320dac33 is strict on the sequence of the register writes, if the register
749 * writes happens in different order, than dac33 might end up in unknown state.
750 * Use the known, working sequence of register writes to initialize the dac33.
751 */
752static int dac33_prepare_chip(struct snd_pcm_substream *substream)
753{
754 struct snd_soc_pcm_runtime *rtd = substream->private_data;
755 struct snd_soc_device *socdev = rtd->socdev;
756 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 757 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 758 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 759 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 760
761 switch (substream->runtime->rate) {
762 case 44100:
763 case 48000:
764 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
765 ratioset = CALC_RATIOSET(substream->runtime->rate,
766 dac33->refclk);
767 break;
768 default:
769 dev_err(codec->dev, "unsupported rate %d\n",
770 substream->runtime->rate);
771 return -EINVAL;
772 }
773
774
775 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
776 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 777 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 778 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 779 fifoctrl_a &= ~DAC33_FIFOFLUSH;
780
c8bf93f0
PU		 781 fifoctrl_a &= ~DAC33_WIDTH;
782 switch (substream->runtime->format) {
783 case SNDRV_PCM_FORMAT_S16_LE:
784 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
785 fifoctrl_a |= DAC33_WIDTH;
786 break;
787 default:
788 dev_err(codec->dev, "unsupported format %d\n",
789 substream->runtime->format);
790 return -EINVAL;
791 }
792
793 mutex_lock(&dac33->mutex);
c3746a07 794 dac33_soft_power(codec, 0);
c8bf93f0
PU		 795 dac33_soft_power(codec, 1);
796
797 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
798 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
799
800 /* Write registers 0x08 and 0x09 (MSB, LSB) */
801 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
802
803 /* calib time: 128 is a nice number ;) */
804 dac33_write(codec, DAC33_CALIB_TIME, 128);
805
806 /* adjustment treshold & step */
807 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
808 DAC33_ADJSTEP(1));
809
810 /* div=4 / gain=1 / div */
811 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
812
813 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
814 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
815 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
816
817 dac33_oscwait(codec);
818
7427b4b9 819 if (dac33->fifo_mode) {
aec242dc 820 /* Generic for all FIFO modes */
c8bf93f0 821 /* 50-51 : ASRC Control registers */
fdb6b1e1 822 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 823 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
824
825 /* Write registers 0x34 and 0x35 (MSB, LSB) */
826 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
827
828 /* Set interrupts to high active */
829 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 830 } else {
aec242dc 831 /* FIFO bypass mode */
c8bf93f0
PU		 832 /* 50-51 : ASRC Control registers */
833 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
834 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
835 }
836
aec242dc
PU		 837 /* Interrupt behaviour configuration */
838 switch (dac33->fifo_mode) {
839 case DAC33_FIFO_MODE1:
840 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
841 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 842 break;
28e05d98 843 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 844 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
845 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 846 break;
aec242dc
PU		 847 default:
848 /* in FIFO bypass mode, the interrupts are not used */
849 break;
850 }
851
852 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
853
854 switch (dac33->fifo_mode) {
855 case DAC33_FIFO_MODE1:
856 /*
857 * For mode1:
858 * Disable the FIFO bypass (Enable the use of FIFO)
859 * Select nSample mode
860 * BCLK is only running when data is needed by DAC33
861 */
c8bf93f0 862 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 863 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 864 if (dac33->keep_bclk)
865 aictrl_b |= DAC33_BCLKON;
866 else
867 aictrl_b &= ~DAC33_BCLKON;
aec242dc 868 break;
28e05d98
PU		 869 case DAC33_FIFO_MODE7:
870 /*
871 * For mode1:
872 * Disable the FIFO bypass (Enable the use of FIFO)
873 * Select Threshold mode
874 * BCLK is only running when data is needed by DAC33
875 */
876 fifoctrl_a &= ~DAC33_FBYPAS;
877 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 878 if (dac33->keep_bclk)
879 aictrl_b |= DAC33_BCLKON;
880 else
881 aictrl_b &= ~DAC33_BCLKON;
28e05d98 882 break;
aec242dc
PU		 883 default:
884 /*
885 * For FIFO bypass mode:
886 * Enable the FIFO bypass (Disable the FIFO use)
887 * Set the BCLK as continous
888 */
c8bf93f0 889 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 890 aictrl_b |= DAC33_BCLKON;
891 break;
892 }
c8bf93f0 893
aec242dc 894 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 895 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 896 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 897
6aceabb4
PU		 898 /*
899 * BCLK divide ratio
900 * 0: 1.5
901 * 1: 1
902 * 2: 2
903 * ...
904 * 254: 254
905 * 255: 255
906 */
6cd6cede 907 if (dac33->fifo_mode)
6aceabb4
PU		 908 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
909 dac33->burst_bclkdiv);
6cd6cede
PU		 910 else
911 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 912
6cd6cede
PU		 913 switch (dac33->fifo_mode) {
914 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 915 dac33_write16(codec, DAC33_ATHR_MSB,
916 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 917 break;
28e05d98
PU		 918 case DAC33_FIFO_MODE7:
919 /*
920 * Configure the threshold levels, and leave 10 sample space
921 * at the bottom, and also at the top of the FIFO
922 */
4260393e
PU		 923 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
924 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 925 break;
aec242dc 926 default:
aec242dc 927 break;
c8bf93f0
PU		 928 }
929
930 mutex_unlock(&dac33->mutex);
931
932 return 0;
933}
934
935static void dac33_calculate_times(struct snd_pcm_substream *substream)
936{
937 struct snd_soc_pcm_runtime *rtd = substream->private_data;
938 struct snd_soc_device *socdev = rtd->socdev;
939 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 940 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 941 unsigned int nsample_limit;
942
55abb59c
PU		 943 /* In bypass mode we don't need to calculate */
944 if (!dac33->fifo_mode)
945 return;
946
c8bf93f0
PU		 947 /* Number of samples (16bit, stereo) in one period */
948 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
949
950 /* Number of samples (16bit, stereo) in ALSA buffer */
951 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
952 /* Subtract one period from the total */
953 dac33->nsample_max -= dac33->nsample_min;
954
955 /* Number of samples for LATENCY_TIME_MS / 2 */
956 dac33->alarm_threshold = substream->runtime->rate /
957 (1000 / (LATENCY_TIME_MS / 2));
958
959 /* Find and fix up the lowest nsmaple limit */
960 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
961
962 if (dac33->nsample_min < nsample_limit)
963 dac33->nsample_min = nsample_limit;
964
965 if (dac33->nsample < dac33->nsample_min)
966 dac33->nsample = dac33->nsample_min;
967
968 /*
969 * Find and fix up the highest nsmaple limit
970 * In order to not overflow the DAC33 buffer substract the
971 * alarm_threshold value from the size of the DAC33 buffer
972 */
973 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
974
975 if (dac33->nsample_max > nsample_limit)
976 dac33->nsample_max = nsample_limit;
977
978 if (dac33->nsample > dac33->nsample_max)
979 dac33->nsample = dac33->nsample_max;
f57d2cfa
PU		 980
981 switch (dac33->fifo_mode) {
982 case DAC33_FIFO_MODE1:
983 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
984 dac33->nsample);
985 dac33->t_stamp1 = 0;
986 dac33->t_stamp2 = 0;
987 break;
988 case DAC33_FIFO_MODE7:
989 dac33->mode7_us_to_lthr =
990 SAMPLES_TO_US(substream->runtime->rate,
991 MODE7_UTHR - MODE7_LTHR + 1);
992 dac33->t_stamp1 = 0;
993 break;
994 default:
995 break;
996 }
997
c8bf93f0
PU		 998}
999
1000static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
1001 struct snd_soc_dai *dai)
1002{
1003 dac33_calculate_times(substream);
1004 dac33_prepare_chip(substream);
1005
1006 return 0;
1007}
1008
1009static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1010 struct snd_soc_dai *dai)
1011{
1012 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1013 struct snd_soc_device *socdev = rtd->socdev;
1014 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1015 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1016 int ret = 0;
1017
1018 switch (cmd) {
1019 case SNDRV_PCM_TRIGGER_START:
1020 case SNDRV_PCM_TRIGGER_RESUME:
1021 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1022 if (dac33->fifo_mode) {
c8bf93f0
PU		 1023 dac33->state = DAC33_PREFILL;
1024 queue_work(dac33->dac33_wq, &dac33->work);
1025 }
1026 break;
1027 case SNDRV_PCM_TRIGGER_STOP:
1028 case SNDRV_PCM_TRIGGER_SUSPEND:
1029 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1030 if (dac33->fifo_mode) {
c8bf93f0
PU		 1031 dac33->state = DAC33_FLUSH;
1032 queue_work(dac33->dac33_wq, &dac33->work);
1033 }
1034 break;
1035 default:
1036 ret = -EINVAL;
1037 }
1038
1039 return ret;
1040}
1041
f57d2cfa
PU		 1042static snd_pcm_sframes_t dac33_dai_delay(
1043 struct snd_pcm_substream *substream,
1044 struct snd_soc_dai *dai)
1045{
1046 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1047 struct snd_soc_device *socdev = rtd->socdev;
1048 struct snd_soc_codec *codec = socdev->card->codec;
1049 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1050 unsigned long long t0, t1, t_now;
1051 unsigned int time_delta;
1052 int samples_out, samples_in, samples;
1053 snd_pcm_sframes_t delay = 0;
1054
1055 switch (dac33->fifo_mode) {
1056 case DAC33_FIFO_BYPASS:
1057 break;
1058 case DAC33_FIFO_MODE1:
1059 spin_lock(&dac33->lock);
1060 t0 = dac33->t_stamp1;
1061 t1 = dac33->t_stamp2;
1062 spin_unlock(&dac33->lock);
1063 t_now = ktime_to_us(ktime_get());
1064
1065 /* We have not started to fill the FIFO yet, delay is 0 */
1066 if (!t1)
1067 goto out;
1068
1069 if (t0 > t1) {
1070 /*
1071 * Phase 1:
1072 * After Alarm threshold, and before nSample write
1073 */
1074 time_delta = t_now - t0;
1075 samples_out = time_delta ? US_TO_SAMPLES(
1076 substream->runtime->rate,
1077 time_delta) : 0;
1078
1079 if (likely(dac33->alarm_threshold > samples_out))
1080 delay = dac33->alarm_threshold - samples_out;
1081 else
1082 delay = 0;
1083 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1084 /*
1085 * Phase 2:
1086 * After nSample write (during burst operation)
1087 */
1088 time_delta = t_now - t0;
1089 samples_out = time_delta ? US_TO_SAMPLES(
1090 substream->runtime->rate,
1091 time_delta) : 0;
1092
1093 time_delta = t_now - t1;
1094 samples_in = time_delta ? US_TO_SAMPLES(
1095 dac33->burst_rate,
1096 time_delta) : 0;
1097
1098 samples = dac33->alarm_threshold;
1099 samples += (samples_in - samples_out);
1100
1101 if (likely(samples > 0))
1102 delay = samples;
1103 else
1104 delay = 0;
1105 } else {
1106 /*
1107 * Phase 3:
1108 * After burst operation, before next alarm threshold
1109 */
1110 time_delta = t_now - t0;
1111 samples_out = time_delta ? US_TO_SAMPLES(
1112 substream->runtime->rate,
1113 time_delta) : 0;
1114
1115 samples_in = dac33->nsample;
1116 samples = dac33->alarm_threshold;
1117 samples += (samples_in - samples_out);
1118
1119 if (likely(samples > 0))
1120 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1121 DAC33_BUFFER_SIZE_SAMPLES : samples;
1122 else
1123 delay = 0;
1124 }
1125 break;
1126 case DAC33_FIFO_MODE7:
1127 spin_lock(&dac33->lock);
1128 t0 = dac33->t_stamp1;
1129 spin_unlock(&dac33->lock);
1130 t_now = ktime_to_us(ktime_get());
1131
1132 /* We have not started to fill the FIFO yet, delay is 0 */
1133 if (!t0)
1134 goto out;
1135
1136 if (t_now <= t0) {
1137 /*
1138 * Either the timestamps are messed or equal. Report
1139 * maximum delay
1140 */
1141 delay = MODE7_UTHR;
1142 goto out;
1143 }
1144
1145 time_delta = t_now - t0;
1146 if (time_delta <= dac33->mode7_us_to_lthr) {
1147 /*
1148 * Phase 1:
1149 * After burst (draining phase)
1150 */
1151 samples_out = US_TO_SAMPLES(
1152 substream->runtime->rate,
1153 time_delta);
1154
1155 if (likely(MODE7_UTHR > samples_out))
1156 delay = MODE7_UTHR - samples_out;
1157 else
1158 delay = 0;
1159 } else {
1160 /*
1161 * Phase 2:
1162 * During burst operation
1163 */
1164 time_delta = time_delta - dac33->mode7_us_to_lthr;
1165
1166 samples_out = US_TO_SAMPLES(
1167 substream->runtime->rate,
1168 time_delta);
1169 samples_in = US_TO_SAMPLES(
1170 dac33->burst_rate,
1171 time_delta);
1172 delay = MODE7_LTHR + samples_in - samples_out;
1173
1174 if (unlikely(delay > MODE7_UTHR))
1175 delay = MODE7_UTHR;
1176 }
1177 break;
1178 default:
1179 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1180 dac33->fifo_mode);
1181 break;
1182 }
1183out:
1184 return delay;
1185}
1186
c8bf93f0
PU		 1187static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1188 int clk_id, unsigned int freq, int dir)
1189{
1190 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1191 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1192 u8 ioc_reg, asrcb_reg;
1193
1194 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1195 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1196 switch (clk_id) {
1197 case TLV320DAC33_MCLK:
1198 ioc_reg |= DAC33_REFSEL;
1199 asrcb_reg |= DAC33_SRCREFSEL;
1200 break;
1201 case TLV320DAC33_SLEEPCLK:
1202 ioc_reg &= ~DAC33_REFSEL;
1203 asrcb_reg &= ~DAC33_SRCREFSEL;
1204 break;
1205 default:
1206 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1207 break;
1208 }
1209 dac33->refclk = freq;
1210
1211 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1212 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1213
1214 return 0;
1215}
1216
1217static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1218 unsigned int fmt)
1219{
1220 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1221 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1222 u8 aictrl_a, aictrl_b;
1223
1224 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1225 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1226 /* set master/slave audio interface */
1227 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1228 case SND_SOC_DAIFMT_CBM_CFM:
1229 /* Codec Master */
1230 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1231 break;
1232 case SND_SOC_DAIFMT_CBS_CFS:
1233 /* Codec Slave */
adcb8bc0
PU		 1234 if (dac33->fifo_mode) {
1235 dev_err(codec->dev, "FIFO mode requires master mode\n");
1236 return -EINVAL;
1237 } else
1238 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1239 break;
1240 default:
1241 return -EINVAL;
1242 }
1243
1244 aictrl_a &= ~DAC33_AFMT_MASK;
1245 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1246 case SND_SOC_DAIFMT_I2S:
1247 aictrl_a |= DAC33_AFMT_I2S;
1248 break;
1249 case SND_SOC_DAIFMT_DSP_A:
1250 aictrl_a |= DAC33_AFMT_DSP;
1251 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1252 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1253 break;
1254 case SND_SOC_DAIFMT_RIGHT_J:
1255 aictrl_a |= DAC33_AFMT_RIGHT_J;
1256 break;
1257 case SND_SOC_DAIFMT_LEFT_J:
1258 aictrl_a |= DAC33_AFMT_LEFT_J;
1259 break;
1260 default:
1261 dev_err(codec->dev, "Unsupported format (%u)\n",
1262 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1263 return -EINVAL;
1264 }
1265
1266 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1267 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1268
1269 return 0;
1270}
1271
1272static void dac33_init_chip(struct snd_soc_codec *codec)
1273{
1274 /* 44-46: DAC Control Registers */
1275 /* A : DAC sample rate Fsref/1.5 */
fdb6b1e1 1276 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
c8bf93f0
PU		 1277 /* B : DAC src=normal, not muted */
1278 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
1279 DAC33_DACSRCL_LEFT);
1280 /* C : (defaults) */
1281 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
1282
1283 /* 64-65 : L&R DAC power control
1284 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1285 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1286 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1287
1288 /* 73 : volume soft stepping control,
1289 clock source = internal osc (?) */
1290 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
1291
1292 /* 66 : LOP/LOM Modes */
1293 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
1294
1295 /* 68 : LOM inverted from LOP */
1296 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
1297
1298 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
1299}
1300
1301static int dac33_soc_probe(struct platform_device *pdev)
1302{
1303 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1304 struct snd_soc_codec *codec;
1305 struct tlv320dac33_priv *dac33;
1306 int ret = 0;
1307
1308 BUG_ON(!tlv320dac33_codec);
1309
1310 codec = tlv320dac33_codec;
1311 socdev->card->codec = codec;
b2c812e2 1312 dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1313
1314 /* Power up the codec */
1315 dac33_hard_power(codec, 1);
1316 /* Set default configuration */
1317 dac33_init_chip(codec);
1318
1319 /* register pcms */
1320 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1321 if (ret < 0) {
1322 dev_err(codec->dev, "failed to create pcms\n");
1323 goto pcm_err;
1324 }
1325
1326 snd_soc_add_controls(codec, dac33_snd_controls,
1327 ARRAY_SIZE(dac33_snd_controls));
1328 /* Only add the nSample controls, if we have valid IRQ number */
1329 if (dac33->irq >= 0)
1330 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1331 ARRAY_SIZE(dac33_nsample_snd_controls));
1332
1333 dac33_add_widgets(codec);
1334
1335 /* power on device */
1336 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1337
3a7aaed7
IK		 1338 /* Bias level configuration has enabled regulator an extra time */
1339 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1340
c8bf93f0 1341 return 0;
fe3e78e0 1342
c8bf93f0
PU		 1343pcm_err:
1344 dac33_hard_power(codec, 0);
1345 return ret;
1346}
1347
1348static int dac33_soc_remove(struct platform_device *pdev)
1349{
1350 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1351 struct snd_soc_codec *codec = socdev->card->codec;
1352
1353 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1354
1355 snd_soc_free_pcms(socdev);
1356 snd_soc_dapm_free(socdev);
1357
1358 return 0;
1359}
1360
1361static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1362{
1363 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1364 struct snd_soc_codec *codec = socdev->card->codec;
1365
1366 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1367
1368 return 0;
1369}
1370
1371static int dac33_soc_resume(struct platform_device *pdev)
1372{
1373 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1374 struct snd_soc_codec *codec = socdev->card->codec;
1375
1376 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1377 dac33_set_bias_level(codec, codec->suspend_bias_level);
1378
1379 return 0;
1380}
1381
1382struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1383 .probe = dac33_soc_probe,
1384 .remove = dac33_soc_remove,
1385 .suspend = dac33_soc_suspend,
1386 .resume = dac33_soc_resume,
1387};
1388EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1389
1390#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1391 SNDRV_PCM_RATE_48000)
1392#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1393
1394static struct snd_soc_dai_ops dac33_dai_ops = {
c8bf93f0
PU		 1395 .hw_params = dac33_hw_params,
1396 .prepare = dac33_pcm_prepare,
1397 .trigger = dac33_pcm_trigger,
f57d2cfa 1398 .delay = dac33_dai_delay,
c8bf93f0
PU		 1399 .set_sysclk = dac33_set_dai_sysclk,
1400 .set_fmt = dac33_set_dai_fmt,
1401};
1402
1403struct snd_soc_dai dac33_dai = {
1404 .name = "tlv320dac33",
1405 .playback = {
1406 .stream_name = "Playback",
1407 .channels_min = 2,
1408 .channels_max = 2,
1409 .rates = DAC33_RATES,
1410 .formats = DAC33_FORMATS,},
1411 .ops = &dac33_dai_ops,
1412};
1413EXPORT_SYMBOL_GPL(dac33_dai);
1414
735fe4cf
MB		 1415static int __devinit dac33_i2c_probe(struct i2c_client *client,
1416 const struct i2c_device_id *id)
c8bf93f0
PU		 1417{
1418 struct tlv320dac33_platform_data *pdata;
1419 struct tlv320dac33_priv *dac33;
1420 struct snd_soc_codec *codec;
3a7aaed7 1421 int ret, i;
c8bf93f0
PU		 1422
1423 if (client->dev.platform_data == NULL) {
1424 dev_err(&client->dev, "Platform data not set\n");
1425 return -ENODEV;
1426 }
1427 pdata = client->dev.platform_data;
1428
1429 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1430 if (dac33 == NULL)
1431 return -ENOMEM;
1432
1433 codec = &dac33->codec;
b2c812e2 1434 snd_soc_codec_set_drvdata(codec, dac33);
c8bf93f0
PU		 1435 codec->control_data = client;
1436
1437 mutex_init(&codec->mutex);
1438 mutex_init(&dac33->mutex);
f57d2cfa 1439 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1440 INIT_LIST_HEAD(&codec->dapm_widgets);
1441 INIT_LIST_HEAD(&codec->dapm_paths);
1442
1443 codec->name = "tlv320dac33";
1444 codec->owner = THIS_MODULE;
1445 codec->read = dac33_read_reg_cache;
1446 codec->write = dac33_write_locked;
1447 codec->hw_write = (hw_write_t) i2c_master_send;
1448 codec->bias_level = SND_SOC_BIAS_OFF;
1449 codec->set_bias_level = dac33_set_bias_level;
1450 codec->dai = &dac33_dai;
1451 codec->num_dai = 1;
1452 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1453 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1454 GFP_KERNEL);
1455 if (codec->reg_cache == NULL) {
1456 ret = -ENOMEM;
1457 goto error_reg;
1458 }
1459
1460 i2c_set_clientdata(client, dac33);
1461
1462 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1463 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
76f47127
PU		 1464 /* Pre calculate the burst rate */
1465 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
eeb309a8 1466 dac33->keep_bclk = pdata->keep_bclk;
c8bf93f0
PU		 1467 dac33->irq = client->irq;
1468 dac33->nsample = NSAMPLE_MAX;
55abb59c 1469 dac33->nsample_max = NSAMPLE_MAX;
c8bf93f0 1470 /* Disable FIFO use by default */
7427b4b9 1471 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1472
1473 tlv320dac33_codec = codec;
1474
1475 codec->dev = &client->dev;
1476 dac33_dai.dev = codec->dev;
1477
1478 /* Check if the reset GPIO number is valid and request it */
1479 if (dac33->power_gpio >= 0) {
1480 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1481 if (ret < 0) {
1482 dev_err(codec->dev,
1483 "Failed to request reset GPIO (%d)\n",
1484 dac33->power_gpio);
1485 snd_soc_unregister_dai(&dac33_dai);
1486 snd_soc_unregister_codec(codec);
1487 goto error_gpio;
1488 }
1489 gpio_direction_output(dac33->power_gpio, 0);
1490 } else {
1491 dac33->chip_power = 1;
1492 }
1493
1494 /* Check if the IRQ number is valid and request it */
1495 if (dac33->irq >= 0) {
1496 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1497 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1498 codec->name, codec);
1499 if (ret < 0) {
1500 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1501 dac33->irq, ret);
1502 dac33->irq = -1;
1503 }
1504 if (dac33->irq != -1) {
1505 /* Setup work queue */
74ea23aa
PU		 1506 dac33->dac33_wq =
1507 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1508 if (dac33->dac33_wq == NULL) {
1509 free_irq(dac33->irq, &dac33->codec);
1510 ret = -ENOMEM;
1511 goto error_wq;
1512 }
1513
1514 INIT_WORK(&dac33->work, dac33_work);
1515 }
1516 }
1517
3a7aaed7
IK		 1518 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1519 dac33->supplies[i].supply = dac33_supply_names[i];
1520
1521 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1522 dac33->supplies);
1523
1524 if (ret != 0) {
1525 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1526 goto err_get;
1527 }
1528
1529 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1530 dac33->supplies);
1531 if (ret != 0) {
1532 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1533 goto err_enable;
1534 }
1535
c8bf93f0
PU		 1536 ret = snd_soc_register_codec(codec);
1537 if (ret != 0) {
1538 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1539 goto error_codec;
1540 }
1541
1542 ret = snd_soc_register_dai(&dac33_dai);
1543 if (ret != 0) {
1544 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1545 snd_soc_unregister_codec(codec);
1546 goto error_codec;
1547 }
1548
1549 /* Shut down the codec for now */
1550 dac33_hard_power(codec, 0);
1551
1552 return ret;
1553
1554error_codec:
3a7aaed7
IK		 1555 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1556err_enable:
1557 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1558err_get:
c8bf93f0
PU		 1559 if (dac33->irq >= 0) {
1560 free_irq(dac33->irq, &dac33->codec);
1561 destroy_workqueue(dac33->dac33_wq);
1562 }
1563error_wq:
1564 if (dac33->power_gpio >= 0)
1565 gpio_free(dac33->power_gpio);
1566error_gpio:
1567 kfree(codec->reg_cache);
1568error_reg:
1569 tlv320dac33_codec = NULL;
1570 kfree(dac33);
1571
1572 return ret;
1573}
1574
735fe4cf 1575static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1576{
1577 struct tlv320dac33_priv *dac33;
1578
1579 dac33 = i2c_get_clientdata(client);
1580 dac33_hard_power(&dac33->codec, 0);
1581
1582 if (dac33->power_gpio >= 0)
1583 gpio_free(dac33->power_gpio);
1584 if (dac33->irq >= 0)
1585 free_irq(dac33->irq, &dac33->codec);
1586
cf134d5b 1587 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
3a7aaed7
IK		 1588 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1589
c8bf93f0
PU		 1590 destroy_workqueue(dac33->dac33_wq);
1591 snd_soc_unregister_dai(&dac33_dai);
1592 snd_soc_unregister_codec(&dac33->codec);
1593 kfree(dac33->codec.reg_cache);
1594 kfree(dac33);
1595 tlv320dac33_codec = NULL;
1596
1597 return 0;
1598}
1599
1600static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1601 {
1602 .name = "tlv320dac33",
1603 .driver_data = 0,
1604 },
1605 { },
1606};
1607
1608static struct i2c_driver tlv320dac33_i2c_driver = {
1609 .driver = {
1610 .name = "tlv320dac33",
1611 .owner = THIS_MODULE,
1612 },
1613 .probe = dac33_i2c_probe,
1614 .remove = __devexit_p(dac33_i2c_remove),
1615 .id_table = tlv320dac33_i2c_id,
1616};
1617
1618static int __init dac33_module_init(void)
1619{
1620 int r;
1621 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1622 if (r < 0) {
1623 printk(KERN_ERR "DAC33: driver registration failed\n");
1624 return r;
1625 }
1626 return 0;
1627}
1628module_init(dac33_module_init);
1629
1630static void __exit dac33_module_exit(void)
1631{
1632 i2c_del_driver(&tlv320dac33_i2c_driver);
1633}
1634module_exit(dac33_module_exit);
1635
1636
1637MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1638MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1639MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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