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ASoC: tlv320dac33: Revised module loading, and DAC33 ID read
[deliverable/linux.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
4260393e
PU		 53#define MODE7_LTHR 10
54#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55
76f47127
PU		 56#define BURST_BASEFREQ_HZ 49152000
57
f57d2cfa
PU		 58#define SAMPLES_TO_US(rate, samples) \
59 (1000000000 / ((rate * 1000) / samples))
60
61#define US_TO_SAMPLES(rate, us) \
62 (rate / (1000000 / us))
63
64
c8bf93f0
PU		 65static struct snd_soc_codec *tlv320dac33_codec;
66
67enum dac33_state {
68 DAC33_IDLE = 0,
69 DAC33_PREFILL,
70 DAC33_PLAYBACK,
71 DAC33_FLUSH,
72};
73
7427b4b9
PU		 74enum dac33_fifo_modes {
75 DAC33_FIFO_BYPASS = 0,
76 DAC33_FIFO_MODE1,
28e05d98 77 DAC33_FIFO_MODE7,
7427b4b9
PU		 78 DAC33_FIFO_LAST_MODE,
79};
80
3a7aaed7
IK		 81#define DAC33_NUM_SUPPLIES 3
82static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
83 "AVDD",
84 "DVDD",
85 "IOVDD",
86};
87
c8bf93f0
PU		 88struct tlv320dac33_priv {
89 struct mutex mutex;
90 struct workqueue_struct *dac33_wq;
91 struct work_struct work;
92 struct snd_soc_codec codec;
3a7aaed7 93 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
c8bf93f0
PU		 94 int power_gpio;
95 int chip_power;
96 int irq;
97 unsigned int refclk;
98
99 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
100 unsigned int nsample_min; /* nsample should not be lower than
101 * this */
102 unsigned int nsample_max; /* nsample should not be higher than
103 * this */
7427b4b9 104 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 105 unsigned int nsample; /* burst read amount from host */
6aceabb4 106 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 107 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 108
eeb309a8
PU		 109 int keep_bclk; /* Keep the BCLK continuously running
110 * in FIFO modes */
f57d2cfa
PU		 111 spinlock_t lock;
112 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
113 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
114
115 unsigned int mode1_us_burst; /* Time to burst read n number of
116 * samples */
117 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
118
c8bf93f0
PU		 119 enum dac33_state state;
120};
121
122static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1230x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1240x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1250x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1260x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1270x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1280x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1290x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1300x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1310x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1320x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1330x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1340x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1350x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1360x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1370x00, 0x00, /* 0x38 - 0x39 */
138/* Registers 0x3a - 0x3f are reserved */
139 0x00, 0x00, /* 0x3a - 0x3b */
1400x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
141
1420x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1430x00, 0x80, /* 0x44 - 0x45 */
144/* Registers 0x46 - 0x47 are reserved */
145 0x80, 0x80, /* 0x46 - 0x47 */
146
1470x80, 0x00, 0x00, /* 0x48 - 0x4a */
148/* Registers 0x4b - 0x7c are reserved */
149 0x00, /* 0x4b */
1500x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1510x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1520x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1530x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1540x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1550x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1560x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1570x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1580x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1590x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1600x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1610x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1620x00, /* 0x7c */
163
164 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
165};
166
167/* Register read and write */
168static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
169 unsigned reg)
170{
171 u8 *cache = codec->reg_cache;
172 if (reg >= DAC33_CACHEREGNUM)
173 return 0;
174
175 return cache[reg];
176}
177
178static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
179 u8 reg, u8 value)
180{
181 u8 *cache = codec->reg_cache;
182 if (reg >= DAC33_CACHEREGNUM)
183 return;
184
185 cache[reg] = value;
186}
187
188static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
189 u8 *value)
190{
b2c812e2 191 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 192 int val;
193
194 *value = reg & 0xff;
195
196 /* If powered off, return the cached value */
197 if (dac33->chip_power) {
198 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
199 if (val < 0) {
200 dev_err(codec->dev, "Read failed (%d)\n", val);
201 value[0] = dac33_read_reg_cache(codec, reg);
202 } else {
203 value[0] = val;
204 dac33_write_reg_cache(codec, reg, val);
205 }
206 } else {
207 value[0] = dac33_read_reg_cache(codec, reg);
208 }
209
210 return 0;
211}
212
213static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
214 unsigned int value)
215{
b2c812e2 216 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 217 u8 data[2];
218 int ret = 0;
219
220 /*
221 * data is
222 * D15..D8 dac33 register offset
223 * D7...D0 register data
224 */
225 data[0] = reg & 0xff;
226 data[1] = value & 0xff;
227
228 dac33_write_reg_cache(codec, data[0], data[1]);
229 if (dac33->chip_power) {
230 ret = codec->hw_write(codec->control_data, data, 2);
231 if (ret != 2)
232 dev_err(codec->dev, "Write failed (%d)\n", ret);
233 else
234 ret = 0;
235 }
236
237 return ret;
238}
239
240static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
241 unsigned int value)
242{
b2c812e2 243 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 244 int ret;
245
246 mutex_lock(&dac33->mutex);
247 ret = dac33_write(codec, reg, value);
248 mutex_unlock(&dac33->mutex);
249
250 return ret;
251}
252
253#define DAC33_I2C_ADDR_AUTOINC 0x80
254static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
255 unsigned int value)
256{
b2c812e2 257 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 258 u8 data[3];
259 int ret = 0;
260
261 /*
262 * data is
263 * D23..D16 dac33 register offset
264 * D15..D8 register data MSB
265 * D7...D0 register data LSB
266 */
267 data[0] = reg & 0xff;
268 data[1] = (value >> 8) & 0xff;
269 data[2] = value & 0xff;
270
271 dac33_write_reg_cache(codec, data[0], data[1]);
272 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
273
274 if (dac33->chip_power) {
275 /* We need to set autoincrement mode for 16 bit writes */
276 data[0] |= DAC33_I2C_ADDR_AUTOINC;
277 ret = codec->hw_write(codec->control_data, data, 3);
278 if (ret != 3)
279 dev_err(codec->dev, "Write failed (%d)\n", ret);
280 else
281 ret = 0;
282 }
283
284 return ret;
285}
286
ef909d67 287static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 288{
b2c812e2 289 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 290
ef909d67 291 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 292 return;
293
ef909d67
PU		 294 /* 44-46: DAC Control Registers */
295 /* A : DAC sample rate Fsref/1.5 */
296 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
297 /* B : DAC src=normal, not muted */
298 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
299 DAC33_DACSRCL_LEFT);
300 /* C : (defaults) */
301 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
302
303 /* 64-65 : L&R DAC power control
304 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
305 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
306 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
307
308 /* 73 : volume soft stepping control,
309 clock source = internal osc (?) */
310 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
311
312 /* 66 : LOP/LOM Modes */
313 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
314
315 /* 68 : LOM inverted from LOP */
316 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
317
318 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
319
320 /* Restore only selected registers (gains mostly) */
321 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
322 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
323 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
324 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
325
326 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
327 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
328 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
329 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
c8bf93f0
PU		 330}
331
239fe55c
PU		 332static inline void dac33_read_id(struct snd_soc_codec *codec)
333{
334 u8 reg;
335
336 dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
337 dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
338 dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
339}
340
c8bf93f0
PU		 341static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
342{
343 u8 reg;
344
345 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
346 if (power)
347 reg |= DAC33_PDNALLB;
348 else
c3746a07
PU		 349 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
350 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 351 dac33_write(codec, DAC33_PWR_CTRL, reg);
352}
353
3a7aaed7 354static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 355{
b2c812e2 356 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7 357 int ret;
c8bf93f0
PU		 358
359 mutex_lock(&dac33->mutex);
360 if (power) {
3a7aaed7
IK		 361 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
362 dac33->supplies);
363 if (ret != 0) {
364 dev_err(codec->dev,
365 "Failed to enable supplies: %d\n", ret);
366 goto exit;
c8bf93f0 367 }
3a7aaed7
IK		 368
369 if (dac33->power_gpio >= 0)
370 gpio_set_value(dac33->power_gpio, 1);
371
372 dac33->chip_power = 1;
373
ef909d67 374 dac33_init_chip(codec);
3a7aaed7 375
c8bf93f0
PU		 376 dac33_soft_power(codec, 1);
377 } else {
378 dac33_soft_power(codec, 0);
3a7aaed7 379 if (dac33->power_gpio >= 0)
c8bf93f0 380 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 381
382 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
383 dac33->supplies);
384 if (ret != 0) {
385 dev_err(codec->dev,
386 "Failed to disable supplies: %d\n", ret);
387 goto exit;
c8bf93f0 388 }
3a7aaed7
IK		 389
390 dac33->chip_power = 0;
c8bf93f0 391 }
c8bf93f0 392
3a7aaed7
IK		 393exit:
394 mutex_unlock(&dac33->mutex);
395 return ret;
c8bf93f0
PU		 396}
397
398static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
399 struct snd_ctl_elem_value *ucontrol)
400{
401 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 402 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 403
404 ucontrol->value.integer.value[0] = dac33->nsample;
405
406 return 0;
407}
408
409static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol)
411{
412 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 413 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 414 int ret = 0;
415
416 if (dac33->nsample == ucontrol->value.integer.value[0])
417 return 0;
418
419 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
f57d2cfa 420 ucontrol->value.integer.value[0] > dac33->nsample_max) {
c8bf93f0 421 ret = -EINVAL;
f57d2cfa 422 } else {
c8bf93f0 423 dac33->nsample = ucontrol->value.integer.value[0];
f57d2cfa
PU		 424 /* Re calculate the burst time */
425 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
426 dac33->nsample);
427 }
c8bf93f0
PU		 428
429 return ret;
430}
431
7427b4b9 432static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 433 struct snd_ctl_elem_value *ucontrol)
434{
435 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 436 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 437
7427b4b9 438 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 439
440 return 0;
441}
442
7427b4b9 443static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 444 struct snd_ctl_elem_value *ucontrol)
445{
446 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 447 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 448 int ret = 0;
449
7427b4b9 450 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 451 return 0;
452 /* Do not allow changes while stream is running*/
453 if (codec->active)
454 return -EPERM;
455
456 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 457 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 458 ret = -EINVAL;
459 else
7427b4b9 460 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 461
462 return ret;
463}
464
7427b4b9
PU		 465/* Codec operation modes */
466static const char *dac33_fifo_mode_texts[] = {
28e05d98 467 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 468};
469
470static const struct soc_enum dac33_fifo_mode_enum =
471 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
472 dac33_fifo_mode_texts);
473
c8bf93f0
PU		 474/*
475 * DACL/R digital volume control:
476 * from 0 dB to -63.5 in 0.5 dB steps
477 * Need to be inverted later on:
478 * 0x00 == 0 dB
479 * 0x7f == -63.5 dB
480 */
481static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
482
483static const struct snd_kcontrol_new dac33_snd_controls[] = {
484 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
485 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
486 0, 0x7f, 1, dac_digivol_tlv),
487 SOC_DOUBLE_R("DAC Digital Playback Switch",
488 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
489 SOC_DOUBLE_R("Line to Line Out Volume",
490 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
491};
492
493static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
494 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
495 dac33_get_nsample, dac33_set_nsample),
7427b4b9
PU		 496 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
497 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 498};
499
500/* Analog bypass */
501static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
502 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
503
504static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
505 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
506
507static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
508 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
509 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
510
511 SND_SOC_DAPM_INPUT("LINEL"),
512 SND_SOC_DAPM_INPUT("LINER"),
513
514 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
515 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
516
517 /* Analog bypass */
518 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
519 &dac33_dapm_abypassl_control),
520 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
521 &dac33_dapm_abypassr_control),
522
523 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
524 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
525 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
526 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
527};
528
529static const struct snd_soc_dapm_route audio_map[] = {
530 /* Analog bypass */
531 {"Analog Left Bypass", "Switch", "LINEL"},
532 {"Analog Right Bypass", "Switch", "LINER"},
533
534 {"Output Left Amp Power", NULL, "DACL"},
535 {"Output Right Amp Power", NULL, "DACR"},
536
537 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
538 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
539
540 /* output */
541 {"LEFT_LO", NULL, "Output Left Amp Power"},
542 {"RIGHT_LO", NULL, "Output Right Amp Power"},
543};
544
545static int dac33_add_widgets(struct snd_soc_codec *codec)
546{
547 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
548 ARRAY_SIZE(dac33_dapm_widgets));
549
550 /* set up audio path interconnects */
551 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 552
553 return 0;
554}
555
556static int dac33_set_bias_level(struct snd_soc_codec *codec,
557 enum snd_soc_bias_level level)
558{
3a7aaed7
IK		 559 int ret;
560
c8bf93f0
PU		 561 switch (level) {
562 case SND_SOC_BIAS_ON:
563 dac33_soft_power(codec, 1);
564 break;
565 case SND_SOC_BIAS_PREPARE:
566 break;
567 case SND_SOC_BIAS_STANDBY:
3a7aaed7
IK		 568 if (codec->bias_level == SND_SOC_BIAS_OFF) {
569 ret = dac33_hard_power(codec, 1);
570 if (ret != 0)
571 return ret;
572 }
573
c8bf93f0
PU		 574 dac33_soft_power(codec, 0);
575 break;
576 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 577 ret = dac33_hard_power(codec, 0);
578 if (ret != 0)
579 return ret;
580
c8bf93f0
PU		 581 break;
582 }
583 codec->bias_level = level;
584
585 return 0;
586}
587
d4f102d4
PU		 588static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
589{
590 struct snd_soc_codec *codec;
591
592 codec = &dac33->codec;
593
594 switch (dac33->fifo_mode) {
595 case DAC33_FIFO_MODE1:
596 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f4d59328 597 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
f57d2cfa
PU		 598
599 /* Take the timestamps */
600 spin_lock_irq(&dac33->lock);
601 dac33->t_stamp2 = ktime_to_us(ktime_get());
602 dac33->t_stamp1 = dac33->t_stamp2;
603 spin_unlock_irq(&dac33->lock);
604
d4f102d4
PU		 605 dac33_write16(codec, DAC33_PREFILL_MSB,
606 DAC33_THRREG(dac33->alarm_threshold));
f4d59328
PU		 607 /* Enable Alarm Threshold IRQ with a delay */
608 udelay(SAMPLES_TO_US(dac33->burst_rate,
609 dac33->alarm_threshold));
610 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 611 break;
28e05d98 612 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 613 /* Take the timestamp */
614 spin_lock_irq(&dac33->lock);
615 dac33->t_stamp1 = ktime_to_us(ktime_get());
616 /* Move back the timestamp with drain time */
617 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
618 spin_unlock_irq(&dac33->lock);
619
28e05d98 620 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 621 DAC33_THRREG(MODE7_LTHR));
f57d2cfa
PU		 622
623 /* Enable Upper Threshold IRQ */
624 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 625 break;
d4f102d4
PU		 626 default:
627 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
628 dac33->fifo_mode);
629 break;
630 }
631}
632
633static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
634{
635 struct snd_soc_codec *codec;
636
637 codec = &dac33->codec;
638
639 switch (dac33->fifo_mode) {
640 case DAC33_FIFO_MODE1:
f57d2cfa
PU		 641 /* Take the timestamp */
642 spin_lock_irq(&dac33->lock);
643 dac33->t_stamp2 = ktime_to_us(ktime_get());
644 spin_unlock_irq(&dac33->lock);
645
d4f102d4
PU		 646 dac33_write16(codec, DAC33_NSAMPLE_MSB,
647 DAC33_THRREG(dac33->nsample));
648 break;
28e05d98
PU		 649 case DAC33_FIFO_MODE7:
650 /* At the moment we are not using interrupts in mode7 */
651 break;
d4f102d4
PU		 652 default:
653 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
654 dac33->fifo_mode);
655 break;
656 }
657}
658
c8bf93f0
PU		 659static void dac33_work(struct work_struct *work)
660{
661 struct snd_soc_codec *codec;
662 struct tlv320dac33_priv *dac33;
663 u8 reg;
664
665 dac33 = container_of(work, struct tlv320dac33_priv, work);
666 codec = &dac33->codec;
667
668 mutex_lock(&dac33->mutex);
669 switch (dac33->state) {
670 case DAC33_PREFILL:
671 dac33->state = DAC33_PLAYBACK;
d4f102d4 672 dac33_prefill_handler(dac33);
c8bf93f0
PU		 673 break;
674 case DAC33_PLAYBACK:
d4f102d4 675 dac33_playback_handler(dac33);
c8bf93f0
PU		 676 break;
677 case DAC33_IDLE:
678 break;
679 case DAC33_FLUSH:
680 dac33->state = DAC33_IDLE;
681 /* Mask all interrupts from dac33 */
682 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
683
684 /* flush fifo */
685 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
686 reg |= DAC33_FIFOFLUSH;
687 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
688 break;
689 }
690 mutex_unlock(&dac33->mutex);
691}
692
693static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
694{
695 struct snd_soc_codec *codec = dev;
b2c812e2 696 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 697
f57d2cfa
PU		 698 spin_lock(&dac33->lock);
699 dac33->t_stamp1 = ktime_to_us(ktime_get());
700 spin_unlock(&dac33->lock);
701
702 /* Do not schedule the workqueue in Mode7 */
703 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
704 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0
PU		 705
706 return IRQ_HANDLED;
707}
708
c8bf93f0
PU		 709static void dac33_oscwait(struct snd_soc_codec *codec)
710{
711 int timeout = 20;
712 u8 reg;
713
714 do {
715 msleep(1);
716 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
717 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
718 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
719 dev_err(codec->dev,
720 "internal oscillator calibration failed\n");
721}
722
723static int dac33_hw_params(struct snd_pcm_substream *substream,
724 struct snd_pcm_hw_params *params,
725 struct snd_soc_dai *dai)
726{
727 struct snd_soc_pcm_runtime *rtd = substream->private_data;
728 struct snd_soc_device *socdev = rtd->socdev;
729 struct snd_soc_codec *codec = socdev->card->codec;
730
731 /* Check parameters for validity */
732 switch (params_rate(params)) {
733 case 44100:
734 case 48000:
735 break;
736 default:
737 dev_err(codec->dev, "unsupported rate %d\n",
738 params_rate(params));
739 return -EINVAL;
740 }
741
742 switch (params_format(params)) {
743 case SNDRV_PCM_FORMAT_S16_LE:
744 break;
745 default:
746 dev_err(codec->dev, "unsupported format %d\n",
747 params_format(params));
748 return -EINVAL;
749 }
750
751 return 0;
752}
753
754#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 755 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 756#define CALC_RATIOSET(rate, refclk) ( \
757 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
758
759/*
760 * tlv320dac33 is strict on the sequence of the register writes, if the register
761 * writes happens in different order, than dac33 might end up in unknown state.
762 * Use the known, working sequence of register writes to initialize the dac33.
763 */
764static int dac33_prepare_chip(struct snd_pcm_substream *substream)
765{
766 struct snd_soc_pcm_runtime *rtd = substream->private_data;
767 struct snd_soc_device *socdev = rtd->socdev;
768 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 769 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 770 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 771 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 772
773 switch (substream->runtime->rate) {
774 case 44100:
775 case 48000:
776 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
777 ratioset = CALC_RATIOSET(substream->runtime->rate,
778 dac33->refclk);
779 break;
780 default:
781 dev_err(codec->dev, "unsupported rate %d\n",
782 substream->runtime->rate);
783 return -EINVAL;
784 }
785
786
787 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
788 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 789 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 790 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 791 fifoctrl_a &= ~DAC33_FIFOFLUSH;
792
c8bf93f0
PU		 793 fifoctrl_a &= ~DAC33_WIDTH;
794 switch (substream->runtime->format) {
795 case SNDRV_PCM_FORMAT_S16_LE:
796 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
797 fifoctrl_a |= DAC33_WIDTH;
798 break;
799 default:
800 dev_err(codec->dev, "unsupported format %d\n",
801 substream->runtime->format);
802 return -EINVAL;
803 }
804
805 mutex_lock(&dac33->mutex);
c3746a07 806 dac33_soft_power(codec, 0);
c8bf93f0
PU		 807 dac33_soft_power(codec, 1);
808
809 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
810 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
811
812 /* Write registers 0x08 and 0x09 (MSB, LSB) */
813 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
814
815 /* calib time: 128 is a nice number ;) */
816 dac33_write(codec, DAC33_CALIB_TIME, 128);
817
818 /* adjustment treshold & step */
819 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
820 DAC33_ADJSTEP(1));
821
822 /* div=4 / gain=1 / div */
823 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
824
825 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
826 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
827 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
828
829 dac33_oscwait(codec);
830
7427b4b9 831 if (dac33->fifo_mode) {
aec242dc 832 /* Generic for all FIFO modes */
c8bf93f0 833 /* 50-51 : ASRC Control registers */
fdb6b1e1 834 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 835 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
836
837 /* Write registers 0x34 and 0x35 (MSB, LSB) */
838 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
839
840 /* Set interrupts to high active */
841 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 842 } else {
aec242dc 843 /* FIFO bypass mode */
c8bf93f0
PU		 844 /* 50-51 : ASRC Control registers */
845 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
846 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
847 }
848
aec242dc
PU		 849 /* Interrupt behaviour configuration */
850 switch (dac33->fifo_mode) {
851 case DAC33_FIFO_MODE1:
852 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
853 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 854 break;
28e05d98 855 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 856 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
857 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 858 break;
aec242dc
PU		 859 default:
860 /* in FIFO bypass mode, the interrupts are not used */
861 break;
862 }
863
864 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
865
866 switch (dac33->fifo_mode) {
867 case DAC33_FIFO_MODE1:
868 /*
869 * For mode1:
870 * Disable the FIFO bypass (Enable the use of FIFO)
871 * Select nSample mode
872 * BCLK is only running when data is needed by DAC33
873 */
c8bf93f0 874 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 875 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 876 if (dac33->keep_bclk)
877 aictrl_b |= DAC33_BCLKON;
878 else
879 aictrl_b &= ~DAC33_BCLKON;
aec242dc 880 break;
28e05d98
PU		 881 case DAC33_FIFO_MODE7:
882 /*
883 * For mode1:
884 * Disable the FIFO bypass (Enable the use of FIFO)
885 * Select Threshold mode
886 * BCLK is only running when data is needed by DAC33
887 */
888 fifoctrl_a &= ~DAC33_FBYPAS;
889 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 890 if (dac33->keep_bclk)
891 aictrl_b |= DAC33_BCLKON;
892 else
893 aictrl_b &= ~DAC33_BCLKON;
28e05d98 894 break;
aec242dc
PU		 895 default:
896 /*
897 * For FIFO bypass mode:
898 * Enable the FIFO bypass (Disable the FIFO use)
899 * Set the BCLK as continous
900 */
c8bf93f0 901 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 902 aictrl_b |= DAC33_BCLKON;
903 break;
904 }
c8bf93f0 905
aec242dc 906 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 907 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 908 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 909
6aceabb4
PU		 910 /*
911 * BCLK divide ratio
912 * 0: 1.5
913 * 1: 1
914 * 2: 2
915 * ...
916 * 254: 254
917 * 255: 255
918 */
6cd6cede 919 if (dac33->fifo_mode)
6aceabb4
PU		 920 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
921 dac33->burst_bclkdiv);
6cd6cede
PU		 922 else
923 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 924
6cd6cede
PU		 925 switch (dac33->fifo_mode) {
926 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 927 dac33_write16(codec, DAC33_ATHR_MSB,
928 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 929 break;
28e05d98
PU		 930 case DAC33_FIFO_MODE7:
931 /*
932 * Configure the threshold levels, and leave 10 sample space
933 * at the bottom, and also at the top of the FIFO
934 */
4260393e
PU		 935 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
936 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 937 break;
aec242dc 938 default:
aec242dc 939 break;
c8bf93f0
PU		 940 }
941
942 mutex_unlock(&dac33->mutex);
943
944 return 0;
945}
946
947static void dac33_calculate_times(struct snd_pcm_substream *substream)
948{
949 struct snd_soc_pcm_runtime *rtd = substream->private_data;
950 struct snd_soc_device *socdev = rtd->socdev;
951 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 952 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 953 unsigned int nsample_limit;
954
55abb59c
PU		 955 /* In bypass mode we don't need to calculate */
956 if (!dac33->fifo_mode)
957 return;
958
c8bf93f0
PU		 959 /* Number of samples (16bit, stereo) in one period */
960 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
961
962 /* Number of samples (16bit, stereo) in ALSA buffer */
963 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
964 /* Subtract one period from the total */
965 dac33->nsample_max -= dac33->nsample_min;
966
967 /* Number of samples for LATENCY_TIME_MS / 2 */
968 dac33->alarm_threshold = substream->runtime->rate /
969 (1000 / (LATENCY_TIME_MS / 2));
970
971 /* Find and fix up the lowest nsmaple limit */
972 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
973
974 if (dac33->nsample_min < nsample_limit)
975 dac33->nsample_min = nsample_limit;
976
977 if (dac33->nsample < dac33->nsample_min)
978 dac33->nsample = dac33->nsample_min;
979
980 /*
981 * Find and fix up the highest nsmaple limit
982 * In order to not overflow the DAC33 buffer substract the
983 * alarm_threshold value from the size of the DAC33 buffer
984 */
985 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
986
987 if (dac33->nsample_max > nsample_limit)
988 dac33->nsample_max = nsample_limit;
989
990 if (dac33->nsample > dac33->nsample_max)
991 dac33->nsample = dac33->nsample_max;
f57d2cfa
PU		 992
993 switch (dac33->fifo_mode) {
994 case DAC33_FIFO_MODE1:
995 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
996 dac33->nsample);
997 dac33->t_stamp1 = 0;
998 dac33->t_stamp2 = 0;
999 break;
1000 case DAC33_FIFO_MODE7:
1001 dac33->mode7_us_to_lthr =
1002 SAMPLES_TO_US(substream->runtime->rate,
1003 MODE7_UTHR - MODE7_LTHR + 1);
1004 dac33->t_stamp1 = 0;
1005 break;
1006 default:
1007 break;
1008 }
1009
c8bf93f0
PU		 1010}
1011
1012static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
1013 struct snd_soc_dai *dai)
1014{
1015 dac33_calculate_times(substream);
1016 dac33_prepare_chip(substream);
1017
1018 return 0;
1019}
1020
1021static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1022 struct snd_soc_dai *dai)
1023{
1024 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1025 struct snd_soc_device *socdev = rtd->socdev;
1026 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1027 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1028 int ret = 0;
1029
1030 switch (cmd) {
1031 case SNDRV_PCM_TRIGGER_START:
1032 case SNDRV_PCM_TRIGGER_RESUME:
1033 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1034 if (dac33->fifo_mode) {
c8bf93f0
PU		 1035 dac33->state = DAC33_PREFILL;
1036 queue_work(dac33->dac33_wq, &dac33->work);
1037 }
1038 break;
1039 case SNDRV_PCM_TRIGGER_STOP:
1040 case SNDRV_PCM_TRIGGER_SUSPEND:
1041 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1042 if (dac33->fifo_mode) {
c8bf93f0
PU		 1043 dac33->state = DAC33_FLUSH;
1044 queue_work(dac33->dac33_wq, &dac33->work);
1045 }
1046 break;
1047 default:
1048 ret = -EINVAL;
1049 }
1050
1051 return ret;
1052}
1053
f57d2cfa
PU		 1054static snd_pcm_sframes_t dac33_dai_delay(
1055 struct snd_pcm_substream *substream,
1056 struct snd_soc_dai *dai)
1057{
1058 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1059 struct snd_soc_device *socdev = rtd->socdev;
1060 struct snd_soc_codec *codec = socdev->card->codec;
1061 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1062 unsigned long long t0, t1, t_now;
1063 unsigned int time_delta;
1064 int samples_out, samples_in, samples;
1065 snd_pcm_sframes_t delay = 0;
1066
1067 switch (dac33->fifo_mode) {
1068 case DAC33_FIFO_BYPASS:
1069 break;
1070 case DAC33_FIFO_MODE1:
1071 spin_lock(&dac33->lock);
1072 t0 = dac33->t_stamp1;
1073 t1 = dac33->t_stamp2;
1074 spin_unlock(&dac33->lock);
1075 t_now = ktime_to_us(ktime_get());
1076
1077 /* We have not started to fill the FIFO yet, delay is 0 */
1078 if (!t1)
1079 goto out;
1080
1081 if (t0 > t1) {
1082 /*
1083 * Phase 1:
1084 * After Alarm threshold, and before nSample write
1085 */
1086 time_delta = t_now - t0;
1087 samples_out = time_delta ? US_TO_SAMPLES(
1088 substream->runtime->rate,
1089 time_delta) : 0;
1090
1091 if (likely(dac33->alarm_threshold > samples_out))
1092 delay = dac33->alarm_threshold - samples_out;
1093 else
1094 delay = 0;
1095 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1096 /*
1097 * Phase 2:
1098 * After nSample write (during burst operation)
1099 */
1100 time_delta = t_now - t0;
1101 samples_out = time_delta ? US_TO_SAMPLES(
1102 substream->runtime->rate,
1103 time_delta) : 0;
1104
1105 time_delta = t_now - t1;
1106 samples_in = time_delta ? US_TO_SAMPLES(
1107 dac33->burst_rate,
1108 time_delta) : 0;
1109
1110 samples = dac33->alarm_threshold;
1111 samples += (samples_in - samples_out);
1112
1113 if (likely(samples > 0))
1114 delay = samples;
1115 else
1116 delay = 0;
1117 } else {
1118 /*
1119 * Phase 3:
1120 * After burst operation, before next alarm threshold
1121 */
1122 time_delta = t_now - t0;
1123 samples_out = time_delta ? US_TO_SAMPLES(
1124 substream->runtime->rate,
1125 time_delta) : 0;
1126
1127 samples_in = dac33->nsample;
1128 samples = dac33->alarm_threshold;
1129 samples += (samples_in - samples_out);
1130
1131 if (likely(samples > 0))
1132 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1133 DAC33_BUFFER_SIZE_SAMPLES : samples;
1134 else
1135 delay = 0;
1136 }
1137 break;
1138 case DAC33_FIFO_MODE7:
1139 spin_lock(&dac33->lock);
1140 t0 = dac33->t_stamp1;
1141 spin_unlock(&dac33->lock);
1142 t_now = ktime_to_us(ktime_get());
1143
1144 /* We have not started to fill the FIFO yet, delay is 0 */
1145 if (!t0)
1146 goto out;
1147
1148 if (t_now <= t0) {
1149 /*
1150 * Either the timestamps are messed or equal. Report
1151 * maximum delay
1152 */
1153 delay = MODE7_UTHR;
1154 goto out;
1155 }
1156
1157 time_delta = t_now - t0;
1158 if (time_delta <= dac33->mode7_us_to_lthr) {
1159 /*
1160 * Phase 1:
1161 * After burst (draining phase)
1162 */
1163 samples_out = US_TO_SAMPLES(
1164 substream->runtime->rate,
1165 time_delta);
1166
1167 if (likely(MODE7_UTHR > samples_out))
1168 delay = MODE7_UTHR - samples_out;
1169 else
1170 delay = 0;
1171 } else {
1172 /*
1173 * Phase 2:
1174 * During burst operation
1175 */
1176 time_delta = time_delta - dac33->mode7_us_to_lthr;
1177
1178 samples_out = US_TO_SAMPLES(
1179 substream->runtime->rate,
1180 time_delta);
1181 samples_in = US_TO_SAMPLES(
1182 dac33->burst_rate,
1183 time_delta);
1184 delay = MODE7_LTHR + samples_in - samples_out;
1185
1186 if (unlikely(delay > MODE7_UTHR))
1187 delay = MODE7_UTHR;
1188 }
1189 break;
1190 default:
1191 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1192 dac33->fifo_mode);
1193 break;
1194 }
1195out:
1196 return delay;
1197}
1198
c8bf93f0
PU		 1199static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1200 int clk_id, unsigned int freq, int dir)
1201{
1202 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1203 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1204 u8 ioc_reg, asrcb_reg;
1205
1206 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1207 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1208 switch (clk_id) {
1209 case TLV320DAC33_MCLK:
1210 ioc_reg |= DAC33_REFSEL;
1211 asrcb_reg |= DAC33_SRCREFSEL;
1212 break;
1213 case TLV320DAC33_SLEEPCLK:
1214 ioc_reg &= ~DAC33_REFSEL;
1215 asrcb_reg &= ~DAC33_SRCREFSEL;
1216 break;
1217 default:
1218 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1219 break;
1220 }
1221 dac33->refclk = freq;
1222
1223 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1224 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1225
1226 return 0;
1227}
1228
1229static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1230 unsigned int fmt)
1231{
1232 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1233 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1234 u8 aictrl_a, aictrl_b;
1235
1236 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1237 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1238 /* set master/slave audio interface */
1239 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1240 case SND_SOC_DAIFMT_CBM_CFM:
1241 /* Codec Master */
1242 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1243 break;
1244 case SND_SOC_DAIFMT_CBS_CFS:
1245 /* Codec Slave */
adcb8bc0
PU		 1246 if (dac33->fifo_mode) {
1247 dev_err(codec->dev, "FIFO mode requires master mode\n");
1248 return -EINVAL;
1249 } else
1250 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1251 break;
1252 default:
1253 return -EINVAL;
1254 }
1255
1256 aictrl_a &= ~DAC33_AFMT_MASK;
1257 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1258 case SND_SOC_DAIFMT_I2S:
1259 aictrl_a |= DAC33_AFMT_I2S;
1260 break;
1261 case SND_SOC_DAIFMT_DSP_A:
1262 aictrl_a |= DAC33_AFMT_DSP;
1263 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1264 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1265 break;
1266 case SND_SOC_DAIFMT_RIGHT_J:
1267 aictrl_a |= DAC33_AFMT_RIGHT_J;
1268 break;
1269 case SND_SOC_DAIFMT_LEFT_J:
1270 aictrl_a |= DAC33_AFMT_LEFT_J;
1271 break;
1272 default:
1273 dev_err(codec->dev, "Unsupported format (%u)\n",
1274 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1275 return -EINVAL;
1276 }
1277
1278 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1279 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1280
1281 return 0;
1282}
1283
c8bf93f0
PU		 1284static int dac33_soc_probe(struct platform_device *pdev)
1285{
1286 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1287 struct snd_soc_codec *codec;
1288 struct tlv320dac33_priv *dac33;
1289 int ret = 0;
1290
1291 BUG_ON(!tlv320dac33_codec);
1292
1293 codec = tlv320dac33_codec;
1294 socdev->card->codec = codec;
b2c812e2 1295 dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 1296
c8bf93f0
PU		 1297 /* register pcms */
1298 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1299 if (ret < 0) {
1300 dev_err(codec->dev, "failed to create pcms\n");
1301 goto pcm_err;
1302 }
1303
1304 snd_soc_add_controls(codec, dac33_snd_controls,
1305 ARRAY_SIZE(dac33_snd_controls));
1306 /* Only add the nSample controls, if we have valid IRQ number */
1307 if (dac33->irq >= 0)
1308 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1309 ARRAY_SIZE(dac33_nsample_snd_controls));
1310
1311 dac33_add_widgets(codec);
1312
1313 /* power on device */
1314 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1315
c8bf93f0 1316 return 0;
fe3e78e0 1317
c8bf93f0
PU		 1318pcm_err:
1319 dac33_hard_power(codec, 0);
1320 return ret;
1321}
1322
1323static int dac33_soc_remove(struct platform_device *pdev)
1324{
1325 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1326 struct snd_soc_codec *codec = socdev->card->codec;
1327
1328 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1329
1330 snd_soc_free_pcms(socdev);
1331 snd_soc_dapm_free(socdev);
1332
1333 return 0;
1334}
1335
1336static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1337{
1338 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1339 struct snd_soc_codec *codec = socdev->card->codec;
1340
1341 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1342
1343 return 0;
1344}
1345
1346static int dac33_soc_resume(struct platform_device *pdev)
1347{
1348 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1349 struct snd_soc_codec *codec = socdev->card->codec;
1350
1351 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1352 dac33_set_bias_level(codec, codec->suspend_bias_level);
1353
1354 return 0;
1355}
1356
1357struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1358 .probe = dac33_soc_probe,
1359 .remove = dac33_soc_remove,
1360 .suspend = dac33_soc_suspend,
1361 .resume = dac33_soc_resume,
1362};
1363EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1364
1365#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1366 SNDRV_PCM_RATE_48000)
1367#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1368
1369static struct snd_soc_dai_ops dac33_dai_ops = {
c8bf93f0
PU		 1370 .hw_params = dac33_hw_params,
1371 .prepare = dac33_pcm_prepare,
1372 .trigger = dac33_pcm_trigger,
f57d2cfa 1373 .delay = dac33_dai_delay,
c8bf93f0
PU		 1374 .set_sysclk = dac33_set_dai_sysclk,
1375 .set_fmt = dac33_set_dai_fmt,
1376};
1377
1378struct snd_soc_dai dac33_dai = {
1379 .name = "tlv320dac33",
1380 .playback = {
1381 .stream_name = "Playback",
1382 .channels_min = 2,
1383 .channels_max = 2,
1384 .rates = DAC33_RATES,
1385 .formats = DAC33_FORMATS,},
1386 .ops = &dac33_dai_ops,
1387};
1388EXPORT_SYMBOL_GPL(dac33_dai);
1389
735fe4cf
MB		 1390static int __devinit dac33_i2c_probe(struct i2c_client *client,
1391 const struct i2c_device_id *id)
c8bf93f0
PU		 1392{
1393 struct tlv320dac33_platform_data *pdata;
1394 struct tlv320dac33_priv *dac33;
1395 struct snd_soc_codec *codec;
3a7aaed7 1396 int ret, i;
c8bf93f0
PU		 1397
1398 if (client->dev.platform_data == NULL) {
1399 dev_err(&client->dev, "Platform data not set\n");
1400 return -ENODEV;
1401 }
1402 pdata = client->dev.platform_data;
1403
1404 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1405 if (dac33 == NULL)
1406 return -ENOMEM;
1407
1408 codec = &dac33->codec;
b2c812e2 1409 snd_soc_codec_set_drvdata(codec, dac33);
c8bf93f0
PU		 1410 codec->control_data = client;
1411
1412 mutex_init(&codec->mutex);
1413 mutex_init(&dac33->mutex);
f57d2cfa 1414 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1415 INIT_LIST_HEAD(&codec->dapm_widgets);
1416 INIT_LIST_HEAD(&codec->dapm_paths);
1417
1418 codec->name = "tlv320dac33";
1419 codec->owner = THIS_MODULE;
1420 codec->read = dac33_read_reg_cache;
1421 codec->write = dac33_write_locked;
1422 codec->hw_write = (hw_write_t) i2c_master_send;
1423 codec->bias_level = SND_SOC_BIAS_OFF;
1424 codec->set_bias_level = dac33_set_bias_level;
1425 codec->dai = &dac33_dai;
1426 codec->num_dai = 1;
1427 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1428 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1429 GFP_KERNEL);
1430 if (codec->reg_cache == NULL) {
1431 ret = -ENOMEM;
1432 goto error_reg;
1433 }
1434
1435 i2c_set_clientdata(client, dac33);
1436
1437 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1438 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
76f47127
PU		 1439 /* Pre calculate the burst rate */
1440 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
eeb309a8 1441 dac33->keep_bclk = pdata->keep_bclk;
c8bf93f0
PU		 1442 dac33->irq = client->irq;
1443 dac33->nsample = NSAMPLE_MAX;
55abb59c 1444 dac33->nsample_max = NSAMPLE_MAX;
c8bf93f0 1445 /* Disable FIFO use by default */
7427b4b9 1446 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1447
1448 tlv320dac33_codec = codec;
1449
1450 codec->dev = &client->dev;
1451 dac33_dai.dev = codec->dev;
1452
1453 /* Check if the reset GPIO number is valid and request it */
1454 if (dac33->power_gpio >= 0) {
1455 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1456 if (ret < 0) {
1457 dev_err(codec->dev,
1458 "Failed to request reset GPIO (%d)\n",
1459 dac33->power_gpio);
1460 snd_soc_unregister_dai(&dac33_dai);
1461 snd_soc_unregister_codec(codec);
1462 goto error_gpio;
1463 }
1464 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1465 }
1466
1467 /* Check if the IRQ number is valid and request it */
1468 if (dac33->irq >= 0) {
1469 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1470 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1471 codec->name, codec);
1472 if (ret < 0) {
1473 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1474 dac33->irq, ret);
1475 dac33->irq = -1;
1476 }
1477 if (dac33->irq != -1) {
1478 /* Setup work queue */
74ea23aa
PU		 1479 dac33->dac33_wq =
1480 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1481 if (dac33->dac33_wq == NULL) {
1482 free_irq(dac33->irq, &dac33->codec);
1483 ret = -ENOMEM;
1484 goto error_wq;
1485 }
1486
1487 INIT_WORK(&dac33->work, dac33_work);
1488 }
1489 }
1490
3a7aaed7
IK		 1491 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1492 dac33->supplies[i].supply = dac33_supply_names[i];
1493
1494 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1495 dac33->supplies);
1496
1497 if (ret != 0) {
1498 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1499 goto err_get;
1500 }
1501
239fe55c
PU		 1502 /* Read the tlv320dac33 ID registers */
1503 ret = dac33_hard_power(codec, 1);
3a7aaed7 1504 if (ret != 0) {
239fe55c
PU		 1505 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1506 goto error_codec;
3a7aaed7 1507 }
239fe55c
PU		 1508 dac33_read_id(codec);
1509 dac33_hard_power(codec, 0);
3a7aaed7 1510
c8bf93f0
PU		 1511 ret = snd_soc_register_codec(codec);
1512 if (ret != 0) {
1513 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1514 goto error_codec;
1515 }
1516
1517 ret = snd_soc_register_dai(&dac33_dai);
1518 if (ret != 0) {
1519 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1520 snd_soc_unregister_codec(codec);
1521 goto error_codec;
1522 }
1523
c8bf93f0
PU		 1524 return ret;
1525
1526error_codec:
3a7aaed7
IK		 1527 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1528err_get:
c8bf93f0
PU		 1529 if (dac33->irq >= 0) {
1530 free_irq(dac33->irq, &dac33->codec);
1531 destroy_workqueue(dac33->dac33_wq);
1532 }
1533error_wq:
1534 if (dac33->power_gpio >= 0)
1535 gpio_free(dac33->power_gpio);
1536error_gpio:
1537 kfree(codec->reg_cache);
1538error_reg:
1539 tlv320dac33_codec = NULL;
1540 kfree(dac33);
1541
1542 return ret;
1543}
1544
735fe4cf 1545static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1546{
1547 struct tlv320dac33_priv *dac33;
1548
1549 dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1550
1551 if (unlikely(dac33->chip_power))
1552 dac33_hard_power(&dac33->codec, 0);
c8bf93f0
PU		 1553
1554 if (dac33->power_gpio >= 0)
1555 gpio_free(dac33->power_gpio);
1556 if (dac33->irq >= 0)
1557 free_irq(dac33->irq, &dac33->codec);
1558
3a7aaed7
IK		 1559 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1560
c8bf93f0
PU		 1561 destroy_workqueue(dac33->dac33_wq);
1562 snd_soc_unregister_dai(&dac33_dai);
1563 snd_soc_unregister_codec(&dac33->codec);
1564 kfree(dac33->codec.reg_cache);
1565 kfree(dac33);
1566 tlv320dac33_codec = NULL;
1567
1568 return 0;
1569}
1570
1571static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1572 {
1573 .name = "tlv320dac33",
1574 .driver_data = 0,
1575 },
1576 { },
1577};
1578
1579static struct i2c_driver tlv320dac33_i2c_driver = {
1580 .driver = {
1581 .name = "tlv320dac33",
1582 .owner = THIS_MODULE,
1583 },
1584 .probe = dac33_i2c_probe,
1585 .remove = __devexit_p(dac33_i2c_remove),
1586 .id_table = tlv320dac33_i2c_id,
1587};
1588
1589static int __init dac33_module_init(void)
1590{
1591 int r;
1592 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1593 if (r < 0) {
1594 printk(KERN_ERR "DAC33: driver registration failed\n");
1595 return r;
1596 }
1597 return 0;
1598}
1599module_init(dac33_module_init);
1600
1601static void __exit dac33_module_exit(void)
1602{
1603 i2c_del_driver(&tlv320dac33_i2c_driver);
1604}
1605module_exit(dac33_module_exit);
1606
1607
1608MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1609MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1610MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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